OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/Other
    from Rev 43 to Rev 48
    ↔ Reverse comparison
  •

Rev 43 → Rev 48

/dummy_module.IP
11,7 → 11,7
 
$wb_master_dummy_request = bless( {
'version' => 1,
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/wb_master_dummy_request.v',
'file_name' => 'mpsoc/rtl/src_peripheral/DMA/wb_master_dummy_request.v',
'ip_name' => 'dummy_module',
'ports' => {
'clk' => {
190,7 → 190,7
'status' => 'ideal'
},
'hdl_files' => [
'/mpsoc/src_peripheral/Other/wb_master_dummy_request.v'
'/mpsoc/rtl/src_peripheral/Other/wb_master_dummy_request.v'
],
'category' => 'Other',
'unused' => {
/fout_sim.IP
0,0 → 1,233
#######################################################################
## File: fout_sim.IP
##
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
 
$ipgen = bless( {
'version' => 29,
'sw_files' => [
'/mpsoc/src_processor/src_lib/simple-printf'
],
'modules' => {
'fout_simulator' => {}
},
'ip_name' => 'fout_sim',
'module_name' => 'fout_simulator',
'parameters' => {
'BUFFER_SIZE' => {
'content' => '10,1024,1',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Buffer width for getting for getting fle name.',
'type' => 'Spin-button',
'default' => '255 '
}
},
'hdl_files_ticked' => [],
'ports' => {
's_we_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i',
'range' => ''
},
's_cyc_i' => {
'intfc_port' => 'cyc_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'range' => ''
},
's_ack_o' => {
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output',
'range' => ''
},
's_addr_i' => {
'range' => '2 : 0',
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input'
},
's_dat_o' => {
'range' => '31 : 0',
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => ''
},
's_dat_i' => {
'range' => '31 : 0',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input'
},
's_cti_i' => {
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => '2 : 0'
},
'reset' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'range' => ''
},
's_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => '3 : 0'
},
's_stb_i' => {
'range' => '',
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input'
}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'system_c' => '#define MODE_NOT_SOPPRTED 0
#define MODE_CLOSE 1
#define MODE_W 2
#define MODE_WB 3
#define MODE_A 4
#define MODE_AB 5
 
FILE file_ptr [50]={0};
FILE * fopen (const char *filename, const char *mode){
//alloacte a new pointer;
int i=0;
while(file_ptr [i]!=0 && i<50) i++;
if(i==50) return ((FILE *)0) ;
//set file ,ode
if (mode[0] == \'w\' ){
if(mode[1]==\'b\') ${IP}_FILE_MODE = MODE_WB;
else ${IP}_FILE_MODE = MODE_W;
}else if (mode[0] == \'a\' ){
if(mode[1]==\'b\') ${IP}_FILE_MODE = MODE_AB;
else ${IP}_FILE_MODE = MODE_A;
}else { // not supported mode
//${IP}_FILE_MODE = MODE_NOT_SOPPRTED;
return ((FILE *)0);
}
 
 
file_ptr [i]=i+1;
//send file pointer
${IP}_GET_FLE_PTR = file_ptr [i];
//send file name
do{
${IP}_GET_FILE_NAME = *filename;
filename++;
}while(*filename!=0);
// activate the Verilog Fwrite command once sending zero
${IP}_GET_FILE_NAME = 0;
return (& file_ptr[i]);
}
 
 
 
void fclose(FILE * f){
//write file pointer
${IP}_GET_FLE_PTR = *f;
${IP}_FILE_MODE = MODE_CLOSE; // activate the Verilog fclose
*f = 0; //set free the pointer
}
 
void foutbyte( char c){
//write content
${IP}_GET_FILE_CONTENT = c;
}
 
void fout_select (FILE *f){
//write file pointer
${IP}_GET_FLE_PTR = *f;
}
 
#include "simple-printf/sim_fprintf.c"
',
'category' => 'Other',
'description' => 'A simple module to replicate the fprintf/fopen instructions in simulator enviremets. ',
'file_name' => '/home/alireza/work/git/hca_git/ProNoC/mpsoc/rtl/src_peripheral/Other/fout_simulator.v',
'unused' => {
'plug:wb_slave[0]' => [
'tag_i',
'rty_o',
'bte_i',
'err_o'
]
},
'ports_order' => [
'reset',
'clk',
's_dat_i',
's_sel_i',
's_addr_i',
's_cti_i',
's_stb_i',
's_cyc_i',
's_we_i',
's_dat_o',
's_ack_o'
],
'plugs' => {
'reset' => {
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'reset'
}
},
'wb_slave' => {
'0' => {
'name' => 'wb_slave',
'width' => 5,
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'
},
'type' => 'num',
'value' => 1
},
'clk' => {
'value' => 1,
'type' => 'num',
'0' => {
'name' => 'clk'
}
}
},
'parameters_order' => [
'BUFFER_SIZE'
],
'hdl_files' => [
'/mpsoc/rtl/src_peripheral/Other/fout_simulator.v'
],
'system_h' => '#include "simple-printf/sim_fprintf.h"
 
#define ${IP}_GET_FLE_PTR (*((volatile unsigned int *) ($BASE)))
#define ${IP}_GET_FILE_NAME (*((volatile unsigned int *) ($BASE+4)))
#define ${IP}_GET_FILE_CONTENT (*((volatile unsigned int *) ($BASE+8)))
#define ${IP}_FILE_MODE (*((volatile unsigned int *) ($BASE+12)))
 
#define FILE char
 
FILE * fopen (const char *filename, const char *mode);
void fclose(FILE * f);
void foutbyte(char c);
void fout_select(FILE * f);'
}, 'ip_gen' );
/gcd.IP
1,199 → 1,148
#######################################################################
## File: gcd.IP
##
## Copyright (C) 2014-2016 Alireza Monemi
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.8.0
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
## MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
 
$ipgen = bless( {
'parameters' => {
'SELw' => {
'type' => 'Fixed',
'default' => '4',
'content' => '',
'global_param' => 'Localparam',
'info' => 'Parameter',
'redefine_param' => 1
},
'GCDw' => {
'global_param' => 'Parameter',
'default' => '32',
'type' => 'Combo-box',
'content' => '8,16,32',
'info' => 'GCD\'s Input/output width in bits',
'redefine_param' => 1
},
'TAGw' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'default' => '3'
},
'Dw' => {
'default' => 'GCDw',
'type' => 'Fixed',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Parameter'
},
'Aw' => {
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '5',
'type' => 'Fixed',
'content' => '',
'global_param' => 'Localparam'
}
},
'system_h' => '#define ${IP}_DONE_ADDR (*((volatile unsigned int *) ($BASE)))
#define ${IP}_IN_1_ADDR (*((volatile unsigned int *) ($BASE+4)))
#define ${IP}_IN_2_ADDR (*((volatile unsigned int *) ($BASE+8)))
#define ${IP}_GCD_ADDR (*((volatile unsigned int *) ($BASE+12)))
 
 
#define ${IP}_IN1_WRITE(value) ${IP}_IN_1_ADDR=value
#define ${IP}_IN2_WRITE(value) ${IP}_IN_2_ADDR=value
#define ${IP}_DONE_READ() ${IP}_DONE_ADDR
#define ${IP}_READ() ${IP}_GCD_ADDR
 
unsigned int gcd_hardware ( unsigned int p, unsigned int q );',
'system_c' => 'unsigned int gcd_hardware ( unsigned int p, unsigned int q ){
${IP}_IN1_WRITE(p);
${IP}_IN2_WRITE(q);
while (${IP}_DONE_READ()!=1);
return ${IP}_READ();
}',
'ports' => {
's_tag_i' => {
'intfc_port' => 'tag_i',
's_cyc_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cyc_i',
'type' => 'input',
'range' => 'TAGw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]'
'range' => ''
},
's_dat_o' => {
'range' => 'Dw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_o',
'type' => 'output'
},
's_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'stb_i'
'range' => ''
},
's_dat_i' => {
'range' => 'Dw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => 'Dw-1 : 0'
'type' => 'input'
},
's_cyc_i' => {
'intfc_port' => 'cyc_i',
's_rty_o' => {
'range' => '',
'intfc_port' => 'rty_o',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => ''
'type' => 'output'
},
'clk' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i'
},
's_sel_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'SELw-1 : 0',
'type' => 'input'
'range' => 'SELw-1 : 0'
},
's_rty_o' => {
'intfc_port' => 'rty_o',
's_ack_o' => {
'range' => '',
'type' => 'output',
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[0]'
},
's_we_i' => {
'range' => '',
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input'
},
'reset' => {
'range' => '',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
},
's_tag_i' => {
'intfc_port' => 'tag_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => 'TAGw-1 : 0'
},
's_addr_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => 'Aw-1 : 0'
},
's_err_o' => {
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'err_o'
},
's_ack_o' => {
'intfc_port' => 'ack_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_slave[0]'
},
's_we_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i'
},
'clk' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
},
's_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output',
'range' => 'Dw-1 : 0'
'intfc_port' => 'err_o',
'range' => ''
}
},
'ip_name' => 'gcd',
'modules' => {
'gcd_ip' => {}
},
'file_name' => '/home/alireza/mywork/workshop/files/gcd_ip.v',
'category' => 'Other',
'version' => 3,
'parameters_order' => [
'GCDw',
'Dw',
'Aw',
'TAGw',
'SELw'
],
'unused' => {
'plug:wb_slave[0]' => [
'cti_i',
'bte_i'
]
},
'version' => 4,
'module_name' => 'gcd_ip',
'plugs' => {
'clk' => {
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'clk'
},
'value' => 1
'type' => 'num'
},
'wb_slave' => {
'value' => 1,
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'wb_slave',
'width' => 5,
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'name' => 'wb_slave'
'addr' => '0xb800_0000 0xbfff_ffff custom devices'
}
},
'reset' => {
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'reset'
}
},
'value' => 1
}
},
'system_h' => '#define ${IP}_DONE_ADDR (*((volatile unsigned int *) ($BASE)))
#define ${IP}_IN_1_ADDR (*((volatile unsigned int *) ($BASE+4)))
#define ${IP}_IN_2_ADDR (*((volatile unsigned int *) ($BASE+8)))
#define ${IP}_GCD_ADDR (*((volatile unsigned int *) ($BASE+12)))
 
 
#define ${IP}_IN1_WRITE(value) ${IP}_IN_1_ADDR=value
#define ${IP}_IN2_WRITE(value) ${IP}_IN_2_ADDR=value
#define ${IP}_DONE_READ() ${IP}_DONE_ADDR
#define ${IP}_READ() ${IP}_GCD_ADDR
 
unsigned int gcd_hardware ( unsigned int p, unsigned int q ){
${IP}_IN1_WRITE(p);
${IP}_IN2_WRITE(q);
while (${IP}_DONE_READ()!=1);
return ${IP}_READ();
}',
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'description' => 'gcd module',
'module_name' => 'gcd_ip',
'file_name' => '/home/alireza/mywork/workshop/files/gcd_ip.v',
'ports_order' => [
'clk',
'reset',
209,14 → 158,67
's_err_o',
's_rty_o'
],
'parameters_order' => [
'GCDw',
'Dw',
'Aw',
'TAGw',
'SELw'
],
'hdl_files_ticked' => [],
'parameters' => {
'Aw' => {
'global_param' => 'Localparam',
'default' => '5',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => 'Parameter'
},
'Dw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => 'GCDw'
},
'GCDw' => {
'info' => 'GCD\'s Input/output width in bits',
'global_param' => 'Parameter',
'default' => '32',
'content' => '8,16,32',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'SELw' => {
'info' => 'Parameter',
'global_param' => 'Localparam',
'default' => '4',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed'
},
'TAGw' => {
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'default' => '3',
'global_param' => 'Localparam'
}
},
'category' => 'Other',
'description' => 'gcd module',
'hdl_files' => [
'/workshop/files/gcd.v',
'/workshop/files/gcd_ip.v'
'/mpsoc/rtl/src_peripheral/Other/gcd_ip.v',
'/mpsoc/rtl/src_peripheral/Other/gcd.v'
],
'unused' => {
'plug:wb_slave[0]' => [
'bte_i',
'cti_i'
]
}
'modules' => {
'gcd_ip' => {}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
}
}, 'ip_gen' );
/noc_based_mpsoc.IP
0,0 → 1,795
#######################################################################
## File: noc_based_mpsoc.IP
##
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$ipgen = bless( {
'hdl_files' => [],
'version' => 1,
'sockets' => {
'jtag_to_wb' => {
'type' => 'num',
'0' => {
'name' => 'jtag_to_wb_0'
},
'2' => {
'name' => 'jtag_to_wb_2'
},
'1' => {
'name' => 'jtag_to_wb_1'
},
'value' => 3
}
},
'category' => 'Other',
'unused' => undef,
'parameters' => {
'T0_ram_JINDEXw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T2_cpu_FEATURE_DMMU' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef
},
'T0_timer_PRESCALER_WIDTH' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T3_ram_JINDEXw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'type' => 'Fixed',
'default' => '8',
'info' => undef
},
'T2_cpu_FEATURE_INSTRUCTIONCACHE' => {
'info' => undef,
'default' => '"ENABLED"',
'type' => 'Fixed',
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T2_ram_Aw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => '14',
'info' => undef
},
'T1_ram_Aw' => {
'info' => undef,
'default' => '14',
'type' => 'Fixed',
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T0_cpu_FEATURE_DMMU' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T1_cpu_FEATURE_DATACACHE' => {
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T1_cpu_FEATURE_IMMU' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T0_ram_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'default' => '"XILINX"',
'type' => 'Fixed',
'info' => undef
},
'T0_ram_JSTATUSw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed',
'default' => '8'
},
'T2_cpu_IRQ_NUM' => {
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T2_led_PORT_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => ' 1',
'info' => undef
},
'T0_ram_JTAG_CONNECT' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '"XILINX_JTAG_WB"'
},
'T3_ram_JDw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => 'T3_ram_Dw',
'type' => 'Fixed',
'info' => undef
},
'T3_ram_J2WBw' => {
'default' => '(T3_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T3_ram_JDw+T3_ram_JAw : 1',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T3_ram_JTAG_CONNECT' => {
'type' => 'Fixed',
'default' => '"XILINX_JTAG_WB"',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_cpu_OPTION_DCACHE_SNOOP' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'default' => '"ENABLED"',
'type' => 'Fixed'
},
'T0_cpu_FEATURE_DATACACHE' => {
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_ram_JTAG_CONNECT' => {
'info' => undef,
'default' => '"XILINX_JTAG_WB"',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T0_cpu_OPTION_OPERAND_WIDTH' => {
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_ram_J2WBw' => {
'default' => '(T2_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T2_ram_JDw+T2_ram_JAw : 1',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_ram_JAw' => {
'type' => 'Fixed',
'default' => '32',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T1_cpu_FEATURE_INSTRUCTIONCACHE' => {
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_ram_JDw' => {
'info' => undef,
'default' => 'T1_ram_Dw',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_cpu_OPTION_DCACHE_SNOOP' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef
},
'T2_cpu_FEATURE_IMMU' => {
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_ram_J2WBw' => {
'info' => undef,
'default' => '(T0_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T0_ram_JDw+T0_ram_JAw : 1',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_ram_FPGA_VENDOR' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => '"XILINX"',
'info' => undef
},
'T2_ram_JSTATUSw' => {
'default' => '8',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_cpu_FEATURE_DATACACHE' => {
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_cpu_FEATURE_INSTRUCTIONCACHE' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef
},
'T2_cpu_FEATURE_DATACACHE' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef
},
'T2_ram_JINDEXw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '8',
'info' => undef
},
'T3_ram_WB2Jw' => {
'default' => '(T3_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T3_ram_JSTATUSw+T3_ram_JINDEXw+1+T3_ram_JDw : 1',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T1_ram_FPGA_VENDOR' => {
'info' => undef,
'default' => '"XILINX"',
'type' => 'Fixed',
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T1_cpu_IRQ_NUM' => {
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T0_ram_Aw' => {
'info' => undef,
'type' => 'Fixed',
'default' => '14',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T2_cpu_OPTION_DCACHE_SNOOP' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef
},
'T1_ram_WB2Jw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'default' => '(T1_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T1_ram_JSTATUSw+T1_ram_JINDEXw+1+T1_ram_JDw : 1',
'type' => 'Fixed',
'info' => undef
},
'T1_ram_Dw' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T3_led_PORT_WIDTH' => {
'type' => 'Fixed',
'default' => ' 1',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_ram_WB2Jw' => {
'info' => undef,
'default' => '(T0_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T0_ram_JSTATUSw+T0_ram_JINDEXw+1+T0_ram_JDw : 1',
'type' => 'Fixed',
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_cpu_FEATURE_DMMU' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T2_cpu_OPTION_OPERAND_WIDTH' => {
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_ram_FPGA_VENDOR' => {
'type' => 'Fixed',
'default' => '"XILINX"',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_cpu_FEATURE_DMMU' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_ram_J2WBw' => {
'type' => 'Fixed',
'default' => '(T1_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T1_ram_JDw+T1_ram_JAw : 1',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_ram_Aw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '14',
'info' => undef
},
'T1_timer_PRESCALER_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'type' => 'Fixed',
'default' => '8',
'info' => undef
},
'T2_ram_WB2Jw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'default' => '(T2_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T2_ram_JSTATUSw+T2_ram_JINDEXw+1+T2_ram_JDw : 1',
'type' => 'Fixed',
'info' => undef
},
'T1_ram_JINDEXw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => '8',
'type' => 'Fixed'
},
'T3_cpu_IRQ_NUM' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => undef
},
'T0_ram_JDw' => {
'info' => undef,
'default' => 'T0_ram_Dw',
'type' => 'Fixed',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T3_ram_JSTATUSw' => {
'info' => undef,
'default' => '8',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T0_cpu_FEATURE_IMMU' => {
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T1_ram_JTAG_CONNECT' => {
'type' => 'Fixed',
'default' => '"XILINX_JTAG_WB"',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_cpu_FEATURE_INSTRUCTIONCACHE' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T0_cpu_IRQ_NUM' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => '32',
'info' => undef
},
'T0_ram_JAw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'default' => '32',
'type' => 'Fixed',
'info' => undef
},
'T0_ram_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'default' => '32',
'type' => 'Fixed',
'info' => undef
},
'T1_cpu_OPTION_OPERAND_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '32'
},
'T0_led_PORT_WIDTH' => {
'info' => undef,
'type' => 'Fixed',
'default' => ' 1',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T3_cpu_FEATURE_IMMU' => {
'info' => undef,
'default' => '"ENABLED"',
'type' => 'Fixed',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T1_ram_JSTATUSw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'type' => 'Fixed',
'default' => '8'
},
'T3_ram_Dw' => {
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_timer_PRESCALER_WIDTH' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'default' => '8',
'type' => 'Fixed'
},
'T3_ram_JAw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'default' => '32',
'type' => 'Fixed'
},
'T1_led_PORT_WIDTH' => {
'type' => 'Fixed',
'default' => ' 1',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T0_cpu_OPTION_DCACHE_SNOOP' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"'
},
'T3_cpu_OPTION_OPERAND_WIDTH' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => undef
},
'T2_ram_JDw' => {
'info' => undef,
'type' => 'Fixed',
'default' => 'T2_ram_Dw',
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T2_ram_JAw' => {
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T2_ram_Dw' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'parameters_order' => [
'cpu_FEATURE_DATACACHE',
'cpu_FEATURE_DMMU',
'cpu_FEATURE_IMMU',
'cpu_FEATURE_INSTRUCTIONCACHE',
'cpu_IRQ_NUM',
'cpu_OPTION_DCACHE_SNOOP',
'cpu_OPTION_OPERAND_WIDTH',
'led_PORT_WIDTH',
'ram_Aw',
'ram_Dw',
'ram_FPGA_VENDOR',
'ram_J2WBw',
'ram_JAw',
'ram_JDw',
'ram_JINDEXw',
'ram_JSTATUSw',
'ram_JTAG_CONNECT',
'ram_WB2Jw',
'timer_PRESCALER_WIDTH'
],
'file_name' => undef,
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'ports' => {
'T0_led_port_o' => {
'range' => 'T0_led_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'type' => 'output',
'intfc_name' => 'IO'
},
'T2_led_port_o' => {
'range' => 'T2_led_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'type' => 'output',
'intfc_name' => 'IO'
},
'enable0' => {
'range' => undef,
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]'
},
'T3_ram_jtag_to_wb' => {
'intfc_name' => 'IO',
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T3_ram_J2WBw-1 : 0'
},
'hh' => {
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => undef,
'intfc_port' => 'clk_i'
},
'T2_ram_wb_to_jtag' => {
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[2]'
},
'T1_led_port_o' => {
'range' => 'T1_led_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'type' => 'output',
'intfc_name' => 'IO'
},
'T0_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o'
},
'reset0' => {
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => undef,
'intfc_port' => 'reset_i'
},
'T1_ram_wb_to_jtag' => {
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[1]'
},
'T3_led_port_o' => {
'range' => 'T3_led_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'type' => 'output',
'intfc_name' => 'IO'
},
'clk1' => {
'intfc_name' => 'plug:clk[1]',
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => undef
},
'T2_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[2]',
'type' => 'input'
},
'T1_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[1]',
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T1_ram_J2WBw-1 : 0'
},
'T0_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i'
},
'T3_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_name' => 'IO',
'range' => 'T3_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o'
}
},
'plugs' => {
'reset' => {
'value' => 1,
'0' => {
'name' => 'reset0'
},
'type' => 'num'
},
'enable' => {
'0' => {
'name' => 'enable0'
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'value' => '2',
'1' => {
'name' => 'clk1'
},
'0' => {
'name' => 'hh'
},
'type' => 'num'
}
},
'ports_order' => [],
'ip_name' => 'noc_based_mpsoc',
'module_name' => 'noc_based_mpsoc'
}, 'ip_gen' );
/sim_uart.IP
41,7 → 41,7
's_dat_o',
's_ack_o'
],
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/Other/simulator_UART.v',
'file_name' => 'mpsoc/rtl/src_peripheral/Other/simulator_UART.v',
'version' => 7,
'unused' => {
'plug:wb_slave[0]' => [
196,7 → 196,7
},
'ip_name' => 'sim_uart',
'hdl_files' => [
'/mpsoc/src_peripheral/Other/simulator_UART.v'
'/mpsoc/rtl/src_peripheral/Other/simulator_UART.v'
],
'plugs' => {
'clk' => {
/test.IP
0,0 → 1,790
#######################################################################
## File: gpo.IP
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$ipgen =bless( {
'sockets' => {
'jtag_to_wb' => {
'1' => {
'name' => 'jtag_to_wb_1'
},
'value' => 3,
'0' => {
'name' => 'jtag_to_wb_0'
},
'2' => {
'name' => 'jtag_to_wb_2'
},
'type' => 'num'
}
},
'hdl_files' => [],
'category' => 'Other',
'parameters' => {
'T2_ram_Aw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed',
'default' => '14'
},
'T1_ram_Aw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => '14',
'type' => 'Fixed'
},
'T3_ram_JINDEXw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'default' => '8',
'type' => 'Fixed'
},
'T2_cpu_FEATURE_INSTRUCTIONCACHE' => {
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T0_timer_PRESCALER_WIDTH' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T2_cpu_FEATURE_DMMU' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T0_ram_JINDEXw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T2_led_PORT_WIDTH' => {
'default' => ' 1',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T3_timer_PRESCALER_WIDTH' => {
'type' => 'Fixed',
'default' => '8',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_cpu_IRQ_NUM' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'type' => 'Fixed',
'default' => '32'
},
'T1_cpu_FEATURE_IMMU' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef
},
'T0_ram_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'type' => 'Fixed',
'default' => '"XILINX"',
'info' => undef
},
'T0_ram_JSTATUSw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => '8',
'type' => 'Fixed'
},
'T0_cpu_FEATURE_DMMU' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T1_cpu_FEATURE_DATACACHE' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_ram_J2WBw' => {
'default' => '(T2_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T2_ram_JDw+T2_ram_JAw : 1',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T0_cpu_OPTION_OPERAND_WIDTH' => {
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T2_ram_JTAG_CONNECT' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => '"XILINX_JTAG_WB"',
'type' => 'Fixed'
},
'T1_cpu_OPTION_DCACHE_SNOOP' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef
},
'T0_cpu_FEATURE_DATACACHE' => {
'info' => undef,
'default' => '"ENABLED"',
'type' => 'Fixed',
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_ram_JTAG_CONNECT' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"XILINX_JTAG_WB"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_ram_J2WBw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '(T3_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T3_ram_JDw+T3_ram_JAw : 1',
'type' => 'Fixed',
'info' => undef
},
'T3_ram_JDw' => {
'default' => 'T3_ram_Dw',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T0_ram_JTAG_CONNECT' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"XILINX_JTAG_WB"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_ram_J2WBw' => {
'info' => undef,
'default' => '(T0_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T0_ram_JDw+T0_ram_JAw : 1',
'type' => 'Fixed',
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T2_cpu_FEATURE_IMMU' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"'
},
'T1_ram_JDw' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => undef,
'default' => 'T1_ram_Dw',
'type' => 'Fixed'
},
'T3_cpu_OPTION_DCACHE_SNOOP' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"'
},
'T1_cpu_FEATURE_INSTRUCTIONCACHE' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_ram_JAw' => {
'type' => 'Fixed',
'default' => '32',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_led_PORT_WIDTH' => {
'default' => ' 1',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T1_ram_Dw' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T0_ram_WB2Jw' => {
'info' => undef,
'type' => 'Fixed',
'default' => '(T0_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T0_ram_JSTATUSw+T0_ram_JINDEXw+1+T0_ram_JDw : 1',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_cpu_OPTION_DCACHE_SNOOP' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'info' => undef,
'default' => '"ENABLED"',
'type' => 'Fixed'
},
'T1_ram_WB2Jw' => {
'info' => undef,
'default' => '(T1_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T1_ram_JSTATUSw+T1_ram_JINDEXw+1+T1_ram_JDw : 1',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_ram_Aw' => {
'type' => 'Fixed',
'default' => '14',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_cpu_IRQ_NUM' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T1_ram_FPGA_VENDOR' => {
'type' => 'Fixed',
'default' => '"XILINX"',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_ram_WB2Jw' => {
'default' => '(T3_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T3_ram_JSTATUSw+T3_ram_JINDEXw+1+T3_ram_JDw : 1',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_ram_JINDEXw' => {
'default' => '8',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_cpu_FEATURE_DATACACHE' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef
},
'T0_cpu_FEATURE_INSTRUCTIONCACHE' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"'
},
'T2_cpu_FEATURE_DATACACHE' => {
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T2_ram_FPGA_VENDOR' => {
'type' => 'Fixed',
'default' => '"XILINX"',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T2_ram_JSTATUSw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => '8',
'info' => undef
},
'T3_ram_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '14'
},
'T1_ram_J2WBw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'type' => 'Fixed',
'default' => '(T1_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T1_ram_JDw+T1_ram_JAw : 1',
'info' => undef
},
'T1_cpu_FEATURE_DMMU' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T3_ram_FPGA_VENDOR' => {
'type' => 'Fixed',
'default' => '"XILINX"',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T2_cpu_OPTION_OPERAND_WIDTH' => {
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_cpu_FEATURE_DMMU' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Fixed',
'info' => undef
},
'T0_ram_Dw' => {
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_ram_JAw' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T0_cpu_IRQ_NUM' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '32',
'info' => undef
},
'T3_cpu_FEATURE_INSTRUCTIONCACHE' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"'
},
'T1_ram_JTAG_CONNECT' => {
'type' => 'Fixed',
'default' => '"XILINX_JTAG_WB"',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T3_ram_JSTATUSw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef,
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T0_cpu_FEATURE_IMMU' => {
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef
},
'T0_ram_JDw' => {
'info' => undef,
'default' => 'T0_ram_Dw',
'type' => 'Fixed',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T3_cpu_IRQ_NUM' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_timer_PRESCALER_WIDTH' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '8',
'info' => undef
},
'T2_ram_WB2Jw' => {
'default' => '(T2_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T2_ram_JSTATUSw+T2_ram_JINDEXw+1+T2_ram_JDw : 1',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T1_ram_JINDEXw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'default' => '8',
'type' => 'Fixed',
'info' => undef
},
'T2_ram_Dw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '32',
'type' => 'Fixed',
'info' => undef
},
'T3_cpu_OPTION_OPERAND_WIDTH' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T2_ram_JDw' => {
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'T2_ram_Dw',
'info' => undef
},
'T2_ram_JAw' => {
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T0_cpu_OPTION_DCACHE_SNOOP' => {
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => undef
},
'T2_timer_PRESCALER_WIDTH' => {
'info' => undef,
'type' => 'Fixed',
'default' => '8',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T3_ram_JAw' => {
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef
},
'T1_led_PORT_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'type' => 'Fixed',
'default' => ' 1',
'info' => undef
},
'T1_ram_JSTATUSw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'info' => undef,
'type' => 'Fixed',
'default' => '8'
},
'T3_ram_Dw' => {
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'content' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'T3_cpu_FEATURE_IMMU' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'T0_led_PORT_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => undef,
'type' => 'Fixed',
'default' => ' 1',
'info' => undef
},
'T1_cpu_OPTION_OPERAND_WIDTH' => {
'type' => 'Fixed',
'default' => '32',
'info' => undef,
'content' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
}
},
'parameters_order' => [
'cpu_FEATURE_DATACACHE',
'cpu_FEATURE_DMMU',
'cpu_FEATURE_IMMU',
'cpu_FEATURE_INSTRUCTIONCACHE',
'cpu_IRQ_NUM',
'cpu_OPTION_DCACHE_SNOOP',
'cpu_OPTION_OPERAND_WIDTH',
'led_PORT_WIDTH',
'ram_Aw',
'ram_Dw',
'ram_FPGA_VENDOR',
'ram_J2WBw',
'ram_JAw',
'ram_JDw',
'ram_JINDEXw',
'ram_JSTATUSw',
'ram_JTAG_CONNECT',
'ram_WB2Jw',
'timer_PRESCALER_WIDTH'
],
'file_name' => undef,
'ports' => {
'T0_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T0_ram_J2WBw-1 : 0'
},
'T1_ram_jtag_to_wb' => {
'range' => 'T1_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[1]'
},
'T2_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[2]',
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i'
},
'T3_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[3]',
'range' => 'T3_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o'
},
'T1_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[1]',
'type' => 'output'
},
'clk1' => {
'range' => undef,
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[1]'
},
'T3_led_port_o' => {
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO',
'range' => 'T3_led_PORT_WIDTH-1 : 0'
},
'hh' => {
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => undef,
'intfc_port' => 'clk_i'
},
'reset0' => {
'range' => undef,
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]'
},
'T0_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o'
},
'T1_led_port_o' => {
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO',
'range' => 'T1_led_PORT_WIDTH-1 : 0'
},
'T2_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[2]',
'type' => 'output'
},
'T0_led_port_o' => {
'type' => 'output',
'intfc_name' => 'IO',
'range' => 'T0_led_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
},
'T3_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[3]',
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T3_ram_J2WBw-1 : 0'
},
'enable0' => {
'intfc_port' => 'enable_i',
'range' => undef,
'intfc_name' => 'plug:enable[0]',
'type' => 'input'
},
'T2_led_port_o' => {
'type' => 'output',
'intfc_name' => 'IO',
'range' => 'T2_led_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
}
},
'plugs' => {
'clk' => {
'0' => {
'name' => 'hh'
},
'value' => '2',
'1' => {
'name' => 'clk1'
},
'type' => 'num'
},
'reset' => {
'type' => 'num',
'0' => {
'name' => 'reset0'
},
'value' => 1
},
'enable' => {
'type' => 'num',
'0' => {
'name' => 'enable0'
},
'value' => 1
}
},
'ports_order' => [],
'ip_name' => 'noc_based_mpsoc',
'module_name' => 'noc_based_mpsoc'
}, 'ip_gen' );
 

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