OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

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  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/Processor
    from Rev 42 to Rev 48
    ↔ Reverse comparison
  •

Rev 42 → Rev 48

/Or1200.IP
1,567 → 1,567
#######################################################################
## File: Or1200.IP
##
## Copyright (C) 2014-2016 Alireza Monemi
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.7.0
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$or1200 = bless( {
'system_h' => ' #include "or1200/system.h"
 
 
inline void nop (){
__asm__("l.nop 1");
}',
'category' => 'Processor',
'sw_files' => [
'/mpsoc/src_processor/or1200/sw/Makefile',
'/mpsoc/src_processor/or1200/sw/or1200',
'/mpsoc/src_processor/or1200/sw/link.ld',
'/mpsoc/src_processor/or1200/sw/define_printf.h',
'/mpsoc/src_processor/src_lib/simple-printf'
$ipgen = bless( {
'ip_name' => 'Or1200',
'parameters_order' => [
'dw',
'aw',
'ppic_ints',
'boot_adr',
'Data_cashe_size',
'Instruction_cashe_size',
'Data_cashe_enable',
'Instruction_cashe_enable',
'Data_MMU_enable',
'Instruction_MMU_enable',
'implementation_addc',
'implement_sub',
'implement_cy',
'implement_0v',
'implement_OVE',
'implement_alu_rotate',
'implement_alu_compare',
'implement_alu_ext',
'multiplier_type',
'divider_type'
],
'version' => 34,
'hdl_files' => [
'/mpsoc/src_processor/or1200/verilog/or1200.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_alu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_amultp2_32x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_cfgr.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_cpu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_ctrl.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_fsm.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_ram.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_tag.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_tlb.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_32x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_256x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_du.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_except.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_addsub.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_arith.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_div.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_fcmp.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv_except.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_mul.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_addsub.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_div.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_intfloat_conv.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_mul.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_addsub.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_div.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_mul.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_freeze.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_genpc.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_gmultp2_32x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_fsm.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_ram.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_tag.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_if.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_immu_tlb.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_immu_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_iwb_biu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_lsu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_mem2reg.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_mult_mac.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_operandmuxes.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_pic.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_pm.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_qmem_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_reg2mem.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_rf.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_rfram_generic.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_sb.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_sb_fifo.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32_bw.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32x24.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x14.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x22.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x24.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_128x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_256x21.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_512x20.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x8.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32_bw.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x8.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32_bw.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_sprs.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_tpram_32x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_tt.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_wb_biu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_wbmux.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_xcv_ram32x8d.v',
'/mpsoc/src_processor/or1200/verilog/src/timescale.v'
],
'file_name' => '/home/alireza/mywork/mpsoc/src_processor/or1200/verilog/or1200.v',
'hdl_files' => [
'/mpsoc/src_processor/or1200/verilog/or1200.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_alu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_amultp2_32x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_cfgr.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_cpu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_ctrl.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_fsm.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_ram.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_tag.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_tlb.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_32x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_256x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_du.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_except.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_addsub.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_arith.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_div.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_fcmp.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv_except.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_mul.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_addsub.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_div.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_intfloat_conv.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_mul.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_addsub.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_div.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_mul.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_freeze.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_genpc.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_gmultp2_32x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_fsm.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_ram.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_tag.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_if.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_immu_tlb.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_immu_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_iwb_biu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_lsu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_mem2reg.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_mult_mac.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_operandmuxes.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_pic.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_pm.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_qmem_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_reg2mem.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_rf.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_rfram_generic.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_sb.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_sb_fifo.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32_bw.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32x24.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x14.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x22.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x24.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_128x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_256x21.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_512x20.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x8.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32_bw.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x8.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32_bw.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_sprs.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_top.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_tpram_32x32.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_tt.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_wb_biu.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_wbmux.v',
'/mpsoc/src_processor/or1200/verilog/src/or1200_xcv_ram32x8d.v',
'/mpsoc/src_processor/or1200/verilog/src/timescale.v'
],
'ip_name' => 'Or1200',
'plugs' => {
'reset' => {
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'reset'
}
},
'enable' => {
'0' => {
'name' => 'enable'
},
'enable' => {},
'value' => 1,
'type' => 'num'
},
'wb_master' => {
'0' => {
'name' => 'iwb'
},
'type' => 'num',
'value' => 2,
'1' => {
'name' => 'dwb'
}
},
'clk' => {
'0' => {
'name' => 'clk'
},
'type' => 'num',
'value' => 1
}
},
'ports' => {
'reset' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
},
'dwb_sel_o' => {
'type' => 'output',
'range' => '3:0',
'intfc_port' => 'sel_o',
'intfc_name' => 'plug:wb_master[1]'
},
'dwb_cti_o' => {
'intfc_port' => 'cti_o',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'range' => '2:0'
},
'dwb_bte_o' => {
'type' => 'output',
'range' => '1:0',
'intfc_port' => 'bte_o',
'intfc_name' => 'plug:wb_master[1]'
},
'iwb_cyc_o' => {
'intfc_port' => 'cyc_o',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'range' => ''
},
'dwb_adr_o' => {
'intfc_port' => 'adr_o',
'intfc_name' => 'plug:wb_master[1]',
'range' => 'aw-1:0',
'type' => 'output'
},
'iwb_err_i' => {
'intfc_port' => 'err_i',
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'type' => 'input'
},
'dwb_we_o' => {
'range' => '',
'gen_hw_files' => [
'/mpsoc/src_processor/or1200/verilog/or1200_definesfrename_sep_tlib/or1200_defines.v'
],
'ports' => {
'iwb_stb_o' => {
'intfc_port' => 'stb_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'we_o'
'intfc_name' => 'plug:wb_master[0]',
'range' => ''
},
'dwb_rty_i' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'rty_i',
'type' => 'input',
'range' => ''
},
'dwb_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'range' => 'dw-1:0'
},
'iwb_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'range' => 'dw-1:0'
},
'iwb_rty_i' => {
'intfc_port' => 'rty_i',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input',
'range' => ''
},
'iwb_sel_o' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'sel_o',
'type' => 'output',
'range' => '3:0'
},
'clk' => {
'en_i' => {
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]'
'intfc_port' => 'enable_i'
},
'en_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'range' => ''
'iwb_bte_o' => {
'intfc_port' => 'bte_o',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'range' => '1:0'
},
'dwb_dat_o' => {
'intfc_port' => 'dat_o',
'range' => 'dw-1:0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
},
'iwb_err_i' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'err_i'
},
'reset' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
},
'dwb_cyc_o' => {
'type' => 'output',
'range' => '',
'intfc_port' => 'cyc_o',
'intfc_name' => 'plug:wb_master[1]'
},
'iwb_dat_i' => {
'range' => 'dw-1:0',
'type' => 'input',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_master[0]'
},
'iwb_stb_o' => {
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'stb_o'
},
'dwb_ack_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'ack_i'
},
'dwb_dat_i' => {
'type' => 'input',
'range' => 'dw-1:0',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'dat_i'
},
'iwb_cti_o' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'cti_o',
'type' => 'output',
'range' => '2:0'
},
'iwb_we_o' => {
'intfc_port' => 'we_o',
'dwb_stb_o' => {
'intfc_port' => 'stb_o',
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
},
'iwb_dat_o' => {
'intfc_port' => 'dat_o',
'range' => 'dw-1:0',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output'
},
'iwb_rty_i' => {
'intfc_port' => 'rty_i',
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:wb_master[0]'
},
'dwb_we_o' => {
'intfc_port' => 'we_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'range' => ''
},
'iwb_dat_i' => {
'range' => 'dw-1:0',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input',
'intfc_port' => 'dat_i'
},
'iwb_we_o' => {
'intfc_port' => 'we_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'range' => ''
},
'dwb_cyc_o' => {
'intfc_port' => 'cyc_o',
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
},
'iwb_adr_o' => {
'range' => 'aw-1:0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'adr_o'
'dwb_cti_o' => {
'intfc_port' => 'cti_o',
'range' => '2:0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
},
'iwb_cyc_o' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'range' => '',
'intfc_port' => 'cyc_o'
},
'dwb_err_i' => {
'intfc_port' => 'err_i',
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input'
},
'pic_ints_i' => {
'intfc_port' => 'int_i',
'range' => 'ppic_ints-1:0',
'intfc_name' => 'socket:interrupt_peripheral[array]',
'type' => 'input'
},
'dwb_err_i' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'err_i',
'intfc_name' => 'plug:wb_master[1]'
},
'iwb_bte_o' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'bte_o',
'type' => 'output',
'range' => '1:0'
},
'dwb_stb_o' => {
'intfc_port' => 'stb_o',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'range' => ''
},
'iwb_ack_i' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'ack_i',
'intfc_name' => 'plug:wb_master[0]'
},
'pic_ints_i' => {
'intfc_port' => 'int_i',
'intfc_name' => 'socket:interrupt_peripheral[array]',
'range' => 'ppic_ints-1:0',
'type' => 'input'
}
'iwb_sel_o' => {
'intfc_port' => 'sel_o',
'range' => '3:0',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output'
},
'dwb_rty_i' => {
'intfc_port' => 'rty_i',
'type' => 'input',
'intfc_name' => 'plug:wb_master[1]',
'range' => ''
},
'dwb_adr_o' => {
'intfc_port' => 'adr_o',
'range' => 'aw-1:0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
},
'iwb_cti_o' => {
'intfc_port' => 'cti_o',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'range' => '2:0'
},
'dwb_sel_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'range' => '3:0',
'intfc_port' => 'sel_o'
},
'iwb_adr_o' => {
'range' => 'aw-1:0',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'adr_o'
},
'dwb_bte_o' => {
'intfc_port' => 'bte_o',
'range' => '1:0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
},
'dwb_dat_i' => {
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input',
'range' => 'dw-1:0',
'intfc_port' => 'dat_i'
},
'iwb_ack_i' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'ack_i'
},
'clk' => {
'intfc_port' => 'clk_i',
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:clk[0]'
},
'dwb_ack_i' => {
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input',
'intfc_port' => 'ack_i'
}
},
'system_h' => ' #include "or1200/system.h"
 
 
static inline void nop (){
__asm__("l.nop 1");
}',
'plugs' => {
'reset' => {
'0' => {
'name' => 'reset'
},
'type' => 'num',
'value' => 1
},
'clk' => {
'value' => 1,
'type' => 'num',
'0' => {
'name' => 'clk'
}
},
'wb_master' => {
'type' => 'num',
'0' => {
'name' => 'iwb'
},
'1' => {
'name' => 'dwb'
},
'value' => 2
},
'enable' => {
'0' => {
'name' => 'enable'
},
'type' => 'num',
'value' => 1,
'enable' => {}
}
},
'ports_order' => [
'clk',
'reset',
'en_i',
'pic_ints_i',
'iwb_ack_i',
'iwb_err_i',
'iwb_rty_i',
'iwb_dat_i',
'iwb_cyc_o',
'iwb_adr_o',
'iwb_stb_o',
'iwb_we_o',
'iwb_sel_o',
'iwb_dat_o',
'iwb_cti_o',
'iwb_bte_o',
'dwb_ack_i',
'dwb_err_i',
'dwb_rty_i',
'dwb_dat_i',
'dwb_cyc_o',
'dwb_adr_o',
'dwb_stb_o',
'dwb_we_o',
'dwb_sel_o',
'dwb_dat_o',
'dwb_cti_o',
'dwb_bte_o'
],
'modules' => {
'or1200' => {}
},
'unused' => {
'plug:wb_master[0]' => [
'tag_o'
],
'plug:wb_master[1]' => [
'tag_o'
]
},
'parameters_order' => [
'dw',
'aw',
'ppic_ints',
'boot_adr',
'Data_cashe_size',
'Instruction_cashe_size',
'Data_cashe_enable',
'Instruction_cashe_enable',
'Data_MMU_enable',
'Instruction_MMU_enable',
'implementation_addc',
'implement_sub',
'implement_cy',
'implement_0v',
'implement_OVE',
'implement_alu_rotate',
'implement_alu_compare',
'implement_alu_ext',
'multiplier_type',
'divider_type'
],
'unused' => {
'plug:wb_master[1]' => [
'tag_o'
],
'plug:wb_master[0]' => [
'tag_o'
]
},
'parameters' => {
'implement_0v' => {
'content' => '0V,NO_0V',
'parameters' => {
'implement_alu_ext' => {
'redefine_param' => 0,
'info' => 'Implement l.extXs and l.extXz instructions',
'default' => 'NO_EXT',
'type' => 'Combo-box',
'global_param' => 'Don\'t include',
'content' => 'EXT,NO_EXT'
},
'multiplier_type' => {
'global_param' => 'Don\'t include',
'content' => 'SERIAL,PARALLEL',
'default' => 'SERIAL',
'redefine_param' => 0,
'info' => undef,
'type' => 'Combo-box'
},
'Instruction_cashe_size' => {
'default' => '8K',
'redefine_param' => 0,
'info' => 'Instruction Cashe Size in B',
'type' => 'Combo-box',
'global_param' => 'Don\'t include',
'content' => '512,4K,8K,16K,32K'
},
'divider_type' => {
'global_param' => 'Don\'t include',
'content' => 'SERIAL,PARALLEL',
'info' => undef,
'redefine_param' => 0,
'default' => 'SERIAL',
'type' => 'Combo-box'
},
'dw' => {
'global_param' => 'Localparam',
'content' => '',
'default' => '32',
'info' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'implement_alu_compare' => {
'default' => '2',
'redefine_param' => 0,
'info' => 'Type of ALU compare to implement
Try to find which synthesizes with most efficient logic use or highest speed.',
'type' => 'Combo-box',
'global_param' => 'Don\'t include',
'content' => '1,2,3'
},
'implement_alu_rotate' => {
'type' => 'Combo-box',
'default' => 'ROTATE',
'info' => 'Implement rotate in the ALU
At the time of writing this, or32 C/C++ compiler doesn\'t generate rotate instructions. However or32 assembler can assemble code that uses rotate insn.
This means that rotate instructions must be used manually inserted.
By default implementation of rotate is disabled to save area and increase is disabled to save area and increase clock frequency.',
'redefine_param' => 0,
'content' => 'ROTATE,NO_ROTATE',
'global_param' => 'Don\'t include'
},
'implement_OVE' => {
'global_param' => 'Don\'t include',
'content' => 'OVE,NO_OVE',
'default' => 'NO_OVE',
'redefine_param' => 0,
'global_param' => 'Don\'t include',
'info' => 'Implement carry bit SR[OV]
Compiler doesn\'t use this, but other code may like to.',
'default' => '0V',
'info' => 'Implement carry bit SR[OVE]
Overflow interrupt indicator. When enabled, SR[OV] flag does not remain asserted after exception.',
'type' => 'Combo-box'
},
'implement_alu_ext' => {
'global_param' => 'Don\'t include',
'content' => 'EXT,NO_EXT',
'redefine_param' => 0,
'type' => 'Combo-box',
'info' => 'Implement l.extXs and l.extXz instructions',
'default' => 'NO_EXT'
},
'Data_MMU_enable' => {
'content' => 'NO,YES',
'redefine_param' => 0,
'global_param' => 'Don\'t include',
'default' => 'YES',
'info' => undef,
'type' => 'Combo-box'
},
'aw' => {
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'Data_cashe_enable' => {
'info' => undef,
'default' => 'YES',
'type' => 'Combo-box',
'redefine_param' => 0,
'content' => 'NO,YES',
'global_param' => 'Don\'t include'
},
'implement_OVE' => {
'redefine_param' => 0,
'content' => 'OVE,NO_OVE',
'global_param' => 'Don\'t include',
'info' => 'Implement carry bit SR[OVE]
Overflow interrupt indicator. When enabled, SR[OV] flag does not remain asserted after exception.',
'default' => 'NO_OVE',
'type' => 'Combo-box'
},
'implementation_addc' => {
'global_param' => 'Don\'t include',
'content' => 'ADDC,NO_ADDC',
'redefine_param' => 0,
'type' => 'Combo-box',
'default' => 'ADDC',
'info' => 'Implement l.addc/l.addic instructions
'Data_cashe_enable' => {
'type' => 'Combo-box',
'default' => 'YES',
'info' => undef,
'redefine_param' => 0,
'content' => 'NO,YES',
'global_param' => 'Don\'t include'
},
'ppic_ints' => {
'default' => '20',
'redefine_param' => 1,
'info' => 'Number of interrupts',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'content' => '3,31,1'
},
'Instruction_cashe_enable' => {
'info' => undef,
'redefine_param' => 0,
'default' => 'YES',
'type' => 'Combo-box',
'global_param' => 'Don\'t include',
'content' => 'NO,YES'
},
'implementation_addc' => {
'default' => 'ADDC',
'info' => 'Implement l.addc/l.addic instructions
By default implementation of l.addc/l.addic instructions is enabled in case you need them.
If you don\'t use them, then disable implementation to save area.'
},
'implement_sub' => {
'type' => 'Combo-box',
'default' => 'SUB',
'info' => 'Implement l.sub instruction
If you don\'t use them, then disable implementation to save area.',
'redefine_param' => 0,
'type' => 'Combo-box',
'global_param' => 'Don\'t include',
'content' => 'ADDC,NO_ADDC'
},
'aw' => {
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'redefine_param' => 1,
'default' => '32'
},
'implement_sub' => {
'content' => 'SUB,NO_SUB',
'global_param' => 'Don\'t include',
'type' => 'Combo-box',
'info' => 'Implement l.sub instruction
By default implementation of l.sub instructions is enabled to be compliant with the simulator.
If you don\'t use carry bit, then disable implementation to save area.',
'global_param' => 'Don\'t include',
'content' => 'SUB,NO_SUB',
'redefine_param' => 0
},
'divider_type' => {
'type' => 'Combo-box',
'default' => 'SERIAL',
'info' => undef,
'global_param' => 'Don\'t include',
'redefine_param' => 0,
'content' => 'SERIAL,PARALLEL'
'default' => 'SUB'
},
'Instruction_MMU_enable' => {
'global_param' => 'Don\'t include',
'content' => 'NO,YES',
'redefine_param' => 0,
'type' => 'Combo-box',
'default' => 'YES',
'info' => undef
},
'implement_alu_rotate' => {
'global_param' => 'Don\'t include',
'redefine_param' => 0,
'content' => 'ROTATE,NO_ROTATE',
'type' => 'Combo-box',
'info' => 'Implement rotate in the ALU
At the time of writing this, or32 C/C++ compiler doesn\'t generate rotate instructions. However or32 assembler can assemble code that uses rotate insn.
This means that rotate instructions must be used manually inserted.
By default implementation of rotate is disabled to save area and increase is disabled to save area and increase clock frequency.',
'default' => 'ROTATE'
},
'multiplier_type' => {
'global_param' => 'Don\'t include',
'redefine_param' => 0,
'content' => 'SERIAL,PARALLEL',
'type' => 'Combo-box',
'info' => undef,
'default' => 'SERIAL'
},
'boot_adr' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '32\'h00000100',
'type' => 'Fixed'
},
'Instruction_cashe_enable' => {
'global_param' => 'Don\'t include',
'redefine_param' => 0,
'content' => 'NO,YES',
'type' => 'Combo-box',
'info' => undef,
'default' => 'YES'
},
'ppic_ints' => {
'content' => '3,31,1',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'Number of interrupts',
'default' => '20',
'type' => 'Spin-button'
},
'Data_cashe_size' => {
'content' => '512,4K,8K,16K,32K',
'redefine_param' => 0,
'global_param' => 'Don\'t include',
'info' => 'Data Cashe Size in B',
'default' => '8K',
'type' => 'Combo-box'
},
'Instruction_cashe_size' => {
'default' => '8K',
'info' => 'Instruction Cashe Size in B',
'type' => 'Combo-box',
'content' => '512,4K,8K,16K,32K',
'redefine_param' => 0,
'global_param' => 'Don\'t include'
},
'implement_alu_compare' => {
'Data_cashe_size' => {
'global_param' => 'Don\'t include',
'content' => '512,4K,8K,16K,32K',
'default' => '8K',
'redefine_param' => 0,
'info' => 'Data Cashe Size in B',
'type' => 'Combo-box'
},
'Data_MMU_enable' => {
'default' => 'YES',
'redefine_param' => 0,
'info' => undef,
'type' => 'Combo-box',
'global_param' => 'Don\'t include',
'content' => 'NO,YES'
},
'boot_adr' => {
'type' => 'Fixed',
'default' => '32\'h00000100',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam'
},
'implement_0v' => {
'content' => '0V,NO_0V',
'global_param' => 'Don\'t include',
'type' => 'Combo-box',
'default' => '0V',
'redefine_param' => 0,
'info' => 'Implement carry bit SR[OV]
Compiler doesn\'t use this, but other code may like to.'
},
'implement_cy' => {
'content' => 'CY,NO_CY',
'global_param' => 'Don\'t include',
'type' => 'Combo-box',
'info' => 'Implement carry bit SR[CY]
By default implementation of SR[CY] is enabled to be compliant with the simulator. However SR[CY] is explicitly only used by l.addc/l.addic/l.sub instructions and if these three insns are not implemented there is not much point having SR[CY].',
'redefine_param' => 0,
'default' => 'CY'
},
'Instruction_MMU_enable' => {
'global_param' => 'Don\'t include',
'content' => 'NO,YES',
'redefine_param' => 0,
'content' => '1,2,3',
'type' => 'Combo-box',
'default' => '2',
'info' => 'Type of ALU compare to implement
Try to find which synthesizes with most efficient logic use or highest speed.'
},
'dw' => {
'default' => '32',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter'
},
'implement_cy' => {
'type' => 'Combo-box',
'info' => 'Implement carry bit SR[CY]
By default implementation of SR[CY] is enabled to be compliant with the simulator. However SR[CY] is explicitly only used by l.addc/l.addic/l.sub instructions and if these three insns are not implemented there is not much point having SR[CY].',
'default' => 'CY',
'global_param' => 'Don\'t include',
'redefine_param' => 0,
'content' => 'CY,NO_CY'
}
},
'modules' => {
'or1200' => {}
},
'sockets' => {
'interrupt_peripheral' => {
'type' => 'param',
'value' => 'ppic_ints',
'connection_num' => 'single connection',
'0' => {
'name' => 'interrupt'
}
}
},
'ports_order' => [
'clk',
'reset',
'en_i',
'pic_ints_i',
'iwb_ack_i',
'iwb_err_i',
'iwb_rty_i',
'iwb_dat_i',
'iwb_cyc_o',
'iwb_adr_o',
'iwb_stb_o',
'iwb_we_o',
'iwb_sel_o',
'iwb_dat_o',
'iwb_cti_o',
'iwb_bte_o',
'dwb_ack_i',
'dwb_err_i',
'dwb_rty_i',
'dwb_dat_i',
'dwb_cyc_o',
'dwb_adr_o',
'dwb_stb_o',
'dwb_we_o',
'dwb_sel_o',
'dwb_dat_o',
'dwb_cti_o',
'dwb_bte_o'
],
'module_name' => 'or1200',
'gen_hw_files' => [
'/mpsoc/src_processor/or1200/verilog/or1200_definesfrename_sep_tlib/or1200_defines.v'
],
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'version' => 32
}, 'ip_gen' );
'info' => undef,
'default' => 'YES',
'type' => 'Combo-box'
}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'sockets' => {
'interrupt_peripheral' => {
'connection_num' => 'single connection',
'value' => 'ppic_ints',
'0' => {
'name' => 'interrupt'
},
'type' => 'param'
}
},
'sw_files' => [
'/mpsoc/src_processor/or1200/sw/Makefile',
'/mpsoc/src_processor/or1200/sw/or1200',
'/mpsoc/src_processor/or1200/sw/link.ld',
'/mpsoc/src_processor/or1200/sw/define_printf.h',
'/mpsoc/src_processor/src_lib/simple-printf'
],
'category' => 'Processor',
'module_name' => 'or1200',
'file_name' => 'mpsoc/src_processor/or1200/verilog/or1200.v'
}, 'ip_gen' );
/aeMB.IP
1,90 → 1,206
#######################################################################
## File: aeMB.IP
##
## Copyright (C) 2014-2016 Alireza Monemi
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.7.0
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
## MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
 
$ipgen = bless( {
'unused' => undef,
'plugs' => {
'enable' => {
'value' => 1,
'0' => {
'name' => 'enable'
},
'enable' => {},
'type' => 'num'
},
'wb_master' => {
'wb_master' => {},
'value' => 2,
'type' => 'num',
'0' => {
'name' => 'iwb'
},
'1' => {
'name' => 'dwb'
}
},
'clk' => {
'clk' => {},
'0' => {
'name' => 'clk'
},
'type' => 'num',
'value' => 1
},
'reset' => {
'reset' => {},
'value' => 1,
'type' => 'num',
'0' => {
'name' => 'reset'
}
}
},
'sockets' => {
'interrupt_cpu' => {
'type' => 'num',
'0' => {
'name' => 'interrupt_cpu'
},
'connection_num' => 'single connection',
'value' => 1
}
},
'gen_sw_files_ticked' => [],
'system_h' => '
#include "aemb/core.hh"
static inline void nop (void) {
asm volatile ("nop");
}
 
void general_int_main( void ) __attribute__ ((interrupt_handler)); // general_int_main() is defined by interrupt controller
void aemb_enable_interrupt (void);
void exit (int);
 
#define general_cpu_int_en aemb_enable_interrupt
 
',
'parameters' => {
'AEMB_DWB' => {
'redefine_param' => 1,
'info' => undef,
'default' => ' 32',
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'AEMB_BSF' => {
'default' => ' 1',
'content' => '',
'redefine_param' => 1,
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'AEMB_IWB' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'default' => ' 32',
'info' => undef,
'redefine_param' => 1,
'info' => undef
'default' => ' 1'
},
'AEMB_XWB' => {
'type' => 'Fixed',
'AEMB_ICH' => {
'global_param' => 'Localparam',
'content' => '',
'default' => ' 7',
'default' => ' 11',
'redefine_param' => 1,
'info' => undef,
'redefine_param' => 1
'type' => 'Fixed'
},
'HEAP_SIZE' => {
'info' => undef,
'redefine_param' => 0,
'content' => '',
'default' => '0x400',
'type' => 'Entry',
'global_param' => 'Don\'t include'
},
'AEMB_MUL' => {
'default' => ' 1',
'content' => '',
'AEMB_IDX' => {
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'type' => 'Fixed',
'default' => ' 6',
'content' => '',
'global_param' => 'Localparam'
},
'AEMB_IDX' => {
'AEMB_IWB' => {
'info' => undef,
'type' => 'Fixed',
'redefine_param' => 1,
'default' => ' 6',
'default' => ' 32',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'AEMB_ICH' => {
'AEMB_DWB' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'default' => ' 11',
'default' => ' 32',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => undef
},
'AEMB_MUL' => {
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => ' 1',
'redefine_param' => 1
},
'STACK_SIZE' => {
'content' => '',
'global_param' => 'Don\'t include',
'type' => 'Entry',
'global_param' => 'Don\'t include',
'default' => '0x400',
'content' => '',
'info' => 'The stack size in hex',
'redefine_param' => 0
}
'redefine_param' => 0,
'default' => '0x400'
},
'AEMB_XWB' => {
'global_param' => 'Localparam',
'content' => '',
'default' => ' 7',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => undef
},
'HEAP_SIZE' => {
'global_param' => 'Don\'t include',
'content' => '',
'default' => '0x400',
'redefine_param' => 0,
'type' => 'Entry',
'info' => undef
}
},
'description' => 'AEMB 32-bit Microprocessor Core
For more information check http://opencores.org/project,aemb',
'ip_name' => 'aeMB',
'module_name' => 'aeMB_top',
'ports_order' => [
'dwb_adr_o',
'dwb_cyc_o',
'dwb_dat_o',
'dwb_sel_o',
'dwb_stb_o',
'dwb_tag_o',
'dwb_wre_o',
'dwb_cti_o',
'dwb_bte_o',
'dwb_ack_i',
'dwb_dat_i',
'dwb_err_i',
'dwb_rty_i',
'iwb_adr_o',
'iwb_cyc_o',
'iwb_sel_o',
'iwb_stb_o',
'iwb_tag_o',
'iwb_wre_o',
'iwb_dat_o',
'iwb_cti_o',
'iwb_bte_o',
'iwb_ack_i',
'iwb_dat_i',
'iwb_err_i',
'iwb_rty_i',
'clk',
'reset',
'sys_int_i',
'sys_ena_i'
],
'parameters_order' => [
'AEMB_IWB',
'AEMB_DWB',
'AEMB_XWB',
'AEMB_ICH',
'AEMB_IDX',
'AEMB_BSF',
'AEMB_MUL',
'STACK_SIZE',
'HEAP_SIZE'
],
'file_name' => 'mpsoc/src_processor/aeMB/verilog/aemb.v',
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'modules' => {
'aeMB_top' => {}
},
'hdl_files' => [
'/mpsoc/src_processor/aeMB/verilog/aemb.v',
'/mpsoc/src_processor/aeMB/verilog/src/aeMB_core.v',
117,308 → 233,237
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iche.v',
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iwbif.v'
],
'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/aeMB/verilog/aemb.v',
'module_name' => 'aeMB_top',
'sockets' => {
'interrupt_cpu' => {
'connection_num' => 'single connection',
'type' => 'num',
'0' => {
'name' => 'interrupt_cpu'
},
'value' => 1
}
},
'version' => 2,
'description' => 'AEMB 32-bit Microprocessor Core
For more information check http://opencores.org/project,aemb',
'gen_sw_files' => [
'/mpsoc/src_processor/aeMB/sw/compile/gccromfrename_sep_tcompile/gccrom',
'/mpsoc/src_processor/aeMB/sw/Makefilefrename_sep_tMakefile'
'/mpsoc/src_processor/aeMB/sw/link.ldfrename_sep_tlink.ld'
],
'plugs' => {
'enable' => {
'type' => 'num',
'0' => {
'name' => 'enable'
},
'value' => 1,
'enable' => {}
},
'clk' => {
'clk' => {},
'value' => 1,
'0' => {
'name' => 'clk'
},
'type' => 'num'
},
'wb_master' => {
'wb_master' => {},
'1' => {
'name' => 'dwb'
},
'value' => 2,
'type' => 'num',
'0' => {
'name' => 'iwb'
}
},
'reset' => {
'reset' => {},
'0' => {
'name' => 'reset'
},
'type' => 'num',
'value' => 1
}
},
'sw_files' => [
'/mpsoc/src_processor/aeMB/sw/aemb',
'/mpsoc/src_processor/aeMB/sw/aemb.specs',
'/mpsoc/src_processor/aeMB/sw/Makefile'
],
'unused' => undef,
'category' => 'Processor',
'version' => 10,
'ports' => {
'iwb_tag_o' => {
'dwb_wre_o' => {
'type' => 'output',
'intfc_port' => 'we_o',
'intfc_name' => 'plug:wb_master[1]',
'range' => ''
},
'dwb_ack_i' => {
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input',
'intfc_port' => 'ack_i'
},
'iwb_bte_o' => {
'range' => '1:0',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'tag_o',
'range' => '2:0'
'type' => 'output',
'intfc_port' => 'bte_o'
},
'iwb_adr_o' => {
'iwb_wre_o' => {
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'we_o'
},
'iwb_ack_i' => {
'type' => 'input',
'intfc_port' => 'ack_i',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
'dwb_adr_o' => {
'range' => '31:0',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'adr_o',
'range' => '31:0'
'type' => 'output'
},
'clk' => {
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]'
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'dwb_rty_i' => {
'iwb_tag_o' => {
'intfc_port' => 'tag_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'range' => '2:0'
},
'iwb_err_i' => {
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input',
'intfc_port' => 'err_i'
},
'dwb_cti_o' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'rty_i',
'range' => ''
'range' => '2:0',
'intfc_port' => 'cti_o',
'type' => 'output'
},
'dwb_stb_o' => {
'dwb_cyc_o' => {
'type' => 'output',
'intfc_port' => 'cyc_o',
'range' => '',
'intfc_port' => 'stb_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
},
'dwb_wre_o' => {
'dwb_err_i' => {
'range' => '',
'intfc_port' => 'we_o',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
'type' => 'input',
'intfc_port' => 'err_i'
},
'iwb_stb_o' => {
'range' => '',
'intfc_port' => 'stb_o',
'dwb_bte_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '1:0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
'intfc_port' => 'bte_o'
},
'reset' => {
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'intfc_port' => 'reset_i',
'range' => ''
},
'dwb_bte_o' => {
'iwb_cti_o' => {
'intfc_port' => 'cti_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'bte_o',
'range' => '1:0'
'range' => '2:0',
'intfc_name' => 'plug:wb_master[0]'
},
'dwb_dat_i' => {
'range' => '31:0',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input'
},
'dwb_dat_o' => {
'range' => '31:0',
'intfc_port' => 'dat_o',
'iwb_adr_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
'intfc_port' => 'adr_o',
'intfc_name' => 'plug:wb_master[0]',
'range' => '31:0'
},
'iwb_rty_i' => {
'sys_ena_i' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'intfc_port' => 'rty_i',
'type' => 'input',
'intfc_name' => 'plug:wb_master[0]'
'intfc_port' => 'enable_i',
'type' => 'input'
},
'iwb_cyc_o' => {
'intfc_port' => 'cyc_o',
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'cyc_o',
'type' => 'output'
},
'dwb_cyc_o' => {
'dwb_dat_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '31:0',
'type' => 'output',
'intfc_port' => 'dat_o'
},
'dwb_stb_o' => {
'range' => '',
'intfc_port' => 'cyc_o'
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'stb_o',
'type' => 'output'
},
'dwb_sel_o' => {
'intfc_port' => 'sel_o',
'range' => '3:0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
},
'sys_int_i' => {
'intfc_port' => 'int_i',
'iwb_rty_i' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'socket:interrupt_cpu[0]'
},
'iwb_dat_i' => {
'intfc_port' => 'dat_i',
'range' => '31:0',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'rty_i',
'type' => 'input'
},
'dwb_err_i' => {
'intfc_port' => 'err_i',
'iwb_stb_o' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'stb_o'
},
'dwb_dat_i' => {
'range' => '31:0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input',
'intfc_name' => 'plug:wb_master[1]'
'intfc_port' => 'dat_i'
},
'iwb_sel_o' => {
'intfc_port' => 'sel_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'sel_o',
'range' => '3:0'
},
'iwb_wre_o' => {
'intfc_port' => 'we_o',
'range' => '',
'dwb_sel_o' => {
'intfc_port' => 'sel_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
},
'dwb_adr_o' => {
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_port' => 'adr_o',
'range' => '31:0'
'range' => '3:0'
},
'iwb_cti_o' => {
'range' => '2:0',
'intfc_port' => 'cti_o',
'iwb_dat_o' => {
'range' => '31:0',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
'intfc_port' => 'dat_o'
},
'iwb_err_i' => {
'intfc_port' => 'err_i',
'sys_int_i' => {
'type' => 'input',
'intfc_port' => 'int_i',
'range' => '',
'intfc_name' => 'socket:interrupt_cpu[0]'
},
'iwb_dat_i' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input'
},
'dwb_tag_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'tag_o',
'range' => '2:0'
},
'sys_ena_i' => {
'intfc_name' => 'plug:enable[0]',
'range' => '31:0',
'type' => 'input',
'intfc_port' => 'enable_i',
'range' => ''
'intfc_port' => 'dat_i'
},
'dwb_ack_i' => {
'dwb_rty_i' => {
'range' => '',
'intfc_port' => 'ack_i',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input'
'type' => 'input',
'intfc_port' => 'rty_i'
},
'iwb_bte_o' => {
'range' => '1:0',
'intfc_port' => 'bte_o',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output'
},
'iwb_dat_o' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'dat_o',
'range' => '31:0'
},
'dwb_cti_o' => {
'type' => 'output',
'reset' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'dwb_tag_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '2:0',
'intfc_port' => 'cti_o'
},
'iwb_ack_i' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input',
'intfc_port' => 'ack_i',
'range' => ''
'type' => 'output',
'intfc_port' => 'tag_o'
}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'modules' => {
'aeMB_top' => {}
},
'ip_name' => 'aeMB',
'system_h' => ' #include <stdio.h>
#include <stdlib.h>
#include "aemb/core.hh"
inline void nop (void) {
asm volatile ("nop");
}',
'ports_order' => [
'dwb_adr_o',
'dwb_cyc_o',
'dwb_dat_o',
'dwb_sel_o',
'dwb_stb_o',
'dwb_tag_o',
'dwb_wre_o',
'dwb_cti_o',
'dwb_bte_o',
'dwb_ack_i',
'dwb_dat_i',
'dwb_err_i',
'dwb_rty_i',
'iwb_adr_o',
'iwb_cyc_o',
'iwb_sel_o',
'iwb_stb_o',
'iwb_tag_o',
'iwb_wre_o',
'iwb_dat_o',
'iwb_cti_o',
'iwb_bte_o',
'iwb_ack_i',
'iwb_dat_i',
'iwb_err_i',
'iwb_rty_i',
'clk',
'reset',
'sys_int_i',
'sys_ena_i'
],
'category' => 'Processor',
'sw_files' => [
'/mpsoc/src_processor/aeMB/sw/aemb',
'/mpsoc/src_processor/aeMB/sw/compile',
'/mpsoc/src_processor/aeMB/sw/program',
'/mpsoc/src_processor/program.sh',
'/mpsoc/src_processor/aeMB/sw/define_printf.h'
],
'parameters_order' => [
'AEMB_IWB',
'AEMB_DWB',
'AEMB_XWB',
'AEMB_ICH',
'AEMB_IDX',
'AEMB_BSF',
'AEMB_MUL',
'STACK_SIZE',
'HEAP_SIZE'
]
'system_c' => '
#include "aemb/core.cc"
 
/*!
* Assembly macro to enable MSR_IE
*/
void aemb_enable_interrupt ()
{
int msr, tmp;
asm volatile ("mfs %0, rmsr;"
"ori %1, %0, 0x02;"
"mts rmsr, %1;"
: "=r"(msr)
: "r" (tmp)
);
}
 
void aemb_disable_interrupt ()
{
int msr, tmp;
asm volatile ("mfs %0, rmsr;"
"andi %1, %0, 0xFD;"
"mts rmsr, %1;"
: "=r"(msr)
: "r" (tmp)
);
}
 
 
/* Loops/exits simulation */
void exit (int i)
{
aemb_disable_interrupt ();
while (1);
}
 
 
 
 
'
}, 'ip_gen' );
/lm32.IP
1,381 → 1,448
#######################################################################
## File: lm32.IP
##
## Copyright (C) 2014-2016 Alireza Monemi
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.7.0
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$lm32 = bless( {
'hdl_files' => [
'/mpsoc/src_processor/lm32/verilog/src/er1.v',
'/mpsoc/src_processor/lm32/verilog/src/JTAGB.v',
'/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_include.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_top.v',
'/mpsoc/src_processor/lm32/verilog/src/spiprog.v',
'/mpsoc/src_processor/lm32/verilog/src/system_conf.v',
'/mpsoc/src_processor/lm32/verilog/src/typea.v',
'/mpsoc/src_processor/lm32/verilog/src/typeb.v'
],
'category' => 'Processor',
'sockets' => {
'interrupt_peripheral' => {
'type' => 'param',
'interrupt_peripheral' => {},
'0' => {
'name' => 'interrupt_peripheral'
},
'value' => 'INTR_NUM',
'connection_num' => 'single connection'
}
},
'sw_files' => [
'/mpsoc/src_processor/lm32/sw/crt0ram.S',
'/mpsoc/src_processor/lm32/sw/linker.ld',
'/mpsoc/src_processor/lm32/sw/lm32_system.h',
'/mpsoc/src_processor/lm32/sw/Makefile',
'/mpsoc/src_processor/lm32/sw/program',
'/mpsoc/src_processor/program.sh',
'/mpsoc/src_processor/lm32/sw/define_printf.h',
'/mpsoc/src_processor/src_lib/simple-printf'
],
'unused' => {
'plug:wb_master[0]' => [
'tag_o'
],
'plug:wb_master[1]' => [
'tag_o'
]
},
'module_name' => 'lm32',
'parameters_order' => [
'INTR_NUM',
'CFG_PL_MULTIPLY',
'CFG_PL_BARREL_SHIFT',
'CFG_SIGN_EXTEND',
'CFG_MC_DIVIDE'
],
'system_h' => '#include "lm32_system.h"
inline void nop (void) {
asm volatile ("nop");
}',
'modules' => {
'lm32' => {}
},
'ip_name' => 'lm32',
'plugs' => {
'reset' => {
'0' => {
'name' => 'reset'
},
'type' => 'num',
'reset' => {},
'1' => {
'name' => 'reset_1'
},
'value' => 1
},
'clk' => {
'0' => {
'name' => 'clk'
},
'type' => 'num',
'clk' => {},
'value' => 1
},
'enable' => {
'enable' => {},
'type' => 'num',
$ipgen = bless( {
'version' => 5,
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'ports_order' => [
'clk_i',
'rst_i',
'en_i',
'interrupt',
'I_DAT_I',
'I_ACK_I',
'I_ERR_I',
'I_RTY_I',
'I_DAT_O',
'I_ADR_O',
'I_CYC_O',
'I_SEL_O',
'I_STB_O',
'I_WE_O',
'I_CTI_O',
'I_BTE_O',
'D_DAT_I',
'D_ACK_I',
'D_ERR_I',
'D_RTY_I',
'D_DAT_O',
'D_ADR_O',
'D_CYC_O',
'D_SEL_O',
'D_STB_O',
'D_WE_O',
'D_CTI_O',
'D_BTE_O'
],
'ip_name' => 'lm32',
'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement.
 
for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx',
'plugs' => {
'enable' => {
'type' => 'num',
'enable' => {},
'value' => 1,
'0' => {
'name' => 'enable'
}
},
'clk' => {
'clk' => {},
'value' => 1,
'0' => {
'name' => 'clk'
},
'type' => 'num'
},
'wb_master' => {
'1' => {
'name' => 'dwb'
},
'0' => {
'name' => 'iwb'
},
'value' => 2,
'type' => 'num',
'wb_master' => {}
},
'reset' => {
'value' => 1,
'1' => {
'name' => 'reset_1'
},
'0' => {
'name' => 'enable'
'name' => 'reset'
},
'value' => 1
},
'wb_master' => {
'1' => {
'name' => 'dwb'
},
'value' => 2,
'0' => {
'name' => 'iwb'
},
'type' => 'num',
'wb_master' => {}
}
},
'ports' => {
'interrupt' => {
'intfc_port' => 'int_i',
'type' => 'input',
'range' => '(32-1):0',
'intfc_name' => 'socket:interrupt_peripheral[array]'
},
'D_ACK_I' => {
'intfc_port' => 'ack_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'D_RTY_I' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'rty_i',
'range' => '',
'type' => 'input'
},
'I_CTI_O' => {
'intfc_name' => 'plug:wb_master[0]',
'reset' => {},
'type' => 'num'
}
},
'ports' => {
'D_CYC_O' => {
'type' => 'output',
'intfc_port' => 'cyc_o',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'I_WE_O' => {
'type' => 'output',
'range' => '(3-1):0',
'intfc_port' => 'cti_o'
},
'I_DAT_O' => {
'type' => 'output',
'range' => '(32-1):0',
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_master[0]'
},
'I_DAT_I' => {
'type' => 'input',
'range' => '(32-1):0',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_master[0]'
},
'D_ADR_O' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'adr_o',
'type' => 'output',
'range' => '(32-1):0'
},
'I_ACK_I' => {
'intfc_port' => 'ack_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
'I_BTE_O' => {
'intfc_port' => 'bte_o',
'type' => 'output',
'range' => '(2-1):0',
'intfc_name' => 'plug:wb_master[0]'
},
'I_RTY_I' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'rty_i'
'intfc_port' => 'we_o'
},
'clk_i' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]'
},
'D_CTI_O' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '(3-1):0',
'type' => 'output',
'intfc_port' => 'cti_o'
},
'D_DAT_I' => {
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input',
'range' => '(32-1):0',
'intfc_port' => 'dat_i'
},
'D_WE_O' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'we_o',
'I_DAT_O' => {
'intfc_port' => 'dat_o',
'range' => '(32-1):0',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output'
},
'rst_i' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'range' => '',
'type' => 'output'
'intfc_name' => 'plug:reset[0]'
},
'rst_i' => {
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'D_ERR_I' => {
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'err_i',
'type' => 'input'
},
'D_CTI_O' => {
'intfc_port' => 'cti_o',
'range' => '(3-1):0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
},
'en_i' => {
'range' => '',
'intfc_port' => 'reset_i'
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
},
'en_i' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]'
},
'D_BTE_O' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'bte_o',
'type' => 'output',
'range' => '(2-1):0'
},
'I_SEL_O' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '(4-1):0',
'type' => 'output',
'intfc_port' => 'sel_o'
},
'D_DAT_O' => {
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'range' => '(32-1):0',
'intfc_port' => 'dat_o'
},
'D_ERR_I' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'err_i',
'range' => '',
'type' => 'input'
},
'I_STB_O' => {
'type' => 'output',
'range' => '',
'intfc_port' => 'stb_o',
'intfc_name' => 'plug:wb_master[0]'
},
'I_WE_O' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'we_o',
'I_ERR_I' => {
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'err_i',
'type' => 'input'
},
'clk_i' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => '',
'type' => 'output'
'intfc_name' => 'plug:clk[0]'
},
'I_ADR_O' => {
'intfc_name' => 'plug:wb_master[0]',
'I_ACK_I' => {
'intfc_port' => 'ack_i',
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input'
},
'I_ADR_O' => {
'type' => 'output',
'intfc_port' => 'adr_o',
'intfc_name' => 'plug:wb_master[0]',
'range' => '(32-1):0'
},
'D_ADR_O' => {
'intfc_port' => 'adr_o',
'intfc_name' => 'plug:wb_master[1]',
'range' => '(32-1):0',
'type' => 'output'
},
'D_STB_O' => {
'intfc_port' => 'stb_o',
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
},
'I_RTY_I' => {
'intfc_port' => 'rty_i',
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input'
},
'interrupt' => {
'type' => 'input',
'intfc_port' => 'int_i',
'intfc_name' => 'socket:interrupt_peripheral[array]',
'range' => '(32-1):0'
},
'D_BTE_O' => {
'range' => '(2-1):0',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'bte_o',
'type' => 'output'
},
'D_RTY_I' => {
'intfc_port' => 'rty_i',
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input'
},
'I_CTI_O' => {
'type' => 'output',
'intfc_port' => 'cti_o',
'intfc_name' => 'plug:wb_master[0]',
'range' => '(3-1):0'
},
'D_WE_O' => {
'type' => 'output',
'range' => '(32-1):0',
'intfc_port' => 'adr_o'
},
'I_ERR_I' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input',
'range' => '',
'intfc_port' => 'err_i'
},
'D_STB_O' => {
'intfc_port' => 'we_o',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'stb_o',
'range' => '',
'type' => 'output'
'range' => ''
},
'D_CYC_O' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'cyc_o',
'range' => '',
'type' => 'output'
},
'D_SEL_O' => {
'range' => '(4-1):0',
'type' => 'output',
'intfc_port' => 'sel_o',
'intfc_name' => 'plug:wb_master[1]'
},
'I_CYC_O' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'cyc_o',
'type' => 'output',
'range' => ''
}
},
'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement.
 
for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx',
'ports_order' => [
'clk_i',
'rst_i',
'en_i',
'interrupt',
'I_DAT_I',
'I_ACK_I',
'I_ERR_I',
'I_RTY_I',
'I_DAT_O',
'I_ADR_O',
'I_CYC_O',
'I_SEL_O',
'I_STB_O',
'I_WE_O',
'I_CTI_O',
'I_BTE_O',
'D_DAT_I',
'D_ACK_I',
'D_ERR_I',
'D_RTY_I',
'D_DAT_O',
'D_ADR_O',
'D_CYC_O',
'D_SEL_O',
'D_STB_O',
'D_WE_O',
'D_CTI_O',
'D_BTE_O'
],
'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v',
'version' => 2,
'I_CYC_O' => {
'type' => 'output',
'intfc_port' => 'cyc_o',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
'D_DAT_I' => {
'type' => 'input',
'intfc_port' => 'dat_i',
'range' => '(32-1):0',
'intfc_name' => 'plug:wb_master[1]'
},
'I_SEL_O' => {
'type' => 'output',
'intfc_port' => 'sel_o',
'intfc_name' => 'plug:wb_master[0]',
'range' => '(4-1):0'
},
'I_BTE_O' => {
'type' => 'output',
'range' => '(2-1):0',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'bte_o'
},
'I_STB_O' => {
'intfc_port' => 'stb_o',
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output'
},
'D_ACK_I' => {
'intfc_port' => 'ack_i',
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input'
},
'D_SEL_O' => {
'type' => 'output',
'intfc_port' => 'sel_o',
'intfc_name' => 'plug:wb_master[1]',
'range' => '(4-1):0'
},
'D_DAT_O' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'range' => '(32-1):0',
'intfc_port' => 'dat_o'
},
'I_DAT_I' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '(32-1):0',
'intfc_port' => 'dat_i',
'type' => 'input'
}
},
'hdl_files' => [
'/mpsoc/src_processor/lm32/verilog/src/er1.v',
'/mpsoc/src_processor/lm32/verilog/src/JTAGB.v',
'/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_include.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v',
'/mpsoc/src_processor/lm32/verilog/src/lm32_top.v',
'/mpsoc/src_processor/lm32/verilog/src/spiprog.v',
'/mpsoc/src_processor/lm32/verilog/src/system_conf.v',
'/mpsoc/src_processor/lm32/verilog/src/typea.v',
'/mpsoc/src_processor/lm32/verilog/src/typeb.v'
],
'unused' => {
'plug:wb_master[0]' => [
'tag_o'
],
'plug:wb_master[1]' => [
'tag_o'
]
},
'module_name' => 'lm32',
'parameters_order' => [
'INTR_NUM',
'BARREL_SHIFT',
'SIGN_EXTEND',
'BARREL_SHIFT',
'MULTIPLIER_TYPE',
'DIVIDOR_TYPE',
'INSTRUCTION_CACHE',
'ICACHE_ASSOCIATIVITY',
'ICACHE_SETS',
'DATA_CACHE',
'DCACHE_ASSOCIATIVITY',
'DCACHE_SETS'
],
'system_c' => '#include "lm32/lm32_system.c"',
'category' => 'Processor',
'modules' => {
'lm32' => {}
},
'gen_sw_files' => [
'/mpsoc/src_processor/new_lm32/sw/cpu_flags_genfrename_sep_tcpu_flags'
],
'gen_hw_files' => [
'/mpsoc/src_processor/new_lm32/config/lm32_config_gen.vfrename_sep_tlib/lm32_config.v'
],
'sw_files' => [
'/mpsoc/src_processor/lm32/sw/lm32',
'/mpsoc/src_processor/lm32/sw/linker.ld',
'/mpsoc/src_processor/lm32/sw/Makefile'
],
'parameters' => {
'CFG_MC_DIVIDE' => {
'global_param' => 0,
'content' => '"ENABLED","DISABLED"',
'info' => undef,
'INTR_NUM' => {
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'default' => '32',
'info' => undef
},
'SIGN_EXTEND' => {
'content' => 'ENABLED,DISABLED',
'global_param' => 'Don\'t include',
'type' => 'Combo-box',
'redefine_param' => 1,
'info' => 'Enable sign-extension instructions',
'default' => 'ENABLED'
},
'INSTRUCTION_CACHE' => {
'default' => 'ENABLED',
'info' => 'Enable/Disable Instruction cache',
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => 'ENABLED,DISABLED',
'global_param' => 'Don\'t include'
},
'BARREL_SHIFT' => {
'content' => 'MULTI_CYCLE,PIPE_LINE,NONE',
'global_param' => 'Don\'t include',
'type' => 'Combo-box',
'redefine_param' => 1,
'default' => '"DISABLED"',
'type' => 'Fixed'
'info' => 'Shifter
You may either enable the piplined or the multi-cycle barrel
shifter. The multi-cycle shifter will stall the pipeline until
the result is available after 32 cycles.
If both options are disabled, only "right shift by one bit" is
available.',
'default' => 'PIPE_LINE'
},
'INTR_NUM' => {
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'content' => '',
'global_param' => 0
},
'CFG_SIGN_EXTEND' => {
'type' => 'Fixed',
'default' => '"ENABLED"',
'redefine_param' => 1,
'info' => undef,
'content' => '"ENABLED","DISABLED"',
'global_param' => 0
},
'CFG_PL_MULTIPLY' => {
'content' => '"ENABLED","DISABLED"',
'global_param' => 0,
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed',
'default' => '"ENABLED"'
},
'CFG_PL_BARREL_SHIFT' => {
'content' => '"ENABLED","DISABLED"',
'global_param' => 0,
'type' => 'Fixed',
'default' => '"ENABLED"',
'redefine_param' => 1,
'info' => undef
}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
}
}, 'ip_gen' );
'DCACHE_ASSOCIATIVITY' => {
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '1,2,4,8',
'global_param' => 'Don\'t include',
'default' => '1',
'info' => 'Data cache assocativity number '
},
'DIVIDOR_TYPE' => {
'info' => ' Enable the multi-cycle divider. Stalls the pipe until the result
is ready after 32 cycles. If disabled, the divide operation is not supported.',
'default' => 'MULTI_CYCLE',
'global_param' => 'Don\'t include',
'content' => 'MULTI_CYCLE,NONE',
'type' => 'Combo-box',
'redefine_param' => 1
},
'MULTIPLIER_TYPE' => {
'info' => '// Multiplier
The multiplier is available either in a multi-cycle version or
in a pipelined one. The multi-cycle multiplier stalls the pipe
for 32 cycles. If both options are disabled, multiply operations
are not supported.',
'default' => 'PIPE_LINE',
'global_param' => 'Don\'t include',
'content' => 'MULTI_CYCLE,PIPE_LINE,NONE',
'type' => 'Combo-box',
'redefine_param' => 1
},
'DATA_CACHE' => {
'redefine_param' => 1,
'type' => 'Combo-box',
'global_param' => 'Don\'t include',
'content' => 'ENABLED,DISABLED',
'default' => 'ENABLED',
'info' => 'Enable/Disable the data cache'
},
'DCACHE_SETS' => {
'info' => ' Number of sets',
'default' => '256',
'global_param' => 'Don\'t include',
'content' => '128,256,512,1024,2048,4096,8119,16384',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'ICACHE_ASSOCIATIVITY' => {
'info' => 'Istruction cache assocativity number ',
'default' => '1',
'global_param' => 'Don\'t include',
'content' => '1,2,4,8',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'ICACHE_SETS' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Don\'t include',
'content' => '128,256,512,1024,2048,4096,8119,16384',
'default' => '256',
'info' => ' Number of sets'
}
},
'system_h' => '#include "lm32/lm32_system.h"
static inline void nop (void) {
asm volatile ("nop");
}',
'sockets' => {
'interrupt_peripheral' => {
'connection_num' => 'single connection',
'type' => 'param',
'interrupt_peripheral' => {},
'0' => {
'name' => 'interrupt_peripheral'
},
'value' => 'INTR_NUM'
}
},
'file_name' => 'mpsoc/src_processor/lm32/verilog/src/lm32.v'
}, 'ip_gen' );
/lm32_new.IP
0,0 → 1,442
#######################################################################
## File: lm32_new.IP
##
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$ipgen = bless( {
'parameters_order' => [
'INTR_NUM',
'BARREL_SHIFT',
'SIGN_EXTEND',
'BARREL_SHIFT',
'MULTIPLIER_TYPE',
'DIVIDOR_TYPE',
'INSTRUCTION_CACHE',
'ICACHE_ASSOCIATIVITY',
'ICACHE_SETS',
'DATA_CACHE',
'DCACHE_ASSOCIATIVITY',
'DCACHE_SETS'
],
'sw_files' => [
'/mpsoc/src_processor/lm32/sw/lm32',
'/mpsoc/src_processor/lm32/sw/linker.ld',
'/mpsoc/src_processor/lm32/sw/Makefile'
],
'version' => 17,
'system_h' => '#include "lm32/lm32_system.h"
static inline void nop (void) {
asm volatile ("nop");
}',
'sockets' => {
'interrupt_peripheral' => {
'interrupt_peripheral' => {},
'value' => 'INTR_NUM',
'type' => 'param',
'connection_num' => 'single connection',
'0' => {
'name' => 'interrupt_peripheral'
}
}
},
'hdl_files' => [
'/mpsoc/src_processor/new_lm32/rtl/lm32_top.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_shifter.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_ram.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_multiplier.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_mc_arithmetic.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_logic_op.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_load_store_unit.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_jtag.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_itlb.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_interrupt.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_instruction_unit.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_include.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_icache.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_dtlb.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_dp_ram.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_decoder.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_debug.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_dcache.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_cpu.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_addsub.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32_adder.v',
'/mpsoc/src_processor/new_lm32/rtl/lm32.v',
'/mpsoc/src_processor/new_lm32/rtl/jtag_tap_spartan6.v',
'/mpsoc/src_processor/new_lm32/rtl/jtag_cores.v'
],
'file_name' => 'mpsoc/src_processor/lm32/verilog/src/lm32.v',
'module_name' => 'lm32',
'ip_name' => 'lm32_new',
'parameters' => {
'INTR_NUM' => {
'type' => 'Fixed',
'redefine_param' => 1,
'default' => '32',
'content' => '',
'info' => undef,
'global_param' => 'Localparam'
},
'DIVIDOR_TYPE' => {
'global_param' => 'Don\'t include',
'info' => ' Enable the multi-cycle divider. Stalls the pipe until the result
is ready after 32 cycles. If disabled, the divide operation is not supported.',
'content' => 'MULTI_CYCLE,NONE',
'default' => 'MULTI_CYCLE',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'BARREL_SHIFT' => {
'default' => 'PIPE_LINE',
'global_param' => 'Don\'t include',
'info' => 'Shifter
You may either enable the piplined or the multi-cycle barrel
shifter. The multi-cycle shifter will stall the pipeline until
the result is available after 32 cycles.
If both options are disabled, only "right shift by one bit" is
available.',
'content' => 'MULTI_CYCLE,PIPE_LINE,NONE',
'type' => 'Combo-box',
'redefine_param' => 1
},
'DCACHE_SETS' => {
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '128,256,512,1024,2048,4096,8119,16384',
'info' => ' Number of sets',
'global_param' => 'Don\'t include',
'default' => '256'
},
'DCACHE_ASSOCIATIVITY' => {
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '1,2,4,8',
'global_param' => 'Don\'t include',
'info' => 'Data cache assocativity number ',
'default' => '1'
},
'INSTRUCTION_CACHE' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'default' => 'ENABLED',
'global_param' => 'Don\'t include',
'info' => 'Enable/Disable Instruction cache',
'content' => 'ENABLED,DISABLED'
},
'DATA_CACHE' => {
'content' => 'ENABLED,DISABLED',
'global_param' => 'Don\'t include',
'info' => 'Enable/Disable the data cache',
'default' => 'ENABLED',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'ICACHE_ASSOCIATIVITY' => {
'redefine_param' => 1,
'type' => 'Combo-box',
'global_param' => 'Don\'t include',
'content' => '1,2,4,8',
'info' => 'Istruction cache assocativity number ',
'default' => '1'
},
'ICACHE_SETS' => {
'default' => '256',
'info' => ' Number of sets',
'global_param' => 'Don\'t include',
'content' => '128,256,512,1024,2048,4096,8119,16384',
'type' => 'Combo-box',
'redefine_param' => 1
},
'MULTIPLIER_TYPE' => {
'content' => 'MULTI_CYCLE,PIPE_LINE,NONE',
'global_param' => 'Don\'t include',
'info' => '// Multiplier
The multiplier is available either in a multi-cycle version or
in a pipelined one. The multi-cycle multiplier stalls the pipe
for 32 cycles. If both options are disabled, multiply operations
are not supported.',
'default' => 'PIPE_LINE',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'SIGN_EXTEND' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'default' => 'ENABLED',
'global_param' => 'Don\'t include',
'content' => 'ENABLED,DISABLED',
'info' => 'Enable sign-extension instructions'
}
},
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'modules' => {
'lm32' => {}
},
'ports' => {
'I_ERR_I' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'err_i'
},
'D_ERR_I' => {
'intfc_port' => 'err_i',
'intfc_name' => 'plug:wb_master[1]',
'range' => '',
'type' => 'input'
},
'I_CTI_O' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'range' => '(3-1):0',
'intfc_port' => 'cti_o'
},
'D_SEL_O' => {
'intfc_port' => 'sel_o',
'range' => '(4-1):0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
},
'I_SEL_O' => {
'range' => '(4-1):0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'sel_o'
},
'en_i' => {
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'intfc_port' => 'enable_i'
},
'interrupt' => {
'type' => 'input',
'range' => '(32-1):0',
'intfc_name' => 'socket:interrupt_peripheral[array]',
'intfc_port' => 'int_i'
},
'I_DAT_O' => {
'type' => 'output',
'range' => '(32-1):0',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'dat_o'
},
'D_ADR_O' => {
'intfc_port' => 'adr_o',
'range' => '(32-1):0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
},
'I_BTE_O' => {
'type' => 'output',
'range' => '(2-1):0',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'bte_o'
},
'D_STB_O' => {
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'stb_o'
},
'I_ACK_I' => {
'intfc_port' => 'ack_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
'I_DAT_I' => {
'intfc_port' => 'dat_i',
'type' => 'input',
'range' => '(32-1):0',
'intfc_name' => 'plug:wb_master[0]'
},
'D_CYC_O' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'range' => '',
'intfc_port' => 'cyc_o'
},
'clk_i' => {
'intfc_port' => 'clk_i',
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:clk[0]'
},
'I_ADR_O' => {
'intfc_port' => 'adr_o',
'type' => 'output',
'range' => '(32-1):0',
'intfc_name' => 'plug:wb_master[0]'
},
'rst_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
},
'D_DAT_O' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '(32-1):0',
'type' => 'output',
'intfc_port' => 'dat_o'
},
'I_STB_O' => {
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'stb_o'
},
'D_RTY_I' => {
'intfc_port' => 'rty_i',
'intfc_name' => 'plug:wb_master[1]',
'range' => '',
'type' => 'input'
},
'I_RTY_I' => {
'intfc_port' => 'rty_i',
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'input'
},
'I_CYC_O' => {
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'cyc_o'
},
'D_CTI_O' => {
'intfc_port' => 'cti_o',
'range' => '(3-1):0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output'
},
'D_ACK_I' => {
'intfc_port' => 'ack_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'I_WE_O' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'we_o'
},
'D_DAT_I' => {
'intfc_port' => 'dat_i',
'type' => 'input',
'range' => '(32-1):0',
'intfc_name' => 'plug:wb_master[1]'
},
'D_BTE_O' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '(2-1):0',
'type' => 'output',
'intfc_port' => 'bte_o'
},
'D_WE_O' => {
'intfc_port' => 'we_o',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'range' => ''
}
},
'unused' => {
'plug:wb_master[1]' => [
'tag_o'
],
'plug:wb_master[0]' => [
'tag_o'
]
},
'category' => 'Processor',
'gen_sw_files' => [
'/mpsoc/src_processor/new_lm32/sw/cpu_flags_genfrename_sep_tcpu_flags'
],
'description' => 'A fork of the original LatticeMico32 sources that includes new features. The source code is adopted from:
https://github.com/m-labs/lm32',
'plugs' => {
'enable' => {
'enable' => {},
'type' => 'num',
'0' => {
'name' => 'enable'
},
'value' => 1
},
'clk' => {
'0' => {
'name' => 'clk'
},
'type' => 'num',
'value' => 1,
'clk' => {}
},
'wb_master' => {
'value' => 2,
'type' => 'num',
'0' => {
'name' => 'iwb'
},
'1' => {
'name' => 'dwb'
},
'wb_master' => {}
},
'reset' => {
'type' => 'num',
'0' => {
'name' => 'reset'
},
'value' => 1,
'1' => {
'name' => 'reset_1'
},
'reset' => {}
}
},
'gen_hw_files' => [
'/mpsoc/src_processor/new_lm32/config/lm32_config_gen.vfrename_sep_tlib/lm32_config.v'
],
'system_c' => '#include "lm32/lm32_system.c"',
'ports_order' => [
'clk_i',
'rst_i',
'en_i',
'interrupt',
'I_DAT_I',
'I_ACK_I',
'I_ERR_I',
'I_RTY_I',
'I_DAT_O',
'I_ADR_O',
'I_CYC_O',
'I_SEL_O',
'I_STB_O',
'I_WE_O',
'I_CTI_O',
'I_BTE_O',
'D_DAT_I',
'D_ACK_I',
'D_ERR_I',
'D_RTY_I',
'D_DAT_O',
'D_ADR_O',
'D_CYC_O',
'D_SEL_O',
'D_STB_O',
'D_WE_O',
'D_CTI_O',
'D_BTE_O'
]
}, 'ip_gen' );
/mor1kx.IP
1,65 → 1,15
#######################################################################
## File: mor1kx.IP
##
## Copyright (C) 2014-2016 Alireza Monemi
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.8.1
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
## MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
 
$ipgen = bless( {
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'modules' => {
'mor1k' => {}
},
'hdl_files' => [
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_branch_prediction.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_avalon.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_wb32.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cache_lru.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cfgrs.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dcache.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode_execute_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-defines.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dmmu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_alu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_icache.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_immu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_pic.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_simple_dpram_sclk.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-sprs.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_store_buffer.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ticktimer.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_true_dpram_sclk.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_utils.vh',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v'
],
'module_name' => 'mor1k',
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM',
67,135 → 17,123
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU'
'FEATURE_DMMU',
'FEATURE_MULTIPLIER',
'FEATURE_DIVIDER',
'OPTION_SHIFTER'
],
'sw_files' => [
'/mpsoc/src_processor/mor1kx-3.1/sw/link.ld',
'/mpsoc/src_processor/mor1kx-3.1/sw/Makefile',
'/mpsoc/src_processor/mor1kx-3.1/sw/mor1kx',
'/mpsoc/src_processor/src_lib/simple-printf',
'/mpsoc/src_processor/mor1kx-3.1/sw/define_printf.h'
],
'version' => 17,
'sockets' => {
'interrupt_peripheral' => {
'type' => 'param',
'value' => 'IRQ_NUM',
'0' => {
'name' => 'interrupt_peripheral'
},
'connection_num' => 'single connection'
}
},
'ip_name' => 'mor1kx',
'category' => 'Processor',
'file_name' => '/home/alireza/mywork/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v',
'unused' => {
'plug:wb_master[1]' => [
'tag_o'
],
'plug:wb_master[0]' => [
'tag_o'
]
},
'parameters' => {
'FEATURE_IMMU' => {
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => ''
},
'OPTION_OPERAND_WIDTH' => {
'info' => 'Parameter',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'default' => '32',
'content' => '',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter'
'global_param' => 'Localparam'
},
'FEATURE_DMMU' => {
'info' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"',
'content' => '"NONE","ENABLED"'
},
'FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => '',
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'type' => 'Combo-box'
'redefine_param' => 1,
'info' => ''
},
'OPTION_DCACHE_SNOOP' => {
'info' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'default' => '"NONE"',
'type' => 'Combo-box',
'content' => '"NONE","ENABLED"'
'redefine_param' => 1
},
'FEATURE_DMMU' => {
'type' => 'Combo-box',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'redefine_param' => 1,
'info' => ''
},
'FEATURE_DATACACHE' => {
'info' => '',
'type' => 'Combo-box',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => ''
'redefine_param' => 1
},
'OPTION_SHIFTER' => {
'info' => 'Specify the shifter implementation',
'redefine_param' => 1,
'default' => '"BARREL"',
'content' => '"BARREL","SERIAL"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'IRQ_NUM' => {
'info' => undef,
'default' => '32',
'content' => '',
'type' => 'Fixed',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => undef
}
'global_param' => 'Localparam',
'redefine_param' => 1
},
'FEATURE_DIVIDER' => {
'info' => 'Specify the divider implementation',
'redefine_param' => 1,
'default' => '"SERIAL"',
'content' => '"SERIAL","NONE"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'FEATURE_MULTIPLIER' => {
'default' => '"THREESTAGE"',
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Specify the multiplier implementation'
},
'FEATURE_IMMU' => {
'info' => '',
'default' => '"ENABLED"',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1
}
},
'plugs' => {
'reset' => {
'0' => {
'name' => 'reset'
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'0' => {
'name' => 'clk'
},
'value' => 1,
'type' => 'num'
},
'enable' => {
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'enable'
}
},
'wb_master' => {
'1' => {
'name' => 'dwb'
},
'0' => {
'name' => 'iwb'
},
'value' => 2,
'type' => 'num'
},
'snoop' => {
'type' => 'num',
'0' => {
'name' => 'snoop'
},
'value' => 1
}
},
'gen_sw_files' => [
'/mpsoc/src_processor/mor1kx-3.1/sw/march_flags.makfrename_sep_tmarch_flags.mak'
],
'module_name' => 'mor1k',
'sw_files' => [
'/mpsoc/src_processor/mor1kx-3.1/sw/link.ld',
'/mpsoc/src_processor/mor1kx-3.1/sw/Makefile',
'/mpsoc/src_processor/mor1kx-3.1/sw/mor1kx'
],
'system_c' => '',
'unused' => {
'plug:wb_master[1]' => [
'tag_o'
],
'plug:wb_master[0]' => [
'tag_o'
]
},
'sockets' => {
'interrupt_peripheral' => {
'value' => 'IRQ_NUM',
'0' => {
'name' => 'interrupt_peripheral'
},
'type' => 'param',
'connection_num' => 'single connection'
}
},
'file_name' => 'mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v',
'ports_order' => [
'clk',
'rst',
228,9 → 166,50
'dwbm_rty_i',
'irq_i'
],
'plugs' => {
'snoop' => {
'type' => 'num',
'0' => {
'name' => 'snoop'
},
'value' => 1
},
'clk' => {
'type' => 'num',
'0' => {
'name' => 'clk'
},
'value' => 1
},
'wb_master' => {
'0' => {
'name' => 'iwb'
},
'value' => 2,
'type' => 'num',
'1' => {
'name' => 'dwb'
}
},
'enable' => {
'value' => 1,
'0' => {
'name' => 'enable'
},
'type' => 'num'
},
'reset' => {
'0' => {
'name' => 'reset'
},
'value' => 1,
'type' => 'num'
}
},
'version' => 26,
'system_h' => ' #include "mor1kx/system.h"
 
inline void nop (){
static inline void nop (){
__asm__("l.nop 1");
}
/*********************
259,186 → 238,236
}
}
*******************************/',
'category' => 'Processor',
'hdl_files' => [
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_branch_prediction.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_avalon.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_wb32.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cache_lru.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cfgrs.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dcache.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode_execute_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-defines.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dmmu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_alu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_icache.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_immu.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_pic.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_simple_dpram_sclk.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-sprs.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_store_buffer.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ticktimer.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_true_dpram_sclk.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_utils.vh',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_cappuccino.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_espresso.v',
'/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v'
],
'ports' => {
'iwbm_stb_o' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'stb_o',
'dwbm_ack_i' => {
'intfc_port' => 'ack_i',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input',
'range' => ''
},
'dwbm_sel_o' => {
'intfc_port' => 'sel_o',
'type' => 'output',
'range' => '3:0',
'dwbm_dat_i' => {
'range' => '31:0',
'type' => 'input',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_master[1]'
},
'iwbm_sel_o' => {
'iwbm_rty_i' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'rty_i',
'intfc_name' => 'plug:wb_master[0]'
},
'iwbm_cyc_o' => {
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'sel_o',
'type' => 'output',
'range' => '3:0'
'intfc_port' => 'cyc_o'
},
'dwbm_stb_o' => {
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'stb_o'
},
'rst' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]'
},
'iwbm_stb_o' => {
'type' => 'output',
'range' => '',
'intfc_port' => 'stb_o',
'type' => 'output'
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'stb_o'
},
'iwbm_adr_o' => {
'intfc_name' => 'plug:wb_master[0]',
'dwbm_adr_o' => {
'type' => 'output',
'range' => '31:0',
'intfc_port' => 'adr_o',
'type' => 'output'
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'adr_o'
},
'iwbm_err_i' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'err_i',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
'dwbm_cyc_o' => {
'dwbm_rty_i' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'range' => '',
'intfc_port' => 'cyc_o'
'intfc_port' => 'rty_i'
},
'clk' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]'
},
'dwbm_err_i' => {
'dwbm_dat_o' => {
'range' => '31:0',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'dat_o'
},
'iwbm_sel_o' => {
'intfc_port' => 'sel_o',
'intfc_name' => 'plug:wb_master[0]',
'range' => '3:0',
'type' => 'output'
},
'dwbm_cyc_o' => {
'range' => '',
'intfc_port' => 'err_i',
'type' => 'input',
'type' => 'output',
'intfc_port' => 'cyc_o',
'intfc_name' => 'plug:wb_master[1]'
},
'iwbm_rty_i' => {
'dwbm_cti_o' => {
'intfc_port' => 'cti_o',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'range' => '2:0'
},
'iwbm_dat_i' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'dat_i',
'type' => 'input',
'intfc_port' => 'rty_i',
'range' => '31:0'
},
'dwbm_err_i' => {
'intfc_port' => 'err_i',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'input',
'range' => ''
},
'dwbm_dat_o' => {
'type' => 'output',
'intfc_port' => 'dat_o',
'range' => '31:0',
'intfc_name' => 'plug:wb_master[1]'
},
'cpu_en' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'intfc_port' => 'enable_i',
'range' => ''
},
'iwbm_bte_o' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'bte_o',
'range' => '1:0'
},
'iwbm_ack_i' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '',
'intfc_port' => 'ack_i',
'type' => 'input'
},
'dwbm_rty_i' => {
'type' => 'input',
'intfc_port' => 'rty_i',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'dwbm_ack_i' => {
'type' => 'input',
'intfc_port' => 'ack_i',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'snoop_en_i' => {
'intfc_name' => 'plug:snoop[0]',
'intfc_port' => 'snoop_en_i',
'range' => '',
'type' => 'input'
},
'dwbm_adr_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '31:0',
'intfc_port' => 'adr_o',
'type' => 'output'
},
'iwbm_cyc_o' => {
'intfc_port' => 'cyc_o',
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
},
'dwbm_bte_o' => {
'intfc_name' => 'plug:wb_master[1]',
'range' => '1:0',
'iwbm_cti_o' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'cti_o',
'type' => 'output',
'intfc_port' => 'bte_o'
'range' => '2:0'
},
'dwbm_dat_i' => {
'range' => '31:0',
'type' => 'input',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_master[1]'
},
'irq_i' => {
'intfc_name' => 'socket:interrupt_peripheral[array]',
'type' => 'input',
'intfc_port' => 'int_i',
'range' => '31:0'
'range' => '31:0',
'type' => 'input'
},
'iwbm_we_o' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'we_o',
'range' => '',
'type' => 'output'
},
'iwbm_adr_o' => {
'type' => 'output',
'range' => '31:0',
'intfc_port' => 'adr_o',
'intfc_name' => 'plug:wb_master[0]'
},
'snoop_adr_i' => {
'intfc_port' => 'snoop_adr_i',
'intfc_name' => 'plug:snoop[0]',
'intfc_port' => 'snoop_adr_i',
'range' => '31:0',
'type' => 'input'
'type' => 'input',
'range' => '31:0'
},
'dwbm_cti_o' => {
'intfc_port' => 'cti_o',
'range' => '2:0',
'snoop_en_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:snoop[0]',
'intfc_port' => 'snoop_en_i'
},
'dwbm_sel_o' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'sel_o',
'range' => '3:0',
'type' => 'output'
},
'dwbm_bte_o' => {
'intfc_port' => 'bte_o',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
'range' => '1:0'
},
'dwbm_we_o' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'we_o',
'type' => 'output',
'range' => ''
},
'iwbm_dat_o' => {
'intfc_name' => 'plug:wb_master[0]',
'range' => '31:0',
'type' => 'output',
'intfc_port' => 'dat_o',
'type' => 'output'
},
'iwbm_dat_i' => {
'type' => 'input',
'intfc_port' => 'dat_i',
'range' => '31:0',
'intfc_name' => 'plug:wb_master[0]'
},
'iwbm_we_o' => {
'intfc_port' => 'we_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_master[0]'
},
'iwbm_cti_o' => {
'iwbm_bte_o' => {
'intfc_port' => 'bte_o',
'intfc_name' => 'plug:wb_master[0]',
'range' => '2:0',
'intfc_port' => 'cti_o',
'range' => '1:0',
'type' => 'output'
},
'dwbm_we_o' => {
'intfc_port' => 'we_o',
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_master[1]'
},
'rst' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
}
}
}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'modules' => {
'mor1k' => {}
}
}, 'ip_gen' );
/mor1kx5.IP
0,0 → 1,493
#######################################################################
## File: mor1kx5.IP
##
## Copyright (C) 2014-2019 Alireza Monemi
##
## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
 
$ipgen = bless( {
'version' => 29,
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM',
'OPTION_DCACHE_SNOOP',
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU',
'FEATURE_MULTIPLIER',
'FEATURE_DIVIDER',
'OPTION_SHIFTER',
'FEATURE_FPU'
],
'modules' => {
'mor1k' => {}
},
'module_name' => 'mor1k',
'parameters' => {
'FEATURE_IMMU' => {
'default' => '"ENABLED"',
'redefine_param' => 1,
'type' => 'Combo-box',
'info' => '',
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"'
},
'FEATURE_FPU' => {
'content' => '"ENABLED","NONE"',
'global_param' => 'Localparam',
'info' => 'Enable the FPU, for cappuccino pipeline only',
'type' => 'Combo-box',
'redefine_param' => 1,
'default' => '"NONE"'
},
'OPTION_SHIFTER' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'default' => '"BARREL"',
'global_param' => 'Localparam',
'content' => '"BARREL","SERIAL"',
'info' => 'Specify the shifter implementation'
},
'FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'info' => '',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"'
},
'OPTION_OPERAND_WIDTH' => {
'info' => 'Parameter',
'global_param' => 'Localparam',
'content' => '',
'default' => '32',
'redefine_param' => 1,
'type' => 'Fixed'
},
'FEATURE_INSTRUCTIONCACHE' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'redefine_param' => 1
},
'FEATURE_DIVIDER' => {
'default' => '"SERIAL"',
'redefine_param' => 1,
'type' => 'Combo-box',
'info' => 'Specify the divider implementation',
'content' => '"SERIAL","NONE"',
'global_param' => 'Localparam'
},
'IRQ_NUM' => {
'type' => 'Fixed',
'redefine_param' => 1,
'default' => '32',
'global_param' => 'Localparam',
'content' => '',
'info' => undef
},
'OPTION_DCACHE_SNOOP' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'default' => '"ENABLED"',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'info' => ''
},
'FEATURE_MULTIPLIER' => {
'global_param' => 'Localparam',
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'info' => 'Specify the multiplier implementation',
'type' => 'Combo-box',
'redefine_param' => 1,
'default' => '"THREESTAGE"'
},
'FEATURE_DMMU' => {
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'info' => '',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"'
}
},
'ip_name' => 'mor1kx5',
'unused' => {
'plug:wb_master[1]' => [
'tag_o'
],
'plug:wb_master[0]' => [
'tag_o'
]
},
'category' => 'Processor',
'file_name' => 'mpsoc/src_processor/mor1kx-5.0/rtl/mor1k.v',
'ports' => {
'snoop_en_i' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'snoop_en_i',
'intfc_name' => 'plug:snoop[0]'
},
'iwbm_stb_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'stb_o',
'range' => ''
},
'dwbm_dat_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'dat_o',
'range' => '31:0'
},
'iwbm_ack_i' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'ack_i',
'type' => 'input',
'range' => ''
},
'iwbm_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'range' => '31:0'
},
'dwbm_rty_i' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'rty_i'
},
'cpu_en' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i'
},
'snoop_adr_i' => {
'intfc_name' => 'plug:snoop[0]',
'type' => 'input',
'intfc_port' => 'snoop_adr_i',
'range' => '31:0'
},
'irq_i' => {
'range' => '31:0',
'intfc_port' => 'int_i',
'type' => 'input',
'intfc_name' => 'socket:interrupt_peripheral[array]'
},
'dwbm_sel_o' => {
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_port' => 'sel_o',
'range' => '3:0'
},
'iwbm_dat_i' => {
'intfc_port' => 'dat_i',
'type' => 'input',
'intfc_name' => 'plug:wb_master[0]',
'range' => '31:0'
},
'dwbm_dat_i' => {
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'dat_i',
'type' => 'input',
'range' => '31:0'
},
'dwbm_bte_o' => {
'range' => '1:0',
'intfc_port' => 'bte_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
},
'dwbm_err_i' => {
'range' => '',
'intfc_port' => 'err_i',
'type' => 'input',
'intfc_name' => 'plug:wb_master[1]'
},
'iwbm_err_i' => {
'type' => 'input',
'intfc_port' => 'err_i',
'intfc_name' => 'plug:wb_master[0]',
'range' => ''
},
'iwbm_sel_o' => {
'intfc_port' => 'sel_o',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'range' => '3:0'
},
'dwbm_we_o' => {
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_port' => 'we_o',
'range' => ''
},
'dwbm_cyc_o' => {
'type' => 'output',
'intfc_port' => 'cyc_o',
'intfc_name' => 'plug:wb_master[1]',
'range' => ''
},
'dwbm_ack_i' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:wb_master[1]',
'intfc_port' => 'ack_i'
},
'iwbm_cyc_o' => {
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'cyc_o'
},
'dwbm_stb_o' => {
'type' => 'output',
'intfc_port' => 'stb_o',
'intfc_name' => 'plug:wb_master[1]',
'range' => ''
},
'iwbm_adr_o' => {
'intfc_port' => 'adr_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'range' => '31:0'
},
'dwbm_cti_o' => {
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_port' => 'cti_o',
'range' => '2:0'
},
'rst' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]'
},
'clk' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'iwbm_cti_o' => {
'range' => '2:0',
'intfc_port' => 'cti_o',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output'
},
'dwbm_adr_o' => {
'range' => '31:0',
'intfc_port' => 'adr_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
},
'iwbm_bte_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'bte_o',
'range' => '1:0'
},
'iwbm_we_o' => {
'range' => '',
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'we_o'
},
'iwbm_rty_i' => {
'range' => '',
'intfc_port' => 'rty_i',
'type' => 'input',
'intfc_name' => 'plug:wb_master[0]'
}
},
'ports_order' => [
'clk',
'rst',
'cpu_en',
'snoop_adr_i',
'snoop_en_i',
'iwbm_adr_o',
'iwbm_stb_o',
'iwbm_cyc_o',
'iwbm_sel_o',
'iwbm_we_o',
'iwbm_cti_o',
'iwbm_bte_o',
'iwbm_dat_o',
'iwbm_err_i',
'iwbm_ack_i',
'iwbm_dat_i',
'iwbm_rty_i',
'dwbm_adr_o',
'dwbm_stb_o',
'dwbm_cyc_o',
'dwbm_sel_o',
'dwbm_we_o',
'dwbm_cti_o',
'dwbm_bte_o',
'dwbm_dat_o',
'dwbm_err_i',
'dwbm_ack_i',
'dwbm_dat_i',
'dwbm_rty_i',
'irq_i'
],
'hdl_files' => [
'/mpsoc/src_processor/mor1kx-5.0/rtl/mor1k.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_wb_mux_espresso.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_wb_mux_cappuccino.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_utils.vh',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_true_dpram_sclk.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_ticktimer.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_store_buffer.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx-sprs.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_simple_dpram_sclk.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_rf_espresso.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_rf_cappuccino.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_pic.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_pcu.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_lsu_espresso.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_lsu_cappuccino.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_immu.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_icache.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_fetch_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_fetch_espresso.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_fetch_cappuccino.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_execute_alu.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_dmmu.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx-defines.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_decode_execute_cappuccino.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_decode.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_dcache.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_ctrl_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_ctrl_espresso.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_ctrl_cappuccino.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cpu_prontoespresso.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cpu_espresso.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cpu_cappuccino.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cpu.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cfgrs.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cache_lru.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_bus_if_wb32.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_branch_predictor_simple.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_branch_predictor_gshare.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_branch_prediction.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_top.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_rnd.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_muldiv.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_i2f.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_f2i.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_cmp.v',
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_addsub.v'
],
'sockets' => {
'interrupt_peripheral' => {
'connection_num' => 'single connection',
'value' => 'IRQ_NUM',
'0' => {
'name' => 'interrupt_peripheral'
},
'type' => 'param'
}
},
'hdl_files_ticked' => [],
'plugs' => {
'wb_master' => {
'value' => 2,
'1' => {
'name' => 'dwb'
},
'0' => {
'name' => 'iwb'
},
'type' => 'num'
},
'enable' => {
'value' => 1,
'0' => {
'name' => 'enable'
},
'type' => 'num'
},
'snoop' => {
'0' => {
'name' => 'snoop'
},
'type' => 'num',
'value' => 1
},
'reset' => {
'type' => 'num',
'0' => {
'name' => 'reset'
},
'value' => 1
},
'clk' => {
'type' => 'num',
'0' => {
'name' => 'clk'
},
'value' => 1
}
},
'system_c' => '',
'system_h' => ' #include "mor1kx/system.h"
 
static inline void nop (){
__asm__("l.nop 1");
}
/*********************
//Interrupt template: check mor1kx/int.c for more information
// interrupt function
void hw_isr(void){
//place your interrupt code here
 
 
HW_ISR=HW_ISR; //ack the interrupt at the end of isr function
return;
}
 
int main(){
int_init();
//assume hw interrupt pin is connected to 10th cpu intrrupt pin
int_add(10, hw_isr, 0);
// Enable this interrupt
int_enable(10);
cpu_enable_user_interrupts();
hw_init ( ); // hw interrupt enable function
while(1){
//place rest of the code
 
}
}
*******************************/',
'sw_files' => [
'/mpsoc/src_processor/mor1kx-5.0/sw/link.ld',
'/mpsoc/src_processor/mor1kx-5.0/sw/Makefile',
'/mpsoc/src_processor/mor1kx-5.0/sw/mor1kx'
],
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'gen_sw_files' => [
'/mpsoc/src_processor/mor1kx-5.0/sw/march_flags.makfrename_sep_tmarch_flags.mak'
]
}, 'ip_gen' );

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