OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/RAM
    from Rev 25 to Rev 28
    ↔ Reverse comparison
  •

Rev 25 → Rev 28

/dual_port_ram.IP
24,32 → 24,32
'deafult' => 'Dw/8',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1
},
'PORT_B_BURST_MODE' => {
'info' => 'wisbone bus burst mode ebable/disable on port B',
'deafult' => '"DISABLED"',
'global_param' => 'Don\'t include',
'content' => '"DISABLED","ENABLED" ',
'redefine_param' => 1,
'type' => 'Fixed'
},
'Dw' => {
'info' => 'Ram data width in Bits',
'deafult' => '32',
'global_param' => 'Localparam',
'content' => '4,1024,1',
'type' => 'Spin-button',
'redefine_param' => 1
'redefine_param' => 1,
'type' => 'Spin-button'
},
'PORT_B_BURST_MODE' => {
'info' => 'wisbone bus burst mode ebable/disable on port B',
'deafult' => '"DISABLED"',
'global_param' => 'Don\'t include',
'content' => '"DISABLED","ENABLED" ',
'type' => 'Combo-box',
'redefine_param' => 1
},
'BTEw' => {
'info' => 'Parameter',
'deafult' => '2',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1
},
'WB_Aw' => {
'info' => 'Wishbone bus address width in byte',
56,8 → 56,8
'deafult' => 'Aw+2',
'global_param' => 'Don\'t include',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 0
'redefine_param' => 0,
'type' => 'Fixed'
},
'RAM_INDEX' => {
'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only.
66,8 → 66,8
'deafult' => 'CORE_ID',
'global_param' => 'Localparam',
'content' => '',
'type' => 'Entry',
'redefine_param' => 1
'redefine_param' => 1,
'type' => 'Entry'
},
'Aw' => {
'info' => 'Ram address width',
74,8 → 74,8
'deafult' => '12',
'global_param' => 'Localparam',
'content' => '2,31,1',
'type' => 'Spin-button',
'redefine_param' => 1
'redefine_param' => 1,
'type' => 'Spin-button'
},
'TAGw' => {
'info' => 'Parameter',
82,32 → 82,32
'deafult' => '3',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1
},
'PORT_A_BURST_MODE' => {
'info' => ' wisbone bus burst mode enable/disable on port A',
'deafult' => '"DISABLED"',
'global_param' => 'Localparam',
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'BYTE_WR_EN' => {
'info' => 'Parameter',
'deafult' => '"YES"',
'global_param' => 'Localparam',
'content' => '"YES","NO"',
'type' => 'Combo-box',
'redefine_param' => 1
'redefine_param' => 1,
'type' => 'Combo-box'
},
'PORT_A_BURST_MODE' => {
'info' => ' wisbone bus burst mode enable/disable on port A',
'deafult' => '"DISABLED"',
'global_param' => 'Localparam',
'content' => '"DISABLED","ENABLED"',
'type' => 'Combo-box',
'redefine_param' => 1
},
'CTIw' => {
'info' => 'Parameter',
'deafult' => '3',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1
},
'FPGA_VENDOR' => {
'info' => 'Parameter',
114,31 → 114,31
'deafult' => '"ALTERA"',
'global_param' => 'Localparam',
'content' => '"ALTERA","GENERIC"',
'type' => 'Combo-box',
'redefine_param' => 1
'redefine_param' => 1,
'type' => 'Combo-box'
}
},
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
'status' => 'ideal',
'timeout' => 0
},
'plugs' => {
'clk' => {
'clk' => {},
'value' => 1,
'0' => {
'name' => 'clk'
},
'type' => 'num'
},
'reset' => {
'reset' => {},
'value' => 1,
'0' => {
'name' => 'reset'
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'clk' => {},
'0' => {
'name' => 'clk'
},
'value' => 1,
'type' => 'num'
},
'wb_slave' => {
'1' => {
'width' => 'WB_Aw',
145,12 → 145,12
'name' => 'wb_b',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
},
'value' => 2,
'0' => {
'width' => 'WB_Aw',
'name' => 'wb_a',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
},
'value' => 2,
'type' => 'num',
'wb_slave' => {}
}
159,171 → 159,171
'wb_dual_port_ram' => {}
},
'ports' => {
'sb_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sa_tag_i' => {
'intfc_port' => 'tag_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'tag_i',
'range' => 'TAGw-1 : 0',
'type' => 'input'
},
'sb_addr_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'adr_i',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sa_rty_o' => {
'intfc_port' => 'rty_o',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'rty_o',
'range' => '',
'type' => 'output'
},
'sa_cti_i' => {
'sa_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cti_i',
'range' => 'CTIw-1 : 0',
'range' => 'SELw-1 : 0',
'type' => 'input'
},
'sa_sel_i' => {
'sa_cti_i' => {
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'sel_i',
'range' => 'SELw-1 : 0',
'range' => 'CTIw-1 : 0',
'type' => 'input'
},
'sa_bte_i' => {
'intfc_port' => 'bte_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'bte_i',
'range' => 'BTEw-1 : 0',
'type' => 'input'
},
'sa_err_o' => {
'intfc_port' => 'err_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
},
'sa_cyc_i' => {
'intfc_port' => 'cyc_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cyc_i',
'range' => '',
'type' => 'input'
},
'sb_err_o' => {
'intfc_port' => 'err_o',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'err_o',
'range' => '',
'type' => 'output'
},
'sa_err_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'err_o',
'range' => '',
'sb_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'Dw-1 : 0',
'type' => 'output'
},
'sa_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
'range' => '',
'type' => 'output'
},
'reset' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'range' => '',
'type' => 'input'
},
'sb_dat_o' => {
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'sa_ack_o' => {
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
},
'sb_cti_i' => {
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'cti_i',
'range' => 'CTIw-1 : 0',
'type' => 'input'
},
'sb_bte_i' => {
'intfc_port' => 'bte_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'bte_i',
'range' => 'BTEw-1 : 0',
'type' => 'input'
},
'sa_addr_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'adr_i',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sb_ack_o' => {
'sb_cyc_i' => {
'intfc_port' => 'cyc_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'ack_o',
'range' => '',
'type' => 'output'
'type' => 'input'
},
'sb_cyc_i' => {
'sb_ack_o' => {
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'cyc_i',
'range' => '',
'type' => 'input'
'type' => 'output'
},
'sa_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sb_rty_o' => {
'intfc_port' => 'rty_o',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'rty_o',
'range' => '',
'type' => 'output'
},
'sb_dat_i' => {
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'type' => 'input'
},
'sa_dat_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'type' => 'output'
},
'sb_we_i' => {
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'we_i',
'range' => '',
'type' => 'input'
},
'sa_dat_i' => {
'sa_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'type' => 'input'
'type' => 'output'
},
'sb_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'sel_i',
'range' => 'SELw-1 : 0',
'type' => 'input'
},
'sa_dat_i' => {
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Dw-1 : 0',
'type' => 'input'
},
'sa_we_i' => {
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i',
'range' => '',
'type' => 'input'
},
'clk' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'range' => '',
'type' => 'input'
},
'sb_stb_i' => {
'sb_tag_i' => {
'intfc_port' => 'tag_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'stb_i',
'range' => '',
'range' => 'TAGw-1 : 0',
'type' => 'input'
},
'sb_tag_i' => {
'sb_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'tag_i',
'range' => 'TAGw-1 : 0',
'range' => '',
'type' => 'input'
},
'sa_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'stb_i',
'range' => '',
'type' => 'input'
}
/single_port_ram.IP
126,7 → 126,7
},
'JTAG_CONNECT' => {
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb ',
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'deafult' => '"DISABLED"',
'global_param' => 'Localparam',
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"',
141,6 → 141,14
'redefine_param' => 1,
'type' => 'Combo-box'
},
'INIT_FILE_NAME' => {
'info' => 'The name of RAM content memory file (without extention). The file will be used by the JTAG programer to programe the memory at run time.',
'deafult' => '"ram0"',
'global_param' => 'Don\'t include',
'content' => '',
'redefine_param' => 1,
'type' => 'Entry'
},
'CTIw' => {
'info' => 'Parameter',
'deafult' => '3',
170,7 → 178,8
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE'
'BURST_MODE',
'INIT_FILE_NAME'
],
'ports' => {
'sa_tag_i' => {

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.