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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/RAM
    from Rev 34 to Rev 38
    ↔ Reverse comparison
  •

Rev 34 → Rev 38

/dual_port_ram.IP
3,247 → 3,192
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.6.0
## This file is part of ProNoC 1.8.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$wb_dual_port_ram = bless( {
'hdl_files' => [
'/mpsoc/src_peripheral/ram/generic_ram.v',
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',
'/mpsoc/src_peripheral/ram/wb_dual_port_ram.v',
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'
],
'module_name' => 'wb_dual_port_ram',
'category' => 'RAM',
'plugs' => {
'clk' => {
'clk' => {},
'value' => 1,
'type' => 'num',
'0' => {
'name' => 'clk'
}
$ipgen = bless( {
'hdl_files' => [
'/mpsoc/src_peripheral/ram/generic_ram.v',
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',
'/mpsoc/src_peripheral/ram/wb_dual_port_ram.v',
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'
],
'ports_order' => [
'clk',
'reset',
'sa_dat_i',
'sa_sel_i',
'sa_addr_i',
'sa_tag_i',
'sa_cti_i',
'sa_bte_i',
'sa_stb_i',
'sa_cyc_i',
'sa_we_i',
'sa_dat_o',
'sa_ack_o',
'sa_err_o',
'sa_rty_o',
'sb_dat_i',
'sb_sel_i',
'sb_addr_i',
'sb_tag_i',
'sb_cti_i',
'sb_bte_i',
'sb_stb_i',
'sb_cyc_i',
'sb_we_i',
'sb_dat_o',
'sb_ack_o',
'sb_err_o',
'sb_rty_o'
],
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'RAM_INDEX',
'PORT_A_BURST_MODE',
'PORT_B_BURST_MODE',
'INITIAL_EN',
'MEM_CONTENT_FILE_NAME',
'INIT_FILE_PATH'
],
'category' => 'RAM',
'plugs' => {
'reset' => {
'value' => 1,
'0' => {
'name' => 'reset'
},
'reset' => {
'0' => {
'name' => 'reset'
},
'type' => 'num',
'value' => 1,
'reset' => {}
},
'wb_slave' => {
'value' => 2,
'1' => {
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'width' => 'WB_Aw',
'name' => 'wb_b'
},
'type' => 'num',
'wb_slave' => {},
'0' => {
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'width' => 'WB_Aw',
'name' => 'wb_a'
}
}
'type' => 'num',
'reset' => {}
},
'clk' => {
'type' => 'num',
'0' => {
'name' => 'clk'
},
'clk' => {},
'value' => 1
},
'ports' => {
'sb_err_o' => {
'range' => '',
'intfc_port' => 'err_o',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'output'
},
'sa_stb_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'stb_i',
'range' => ''
},
'sb_addr_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input',
'intfc_port' => 'adr_i',
'range' => 'Aw-1 : 0'
},
'sb_rty_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_slave[1]',
'intfc_port' => 'rty_o',
'range' => ''
},
'sb_cyc_i' => {
'intfc_port' => 'cyc_i',
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]'
},
'sa_we_i' => {
'intfc_port' => 'we_i',
'range' => '',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input'
},
'sb_we_i' => {
'intfc_port' => 'we_i',
'range' => '',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input'
},
'sb_dat_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_i'
},
'sa_err_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'intfc_port' => 'err_o'
},
'sb_sel_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'SELw-1 : 0',
'intfc_port' => 'sel_i'
},
'sb_ack_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_slave[1]',
'range' => '',
'intfc_port' => 'ack_o'
},
'sb_cti_i' => {
'intfc_port' => 'cti_i',
'range' => 'CTIw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]'
},
'sb_stb_i' => {
'intfc_port' => 'stb_i',
'range' => '',
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input'
},
'sa_cti_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cti_i',
'range' => 'CTIw-1 : 0'
},
'sb_bte_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'BTEw-1 : 0',
'intfc_port' => 'bte_i'
},
'sa_rty_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output',
'range' => '',
'intfc_port' => 'rty_o'
},
'clk' => {
'intfc_port' => 'clk_i',
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:clk[0]'
'wb_slave' => {
'type' => 'num',
'0' => {
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'width' => 'WB_Aw',
'name' => 'wb_a'
},
'1' => {
'name' => 'wb_b',
'width' => 'WB_Aw',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
},
'wb_slave' => {},
'value' => 2
}
},
'modules' => {
'wb_dual_port_ram' => {}
},
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf',
'version' => 10,
'description' => 'Dual port ram.',
'ip_name' => 'dual_port_ram',
'module_name' => 'wb_dual_port_ram',
'unused' => undef,
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_dual_port_ram.v',
'parameters' => {
'RAM_INDEX' => {
'global_param' => 'Localparam',
'type' => 'Entry',
'content' => '',
'default' => 'CORE_ID',
'redefine_param' => 1,
'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only.
 
'
},
'sa_dat_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_o'
},
'sa_dat_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0'
},
'sa_bte_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'intfc_port' => 'bte_i',
'range' => 'BTEw-1 : 0'
},
'sa_ack_o' => {
'range' => '',
'intfc_port' => 'ack_o',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_sel_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'sel_i',
'range' => 'SELw-1 : 0'
},
'reset' => {
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'range' => '',
'intfc_port' => 'reset_i'
'SELw' => {
'info' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => 'Dw/8',
'global_param' => 'Localparam'
},
'BYTE_WR_EN' => {
'redefine_param' => 1,
'info' => 'Parameter',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'default' => '"YES"',
'global_param' => 'Localparam'
},
'INITIAL_EN' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'If selected as "YES", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'default' => '"NO"',
'content' => '"YES","NO"',
'type' => 'Combo-box'
},
'CTIw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'content' => ''
},
'Dw' => {
'redefine_param' => 1,
'info' => 'Ram data width in Bits',
'type' => 'Spin-button',
'default' => '32',
'content' => '4,1024,1',
'global_param' => 'Localparam'
},
'FPGA_VENDOR' => {
'global_param' => 'Localparam',
'info' => 'Parameter',
'redefine_param' => 1,
'default' => '"GENERIC"',
'type' => 'Combo-box',
'content' => '"ALTERA","GENERIC"'
},
'sa_cyc_i' => {
'range' => '',
'intfc_port' => 'cyc_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
'INIT_FILE_PATH' => {
'global_param' => 'Don\'t include',
'content' => '',
'default' => 'SW_LOC',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => undef
},
'sa_tag_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'tag_i',
'range' => 'TAGw-1 : 0'
},
'sb_dat_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_slave[1]',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_o'
},
'sa_addr_i' => {
'intfc_port' => 'adr_i',
'range' => 'Aw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
},
'sb_tag_i' => {
'intfc_port' => 'tag_i',
'range' => 'TAGw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]'
}
},
'description' => 'Dual port ram.',
'parameters' => {
'WB_Aw' => {
'type' => 'Fixed',
'redefine_param' => 0,
'info' => 'Wishbone bus address width in byte',
'content' => '',
'deafult' => 'Aw+2',
'global_param' => 'Don\'t include'
},
'BTEw' => {
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'deafult' => '2'
},
'MEM_CONTENT_FILE_NAME' => {
'type' => 'Entry',
'redefine_param' => 1,
'content' => '',
'info' => 'MEM_FILE_NAME:
'PORT_A_BURST_MODE' => {
'info' => ' wisbone bus burst mode enable/disable on port A',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"',
'content' => '"DISABLED","ENABLED"',
'global_param' => 'Localparam'
},
'MEM_CONTENT_FILE_NAME' => {
'global_param' => 'Localparam',
'content' => '',
'default' => '"ram0"',
'type' => 'Entry',
'redefine_param' => 1,
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content at initialization time.
 
File Path:
252,165 → 197,221
 
file_type:
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'deafult' => '"ram0"',
'global_param' => 'Localparam'
},
'TAGw' => {
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'deafult' => '3'
},
'CTIw' => {
'redefine_param' => 1,
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'deafult' => '3',
'global_param' => 'Localparam'
},
'INIT_FILE_PATH' => {
'redefine_param' => 1,
'type' => 'Fixed',
'info' => undef,
'content' => '',
'deafult' => 'SW_LOC',
'global_param' => 'Don\'t include'
},
'Aw' => {
'deafult' => '12',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'info' => 'Ram address width',
'content' => '2,31,1'
},
'INITIAL_EN' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'info' => 'If selected as "YES", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'content' => '"YES","NO"',
'deafult' => '"NO"',
'global_param' => 'Localparam'
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . '
},
'RAM_INDEX' => {
'deafult' => 'CORE_ID',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Entry',
'content' => '',
'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only.
 
'
},
'SELw' => {
'deafult' => 'Dw/8',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
},
'Dw' => {
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '4,1024,1',
'info' => 'Ram data width in Bits',
'deafult' => '32',
'global_param' => 'Localparam'
},
'PORT_B_BURST_MODE' => {
'info' => 'wisbone bus burst mode ebable/disable on port B',
'content' => '"DISABLED","ENABLED" ',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'deafult' => '"ENABLED"'
},
'BYTE_WR_EN' => {
'content' => '"YES","NO"',
'info' => 'Parameter',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'deafult' => '"YES"'
},
'PORT_A_BURST_MODE' => {
'deafult' => '"ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '"DISABLED","ENABLED"',
'info' => ' wisbone bus burst mode enable/disable on port A'
},
'FPGA_VENDOR' => {
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '"ALTERA","GENERIC"',
'info' => 'Parameter',
'deafult' => '"GENERIC"',
'global_param' => 'Localparam'
}
'TAGw' => {
'content' => '',
'type' => 'Fixed',
'default' => '3',
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Localparam'
},
'BTEw' => {
'info' => 'Parameter',
'redefine_param' => 1,
'default' => '2',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'Aw' => {
'info' => 'Ram address width',
'redefine_param' => 1,
'default' => '12',
'content' => '2,31,1',
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'PORT_B_BURST_MODE' => {
'redefine_param' => 1,
'info' => 'wisbone bus burst mode ebable/disable on port B',
'type' => 'Combo-box',
'content' => '"DISABLED","ENABLED"',
'default' => '"ENABLED"',
'global_param' => 'Localparam'
},
'WB_Aw' => {
'info' => 'Wishbone bus address width in byte',
'redefine_param' => 0,
'content' => '',
'default' => 'Aw+2',
'type' => 'Fixed',
'global_param' => 'Don\'t include'
}
},
'ports' => {
'reset' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'sb_we_i' => {
'type' => 'input',
'intfc_port' => 'we_i',
'range' => '',
'intfc_name' => 'plug:wb_slave[1]'
},
'sb_err_o' => {
'intfc_port' => 'err_o',
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[1]'
},
'ports_order' => [
'clk',
'reset',
'sa_dat_i',
'sa_sel_i',
'sa_addr_i',
'sa_tag_i',
'sa_cti_i',
'sa_bte_i',
'sa_stb_i',
'sa_cyc_i',
'sa_we_i',
'sa_dat_o',
'sa_ack_o',
'sa_err_o',
'sa_rty_o',
'sb_dat_i',
'sb_sel_i',
'sb_addr_i',
'sb_tag_i',
'sb_cti_i',
'sb_bte_i',
'sb_stb_i',
'sb_cyc_i',
'sb_we_i',
'sb_dat_o',
'sb_ack_o',
'sb_err_o',
'sb_rty_o'
],
'version' => 6,
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
'sa_rty_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output',
'intfc_port' => 'rty_o',
'range' => ''
},
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'RAM_INDEX',
'PORT_A_BURST_MODE',
'PORT_B_BURST_MODE',
'INITIAL_EN',
'MEM_CONTENT_FILE_NAME',
'INIT_FILE_PATH'
],
'unused' => undef,
'ip_name' => 'dual_port_ram',
'modules' => {
'wb_dual_port_ram' => {}
},
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_dual_port_ram.v'
}, 'ip_gen' );
'sa_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
'range' => '',
'type' => 'output'
},
'sa_addr_i' => {
'intfc_port' => 'adr_i',
'range' => 'Aw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
},
'sb_dat_o' => {
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_o',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[1]'
},
'sa_stb_i' => {
'range' => '',
'intfc_port' => 'stb_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_tag_i' => {
'type' => 'input',
'range' => 'TAGw-1 : 0',
'intfc_port' => 'tag_i',
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_dat_i' => {
'type' => 'input',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_we_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => '',
'intfc_port' => 'we_i'
},
'sb_bte_i' => {
'type' => 'input',
'range' => 'BTEw-1 : 0',
'intfc_port' => 'bte_i',
'intfc_name' => 'plug:wb_slave[1]'
},
'sb_addr_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input',
'range' => 'Aw-1 : 0',
'intfc_port' => 'adr_i'
},
'sb_cyc_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input',
'range' => '',
'intfc_port' => 'cyc_i'
},
'sa_sel_i' => {
'type' => 'input',
'range' => 'SELw-1 : 0',
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]'
},
'sb_sel_i' => {
'range' => 'SELw-1 : 0',
'intfc_port' => 'sel_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]'
},
'sb_dat_i' => {
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]'
},
'sb_cti_i' => {
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'input',
'range' => 'CTIw-1 : 0',
'intfc_port' => 'cti_i'
},
'sb_ack_o' => {
'type' => 'output',
'range' => '',
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[1]'
},
'sa_cti_i' => {
'type' => 'input',
'range' => 'CTIw-1 : 0',
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_err_o' => {
'intfc_port' => 'err_o',
'range' => '',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]'
},
'sb_tag_i' => {
'intfc_port' => 'tag_i',
'range' => 'TAGw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[1]'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'range' => '',
'type' => 'input'
},
'sa_dat_o' => {
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]'
},
'sb_stb_i' => {
'type' => 'input',
'intfc_port' => 'stb_i',
'range' => '',
'intfc_name' => 'plug:wb_slave[1]'
},
'sa_bte_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'intfc_port' => 'bte_i',
'range' => 'BTEw-1 : 0'
},
'sa_cyc_i' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'cyc_i',
'intfc_name' => 'plug:wb_slave[0]'
},
'sb_rty_o' => {
'intfc_name' => 'plug:wb_slave[1]',
'type' => 'output',
'intfc_port' => 'rty_o',
'range' => ''
}
},
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
}
}, 'ip_gen' );
/single_port_ram.IP
3,94 → 3,77
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.6.0
## This file is part of ProNoC 1.8.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$wb_single_port_ram = bless( {
'modules' => {
'wb_single_port_ram' => {}
$ipgen = bless( {
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf',
'unused' => undef,
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'modules' => {
'wb_single_port_ram' => {}
},
'parameters' => {
'Aw' => {
'global_param' => 'Parameter',
'info' => 'Memory address width',
'type' => 'Spin-button',
'redefine_param' => 1,
'default' => '12',
'content' => '4,31,1'
},
'module_name' => 'wb_single_port_ram',
'version' => 19,
'category' => 'RAM',
'description' => 'Single port ram with wishbone bus interface.',
'plugs' => {
'reset' => {
'value' => 1,
'reset' => {},
'type' => 'num',
'0' => {
'name' => 'reset'
}
},
'wb_slave' => {
'value' => 1,
'type' => 'num',
'0' => {
'name' => 'wb',
'width' => 'WB_Aw',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
},
'wb_slave' => {}
},
'clk' => {
'type' => 'num',
'0' => {
'name' => 'clk'
},
'value' => 1,
'clk' => {}
}
},
'unused' => undef,
'ip_name' => 'single_port_ram',
'hdl_files' => [
'/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
'/mpsoc/src_peripheral/ram/generic_ram.v',
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'
],
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH'
],
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
'INITIAL_EN' => {
'content' => '"YES","NO"',
'redefine_param' => 1,
'default' => '"NO"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'WB_Aw' => {
'global_param' => 'Don\'t include',
'info' => undef,
'type' => 'Fixed',
'redefine_param' => 1,
'default' => 'Aw+2',
'content' => ''
},
'parameters' => {
'SELw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => '',
'deafult' => 'Dw/8',
'info' => 'Parameter'
},
'MEM_CONTENT_FILE_NAME' => {
'type' => 'Entry',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'MEM_FILE_NAME:
'BYTE_WR_EN' => {
'info' => 'Byte enable',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"YES","NO"',
'default' => '"YES"'
},
'TAGw' => {
'global_param' => 'Localparam',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'default' => '3',
'redefine_param' => 1
},
'FPGA_VENDOR' => {
'content' => '"ALTERA","GENERIC"',
'redefine_param' => 1,
'default' => '"GENERIC"',
'info' => '',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'MEM_CONTENT_FILE_NAME' => {
'default' => '"ram0"',
'content' => '',
'redefine_param' => 1,
'type' => 'Entry',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
101,229 → 84,244
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'deafult' => '"ram0"'
},
'JTAG_CONNECT' => {
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'deafult' => '"DISABLED"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
},
'WB_Aw' => {
'deafult' => 'Aw+2',
'info' => undef,
'global_param' => 'Don\'t include',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => ''
},
'JTAG_INDEX' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'type' => 'Entry',
'deafult' => 'CORE_ID',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
'global_param' => 'Localparam'
},
'Dw' => {
'content' => '8,1024,1',
'redefine_param' => 1,
'default' => '32',
'global_param' => 'Parameter',
'info' => 'Memory data width in Bits.',
'type' => 'Spin-button'
},
'JTAG_INDEX' => {
'content' => '',
'default' => 'CORE_ID',
'redefine_param' => 1,
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
'
},
'Aw' => {
'info' => 'Memory address width',
'deafult' => '12',
'content' => '4,31,1',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'TAGw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'info' => 'Parameter',
'deafult' => '3'
},
'BTEw' => {
'deafult' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'FPGA_VENDOR' => {
'type' => 'Combo-box',
'content' => '"ALTERA","GENERIC"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => '',
'deafult' => '"GENERIC"'
},
'CTIw' => {
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Parameter',
'deafult' => '3'
},
'Dw' => {
'type' => 'Spin-button',
'content' => '8,1024,1',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'Memory data width in Bits.',
'deafult' => '32'
},
'INIT_FILE_PATH' => {
'info' => undef,
'deafult' => 'SW_LOC',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => ''
},
'INITIAL_EN' => {
'deafult' => '"NO"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"YES","NO"',
'type' => 'Combo-box'
},
'BURST_MODE' => {
'deafult' => '"ENABLED"',
'info' => 'Wishbone bus burst read/write mode enable/disable. ',
'type' => 'Combo-box',
'content' => '"DISABLED","ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'BYTE_WR_EN' => {
'info' => '',
'deafult' => '"YES"',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'ports_order' => [
'clk',
'reset',
'sa_dat_i',
'sa_sel_i',
'sa_addr_i',
'sa_tag_i',
'sa_cti_i',
'sa_bte_i',
'sa_stb_i',
'sa_cyc_i',
'sa_we_i',
'sa_dat_o',
'sa_ack_o',
'sa_err_o',
'sa_rty_o'
],
'ports' => {
'sa_cyc_i' => {
'intfc_port' => 'cyc_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => ''
},
'sa_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
'range' => '',
'type' => 'output'
},
'sa_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Dw-1 : 0',
'type' => 'output'
},
'sa_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => 'Aw-1 : 0'
},
'sa_tag_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'tag_i',
'type' => 'input',
'range' => 'TAGw-1 : 0'
},
'sa_dat_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'type' => 'input'
},
'sa_stb_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'stb_i'
},
'sa_rty_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'rty_o',
'range' => '',
'type' => 'output'
},
'sa_we_i' => {
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
},
'sa_sel_i' => {
'type' => 'input',
'range' => 'SELw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'sel_i'
},
'sa_cti_i' => {
'range' => 'CTIw-1 : 0',
'type' => 'input',
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => ''
},
'sa_bte_i' => {
'intfc_port' => 'bte_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'BTEw-1 : 0',
'type' => 'input'
},
'reset' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]'
},
'sa_err_o' => {
'intfc_port' => 'err_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
}
}
}, 'ip_gen' );
',
'type' => 'Entry',
'global_param' => 'Localparam'
},
'CTIw' => {
'content' => '',
'redefine_param' => 1,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter'
},
'SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => 'Dw/8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'BURST_MODE' => {
'default' => '"ENABLED"',
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1,
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'BTEw' => {
'redefine_param' => 1,
'default' => '2',
'content' => '',
'type' => 'Fixed',
'info' => 'Parameter',
'global_param' => 'Localparam'
},
'INIT_FILE_PATH' => {
'type' => 'Fixed',
'info' => undef,
'global_param' => 'Localparam',
'content' => '',
'default' => 'SW_LOC',
'redefine_param' => 1
},
'JTAG_CONNECT' => {
'type' => 'Combo-box',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'global_param' => 'Localparam',
'default' => '"DISABLED"',
'redefine_param' => 1,
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"'
}
},
'version' => 22,
'ports' => {
'reset' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]'
},
'sa_bte_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'bte_i',
'type' => 'input',
'range' => 'BTEw-1 : 0'
},
'sa_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
'range' => '',
'type' => 'output'
},
'sa_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'SELw-1 : 0',
'type' => 'input'
},
'sa_err_o' => {
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'err_o'
},
'sa_tag_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'tag_i',
'type' => 'input',
'range' => 'TAGw-1 : 0'
},
'sa_dat_i' => {
'type' => 'input',
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_cyc_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cyc_i',
'type' => 'input',
'range' => ''
},
'sa_rty_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'rty_o',
'range' => '',
'type' => 'output'
},
'sa_cti_i' => {
'range' => 'CTIw-1 : 0',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cti_i'
},
'sa_we_i' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output',
'range' => 'Dw-1 : 0'
},
'clk' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i'
},
'sa_stb_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'stb_i',
'range' => '',
'type' => 'input'
},
'sa_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Aw-1 : 0',
'type' => 'input'
}
},
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH'
],
'plugs' => {
'reset' => {
'0' => {
'name' => 'reset'
},
'type' => 'num',
'value' => 1,
'reset' => {}
},
'wb_slave' => {
'type' => 'num',
'0' => {
'name' => 'wb',
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'width' => 'WB_Aw'
},
'wb_slave' => {},
'value' => 1
},
'clk' => {
'value' => 1,
'clk' => {},
'type' => 'num',
'0' => {
'name' => 'clk'
}
}
},
'hdl_files' => [
'/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
'/mpsoc/src_peripheral/ram/generic_ram.v',
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'
],
'ip_name' => 'single_port_ram',
'ports_order' => [
'clk',
'reset',
'sa_dat_i',
'sa_sel_i',
'sa_addr_i',
'sa_tag_i',
'sa_cti_i',
'sa_bte_i',
'sa_stb_i',
'sa_cyc_i',
'sa_we_i',
'sa_dat_o',
'sa_ack_o',
'sa_err_o',
'sa_rty_o'
],
'module_name' => 'wb_single_port_ram',
'description' => 'Single port ram with wishbone bus interface.',
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
'category' => 'RAM'
}, 'ip_gen' );

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