URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip
- from Rev 24 to Rev 25
- ↔ Reverse comparison
Rev 24 → Rev 25
/ethmac_100.IP
File deleted
ethmac_100.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: timer.IP
===================================================================
--- timer.IP (revision 24)
+++ timer.IP (nonexistent)
@@ -1,205 +0,0 @@
-$timer = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/timer/timer.v'
- ],
- 'ip_name' => 'timer',
- 'parameters_order' => [
- 'CNTw',
- 'Dw',
- 'Aw',
- 'TAGw',
- 'SELw'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/timer/timer.v',
- 'sockets' => {},
- 'module_name' => 'timer',
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'cti_i',
- 'bte_i'
- ]
- },
- 'category' => 'TIM',
- 'description' => '32 bit timer ',
- 'parameters' => {
- 'Aw' => {
- 'info' => undef,
- 'deafult' => ' 3',
- 'global_param' => undef,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'SELw' => {
- 'info' => undef,
- 'deafult' => ' 4',
- 'global_param' => undef,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'TAGw' => {
- 'info' => undef,
- 'deafult' => '3',
- 'global_param' => undef,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'CNTw' => {
- 'info' => undef,
- 'deafult' => '32 ',
- 'global_param' => undef,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => undef,
- 'content' => '',
- 'type' => 'Fixed'
- }
- },
- 'plugs' => {
- 'clk' => {
- 'clk' => {},
- '0' => {
- 'name' => 'clk'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- '0' => {
- 'name' => 'reset'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'interrupt_peripheral' => {
- 'interrupt_peripheral' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'interrupt_peripheral'
- },
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'value' => 1,
- '0' => {
- 'width' => 5,
- 'name' => 'wb',
- 'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'modules' => {
- 'timer' => {}
- },
- 'ports' => {
- 'sa_tag_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'tag_i',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'sa_rty_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'rty_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_sel_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'sel_i',
- 'range' => 'SELw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'sa_we_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'we_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'irq' => {
- 'intfc_name' => 'plug:interrupt_peripheral[0]',
- 'intfc_port' => 'int_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_cyc_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'cyc_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_err_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'err_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_ack_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'ack_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_addr_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'adr_i',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- },
- 'sa_stb_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'system_h' => '#define ${IP}_TCSR0 (*((volatile unsigned int *) ($BASE )))
-
-/*
-//timer control register
-TCSR0
-bit
-6-3 : clk_dev_ctrl
-3 : timer_isr
-2 : rst_on_cmp_value
-1 : int_enble_on_cmp_value
-0 : timer enable
-*/
- #define ${IP}_TLR0 (*((volatile unsigned int *) ($BASE+4 )))
- #define ${IP}_TCMP0 (*((volatile unsigned int *) ($BASE+8 )))
-#ifndef TIMER_EN
- #define TIMER_EN (1 << 0)
- #define TIMER_INT_EN (1 << 1)
- #define TIMER_RST_ON_CMP (1 << 2)
-#endif'
- }, 'ip_gen' );
timer.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: gpio.IP
===================================================================
--- gpio.IP (revision 24)
+++ gpio.IP (nonexistent)
@@ -1,169 +0,0 @@
-$gpio = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/gpio/gpio.v'
- ],
- 'system_h' => '#define ${IP}_DIR_REG (*((volatile unsigned int *) ($BASE)))
-#define ${IP}_WRITE _REG (*((volatile unsigned int *) ($BASE+4)))
-#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8)))
-
- #define ${IP}_DIR_SET(value) ${IP}_DIR_REG=value
-#define ${IP}_WRITE(value) ${IP}_WRITE _REG=value
-#define ${IP}_READ() ${IP}_READ_REG ',
- 'description' => 'General inout port',
- 'ip_name' => 'gpio',
- 'parameters' => {
- 'PORT_WIDTH' => {
- 'info' => undef,
- 'deafult' => ' 1',
- 'global_param' => 1,
- 'content' => '1,32,1',
- 'type' => 'Spin-button'
- },
- 'Aw' => {
- 'info' => undef,
- 'deafult' => ' 2',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'SELw' => {
- 'info' => undef,
- 'deafult' => ' 4',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- }
- },
- 'plugs' => {
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'value' => 1,
- '0' => {
- 'width' => 5,
- 'name' => 'wb',
- 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'modules' => {
- 'gpi' => {},
- 'gpio' => {},
- 'gpo' => {}
- },
- 'ports' => {
- 'sa_dat_o' => {
- 'intfc_port' => 'dat_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'port_io' => {
- 'intfc_port' => 'IO',
- 'intfc_name' => 'IO',
- 'range' => 'PORT_WIDTH-1 : 0',
- 'type' => 'inout'
- },
- 'sa_rty_o' => {
- 'intfc_port' => 'rty_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_sel_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'sel_i',
- 'range' => 'SELw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'sa_we_i' => {
- 'intfc_port' => 'we_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_err_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'err_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'clk' => {
- 'intfc_port' => 'clk_i',
- 'intfc_name' => 'plug:clk[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_ack_o' => {
- 'intfc_port' => 'ack_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_addr_i' => {
- 'intfc_port' => 'adr_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- },
- 'sa_stb_i' => {
- 'intfc_port' => 'stb_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'parameters_order' => [
- 'PORT_WIDTH',
- 'Dw',
- 'Aw',
- 'SELw'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
- 'sockets' => {},
- 'module_name' => 'gpio',
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'cyc_i',
- 'tag_i',
- 'cti_i',
- 'bte_i'
- ]
- },
- 'category' => 'GPI'
- }, 'ip_gen' );
gpio.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: int_ctrl.IP
===================================================================
--- int_ctrl.IP (revision 24)
+++ int_ctrl.IP (nonexistent)
@@ -1,190 +0,0 @@
-$int_ctrl = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/int_ctrl/int_ctrl.v'
- ],
- 'ip_name' => 'int_ctrl',
- 'description' => 'interrupt controller',
- 'modules' => {
- 'int_ctrl' => {}
- },
- 'plugs' => {
- 'clk' => {
- 'clk' => {},
- '0' => {
- 'name' => 'clk'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- '0' => {
- 'name' => 'reset'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'value' => 1,
- '0' => {
- 'width' => 5,
- 'name' => 'wb',
- 'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'parameters' => {
- 'Aw' => {
- 'info' => undef,
- 'deafult' => ' 3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'SELw' => {
- 'info' => undef,
- 'deafult' => ' 4 ',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'INT_NUM' => {
- 'info' => 'number of inerrupt.',
- 'deafult' => ' 3',
- 'global_param' => 0,
- 'content' => '1,32,1',
- 'type' => 'Spin-button'
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- }
- },
- 'parameters_order' => [
- 'INT_NUM',
- 'Dw',
- 'Aw',
- 'SELw'
- ],
- 'ports' => {
- 'sa_rty_o' => {
- 'intfc_port' => 'rty_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_dat_o' => {
- 'intfc_port' => 'dat_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'sa_sel_i' => {
- 'intfc_port' => 'sel_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'SELw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_i' => {
- 'intfc_port' => 'dat_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'sa_we_i' => {
- 'intfc_port' => 'we_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_err_o' => {
- 'intfc_port' => 'err_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'int_o' => {
- 'intfc_port' => 'int_o',
- 'intfc_name' => 'socket:interrupt_cpu[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'clk' => {
- 'intfc_port' => 'clk_i',
- 'intfc_name' => 'plug:clk[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_ack_o' => {
- 'intfc_port' => 'ack_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_port' => 'reset_i',
- 'intfc_name' => 'plug:reset[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'int_i' => {
- 'intfc_port' => 'int_i',
- 'intfc_name' => 'socket:interrupt_peripheral[array]',
- 'range' => 'INT_NUM-1 : 0',
- 'type' => 'input'
- },
- 'sa_addr_i' => {
- 'intfc_port' => 'adr_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- },
- 'sa_stb_i' => {
- 'intfc_port' => 'stb_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'sockets' => {
- 'interrupt_cpu' => {
- 'interrupt_cpu' => {},
- 'connection_num' => 'single connection',
- '0' => {
- 'name' => 'int_cpu'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'interrupt_peripheral' => {
- 'interrupt_peripheral' => {},
- 'connection_num' => 'single connection',
- 'value' => 'INT_NUM',
- '0' => {
- 'name' => 'int_periph'
- },
- 'type' => 'param'
- }
- },
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/int_ctrl/int_ctrl.v',
- 'module_name' => 'int_ctrl',
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'cyc_i',
- 'tag_i',
- 'cti_i',
- 'bte_i'
- ]
- },
- 'category' => 'interrupt',
- 'system_h' => '
- #define ${IP}_MER (*((volatile unsigned int *) ($BASE )))
- #define ${IP}_IER (*((volatile unsigned int *) ($BASE+4 )))
- #define ${IP}_IAR (*((volatile unsigned int *) ($BASE+8 )))
- #define ${IP}_IPR (*((volatile unsigned int *) ($BASE+12 )))'
- }, 'ip_gen' );
int_ctrl.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: dual_port_ram.IP
===================================================================
--- dual_port_ram.IP (revision 24)
+++ dual_port_ram.IP (nonexistent)
@@ -1,203 +0,0 @@
-$general_dual_port_ram = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/ram/general_dual_port_ram.v'
- ],
- 'description' => 'General dual port ram. It does not support Byte enable.',
- 'ip_name' => 'dual_port_ram',
- 'parameters' => {
- 'Aw' => {
- 'info' => undef,
- 'deafult' => '10',
- 'global_param' => 1,
- 'content' => '2,31,1',
- 'type' => 'Spin-button',
- 'redefine_param' => 1
- },
- 'TAGw' => {
- 'info' => undef,
- 'deafult' => '3 ',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => '32',
- 'global_param' => 1,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'WB_Aw' => {
- 'info' => undef,
- 'deafult' => 'Aw+2',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 0,
- 'type' => 'Fixed'
- }
- },
- 'plugs' => {
- 'clk' => {
- 'clk' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
- 'wb_slave' => {
- '1' => {
- 'width' => 'WB_Aw',
- 'name' => 'wb_b',
- 'addr' => '0x0000_0000 0x3fff_ffff RAM'
- },
- 'value' => 2,
- '0' => {
- 'width' => 'WB_Aw',
- 'name' => 'wb_a',
- 'addr' => '0x0000_0000 0x3fff_ffff RAM'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'modules' => {
- 'dual_port_ram' => {},
- 'general_dual_port_ram' => {}
- },
- 'ports' => {
- 'sa_tag_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'tag_i',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'input'
- },
- 'sb_addr_i' => {
- 'intfc_name' => 'plug:wb_slave[1]',
- 'intfc_port' => 'adr_i',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- },
- 'sb_dat_o' => {
- 'intfc_name' => 'plug:wb_slave[1]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_ack_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'ack_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sb_ack_o' => {
- 'intfc_name' => 'plug:wb_slave[1]',
- 'intfc_port' => 'ack_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_addr_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'adr_i',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- },
- 'sb_dat_i' => {
- 'intfc_name' => 'plug:wb_slave[1]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'sb_we_i' => {
- 'intfc_name' => 'plug:wb_slave[1]',
- 'intfc_port' => 'we_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_dat_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'sa_we_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'we_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sb_stb_i' => {
- 'intfc_name' => 'plug:wb_slave[1]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sb_tag_i' => {
- 'intfc_name' => 'plug:wb_slave[1]',
- 'intfc_port' => 'tag_i',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'input'
- },
- 'sa_stb_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'parameters_order' => [
- 'Dw',
- 'Aw',
- 'TAGw',
- 'WB_Aw'
- ],
- 'ports_order' => [
- 'clk',
- 'reset',
- 'sa_dat_i',
- 'sb_dat_i',
- 'sa_addr_i',
- 'sb_addr_i',
- 'sa_tag_i',
- 'sb_tag_i',
- 'sa_stb_i',
- 'sb_stb_i',
- 'sa_we_i',
- 'sb_we_i',
- 'sa_dat_o',
- 'sb_dat_o',
- 'sa_ack_o',
- 'sb_ack_o'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/general_dual_port_ram.v',
- 'module_name' => 'general_dual_port_ram',
- 'category' => 'RAM'
- }, 'ip_gen' );
Index: wishbone_bus.IP
===================================================================
--- wishbone_bus.IP (revision 24)
+++ wishbone_bus.IP (nonexistent)
@@ -1,354 +0,0 @@
-$wishbone_bus = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/bus/wishbone_bus.v',
- '/mpsoc/src_noc/main_comp.v',
- '/mpsoc/src_noc/arbiter.v'
- ],
- 'ip_name' => 'wishbone_bus',
- 'description' => 'wishbone bus',
- 'parameters' => {
- 'S' => {
- 'info' => 'Number of wishbone slave interface',
- 'deafult' => '4',
- 'global_param' => 0,
- 'content' => '1,256,1',
- 'type' => 'Spin-button',
- 'redefine_param' => 1
- },
- 'SELw' => {
- 'info' => undef,
- 'deafult' => 'Dw/8',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => '32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'BTEw' => {
- 'info' => undef,
- 'deafult' => '2 ',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'M' => {
- 'info' => 'Number of wishbone master interface',
- 'deafult' => ' 4',
- 'global_param' => 0,
- 'content' => '1,256,1',
- 'type' => 'Spin-button',
- 'redefine_param' => 1
- },
- 'Aw' => {
- 'info' => undef,
- 'deafult' => '32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'TAGw' => {
- 'info' => undef,
- 'deafult' => '3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'CTIw' => {
- 'info' => undef,
- 'deafult' => '3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- }
- },
- 'modules' => {
- 'wishbone_bus' => {},
- 'bus_arbiter' => {}
- },
- 'plugs' => {
- 'clk' => {
- 'clk' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- }
- },
- 'ports' => {
- 's_sel_o_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'sel_o',
- 'range' => 'SELw*S-1 : 0',
- 'type' => 'output'
- },
- 's_adr_o_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'adr_o',
- 'range' => 'Aw*S-1 : 0',
- 'type' => 'output'
- },
- 's_dat_o_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw*S-1 : 0',
- 'type' => 'output'
- },
- 'm_cyc_i_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'cyc_i',
- 'range' => 'M-1 : 0',
- 'type' => 'input'
- },
- 'm_grant_addr' => {
- 'intfc_name' => 'socket:wb_addr_map[0]',
- 'intfc_port' => 'grant_addr',
- 'range' => 'Aw-1 : 0',
- 'type' => 'output'
- },
- 's_bte_o_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'bte_o',
- 'range' => 'BTEw*S-1 : 0',
- 'type' => 'output'
- },
- 's_ack_i_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'ack_i',
- 'range' => 'S-1 : 0',
- 'type' => 'input'
- },
- 's_cti_o_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'cti_o',
- 'range' => 'CTIw*S-1 : 0',
- 'type' => 'output'
- },
- 's_tag_o_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'tag_o',
- 'range' => 'TAGw*S-1 : 0',
- 'type' => 'output'
- },
- 's_err_i_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'err_i',
- 'range' => 'S-1 : 0',
- 'type' => 'input'
- },
- 'm_stb_i_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'stb_i',
- 'range' => 'M-1 : 0',
- 'type' => 'input'
- },
- 'm_ack_o_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'ack_o',
- 'range' => 'M-1 : 0',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 's_cyc_o_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'cyc_o',
- 'range' => 'S-1 : 0',
- 'type' => 'output'
- },
- 'm_adr_i_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'adr_i',
- 'range' => 'Aw*M-1 : 0',
- 'type' => 'input'
- },
- 'm_rty_o_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'rty_o',
- 'range' => 'M-1 : 0',
- 'type' => 'output'
- },
- 'm_dat_o_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw*M-1 : 0',
- 'type' => 'output'
- },
- 's_we_o_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'we_o',
- 'range' => 'S-1 : 0',
- 'type' => 'output'
- },
- 'm_dat_i_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw*M-1 : 0',
- 'type' => 'input'
- },
- 'm_bte_i_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'bte_i',
- 'range' => 'BTEw*M-1 : 0',
- 'type' => 'input'
- },
- 'm_err_o_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'err_o',
- 'range' => 'M-1 : 0',
- 'type' => 'output'
- },
- 's_rty_i_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'rty_i',
- 'range' => 'S-1 : 0',
- 'type' => 'input'
- },
- 's_stb_o_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'stb_o',
- 'range' => 'S-1 : 0',
- 'type' => 'output'
- },
- 'm_tag_i_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'tag_i',
- 'range' => 'TAGw*M-1 : 0',
- 'type' => 'input'
- },
- 's_dat_i_all' => {
- 'intfc_name' => 'socket:wb_slave[array]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw*S-1 : 0',
- 'type' => 'input'
- },
- 'm_sel_i_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'sel_i',
- 'range' => 'SELw*M-1 : 0',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'm_cti_i_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'cti_i',
- 'range' => 'CTIw*M-1 : 0',
- 'type' => 'input'
- },
- 'm_we_i_all' => {
- 'intfc_name' => 'socket:wb_master[array]',
- 'intfc_port' => 'we_i',
- 'range' => 'M-1 : 0',
- 'type' => 'input'
- },
- 's_sel_one_hot' => {
- 'intfc_name' => 'socket:wb_addr_map[0]',
- 'intfc_port' => 'sel_one_hot',
- 'range' => 'S-1 : 0',
- 'type' => 'input'
- }
- },
- 'ports_order' => [
- 's_adr_o_all',
- 's_dat_o_all',
- 's_sel_o_all',
- 's_tag_o_all',
- 's_we_o_all',
- 's_cyc_o_all',
- 's_stb_o_all',
- 's_cti_o_all',
- 's_bte_o_all',
- 's_dat_i_all',
- 's_ack_i_all',
- 's_err_i_all',
- 's_rty_i_all',
- 'm_dat_o_all',
- 'm_ack_o_all',
- 'm_err_o_all',
- 'm_rty_o_all',
- 'm_adr_i_all',
- 'm_dat_i_all',
- 'm_sel_i_all',
- 'm_tag_i_all',
- 'm_we_i_all',
- 'm_stb_i_all',
- 'm_cyc_i_all',
- 'm_cti_i_all',
- 'm_bte_i_all',
- 'm_grant_addr',
- 's_sel_one_hot',
- 'clk',
- 'reset'
- ],
- 'parameters_order' => [
- 'M',
- 'S',
- 'Dw',
- 'Aw',
- 'SELw',
- 'TAGw',
- 'CTIw',
- 'BTEw'
- ],
- 'sockets' => {
- 'wb_master' => {
- 'wb_master' => {},
- 'connection_num' => 'single connection',
- 'value' => 'M',
- '0' => {
- 'name' => 'wb_master'
- },
- 'type' => 'param'
- },
- 'wb_addr_map' => {
- 'connection_num' => 'single connection',
- 'value' => 1,
- '0' => {
- 'name' => 'wb_addr_map'
- },
- 'wb_addr_map' => {},
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'connection_num' => 'single connection',
- 'value' => 'S',
- '0' => {
- 'name' => 'wb_slave'
- },
- 'type' => 'param',
- 'wb_slave' => {}
- }
- },
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/bus/wishbone_bus.v',
- 'module_name' => 'wishbone_bus',
- 'unused' => undef,
- 'category' => 'bus'
- }, 'ip_gen' );
wishbone_bus.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: lm32.IP
===================================================================
--- lm32.IP (revision 24)
+++ lm32.IP (nonexistent)
@@ -1,344 +0,0 @@
-$lm32 = bless( {
- 'hdl_files' => [
- '/mpsoc/src_processor/lm32/verilog/src/er1.v',
- '/mpsoc/src_processor/lm32/verilog/src/JTAGB.v',
- '/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_include.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v',
- '/mpsoc/src_processor/lm32/verilog/src/lm32_top.v',
- '/mpsoc/src_processor/lm32/verilog/src/spiprog.v',
- '/mpsoc/src_processor/lm32/verilog/src/system_conf.v',
- '/mpsoc/src_processor/lm32/verilog/src/typea.v',
- '/mpsoc/src_processor/lm32/verilog/src/typeb.v'
- ],
- 'ip_name' => 'lm32',
- 'parameters_order' => [
- 'INTR_NUM',
- 'CFG_PL_MULTIPLY',
- 'CFG_PL_BARREL_SHIFT',
- 'CFG_SIGN_EXTEND',
- 'CFG_MC_DIVIDE'
- ],
- 'ports_order' => [
- 'clk_i',
- 'rst_i',
- 'interrupt',
- 'I_DAT_I',
- 'I_ACK_I',
- 'I_ERR_I',
- 'I_RTY_I',
- 'I_DAT_O',
- 'I_ADR_O',
- 'I_CYC_O',
- 'I_SEL_O',
- 'I_STB_O',
- 'I_WE_O',
- 'I_CTI_O',
- 'I_BTE_O',
- 'D_DAT_I',
- 'D_ACK_I',
- 'D_ERR_I',
- 'D_RTY_I',
- 'D_DAT_O',
- 'D_ADR_O',
- 'D_CYC_O',
- 'D_SEL_O',
- 'D_STB_O',
- 'D_WE_O',
- 'D_CTI_O',
- 'D_BTE_O'
- ],
- 'sockets' => {
- 'interrupt_peripheral' => {
- 'interrupt_peripheral' => {},
- 'connection_num' => 'single connection',
- 'value' => 'INTR_NUM',
- '0' => {
- 'name' => 'interrupt_peripheral'
- },
- 'type' => 'param'
- }
- },
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v',
- 'module_name' => 'lm32',
- 'unused' => {
- 'plug:wb_master[1]' => [
- 'tag_o'
- ],
- 'plug:wb_master[0]' => [
- 'tag_o'
- ]
- },
- 'category' => 'Processor',
- 'sw_files' => [
- '/mpsoc/src_processor/lm32/sw/crt0ram.S',
- '/mpsoc/src_processor/lm32/sw/linker.ld',
- '/mpsoc/src_processor/lm32/sw/lm32_system.h',
- '/mpsoc/src_processor/lm32/sw/Makefile',
- '/mpsoc/src_processor/program_memories.sh'
- ],
- 'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement.
-
-for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx',
- 'plugs' => {
- 'wb_master' => {
- 'wb_master' => {},
- '1' => {
- 'name' => 'dwb'
- },
- 'value' => 2,
- '0' => {
- 'name' => 'iwb'
- },
- 'type' => 'num'
- },
- 'reset' => {
- '1' => {
- 'name' => 'reset_1'
- },
- 'reset' => {},
- '0' => {
- 'name' => 'reset'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- '0' => {
- 'name' => 'clk'
- },
- 'value' => 1,
- 'type' => 'num'
- }
- },
- 'modules' => {
- 'lm32' => {}
- },
- 'parameters' => {
- 'CFG_PL_BARREL_SHIFT' => {
- 'info' => undef,
- 'deafult' => '"ENABLED"',
- 'global_param' => 0,
- 'content' => '"ENABLED","DISABLED"',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'CFG_SIGN_EXTEND' => {
- 'info' => undef,
- 'deafult' => '"ENABLED"',
- 'global_param' => 0,
- 'content' => '"ENABLED","DISABLED"',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'CFG_PL_MULTIPLY' => {
- 'info' => undef,
- 'deafult' => '"ENABLED"',
- 'global_param' => 0,
- 'content' => '"ENABLED","DISABLED"',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'INTR_NUM' => {
- 'info' => undef,
- 'deafult' => '32',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'CFG_MC_DIVIDE' => {
- 'info' => undef,
- 'deafult' => '"DISABLED"',
- 'global_param' => 0,
- 'content' => '"ENABLED","DISABLED"',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- }
- },
- 'ports' => {
- 'I_SEL_O' => {
- 'intfc_port' => 'sel_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '(4-1):0',
- 'type' => 'output'
- },
- 'I_DAT_I' => {
- 'intfc_port' => 'dat_i',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '(32-1):0',
- 'type' => 'input'
- },
- 'I_CTI_O' => {
- 'intfc_port' => 'cti_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '(3-1):0',
- 'type' => 'output'
- },
- 'D_WE_O' => {
- 'intfc_port' => 'we_o',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '',
- 'type' => 'output'
- },
- 'I_ERR_I' => {
- 'intfc_port' => 'err_i',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'D_ADR_O' => {
- 'intfc_port' => 'adr_o',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '(32-1):0',
- 'type' => 'output'
- },
- 'D_CTI_O' => {
- 'intfc_port' => 'cti_o',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '(3-1):0',
- 'type' => 'output'
- },
- 'D_STB_O' => {
- 'intfc_port' => 'stb_o',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '',
- 'type' => 'output'
- },
- 'I_CYC_O' => {
- 'intfc_port' => 'cyc_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'D_DAT_I' => {
- 'intfc_port' => 'dat_i',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '(32-1):0',
- 'type' => 'input'
- },
- 'D_ACK_I' => {
- 'intfc_port' => 'ack_i',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '',
- 'type' => 'input'
- },
- 'D_DAT_O' => {
- 'intfc_port' => 'dat_o',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '(32-1):0',
- 'type' => 'output'
- },
- 'I_ADR_O' => {
- 'intfc_port' => 'adr_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '(32-1):0',
- 'type' => 'output'
- },
- 'I_WE_O' => {
- 'intfc_port' => 'we_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'I_BTE_O' => {
- 'intfc_port' => 'bte_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '(2-1):0',
- 'type' => 'output'
- },
- 'rst_i' => {
- 'intfc_port' => 'reset_i',
- 'intfc_name' => 'plug:reset[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'interrupt' => {
- 'intfc_port' => 'int_i',
- 'intfc_name' => 'socket:interrupt_peripheral[array]',
- 'range' => '(32-1):0',
- 'type' => 'input'
- },
- 'D_BTE_O' => {
- 'intfc_port' => 'bte_o',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '(2-1):0',
- 'type' => 'output'
- },
- 'D_CYC_O' => {
- 'intfc_port' => 'cyc_o',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '',
- 'type' => 'output'
- },
- 'I_STB_O' => {
- 'intfc_port' => 'stb_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'D_SEL_O' => {
- 'intfc_port' => 'sel_o',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '(4-1):0',
- 'type' => 'output'
- },
- 'I_DAT_O' => {
- 'intfc_port' => 'dat_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '(32-1):0',
- 'type' => 'output'
- },
- 'D_ERR_I' => {
- 'intfc_port' => 'err_i',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '',
- 'type' => 'input'
- },
- 'D_RTY_I' => {
- 'intfc_port' => 'rty_i',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => '',
- 'type' => 'input'
- },
- 'I_ACK_I' => {
- 'intfc_port' => 'ack_i',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'I_RTY_I' => {
- 'intfc_port' => 'rty_i',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'clk_i' => {
- 'intfc_port' => 'clk_i',
- 'intfc_name' => 'plug:clk[0]',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'system_h' => '#include "lm32_system.h"'
- }, 'ip_gen' );
lm32.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB.IP
===================================================================
--- aeMB.IP (revision 24)
+++ aeMB.IP (nonexistent)
@@ -1,380 +0,0 @@
-$aeMB_top = bless( {
- 'hdl_files' => [
- '/mpsoc/src_processor/aeMB/verilog/aemb.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_core.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_xecu.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_sim.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_bpcu.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_edk32.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_xslif.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_ctrl.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_ibuf.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_tpsram.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_regf.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_exec.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_sparam.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_intu.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_regs.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_spsram.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_memif.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_mult.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_gprf.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_pipe.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_brcc.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_dparam.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_edk63.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_bsft.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_ctrl.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_dwbif.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_edk62.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_sim.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iche.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iwbif.v'
- ],
- 'description' => 'AEMB 32-bit Microprocessor Core
-For more information check http://opencores.org/project,aemb',
- 'ip_name' => 'aeMB',
- 'parameters' => {
- 'AEMB_XWB' => {
- 'info' => undef,
- 'deafult' => ' 7',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_IDX' => {
- 'info' => undef,
- 'deafult' => ' 6',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_MUL' => {
- 'info' => undef,
- 'deafult' => ' 1',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_IWB' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_BSF' => {
- 'info' => undef,
- 'deafult' => ' 1',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_ICH' => {
- 'info' => undef,
- 'deafult' => ' 11',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_DWB' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- }
- },
- 'plugs' => {
- 'interrupt_cpu' => {
- 'interrupt_cpu' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'intrp'
- },
- 'type' => 'num'
- },
- 'wb_master' => {
- 'wb_master' => {},
- '1' => {
- 'name' => 'dwb'
- },
- 'value' => 2,
- '0' => {
- 'name' => 'iwb'
- },
- 'type' => 'num'
- },
- 'enable' => {
- 'enable' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'enable'
- },
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- }
- },
- 'modules' => {
- 'aeMB_top' => {}
- },
- 'parameters_order' => [
- 'AEMB_IWB',
- 'AEMB_DWB',
- 'AEMB_XWB',
- 'AEMB_ICH',
- 'AEMB_IDX',
- 'AEMB_BSF',
- 'AEMB_MUL'
- ],
- 'ports' => {
- 'iwb_err_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'err_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'dwb_ack_i' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'ack_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'iwb_cyc_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'cyc_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'iwb_dat_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'dat_o',
- 'range' => '31:0',
- 'type' => 'output'
- },
- 'dwb_wre_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'we_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'dwb_cyc_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'cyc_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'dwb_stb_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'stb_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'iwb_adr_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'adr_o',
- 'range' => '31:0',
- 'type' => 'output'
- },
- 'iwb_bte_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'bte_o',
- 'range' => '1:0',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'iwb_rty_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'rty_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sys_int_i' => {
- 'intfc_name' => 'plug:interrupt_cpu[0]',
- 'intfc_port' => 'int_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'dwb_err_i' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'err_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'iwb_tag_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'tag_o',
- 'range' => '2:0',
- 'type' => 'output'
- },
- 'iwb_ack_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'ack_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'iwb_sel_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'sel_o',
- 'range' => '3:0',
- 'type' => 'output'
- },
- 'dwb_tag_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'tag_o',
- 'range' => '2:0',
- 'type' => 'output'
- },
- 'dwb_adr_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'adr_o',
- 'range' => '31:0',
- 'type' => 'output'
- },
- 'dwb_bte_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'bte_o',
- 'range' => '1:0',
- 'type' => 'output'
- },
- 'dwb_dat_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'dat_o',
- 'range' => '31:0',
- 'type' => 'output'
- },
- 'dwb_cti_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'cti_o',
- 'range' => '2:0',
- 'type' => 'output'
- },
- 'iwb_cti_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'cti_o',
- 'range' => '2:0',
- 'type' => 'output'
- },
- 'iwb_stb_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'stb_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'dwb_rty_i' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'rty_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'dwb_dat_i' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'dat_i',
- 'range' => '31:0',
- 'type' => 'input'
- },
- 'iwb_dat_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'dat_i',
- 'range' => '31:0',
- 'type' => 'input'
- },
- 'dwb_sel_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'sel_o',
- 'range' => '3:0',
- 'type' => 'output'
- },
- 'iwb_wre_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'we_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sys_ena_i' => {
- 'intfc_name' => 'plug:enable[0]',
- 'intfc_port' => 'enable_i',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'ports_order' => [
- 'dwb_adr_o',
- 'dwb_cyc_o',
- 'dwb_dat_o',
- 'dwb_sel_o',
- 'dwb_stb_o',
- 'dwb_tag_o',
- 'dwb_wre_o',
- 'dwb_cti_o',
- 'dwb_bte_o',
- 'dwb_ack_i',
- 'dwb_dat_i',
- 'dwb_err_i',
- 'dwb_rty_i',
- 'iwb_adr_o',
- 'iwb_cyc_o',
- 'iwb_sel_o',
- 'iwb_stb_o',
- 'iwb_tag_o',
- 'iwb_wre_o',
- 'iwb_dat_o',
- 'iwb_cti_o',
- 'iwb_bte_o',
- 'iwb_ack_i',
- 'iwb_dat_i',
- 'iwb_err_i',
- 'iwb_rty_i',
- 'clk',
- 'reset',
- 'sys_int_i',
- 'sys_ena_i'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/aeMB/verilog/aemb.v',
- 'module_name' => 'aeMB_top',
- 'unused' => undef,
- 'category' => 'Processor',
- 'system_h' => ' #include
- #include
- #include "aemb/core.hh" ',
- 'sw_files' => [
- '/mpsoc/src_processor/aeMB/sw/aemb',
- '/mpsoc/src_processor/aeMB/sw/compile',
- '/mpsoc/src_processor/aeMB/sw/program',
- '/mpsoc/src_processor/program_memories.sh',
- '/mpsoc/src_processor/aeMB/sw/Makefile'
- ]
- }, 'ip_gen' );
aeMB.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: single_port_ram.IP
===================================================================
--- single_port_ram.IP (revision 24)
+++ single_port_ram.IP (nonexistent)
@@ -1,170 +0,0 @@
-$general_single_port_ram = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/ram/general_single_port_ram.v'
- ],
- 'description' => 'General single port ram. It does not support Byte-enable signal.',
- 'ip_name' => 'single_port_ram',
- 'plugs' => {
- 'clk' => {
- 'clk' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'value' => 1,
- '0' => {
- 'width' => 'WB_Aw',
- 'name' => 'wb',
- 'addr' => '0x0000_0000 0x3fff_ffff RAM'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'modules' => {
- 'general_single_port_ram' => {},
- 'single_port_ram' => {}
- },
- 'parameters' => {
- 'Aw' => {
- 'info' => 'Address width in bit',
- 'deafult' => '10',
- 'global_param' => 1,
- 'content' => '4,32,1',
- 'type' => 'Spin-button',
- 'redefine_param' => 1
- },
- 'TAGw' => {
- 'info' => undef,
- 'deafult' => '3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'Dw' => {
- 'info' => 'Ram Data width in bits',
- 'deafult' => '32',
- 'global_param' => 1,
- 'content' => '1,1024,1',
- 'type' => 'Spin-button',
- 'redefine_param' => 1
- },
- 'WB_Aw' => {
- 'info' => undef,
- 'deafult' => 'Aw+2',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 0,
- 'type' => 'Fixed'
- }
- },
- 'parameters_order' => [
- 'Dw',
- 'Aw',
- 'TAGw',
- 'WB_Aw'
- ],
- 'ports_order' => [
- 'clk',
- 'reset',
- 'sa_dat_i',
- 'sa_addr_i',
- 'sa_tag_i',
- 'sa_stb_i',
- 'sa_cyc_i',
- 'sa_we_i',
- 'sa_dat_o',
- 'sa_ack_o',
- 'sa_err_o',
- 'sa_rty_o'
- ],
- 'ports' => {
- 'sa_tag_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'tag_i',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'sa_rty_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'rty_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_dat_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'sa_we_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'we_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_cyc_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'cyc_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_err_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'err_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_ack_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'ack_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_addr_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'adr_i',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- },
- 'sa_stb_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/general_single_port_ram.v',
- 'module_name' => 'general_single_port_ram',
- 'category' => 'RAM'
- }, 'ip_gen' );
Index: lcd_2x16.IP
===================================================================
--- lcd_2x16.IP (revision 24)
+++ lcd_2x16.IP (nonexistent)
@@ -1,190 +0,0 @@
-$lcd_2x16 = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v'
- ],
- 'system_h' => '#define ${IP}_WR_CMD (*((volatile unsigned int *) ($BASE)))
-#define ${IP}_RD_CMD (*((volatile unsigned int *) ($BASE+4)))
-#define ${IP}_WR_DATA (*((volatile unsigned int *) ($BASE+8)))
-#define ${IP}_RD_DATA (*((volatile unsigned int *) ($BASE+16)))
-
-#define ${IP}_CLK_MHZ $CLK_MHZ
-
-#include "$IP.h"',
- 'ip_name' => 'lcd_2x16',
- 'sw_params_list' => [],
- 'parameters_order' => [
- 'Dw',
- 'Aw',
- 'CLK_MHZ'
- ],
- 'ports_order' => [
- 'clk',
- 'reset',
- 's_dat_i',
- 's_addr_i',
- 's_stb_i',
- 's_cyc_i',
- 's_we_i',
- 's_dat_o',
- 's_ack_o',
- 'lcd_en',
- 'lcd_rs',
- 'lcd_rw',
- 'lcd_data'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v',
- 'module_name' => 'lcd_2x16',
- 'gen_sw_files' => [
- '/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.hgenfrename_sep_t${IP}.h'
- ],
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'err_o',
- 'rty_o',
- 'tag_i',
- 'cti_i',
- 'sel_i',
- 'bte_i'
- ]
- },
- 'category' => 'Display',
- 'sw_files' => [],
- 'description' => 'Alphabet Display LCD 2x16',
- 'parameters' => {
- 'Aw' => {
- 'info' => undef,
- 'deafult' => ' 2',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => ' 8',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'CLK_MHZ' => {
- 'info' => 'The LCD controller clock speed in MHZ. It will be used for measuring the lcd enable delay. You can define a larger value than the actual clk speed but not smaller.',
- 'deafult' => '100',
- 'global_param' => 0,
- 'content' => '2,1000,2',
- 'redefine_param' => 1,
- 'type' => 'Spin-button'
- }
- },
- 'modules' => {
- 'lcd_2x16' => {}
- },
- 'plugs' => {
- 'reset' => {
- 'reset' => {},
- '0' => {
- 'name' => 'reset'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- '0' => {
- 'name' => 'clk'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'wb_slave' => {
- '0' => {
- 'width' => 5,
- 'name' => 'wb_slave',
- 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
- },
- 'value' => 1,
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'ports' => {
- 's_dat_i' => {
- 'intfc_port' => 'dat_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 's_cyc_i' => {
- 'intfc_port' => 'cyc_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'lcd_en' => {
- 'intfc_port' => 'IO',
- 'intfc_name' => 'IO',
- 'range' => '',
- 'type' => 'output'
- },
- 's_ack_o' => {
- 'intfc_port' => 'ack_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 's_we_i' => {
- 'intfc_port' => 'we_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 's_stb_i' => {
- 'intfc_port' => 'stb_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'lcd_data' => {
- 'intfc_port' => 'IO',
- 'intfc_name' => 'IO',
- 'range' => ' 7: 0',
- 'type' => 'inout'
- },
- 'lcd_rs' => {
- 'intfc_port' => 'IO',
- 'intfc_name' => 'IO',
- 'range' => '',
- 'type' => 'output'
- },
- 'clk' => {
- 'intfc_port' => 'clk_i',
- 'intfc_name' => 'plug:clk[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'lcd_rw' => {
- 'intfc_port' => 'IO',
- 'intfc_name' => 'IO',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_port' => 'reset_i',
- 'intfc_name' => 'plug:reset[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 's_dat_o' => {
- 'intfc_port' => 'dat_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 's_addr_i' => {
- 'intfc_port' => 'adr_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- }
- }
- }, 'ip_gen' );
Index: clk_source.IP
===================================================================
--- clk_source.IP (revision 24)
+++ clk_source.IP (nonexistent)
@@ -1,78 +0,0 @@
-$clk_source = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/reset_sync/altera_reset_synchronizer.v',
- '/mpsoc/src_peripheral/reset_sync/clk_source.v'
- ],
- 'ip_name' => 'clk_source',
- 'description' => 'clk source',
- 'modules' => {
- 'clk_source' => {}
- },
- 'plugs' => {
- 'reset' => {
- 'reset' => {},
- '0' => {
- 'name' => 'reset'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- '0' => {
- 'name' => 'clk'
- },
- 'value' => 1,
- 'type' => 'num'
- }
- },
- 'ports' => {
- 'clk_out' => {
- 'intfc_port' => 'clk_o',
- 'intfc_name' => 'socket:clk[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset_out' => {
- 'intfc_port' => 'reset_o',
- 'intfc_name' => 'socket:reset[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'clk_in' => {
- 'intfc_port' => 'clk_i',
- 'intfc_name' => 'plug:clk[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'reset_in' => {
- 'intfc_port' => 'reset_i',
- 'intfc_name' => 'plug:reset[0]',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/reset_sync/clk_source.v',
- 'sockets' => {
- 'clk' => {
- 'clk' => {},
- 'connection_num' => 'multi connection',
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'connection_num' => 'multi connection',
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- }
- },
- 'module_name' => 'clk_source',
- 'category' => 'source'
- }, 'ip_gen' );
clk_source.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: gpi.IP
===================================================================
--- gpi.IP (revision 24)
+++ gpi.IP (nonexistent)
@@ -1,182 +0,0 @@
-$gpi = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/gpio/gpio.v'
- ],
- 'ip_name' => 'gpi',
- 'description' => 'General inout port',
- 'modules' => {
- 'gpi' => {},
- 'gpio' => {},
- 'gpo' => {}
- },
- 'plugs' => {
- 'clk' => {
- 'clk' => {},
- '0' => {
- 'name' => 'clk'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- '0' => {
- 'name' => 'reset'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'value' => 1,
- '0' => {
- 'width' => 5,
- 'name' => 'wb',
- 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'parameters' => {
- 'PORT_WIDTH' => {
- 'info' => 'Input port width ',
- 'deafult' => ' 1',
- 'global_param' => 1,
- 'content' => '1,32,1',
- 'type' => 'Spin-button'
- },
- 'Aw' => {
- 'info' => undef,
- 'deafult' => ' 2',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'SELw' => {
- 'info' => undef,
- 'deafult' => ' 4',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'TAGw' => {
- 'info' => undef,
- 'deafult' => ' 3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- }
- },
- 'ports' => {
- 'sa_tag_i' => {
- 'intfc_port' => 'tag_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'input'
- },
- 'sa_rty_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'rty_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_dat_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'sa_sel_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'sel_i',
- 'range' => 'SELw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'sa_we_i' => {
- 'intfc_port' => 'we_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_err_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'err_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_cyc_i' => {
- 'intfc_port' => 'cyc_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_ack_o' => {
- 'intfc_port' => 'ack_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_port' => 'reset_i',
- 'intfc_name' => 'plug:reset[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'port_i' => {
- 'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
- 'range' => 'PORT_WIDTH-1 : 0',
- 'type' => 'input'
- },
- 'sa_addr_i' => {
- 'intfc_port' => 'adr_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- },
- 'sa_stb_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'parameters_order' => [
- 'PORT_WIDTH',
- 'Dw',
- 'Aw',
- 'TAGw',
- 'SELw'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
- 'sockets' => {},
- 'module_name' => 'gpi',
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'cti_i',
- 'bte_i'
- ]
- },
- 'category' => 'GPI',
- 'system_h' => '#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8)))
-#define ${IP}_READ() ${IP}_READ_REG '
- }, 'ip_gen' );
gpi.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ni.IP
===================================================================
--- ni.IP (revision 24)
+++ ni.IP (nonexistent)
@@ -1,590 +0,0 @@
-$ni = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/ni/ni.v',
- '/mpsoc/src_noc/arbiter.v',
- '/mpsoc/src_noc/flit_buffer.v',
- '/mpsoc/src_noc/inout_ports.v',
- '/mpsoc/src_noc/main_comp.v',
- '/mpsoc/src_noc/route_mesh.v',
- '/mpsoc/src_noc/route_torus.v',
- '/mpsoc/src_noc/routing.v'
- ],
- 'ip_name' => 'ni',
- 'description' => 'Network interface',
- 'modules' => {
- 'ni' => {}
- },
- 'plugs' => {
- 'wb_master' => {
- 'wb_master' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'wb_master'
- },
- 'type' => 'num'
- },
- 'interrupt_peripheral' => {
- 'interrupt_peripheral' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'int_peripheral'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- '0' => {
- 'name' => 'clk'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'value' => 1,
- '0' => {
- 'width' => 5,
- 'name' => 'wb_slave',
- 'addr' => '0xb800_0000 0xbfff_ffff custom devices'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'parameters' => {
- 'Dw' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'DEBUG_EN' => {
- 'info' => undef,
- 'deafult' => '0',
- 'global_param' => 1,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'NY' => {
- 'info' => undef,
- 'deafult' => ' 2',
- 'global_param' => 1,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'NX' => {
- 'info' => undef,
- 'deafult' => ' 2',
- 'global_param' => 1,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'V' => {
- 'info' => undef,
- 'deafult' => ' 4',
- 'global_param' => 1,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'Fw' => {
- 'info' => undef,
- 'deafult' => '2+V+Fpay',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 0,
- 'type' => 'Fixed'
- },
- 'COMB_PCK_SIZE_W' => {
- 'info' => undef,
- 'deafult' => '12',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'TAGw' => {
- 'info' => undef,
- 'deafult' => '3',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'M_Aw' => {
- 'info' => undef,
- 'deafult' => '32',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'COMB_MEM_PTR_W' => {
- 'info' => undef,
- 'deafult' => '20',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'ROUTE_NAME' => {
- 'info' => undef,
- 'deafult' => '"XY"',
- 'global_param' => 1,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'Xw ' => {
- 'info' => undef,
- 'deafult' => 'log2(NX)',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 0
- },
- 'Fpay' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => 1,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'SELw' => {
- 'info' => undef,
- 'deafult' => '4 ',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'ROUTE_TYPE' => {
- 'info' => undef,
- 'deafult' => '"DETERMINISTIC"',
- 'global_param' => 1,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'P' => {
- 'info' => undef,
- 'deafult' => ' 5',
- 'global_param' => 1,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'B' => {
- 'info' => undef,
- 'deafult' => ' 4',
- 'global_param' => 1,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'S_Aw' => {
- 'info' => undef,
- 'deafult' => ' 3',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'TOPOLOGY' => {
- 'info' => undef,
- 'deafult' => '"MESH"',
- 'global_param' => 1,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'Xw' => {
- 'info' => undef,
- 'deafult' => 'log2(NX)',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 0
- },
- 'Yw' => {
- 'info' => undef,
- 'deafult' => 'log2(NY)',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 0,
- 'type' => 'Fixed'
- },
- 'Xwj' => {
- 'info' => undef,
- 'deafult' => 'fvf',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- }
- },
- 'parameters_order' => [
- 'V',
- 'P',
- 'B',
- 'NX',
- 'NY',
- 'Fpay',
- 'TOPOLOGY',
- 'ROUTE_TYPE',
- 'ROUTE_NAME',
- 'DEBUG_EN',
- 'COMB_MEM_PTR_W',
- 'COMB_PCK_SIZE_W',
- 'Dw',
- 'S_Aw',
- 'M_Aw',
- 'TAGw',
- 'SELw',
- 'Yw',
- 'Fw',
- 'Xw'
- ],
- 'ports' => {
- 'm_addr_o' => {
- 'intfc_port' => 'adr_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => 'M_Aw-1 : 0',
- 'type' => 'output'
- },
- 'm_cyc_o' => {
- 'intfc_port' => 'cyc_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 's_dat_i' => {
- 'intfc_port' => 'dat_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 's_cyc_i' => {
- 'intfc_port' => 'cyc_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'm_we_o' => {
- 'intfc_port' => 'we_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'credit_out' => {
- 'intfc_port' => 'credit_out',
- 'intfc_name' => 'socket:ni[0]',
- 'range' => 'V-1: 0',
- 'type' => 'output'
- },
- 'flit_in_wr' => {
- 'intfc_port' => 'flit_in_wr',
- 'intfc_name' => 'socket:ni[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 's_dat_o' => {
- 'intfc_port' => 'dat_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 's_addr_i' => {
- 'intfc_port' => 'adr_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'S_Aw-1 : 0',
- 'type' => 'input'
- },
- 'm_ack_i' => {
- 'intfc_port' => 'ack_i',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 's_cti_i' => {
- 'intfc_port' => 'cti_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'input'
- },
- 'current_y' => {
- 'intfc_port' => 'current_y',
- 'intfc_name' => 'socket:ni[0]',
- 'range' => 'Yw-1 : 0',
- 'type' => 'input'
- },
- 's_sel_i' => {
- 'intfc_port' => 'sel_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'SELw-1 : 0',
- 'type' => 'input'
- },
- 's_we_i' => {
- 'intfc_port' => 'we_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'm_stb_o' => {
- 'intfc_port' => 'stb_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 's_stb_i' => {
- 'intfc_port' => 'stb_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'flit_out_wr' => {
- 'intfc_port' => 'flit_out_wr',
- 'intfc_name' => 'socket:ni[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'm_dat_i' => {
- 'intfc_port' => 'dat_i',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'm_dat_o' => {
- 'intfc_port' => 'dat_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 's_err_o' => {
- 'intfc_port' => 'err_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'm_cti_o' => {
- 'intfc_port' => 'cti_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'output'
- },
- 's_ack_o' => {
- 'intfc_port' => 'ack_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'flit_out' => {
- 'intfc_port' => 'flit_out',
- 'intfc_name' => 'socket:ni[0]',
- 'range' => 'Fw-1 : 0',
- 'type' => 'output'
- },
- 'credit_in' => {
- 'intfc_port' => 'credit_in',
- 'intfc_name' => 'socket:ni[0]',
- 'range' => 'V-1 : 0',
- 'type' => 'input'
- },
- 'reset' => {
- 'intfc_port' => 'reset_i',
- 'intfc_name' => 'plug:reset[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'm_err_i' => {
- 'intfc_port' => 'err_i',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'm_rty_i' => {
- 'intfc_port' => 'rty_i',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'm_sel_o' => {
- 'intfc_port' => 'sel_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => 'SELw-1 : 0',
- 'type' => 'output'
- },
- 'flit_in' => {
- 'intfc_port' => 'flit_in',
- 'intfc_name' => 'socket:ni[0]',
- 'range' => 'Fw-1 : 0',
- 'type' => 'input'
- },
- 'current_x' => {
- 'intfc_port' => 'current_x',
- 'intfc_name' => 'socket:ni[0]',
- 'range' => 'Xw-1 : 0',
- 'type' => 'input'
- },
- 'irq' => {
- 'intfc_port' => 'int_o',
- 'intfc_name' => 'plug:interrupt_peripheral[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'clk' => {
- 'intfc_port' => 'clk_i',
- 'intfc_name' => 'plug:clk[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 's_rty_o' => {
- 'intfc_port' => 'rty_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- }
- },
- 'ports_order' => [
- 'reset',
- 'clk',
- 'current_x',
- 'current_y',
- 'flit_out',
- 'flit_out_wr',
- 'credit_in',
- 'flit_in',
- 'flit_in_wr',
- 'credit_out',
- 's_dat_i',
- 's_sel_i',
- 's_addr_i',
- 's_cti_i',
- 's_stb_i',
- 's_cyc_i',
- 's_we_i',
- 's_dat_o',
- 's_ack_o',
- 's_err_o',
- 's_rty_o',
- 'm_sel_o',
- 'm_dat_o',
- 'm_addr_o',
- 'm_cti_o',
- 'm_stb_o',
- 'm_cyc_o',
- 'm_we_o',
- 'm_dat_i',
- 'm_ack_i',
- 'm_err_i',
- 'm_rty_i',
- 'irq'
- ],
- 'sockets' => {
- 'ni' => {
- 'connection_num' => 'single connection',
- '0' => {
- 'name' => 'ni'
- },
- 'value' => 1,
- 'type' => 'num',
- 'ni' => {}
- }
- },
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ni/ni.v',
- 'module_name' => 'ni',
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'tag_i',
- 'bte_i'
- ],
- 'plug:wb_master[0]' => [
- 'tag_o',
- 'bte_o'
- ]
- },
- 'category' => 'NoC',
- 'system_h' => ' #define ${IP}_BASE_ADDR ${BASE}
- #define ${IP}_ST (*((volatile unsigned int *) (${IP}_BASE_ADDR )))
- #define ${IP}_RD (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 )))
- #define ${IP}_WR (*((volatile unsigned int *) (${IP}_BASE_ADDR+8)))
-
-
-
- #define ${IP}_CLASS_IN_HDR_WIDTH 8
- #define ${IP}_DEST_IN_HDR_WIDTH 8
- #define ${IP}_X_Y_IN_HDR_WIDTH 4
-
- #define ${IP}_BUSY (1<<0)
- #define ${IP}_WR_DONE (1<<1)
- #define ${IP}_RD_DONE (1<<2)
- #define ${IP}_RD_OVR_ERR (1<<3)
- #define ${IP}_RD_NPCK_ERR (1<<4)
- #define ${IP}_HAS_PCK (1<<5)
- #define ${IP}_ALL_VCS_FULL (1<<6)
- #define ${IP}_WR_DONE_INT_EN (1<<7)
- #define ${IP}_RD_DONE_INT_EN (1<<8)
- #define ${IP}_RSV_PCK_INT_EN (1<<9)
- #define ${IP}_WR_DONE_ISR (1<<10)
- #define ${IP}_RD_DONE_ISR (1<<11)
- #define ${IP}_RSV_PCK_ISR (1<<12)
-
-
-
- #define ${IP}_PTR_WIDTH 20
- #define ${IP}_PCK_SIZE_WIDTH 12
-
-
-
-
-
-
-
- #define ${IP}_HDR_DEST_CORE_ADDR(DES_X, DES_Y) ((DES_X << ${IP}_X_Y_IN_HDR_WIDTH) | DES_Y)<<(2*${IP}_X_Y_IN_HDR_WIDTH)
- #define ${IP}_HDR_CLASS(pck_class) (pck_class << ( ${IP}_DEST_IN_HDR_WIDTH+ (4* ${IP}_X_Y_IN_HDR_WIDTH)))
-
-
- #define ${IP}_wait_for_sending_pck() while (!(${IP}_ST & ${IP}_WR_DONE))
- #define ${IP}_wait_for_reading_pck() while (!(${IP}_ST & ${IP}_RD_DONE))
-
- #define ${IP}_wait_for_getting_pck() while (!(${IP}_ST & ${IP}_HAS_PCK))
-
-/*****************************************
-void send_pck (unsigned int * pck_buffer, unsigned int data_size);
-sending a packet through NoC network;
-(unsigned int des_x,unsigned int des_y : destination core address;
-unsigned int * pck_buffer : the buffer which hold the packet; The data must start from buff[1];
-unsigned int data_size : the size of data which wanted to be sent out in word = packet_size-1;
-unsigned int class
-
-****************************************/
- inline void ${IP}_send_pck (unsigned int des_x, unsigned int des_y, volatile unsigned int * pck_buffer, unsigned int data_size, unsigned int pck_class){
- pck_buffer [0] = ${IP}_HDR_DEST_CORE_ADDR(des_x, des_y) | ${IP}_HDR_CLASS(pck_class) ;
- ${IP}_WR = (unsigned int) (& pck_buffer [0]) + (data_size<<${IP}_PTR_WIDTH);
- ${IP}_wait_for_sending_pck();
-
- }
-
-/*******************************************
-void save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size);
-save a received packet on pck_buffer
-unsigned int * pck_buffer: the buffer for storing the packet; The read data start from buff[1];
-********************************************/
- inline void ${IP}_save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size){
- ${IP}_RD = (unsigned int) (& pck_buffer [0]) + (buffer_size<<${IP}_PTR_WIDTH);
- ${IP}_wait_for_reading_pck();
- }'
- }, 'ip_gen' );
ni.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: gpo.IP
===================================================================
--- gpo.IP (revision 24)
+++ gpo.IP (nonexistent)
@@ -1,184 +0,0 @@
-$gpo = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/gpio/gpio.v'
- ],
- 'ip_name' => 'gpo',
- 'description' => 'General output port',
- 'plugs' => {
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'wb_slave' => {
- '0' => {
- 'width' => 5,
- 'name' => 'wb',
- 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
- },
- 'value' => 1,
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'modules' => {
- 'gpi' => {},
- 'gpio' => {},
- 'gpo' => {}
- },
- 'parameters' => {
- 'PORT_WIDTH' => {
- 'info' => 'output port width',
- 'deafult' => ' 1',
- 'global_param' => 1,
- 'content' => '1,32,1',
- 'type' => 'Spin-button'
- },
- 'Aw' => {
- 'info' => undef,
- 'deafult' => ' 2',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'SELw' => {
- 'info' => undef,
- 'deafult' => ' 4',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'TAGw' => {
- 'info' => undef,
- 'deafult' => ' 3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- }
- },
- 'ports' => {
- 'sa_tag_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'tag_i',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'sa_rty_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'rty_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_sel_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'sel_i',
- 'range' => 'SELw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'port_o' => {
- 'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
- 'range' => 'PORT_WIDTH-1 : 0',
- 'type' => 'output'
- },
- 'sa_we_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'we_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_cyc_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'cyc_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_err_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'err_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_ack_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'ack_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_addr_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'adr_i',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- },
- 'sa_stb_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'parameters_order' => [
- 'PORT_WIDTH',
- 'Dw',
- 'Aw',
- 'TAGw',
- 'SELw'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
- 'sockets' => {},
- 'module_name' => 'gpo',
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'cti_i',
- 'bte_i'
- ]
- },
- 'category' => 'GPI',
- 'system_h' => '#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4)))
-#define ${IP}_WRITE(value) ${IP}_WRITE_REG=value
-
-'
- }, 'ip_gen' );
gpo.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: altera_jtag_uart.IP
===================================================================
--- altera_jtag_uart.IP (revision 24)
+++ altera_jtag_uart.IP (nonexistent)
@@ -1,187 +0,0 @@
-$altera_jtag_uart_wb = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/jtag/altera_jtag_uart_wb.v'
- ],
- 'ip_name' => 'altera_jtag_uart',
- 'plugs' => {
- 'clk' => {
- 'clk' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
- 'interrupt_peripheral' => {
- 'interrupt_peripheral' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'interrupt_peripheral'
- },
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'value' => 1,
- '0' => {
- 'width' => 5,
- 'name' => 'wb_slave',
- 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'modules' => {
- 'qsys_jtag_uart_0_scfifo_w' => {},
- 'qsys_jtag_uart_0_scfifo_r' => {},
- 'altera_jtag_uart_wb' => {},
- 'qsys_jtag_uart_0' => {},
- 'qsys_jtag_uart_0_sim_scfifo_r' => {},
- 'qsys_jtag_uart_0_sim_scfifo_w' => {}
- },
- 'ports' => {
- 'wb_irq' => {
- 'intfc_name' => 'plug:interrupt_peripheral[0]',
- 'intfc_port' => 'int_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'cyc_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'cyc_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'stb_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'dat_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => ' 31: 0',
- 'type' => 'input'
- },
- 'ack_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'ack_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'rst' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'readyfordata' => {
- 'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
- 'range' => '',
- 'type' => 'output'
- },
- 'dat_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o',
- 'range' => ' 31: 0',
- 'type' => 'output'
- },
- 'adr_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'adr_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'we_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'we_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'dataavailable' => {
- 'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
- 'range' => '',
- 'type' => 'output'
- }
- },
- 'file_name' => '/home/jaytang/Desktop/alisoc/mpsoc/src_peripheral/jtag/altera_jtag_uart_wb.v',
- 'module_name' => 'altera_jtag_uart_wb',
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'err_o',
- 'rty_o',
- 'tag_i',
- 'cti_i',
- 'sel_i',
- 'bte_i'
- ]
- },
- 'category' => 'Jtag',
- 'system_h' => '#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE)))
-#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4)))
-#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000
-#define ${IP}_DATA_RVALID_MSK 0x00008000
-#define ${IP}_DATA_DATA_MSK 0x000000FF
-
-//////////////////////////////*basic function for jtag_uart*////////////////////////////////////////
-void jtag_putchar(char ch);
-char jtag_getchar(void);
-void outbyte(char c){jtag_putchar(c);} //called in xil_printf();
-char inbyte(){return jtag_getchar();}
-
-void jtag_putchar(char ch){ //print one char from jtag_uart
- while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0);
- ${IP}_DATA_REG=ch;
-}
-
-char jtag_getchar(void){ //get one char from jtag_uart
- unsigned int data;
- data=${IP}_DATA_REG;
- while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input
- data=${IP}_DATA_REG;
- return (data&${IP}_DATA_DATA_MSK);
-}
-
-int jtag_scanstr(char* buf){ //scan string until to buf, return str length
- char ch; unsigned int i=0;
- while(1){
- ch=jtag_getchar();
- if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER
- else if(ch==127) { xil_printf("\\b \\b"); if(i>0) i--; } //backspace
- else { jtag_putchar(ch); buf[i]=ch; i++; } //valid
- }
- return i;
-}
-
-int jtag_scanint(int *num){ //return the scanned integer
- unsigned int curr_num,strlen,i=0;
- char* str=(char*)malloc(11); if(str==NULL) { xil_printf("malloc error\\n");return 1; } //allocate memory
- strlen=jtag_scanstr(str); //scan str
- if(strlen>11) { xil_printf("overflows 32-bit integer value\\n");return 1; } //check overflow
- *num=0;
- for(i=0;i9); //not integer: do nothing
- else *num=*num*10+curr_num; //is integer
- }
- return 0;
-}
-/////////////////////////////*END: basic function for jtag_uart*////////////////////////////////////'
- }, 'ip_gen' );
Index: ext_int.IP
===================================================================
--- ext_int.IP (revision 24)
+++ ext_int.IP (nonexistent)
@@ -1,190 +0,0 @@
-$ext_int = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/ext_int/ext_int.v'
- ],
- 'ip_name' => 'ext_int',
- 'plugs' => {
- 'interrupt_peripheral' => {
- 'interrupt_peripheral' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'interrupt'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'value' => 1,
- '0' => {
- 'width' => 5,
- 'name' => 'wb',
- 'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'modules' => {
- 'ext_int' => {}
- },
- 'parameters' => {
- 'Aw' => {
- 'info' => undef,
- 'deafult' => '3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'SELw' => {
- 'info' => undef,
- 'deafult' => '4',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'TAGw' => {
- 'info' => undef,
- 'deafult' => '3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => '32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed'
- },
- 'EXT_INT_NUM' => {
- 'info' => 'number of external interrupt pins.',
- 'deafult' => '3',
- 'global_param' => 0,
- 'content' => '1,32,1',
- 'type' => 'Spin-button'
- }
- },
- 'ports' => {
- 'sa_tag_i' => {
- 'intfc_port' => 'tag_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'input'
- },
- 'sa_rty_o' => {
- 'intfc_port' => 'rty_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_dat_o' => {
- 'intfc_port' => 'dat_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'sa_sel_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'sel_i',
- 'range' => 'SELw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'ext_int_o' => {
- 'intfc_name' => 'plug:interrupt_peripheral[0]',
- 'intfc_port' => 'int_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_we_i' => {
- 'intfc_port' => 'we_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_cyc_i' => {
- 'intfc_port' => 'cyc_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_err_o' => {
- 'intfc_port' => 'err_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_ack_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'ack_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'ext_int_i' => {
- 'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
- 'range' => 'EXT_INT_NUM-1 : 0',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'reset' => {
- 'intfc_port' => 'reset_i',
- 'intfc_name' => 'plug:reset[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_addr_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'adr_i',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- },
- 'sa_stb_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ext_int/ext_int.v',
- 'sockets' => {},
- 'module_name' => 'ext_int',
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'cti_i',
- 'bte_i'
- ]
- },
- 'category' => 'interrupt',
- 'system_h' => '
- #define ${IP}_GER (*((volatile unsigned int *) ($BASE )))
- #define ${IP}_IER_RISE (*((volatile unsigned int *) ($BASE+4 )))
- #define ${IP}_IER_FALL (*((volatile unsigned int *) ($BASE+8 )))
- #define ${IP}_ISR (*((volatile unsigned int *) ($BASE+12 )))
- #define ${IP}_RD (*((volatile unsigned int *) ($BASE+16 )))'
- }, 'ip_gen' );
ext_int.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: jtag_intfc.IP
===================================================================
--- jtag_intfc.IP (revision 24)
+++ jtag_intfc.IP (nonexistent)
@@ -1,350 +0,0 @@
-$jtag_intfc = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/jtag/jtag_intfc.v'
- ],
- 'ip_name' => 'jtag_intfc',
- 'plugs' => {
- 'wb_master' => {
- 'wb_master' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'wb_master'
- },
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'value' => 1,
- '0' => {
- 'width' => 12,
- 'name' => 'wb_slave',
- 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'parameters' => {
- 'WR_RAM_TAG' => {
- 'info' => undef,
- 'deafult' => '"J_WR"',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'NI_BASE_ADDR' => {
- 'info' => undef,
- 'deafult' => 'ni0_BASE_ADDR',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'SELw' => {
- 'info' => undef,
- 'deafult' => '4',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => '32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'WR_RAMw' => {
- 'info' => undef,
- 'deafult' => '8',
- 'global_param' => 1,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'S_Aw' => {
- 'info' => undef,
- 'deafult' => 'WR_RAMw+1',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'TAGw' => {
- 'info' => undef,
- 'deafult' => '3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'JTAG_BASE_ADDR' => {
- 'info' => undef,
- 'deafult' => 'jtag_intfc0_BASE_ADDR',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'M_Aw' => {
- 'info' => undef,
- 'deafult' => '32',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'RD_RAM_TAG' => {
- 'info' => undef,
- 'deafult' => '"J_RD"',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- }
- },
- 'modules' => {
- 'jtag_intfc' => {},
- 'jtag_sp' => {}
- },
- 'ports' => {
- 'm_dat_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'm_addr_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'adr_o',
- 'range' => 'M_Aw-1 : 0',
- 'type' => 'output'
- },
- 'm_dat_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'm_cyc_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'cyc_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset_all_o' => {
- 'intfc_name' => 'socket:reset[0]',
- 'intfc_port' => 'reset_o',
- 'range' => '',
- 'type' => 'output'
- },
- 's_cyc_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'cyc_i',
- 'range' => '',
- 'type' => 'input'
- },
- 's_dat_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 's_err_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'err_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset_cpus_o' => {
- 'intfc_name' => 'socket:reset[1]',
- 'intfc_port' => 'reset_o',
- 'range' => '',
- 'type' => 'output'
- },
- 's_ack_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'ack_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'm_we_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'we_o',
- 'range' => '',
- 'type' => 'output'
- },
- 's_tag_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'tag_i',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'input'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'm_err_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'err_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'm_ack_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'ack_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'm_rty_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'rty_i',
- 'range' => '',
- 'type' => 'input'
- },
- 's_addr_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'adr_i',
- 'range' => 'S_Aw-1 : 0',
- 'type' => 'input'
- },
- 's_dat_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'm_sel_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'sel_o',
- 'range' => 'SELw-1 : 0',
- 'type' => 'output'
- },
- 's_sel_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'sel_i',
- 'range' => 'SELw-1 : 0',
- 'type' => 'input'
- },
- 'm_stb_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'stb_o',
- 'range' => '',
- 'type' => 'output'
- },
- 's_we_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'we_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'm_tag_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'tag_o',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'output'
- },
- 'irq' => {
- 'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
- 'range' => '',
- 'type' => 'output'
- },
- 's_stb_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 's_rty_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'rty_o',
- 'range' => '',
- 'type' => 'output'
- }
- },
- 'parameters_order' => [
- 'NI_BASE_ADDR',
- 'JTAG_BASE_ADDR',
- 'WR_RAM_TAG',
- 'RD_RAM_TAG',
- 'WR_RAMw',
- 'Dw',
- 'S_Aw',
- 'M_Aw',
- 'TAGw',
- 'SELw'
- ],
- 'ports_order' => [
- 's_dat_i',
- 's_sel_i',
- 's_addr_i',
- 's_tag_i',
- 's_stb_i',
- 's_cyc_i',
- 's_we_i',
- 's_dat_o',
- 's_ack_o',
- 's_err_o',
- 's_rty_o',
- 'm_sel_o',
- 'm_dat_o',
- 'm_addr_o',
- 'm_tag_o',
- 'm_stb_o',
- 'm_cyc_o',
- 'm_we_o',
- 'm_dat_i',
- 'm_ack_i',
- 'm_err_i',
- 'm_rty_i',
- 'irq',
- 'reset_all_o',
- 'reset_cpus_o',
- 'reset',
- 'clk'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/jtag/jtag_intfc.v',
- 'sockets' => {
- 'reset' => {
- '1' => {
- 'name' => 'reset_cpus'
- },
- 'reset' => {},
- 'connection_num' => 'multi connection',
- 'value' => 2,
- '0' => {
- 'name' => 'reset_all'
- },
- 'type' => 'num'
- }
- },
- 'module_name' => 'jtag_intfc',
- 'category' => 'Jtag'
- }, 'ip_gen' );
Index: Altera_single_port_ram.IP
===================================================================
--- Altera_single_port_ram.IP (revision 24)
+++ Altera_single_port_ram.IP (nonexistent)
@@ -1,225 +0,0 @@
-$Altera_single_port_ram = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/ram/Altera_single_port_ram.v'
- ],
- 'ip_name' => 'Altera_single_port_ram',
- 'parameters' => {
- 'RAM_TAG_STRING' => {
- 'info' => undef,
- 'deafult' => 'i2s(CORE_ID)',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Entry',
- 'redefine_param' => 1
- },
- 'SELw' => {
- 'info' => undef,
- 'deafult' => '4',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'type' => 'Fixed'
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => '32',
- 'global_param' => 1,
- 'content' => '8,1024,1',
- 'type' => 'Spin-button',
- 'redefine_param' => 1
- },
- 'WBAw' => {
- 'info' => undef,
- 'deafult' => 'Aw+2',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 0
- },
- 'BTEw' => {
- 'info' => undef,
- 'deafult' => '2',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'Aw' => {
- 'info' => undef,
- 'deafult' => '10',
- 'global_param' => 1,
- 'content' => '4,31,1',
- 'redefine_param' => 1,
- 'type' => 'Spin-button'
- },
- 'TAGw' => {
- 'info' => undef,
- 'deafult' => '3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'CTIw' => {
- 'info' => undef,
- 'deafult' => '3',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- }
- },
- 'plugs' => {
- 'clk' => {
- 'clk' => {},
- '0' => {
- 'name' => 'clk'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
- 'wb_slave' => {
- 'value' => 1,
- '0' => {
- 'width' => 'WBAw',
- 'name' => 'wb_slave',
- 'addr' => '0x0000_0000 0x3fff_ffff RAM'
- },
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'modules' => {
- 'Altera_single_port_ram' => {}
- },
- 'ports' => {
- 'sa_tag_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'tag_i',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- },
- 'sa_rty_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'rty_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_cti_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'cti_i',
- 'range' => 'CTIw-1 : 0',
- 'type' => 'input'
- },
- 'sa_sel_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'sel_i',
- 'range' => 'SELw-1 : 0',
- 'type' => 'input'
- },
- 'sa_bte_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'bte_i',
- 'range' => 'BTEw-1 : 0',
- 'type' => 'input'
- },
- 'sa_dat_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
- 'type' => 'input'
- },
- 'sa_we_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'we_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_cyc_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'cyc_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_err_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'err_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sa_ack_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'ack_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_addr_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'adr_i',
- 'range' => 'Aw-1 : 0',
- 'type' => 'input'
- },
- 'sa_stb_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- }
- },
- 'parameters_order' => [
- 'Dw',
- 'Aw',
- 'TAGw',
- 'SELw',
- 'CTIw',
- 'BTEw',
- 'RAM_TAG_STRING',
- 'WBAw'
- ],
- 'ports_order' => [
- 'clk',
- 'reset',
- 'sa_dat_i',
- 'sa_sel_i',
- 'sa_addr_i',
- 'sa_tag_i',
- 'sa_cti_i',
- 'sa_bte_i',
- 'sa_stb_i',
- 'sa_cyc_i',
- 'sa_we_i',
- 'sa_dat_o',
- 'sa_ack_o',
- 'sa_err_o',
- 'sa_rty_o'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/Altera_single_port_ram.v',
- 'module_name' => 'Altera_single_port_ram',
- 'category' => 'RAM'
- }, 'ip_gen' );
Index: Bus/wishbone_bus.IP
===================================================================
--- Bus/wishbone_bus.IP (nonexistent)
+++ Bus/wishbone_bus.IP (revision 25)
@@ -0,0 +1,369 @@
+#######################################################################
+## File: wishbone_bus.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$wishbone_bus = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/bus/wishbone_bus.v',
+ '/mpsoc/src_noc/main_comp.v',
+ '/mpsoc/src_noc/arbiter.v'
+ ],
+ 'ip_name' => 'wishbone_bus',
+ 'description' => 'wishbone bus',
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'parameters' => {
+ 'S' => {
+ 'info' => 'Number of wishbone slave interface',
+ 'deafult' => '4',
+ 'global_param' => 'Localparam',
+ 'content' => '1,256,1',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1
+ },
+ 'SELw' => {
+ 'info' => undef,
+ 'deafult' => 'Dw/8',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'Dw' => {
+ 'info' => 'The wishbone Bus data width in bits.',
+ 'deafult' => '32',
+ 'global_param' => 'Localparam',
+ 'content' => '8,512,8',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1
+ },
+ 'BTEw' => {
+ 'info' => undef,
+ 'deafult' => '2 ',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'M' => {
+ 'info' => 'Number of wishbone master interface',
+ 'deafult' => ' 4',
+ 'global_param' => 'Localparam',
+ 'content' => '1,256,1',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1
+ },
+ 'Aw' => {
+ 'info' => 'The wishbone Bus address width',
+ 'deafult' => '32',
+ 'global_param' => 'Localparam',
+ 'content' => '4,128,1',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1
+ },
+ 'TAGw' => {
+ 'info' => undef,
+ 'deafult' => '3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'CTIw' => {
+ 'info' => undef,
+ 'deafult' => '3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ }
+ },
+ 'modules' => {
+ 'wishbone_bus' => {},
+ 'bus_arbiter' => {}
+ },
+ 'plugs' => {
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ }
+ },
+ 'ports_order' => [
+ 's_adr_o_all',
+ 's_dat_o_all',
+ 's_sel_o_all',
+ 's_tag_o_all',
+ 's_we_o_all',
+ 's_cyc_o_all',
+ 's_stb_o_all',
+ 's_cti_o_all',
+ 's_bte_o_all',
+ 's_dat_i_all',
+ 's_ack_i_all',
+ 's_err_i_all',
+ 's_rty_i_all',
+ 'm_dat_o_all',
+ 'm_ack_o_all',
+ 'm_err_o_all',
+ 'm_rty_o_all',
+ 'm_adr_i_all',
+ 'm_dat_i_all',
+ 'm_sel_i_all',
+ 'm_tag_i_all',
+ 'm_we_i_all',
+ 'm_stb_i_all',
+ 'm_cyc_i_all',
+ 'm_cti_i_all',
+ 'm_bte_i_all',
+ 'm_grant_addr',
+ 's_sel_one_hot',
+ 'clk',
+ 'reset'
+ ],
+ 'parameters_order' => [
+ 'M',
+ 'S',
+ 'Dw',
+ 'Aw',
+ 'SELw',
+ 'TAGw',
+ 'CTIw',
+ 'BTEw'
+ ],
+ 'ports' => {
+ 's_sel_o_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'sel_o',
+ 'range' => 'SELw*S-1 : 0',
+ 'type' => 'output'
+ },
+ 's_adr_o_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'adr_o',
+ 'range' => 'Aw*S-1 : 0',
+ 'type' => 'output'
+ },
+ 's_dat_o_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw*S-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_cyc_i_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'cyc_i',
+ 'range' => 'M-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_grant_addr' => {
+ 'intfc_name' => 'socket:wb_addr_map[0]',
+ 'intfc_port' => 'grant_addr',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_bte_o_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'bte_o',
+ 'range' => 'BTEw*S-1 : 0',
+ 'type' => 'output'
+ },
+ 's_ack_i_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'ack_i',
+ 'range' => 'S-1 : 0',
+ 'type' => 'input'
+ },
+ 's_cti_o_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'cti_o',
+ 'range' => 'CTIw*S-1 : 0',
+ 'type' => 'output'
+ },
+ 's_tag_o_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'tag_o',
+ 'range' => 'TAGw*S-1 : 0',
+ 'type' => 'output'
+ },
+ 's_err_i_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'err_i',
+ 'range' => 'S-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_stb_i_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'stb_i',
+ 'range' => 'M-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_ack_o_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'ack_o',
+ 'range' => 'M-1 : 0',
+ 'type' => 'output'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_cyc_o_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'cyc_o',
+ 'range' => 'S-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_adr_i_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'adr_i',
+ 'range' => 'Aw*M-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_rty_o_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'rty_o',
+ 'range' => 'M-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_dat_o_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw*M-1 : 0',
+ 'type' => 'output'
+ },
+ 's_we_o_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'we_o',
+ 'range' => 'S-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_dat_i_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw*M-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_bte_i_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'bte_i',
+ 'range' => 'BTEw*M-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_err_o_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'err_o',
+ 'range' => 'M-1 : 0',
+ 'type' => 'output'
+ },
+ 's_rty_i_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'rty_i',
+ 'range' => 'S-1 : 0',
+ 'type' => 'input'
+ },
+ 's_stb_o_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'stb_o',
+ 'range' => 'S-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_tag_i_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'tag_i',
+ 'range' => 'TAGw*M-1 : 0',
+ 'type' => 'input'
+ },
+ 's_dat_i_all' => {
+ 'intfc_name' => 'socket:wb_slave[array]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw*S-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_sel_i_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'sel_i',
+ 'range' => 'SELw*M-1 : 0',
+ 'type' => 'input'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_cti_i_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'cti_i',
+ 'range' => 'CTIw*M-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_we_i_all' => {
+ 'intfc_name' => 'socket:wb_master[array]',
+ 'intfc_port' => 'we_i',
+ 'range' => 'M-1 : 0',
+ 'type' => 'input'
+ },
+ 's_sel_one_hot' => {
+ 'intfc_name' => 'socket:wb_addr_map[0]',
+ 'intfc_port' => 'sel_one_hot',
+ 'range' => 'S-1 : 0',
+ 'type' => 'input'
+ }
+ },
+ 'sockets' => {
+ 'wb_master' => {
+ 'wb_master' => {},
+ 'connection_num' => 'single connection',
+ 'value' => 'M',
+ '0' => {
+ 'name' => 'wb_master'
+ },
+ 'type' => 'param'
+ },
+ 'wb_addr_map' => {
+ 'connection_num' => 'single connection',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'wb_addr_map'
+ },
+ 'wb_addr_map' => {},
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'connection_num' => 'single connection',
+ 'value' => 'S',
+ '0' => {
+ 'name' => 'wb_slave'
+ },
+ 'type' => 'param',
+ 'wb_slave' => {}
+ }
+ },
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/bus/wishbone_bus.v',
+ 'module_name' => 'wishbone_bus',
+ 'unused' => undef,
+ 'category' => 'Bus'
+ }, 'ip_gen' );
Bus/wishbone_bus.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Display/lcd_2x16.IP
===================================================================
--- Display/lcd_2x16.IP (nonexistent)
+++ Display/lcd_2x16.IP (revision 25)
@@ -0,0 +1,205 @@
+#######################################################################
+## File: lcd_2x16.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$lcd_2x16 = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v'
+ ],
+ 'system_h' => '#define ${IP}_WR_CMD (*((volatile unsigned int *) ($BASE)))
+#define ${IP}_RD_CMD (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_WR_DATA (*((volatile unsigned int *) ($BASE+8)))
+#define ${IP}_RD_DATA (*((volatile unsigned int *) ($BASE+16)))
+
+#define ${IP}_CLK_MHZ $CLK_MHZ
+
+#include "$IP.h"',
+ 'ip_name' => 'lcd_2x16',
+ 'sw_params_list' => [],
+ 'parameters_order' => [
+ 'Dw',
+ 'Aw',
+ 'CLK_MHZ'
+ ],
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 's_dat_i',
+ 's_addr_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 'lcd_en',
+ 'lcd_rs',
+ 'lcd_rw',
+ 'lcd_data'
+ ],
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v',
+ 'module_name' => 'lcd_2x16',
+ 'gen_sw_files' => [
+ '/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16frename_sep_t${IP}.h'
+ ],
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'err_o',
+ 'rty_o',
+ 'tag_i',
+ 'cti_i',
+ 'sel_i',
+ 'bte_i'
+ ]
+ },
+ 'category' => 'Display',
+ 'sw_files' => [],
+ 'description' => 'Alphabet Display LCD 2x16',
+ 'modules' => {
+ 'lcd_2x16' => {}
+ },
+ 'plugs' => {
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ '0' => {
+ 'width' => 5,
+ 'name' => 'wb',
+ 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
+ },
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'parameters' => {
+ 'Aw' => {
+ 'info' => undef,
+ 'deafult' => ' 2',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'Dw' => {
+ 'info' => undef,
+ 'deafult' => ' 8',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'CLK_MHZ' => {
+ 'info' => 'The LCD controller clock speed in MHZ. It will be used for measuring the lcd enable delay. You can define a larger value than the actual clk speed but not smaller.',
+ 'deafult' => '100',
+ 'global_param' => 0,
+ 'content' => '2,1000,2',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1
+ }
+ },
+ 'ports' => {
+ 's_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cyc_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_dat_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'lcd_en' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 's_ack_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 's_we_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'we_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'lcd_data' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => ' 7: 0',
+ 'type' => 'inout'
+ },
+ 'lcd_rs' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'lcd_rw' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_addr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_dat_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ }
+ }
+ }, 'ip_gen' );
Display/lcd_2x16.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Eth/ethmac_100.IP
===================================================================
--- Eth/ethmac_100.IP (nonexistent)
+++ Eth/ethmac_100.IP (revision 25)
@@ -0,0 +1,466 @@
+#######################################################################
+## File: ethmac_100.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ethtop = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_clockgen.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_cop.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_crc.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/ethmac.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_maccontrol.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/ethmac_defines.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_macstatus.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_miim.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_outputcontrol.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_random.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_receivecontrol.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_register.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_registers.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_rxaddrcheck.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_rxcounters.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_rxethmac.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_rxstatem.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_shiftreg.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_spram_256x32.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_top.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_transmitcontrol.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_txcounters.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_txethmac.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_txstatem.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_wishbone.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/timescale.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/xilinx_dist_ram_16x32.v',
+ '/mpsoc/src_peripheral/ram/general_single_port_ram.v',
+ '/mpsoc/src_peripheral/ram/general_dual_port_ram.v',
+ '/mpsoc/src_peripheral/ethmac/ethtop.v'
+ ],
+ 'custom_file' => {
+ '0' => {}
+ },
+ 'system_h' => '
+
+void ${IP}_init();
+void ${IP}_interrupt();
+void ${IP}_recv_ack(void);
+int ${IP}_send(int length); //return (-1) or length (still processing previous) or asserted
+
+#define ${IP}_BASE_ADDR $BASE
+#define ${IP}_MODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x00 )))
+#define ${IP}_INT_SOURCE (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x04 )))
+#define ${IP}_INT_MASK (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x08 )))
+#define ${IP}_IPGT (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x0C )))
+#define ${IP}_IPGR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x10 )))
+#define ${IP}_IPGR2 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x14 )))
+#define ${IP}_PACKETLEN (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x18 )))
+#define ${IP}_COLLCONF (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x1C )))
+#define ${IP}_TX_BD_NUM (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x20 )))
+#define ${IP}_CTRLMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x24 )))
+#define ${IP}_MIIMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x28 )))
+#define ${IP}_MIICOMMAND (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x2C )))
+#define ${IP}_MIIADDR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x30 )))
+#define ${IP}_MIITX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x34 )))
+#define ${IP}_MIIRX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x38 )))
+#define ${IP}_MIISTATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x3C )))
+#define ${IP}_MAC_ADDR0 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x40 )))
+#define ${IP}_MAC_ADDR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x44 )))
+#define ${IP}_HASH0_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x48 )))
+#define ${IP}_HASH1_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x4C )))
+#define ${IP}_TXCTRL (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x50 )))
+#define ${IP}_TXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x404 )))
+#define ${IP}_TXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x400 )))
+#define ${IP}_RXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value
+#define ${IP}_RXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value
+
+
+#include "${IP}.h"',
+ 'ip_name' => 'ethmac_100',
+ 'custom_file_num' => 1,
+ 'ports_order' => [
+ 'wb_clk_i',
+ 'wb_rst_i',
+ 'wb_dat_i',
+ 'wb_dat_o',
+ 'wb_adr_i',
+ 'wb_sel_i',
+ 'wb_we_i',
+ 'wb_cyc_i',
+ 'wb_stb_i',
+ 'wb_ack_o',
+ 'wb_err_o',
+ 'm_wb_adr_o',
+ 'm_wb_sel_o',
+ 'm_wb_we_o',
+ 'm_wb_dat_o',
+ 'm_wb_dat_i',
+ 'm_wb_cyc_o',
+ 'm_wb_stb_o',
+ 'm_wb_ack_i',
+ 'm_wb_err_i',
+ 'mtx_clk_pad_i',
+ 'mtxd_pad_o',
+ 'mtxen_pad_o',
+ 'mtxerr_pad_o',
+ 'mrx_clk_pad_i',
+ 'mrxd_pad_i',
+ 'mrxdv_pad_i',
+ 'mrxerr_pad_i',
+ 'mcoll_pad_i',
+ 'mcrs_pad_i',
+ 'mdc_pad_o',
+ 'md_pad_i',
+ 'md_pad_o',
+ 'md_padoe_o',
+ 'int_o'
+ ],
+ 'parameters_order' => [
+ 'TX_FIFO_DATA_WIDTH',
+ 'TX_FIFO_DEPTH',
+ 'TX_FIFO_CNT_WIDTH',
+ 'RX_FIFO_DATA_WIDTH',
+ 'RX_FIFO_DEPTH',
+ 'RX_FIFO_CNT_WIDTH'
+ ],
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ethmac/ethtop.v',
+ 'module_name' => 'ethtop',
+ 'gen_sw_files' => [
+ '/mpsoc/src_peripheral/ethmac/ethfrename_sep_t${IP}.h'
+ ],
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'rty_o',
+ 'tag_i',
+ 'cti_i',
+ 'bte_i'
+ ],
+ 'plug:wb_master[0]' => [
+ 'tag_o',
+ 'bte_o',
+ 'cti_o',
+ 'rty_i'
+ ]
+ },
+ 'category' => 'Eth',
+ 'sw_files' => [],
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'parameters' => {
+ 'RX_FIFO_DEPTH' => {
+ 'info' => undef,
+ 'deafult' => ' 16',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'TX_FIFO_DATA_WIDTH' => {
+ 'info' => undef,
+ 'deafult' => ' 32',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'RX_FIFO_DATA_WIDTH' => {
+ 'info' => undef,
+ 'deafult' => ' 32',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'RX_FIFO_CNT_WIDTH' => {
+ 'info' => undef,
+ 'deafult' => ' 5',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'TX_FIFO_CNT_WIDTH' => {
+ 'info' => undef,
+ 'deafult' => ' 5',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'TX_FIFO_DEPTH' => {
+ 'info' => undef,
+ 'deafult' => ' 16',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ }
+ },
+ 'modules' => {
+ 'ethtop' => {}
+ },
+ 'plugs' => {
+ 'wb_master' => {
+ 'wb_master' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'wb_master'
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ },
+ 'interrupt_peripheral' => {
+ 'interrupt_peripheral' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'interrupt_peripheral'
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ '0' => {
+ 'width' => 11,
+ 'name' => 'wb_slave',
+ 'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller'
+ },
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'ports' => {
+ 'wb_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'sel_i',
+ 'range' => '3:0',
+ 'type' => 'input'
+ },
+ 'm_wb_we_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'we_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'wb_err_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'err_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'wb_we_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'we_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'wb_dat_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'wb_rst_i' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'wb_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cyc_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_wb_err_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'err_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_wb_dat_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => '31:0',
+ 'type' => 'input'
+ },
+ 'mdc_pad_o' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_wb_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'sel_o',
+ 'range' => '3:0',
+ 'type' => 'output'
+ },
+ 'md_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'mcrs_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_wb_dat_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'md_padoe_o' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_wb_adr_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'adr_o',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'wb_adr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'range' => '9:0',
+ 'type' => 'input'
+ },
+ 'mrxerr_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'mrxd_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '3:0',
+ 'type' => 'input'
+ },
+ 'mtxd_pad_o' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '3:0',
+ 'type' => 'output'
+ },
+ 'wb_ack_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'mtxen_pad_o' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'mcoll_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'int_o' => {
+ 'intfc_name' => 'plug:interrupt_peripheral[0]',
+ 'intfc_port' => 'int_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_wb_ack_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'ack_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'wb_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'mrx_clk_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'wb_clk_i' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'md_pad_o' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_wb_cyc_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cyc_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'mrxdv_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'mtxerr_pad_o' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'mtx_clk_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'wb_dat_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => '31:0',
+ 'type' => 'input'
+ },
+ 'm_wb_stb_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'stb_o',
+ 'range' => '',
+ 'type' => 'output'
+ }
+ }
+ }, 'ip_gen' );
Eth/ethmac_100.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: GPIO/gpi.IP
===================================================================
--- GPIO/gpi.IP (nonexistent)
+++ GPIO/gpi.IP (revision 25)
@@ -0,0 +1,202 @@
+#######################################################################
+## File: gpi.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$gpi = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/gpio/gpio.v'
+ ],
+ 'system_h' => '#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8)))
+#define ${IP}_READ() ${IP}_READ_REG ',
+ 'ip_name' => 'gpi',
+ 'description' => 'General inout port',
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'plugs' => {
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ '0' => {
+ 'width' => 5,
+ 'name' => 'wb',
+ 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
+ },
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'parameters' => {
+ 'PORT_WIDTH' => {
+ 'info' => 'Input port width ',
+ 'deafult' => ' 1',
+ 'global_param' => 'Parameter',
+ 'content' => '1,32,1',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1
+ },
+ 'Aw' => {
+ 'info' => undef,
+ 'deafult' => ' 2',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'SELw' => {
+ 'info' => undef,
+ 'deafult' => ' 4',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'TAGw' => {
+ 'info' => undef,
+ 'deafult' => ' 3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Dw' => {
+ 'info' => undef,
+ 'deafult' => 'PORT_WIDTH',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ }
+ },
+ 'modules' => {
+ 'gpi' => {},
+ 'gpo' => {},
+ 'gpio' => {}
+ },
+ 'parameters_order' => [
+ 'PORT_WIDTH',
+ 'Dw',
+ 'Aw',
+ 'TAGw',
+ 'SELw'
+ ],
+ 'ports' => {
+ 'sa_tag_i' => {
+ 'intfc_port' => 'tag_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_rty_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'rty_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 'sa_sel_i' => {
+ 'intfc_port' => 'sel_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_we_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'we_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cyc_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_err_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'err_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_ack_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'port_i' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'range' => 'PORT_WIDTH-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_addr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_stb_i' => {
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'sockets' => {},
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
+ 'module_name' => 'gpi',
+ 'category' => 'GPIO',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'cti_i',
+ 'bte_i'
+ ]
+ }
+ }, 'ip_gen' );
GPIO/gpi.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: GPIO/gpio.IP
===================================================================
--- GPIO/gpio.IP (nonexistent)
+++ GPIO/gpio.IP (revision 25)
@@ -0,0 +1,189 @@
+#######################################################################
+## File: gpio.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$gpio = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/gpio/gpio.v'
+ ],
+ 'system_h' => '#define ${IP}_DIR_REG (*((volatile unsigned int *) ($BASE)))
+#define ${IP}_WRITE _REG (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8)))
+
+ #define ${IP}_DIR_SET(value) ${IP}_DIR_REG=value
+#define ${IP}_WRITE(value) ${IP}_WRITE _REG=value
+#define ${IP}_READ() ${IP}_READ_REG ',
+ 'ip_name' => 'gpio',
+ 'description' => 'General inout port',
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'parameters' => {
+ 'PORT_WIDTH' => {
+ 'info' => undef,
+ 'deafult' => '1',
+ 'global_param' => 'Parameter',
+ 'content' => '1,32,1',
+ 'redefine_param' => 1,
+ 'type' => 'Spin-button'
+ },
+ 'Aw' => {
+ 'info' => undef,
+ 'deafult' => '2',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'SELw' => {
+ 'info' => undef,
+ 'deafult' => '4',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Dw' => {
+ 'info' => undef,
+ 'deafult' => 'PORT_WIDTH',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ }
+ },
+ 'plugs' => {
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ '0' => {
+ 'width' => 5,
+ 'name' => 'wb',
+ 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
+ },
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'modules' => {
+ 'gpi' => {},
+ 'gpio' => {},
+ 'gpo' => {}
+ },
+ 'parameters_order' => [
+ 'PORT_WIDTH',
+ 'Dw',
+ 'Aw',
+ 'SELw',
+ 'Dw'
+ ],
+ 'ports' => {
+ 'sa_rty_o' => {
+ 'intfc_port' => 'rty_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'port_io' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'range' => 'PORT_WIDTH-1 : 0',
+ 'type' => 'inout'
+ },
+ 'sa_dat_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 'sa_sel_i' => {
+ 'intfc_port' => 'sel_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_dat_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_we_i' => {
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_err_o' => {
+ 'intfc_port' => 'err_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_addr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
+ 'sockets' => {},
+ 'module_name' => 'gpio',
+ 'category' => 'GPIO',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'cyc_i',
+ 'tag_i',
+ 'cti_i',
+ 'bte_i'
+ ]
+ }
+ }, 'ip_gen' );
GPIO/gpio.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: GPIO/gpo.IP
===================================================================
--- GPIO/gpo.IP (nonexistent)
+++ GPIO/gpo.IP (revision 25)
@@ -0,0 +1,204 @@
+#######################################################################
+## File: gpo.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$gpo = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/gpio/gpio.v'
+ ],
+ 'system_h' => '#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_WRITE(value) ${IP}_WRITE_REG=value
+
+',
+ 'description' => 'General output port',
+ 'ip_name' => 'gpo',
+ 'plugs' => {
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ '0' => {
+ 'width' => 5,
+ 'name' => 'wb',
+ 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
+ },
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'modules' => {
+ 'gpi' => {},
+ 'gpio' => {},
+ 'gpo' => {}
+ },
+ 'parameters' => {
+ 'PORT_WIDTH' => {
+ 'info' => 'output port width',
+ 'deafult' => ' 1',
+ 'global_param' => 'Parameter',
+ 'content' => '1,32,1',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1
+ },
+ 'Aw' => {
+ 'info' => undef,
+ 'deafult' => ' 2',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'TAGw' => {
+ 'info' => undef,
+ 'deafult' => ' 3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'SELw' => {
+ 'info' => undef,
+ 'deafult' => ' 4',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Dw' => {
+ 'info' => undef,
+ 'deafult' => 'PORT_WIDTH',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ }
+ },
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'parameters_order' => [
+ 'PORT_WIDTH',
+ 'Aw',
+ 'TAGw',
+ 'SELw',
+ 'Dw'
+ ],
+ 'ports' => {
+ 'sa_tag_i' => {
+ 'intfc_port' => 'tag_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_rty_o' => {
+ 'intfc_port' => 'rty_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_dat_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 'sa_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'sel_i',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_dat_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'port_o' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'range' => 'PORT_WIDTH-1 : 0',
+ 'type' => 'output'
+ },
+ 'sa_we_i' => {
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cyc_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_err_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'err_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_ack_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_addr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_stb_i' => {
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
+ 'sockets' => {},
+ 'module_name' => 'gpo',
+ 'category' => 'GPIO',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'cti_i',
+ 'bte_i'
+ ]
+ }
+ }, 'ip_gen' );
GPIO/gpo.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Interrupt/ext_int.IP
===================================================================
--- Interrupt/ext_int.IP (nonexistent)
+++ Interrupt/ext_int.IP (revision 25)
@@ -0,0 +1,212 @@
+#######################################################################
+## File: ext_int.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ext_int = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/ext_int/ext_int.v'
+ ],
+ 'system_h' => '
+ #define ${IP}_GER (*((volatile unsigned int *) ($BASE )))
+ #define ${IP}_IER_RISE (*((volatile unsigned int *) ($BASE+4 )))
+ #define ${IP}_IER_FALL (*((volatile unsigned int *) ($BASE+8 )))
+ #define ${IP}_ISR (*((volatile unsigned int *) ($BASE+12 )))
+ #define ${IP}_RD (*((volatile unsigned int *) ($BASE+16 )))',
+ 'ip_name' => 'ext_int',
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'plugs' => {
+ 'interrupt_peripheral' => {
+ 'interrupt_peripheral' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'interrupt'
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ '0' => {
+ 'width' => 5,
+ 'name' => 'wb',
+ 'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller'
+ },
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'modules' => {
+ 'ext_int' => {}
+ },
+ 'parameters' => {
+ 'Aw' => {
+ 'info' => undef,
+ 'deafult' => '3',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed'
+ },
+ 'SELw' => {
+ 'info' => undef,
+ 'deafult' => '4',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed'
+ },
+ 'TAGw' => {
+ 'info' => undef,
+ 'deafult' => '3',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed'
+ },
+ 'Dw' => {
+ 'info' => undef,
+ 'deafult' => '32',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed'
+ },
+ 'EXT_INT_NUM' => {
+ 'info' => 'number of external interrupt pins.',
+ 'deafult' => '3',
+ 'global_param' => 0,
+ 'content' => '1,32,1',
+ 'type' => 'Spin-button'
+ }
+ },
+ 'parameters_order' => [
+ 'Dw',
+ 'Aw',
+ 'TAGw',
+ 'SELw',
+ 'EXT_INT_NUM'
+ ],
+ 'ports' => {
+ 'sa_tag_i' => {
+ 'intfc_port' => 'tag_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_rty_o' => {
+ 'intfc_port' => 'rty_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 'sa_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'sel_i',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_dat_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'ext_int_o' => {
+ 'intfc_name' => 'plug:interrupt_peripheral[0]',
+ 'intfc_port' => 'int_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_we_i' => {
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_cyc_i' => {
+ 'intfc_port' => 'cyc_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_err_o' => {
+ 'intfc_port' => 'err_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_ack_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'ext_int_i' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => 'EXT_INT_NUM-1 : 0',
+ 'type' => 'input'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_addr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'sockets' => {},
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ext_int/ext_int.v',
+ 'module_name' => 'ext_int',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'cti_i',
+ 'bte_i'
+ ]
+ },
+ 'category' => 'Interrupt'
+ }, 'ip_gen' );
Interrupt/ext_int.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Interrupt/int_ctrl.IP
===================================================================
--- Interrupt/int_ctrl.IP (nonexistent)
+++ Interrupt/int_ctrl.IP (revision 25)
@@ -0,0 +1,205 @@
+#######################################################################
+## File: int_ctrl.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$int_ctrl = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/int_ctrl/int_ctrl.v'
+ ],
+ 'system_h' => '
+ #define ${IP}_MER (*((volatile unsigned int *) ($BASE )))
+ #define ${IP}_IER (*((volatile unsigned int *) ($BASE+4 )))
+ #define ${IP}_IAR (*((volatile unsigned int *) ($BASE+8 )))
+ #define ${IP}_IPR (*((volatile unsigned int *) ($BASE+12 )))',
+ 'ip_name' => 'int_ctrl',
+ 'description' => 'interrupt controller',
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'modules' => {
+ 'int_ctrl' => {}
+ },
+ 'plugs' => {
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ '0' => {
+ 'width' => 5,
+ 'name' => 'wb',
+ 'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller'
+ },
+ 'value' => 1,
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'parameters' => {
+ 'Aw' => {
+ 'info' => undef,
+ 'deafult' => ' 3',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed'
+ },
+ 'SELw' => {
+ 'info' => undef,
+ 'deafult' => ' 4 ',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed'
+ },
+ 'Dw' => {
+ 'info' => undef,
+ 'deafult' => ' 32',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed'
+ },
+ 'INT_NUM' => {
+ 'info' => 'number of inerrupt.',
+ 'deafult' => ' 3',
+ 'global_param' => 0,
+ 'content' => '1,32,1',
+ 'type' => 'Spin-button'
+ }
+ },
+ 'ports' => {
+ 'sa_dat_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 'sa_rty_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'rty_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'sel_i',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_dat_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_we_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'we_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_err_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'err_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_ack_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'int_o' => {
+ 'intfc_name' => 'socket:interrupt_cpu[0]',
+ 'intfc_port' => 'int_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'int_i' => {
+ 'intfc_name' => 'socket:interrupt_peripheral[array]',
+ 'intfc_port' => 'int_i',
+ 'range' => 'INT_NUM-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_addr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'parameters_order' => [
+ 'INT_NUM',
+ 'Dw',
+ 'Aw',
+ 'SELw'
+ ],
+ 'sockets' => {
+ 'interrupt_cpu' => {
+ 'interrupt_cpu' => {},
+ 'connection_num' => 'single connection',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'int_cpu'
+ },
+ 'type' => 'num'
+ },
+ 'interrupt_peripheral' => {
+ 'connection_num' => 'single connection',
+ 'interrupt_peripheral' => {},
+ '0' => {
+ 'name' => 'int_periph'
+ },
+ 'value' => 'INT_NUM',
+ 'type' => 'param'
+ }
+ },
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/int_ctrl/int_ctrl.v',
+ 'module_name' => 'int_ctrl',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'cyc_i',
+ 'tag_i',
+ 'cti_i',
+ 'bte_i'
+ ]
+ },
+ 'category' => 'Interrupt'
+ }, 'ip_gen' );
Interrupt/int_ctrl.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: JTAG/altera_jtag_uart.IP
===================================================================
--- JTAG/altera_jtag_uart.IP (nonexistent)
+++ JTAG/altera_jtag_uart.IP (revision 25)
@@ -0,0 +1,205 @@
+#######################################################################
+## File: altera_jtag_uart.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$altera_jtag_uart_wb = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/jtag/altera_jtag_uart_wb.v'
+ ],
+ 'system_h' => '#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE)))
+#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000
+#define ${IP}_DATA_RVALID_MSK 0x00008000
+#define ${IP}_DATA_DATA_MSK 0x000000FF
+
+//////////////////////////////*basic function for jtag_uart*////////////////////////////////////////
+void jtag_putchar(char ch);
+char jtag_getchar(void);
+void outbyte(char c){jtag_putchar(c);} //called in printf();
+char inbyte(){return jtag_getchar();}
+
+void jtag_putchar(char ch){ //print one char from jtag_uart
+ while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0);
+ ${IP}_DATA_REG=ch;
+}
+
+char jtag_getchar(void){ //get one char from jtag_uart
+ unsigned int data;
+ data=${IP}_DATA_REG;
+ while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input
+ data=${IP}_DATA_REG;
+ return (data & ${IP}_DATA_DATA_MSK);
+}
+
+int jtag_scanstr(char* buf){ //scan string until to buf, return str length
+ char ch; unsigned int i=0;
+ while(1){
+ ch=jtag_getchar();
+ if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER
+ else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace
+ else { jtag_putchar(ch); buf[i]=ch; i++; } //valid
+ }
+ return i;
+}
+
+int jtag_scanint(int *num){ //return the scanned integer
+ unsigned int curr_num,strlen,i=0;
+ char str[11];
+ strlen=jtag_scanstr(str); //scan str
+ if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow
+ *num=0;
+ for(i=0;i9); //not integer: do nothing
+ else *num=*num*10+curr_num; //is integer
+ }
+ return 0;
+}
+
+
+
+/////////////////////////////*END: basic function for jtag_uart*////////////////////////////////////',
+ 'ip_name' => 'altera_jtag_uart',
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'modules' => {
+ 'qsys_jtag_uart_0_scfifo_w' => {},
+ 'qsys_jtag_uart_0_scfifo_r' => {},
+ 'qsys_jtag_uart_0_sim_scfifo_r' => {},
+ 'qsys_jtag_uart_0' => {},
+ 'altera_jtag_uart_wb' => {},
+ 'qsys_jtag_uart_0_sim_scfifo_w' => {}
+ },
+ 'plugs' => {
+ 'interrupt_peripheral' => {
+ 'interrupt_peripheral' => {},
+ '0' => {
+ 'name' => 'intrpt'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ '0' => {
+ 'width' => 5,
+ 'name' => 'wb_slave',
+ 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'
+ },
+ 'value' => 1,
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'ports' => {
+ 'wb_irq' => {
+ 'intfc_port' => 'int_o',
+ 'intfc_name' => 'plug:interrupt_peripheral[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'stb_i' => {
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'cyc_i' => {
+ 'intfc_port' => 'cyc_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => ' 31: 0',
+ 'type' => 'input'
+ },
+ 'rst' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'readyfordata' => {
+ 'intfc_port' => 'NC',
+ 'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'adr_i' => {
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => ' 31: 0',
+ 'type' => 'output'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'we_i' => {
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'dataavailable' => {
+ 'intfc_port' => 'NC',
+ 'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ }
+ },
+ 'file_name' => '/home/jaytang/Desktop/alisoc/mpsoc/src_peripheral/jtag/altera_jtag_uart_wb.v',
+ 'module_name' => 'altera_jtag_uart_wb',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'err_o',
+ 'rty_o',
+ 'tag_i',
+ 'cti_i',
+ 'sel_i',
+ 'bte_i'
+ ]
+ },
+ 'category' => 'JTAG'
+ }, 'ip_gen' );
JTAG/altera_jtag_uart.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: JTAG/jtag_wb.IP
===================================================================
--- JTAG/jtag_wb.IP (nonexistent)
+++ JTAG/jtag_wb.IP (revision 25)
@@ -0,0 +1,219 @@
+#######################################################################
+## File: jtag_wb.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$vjtag_wb = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/jtag/jtag_wb'
+ ],
+ 'description' => 'A jtag to wishbone interface',
+ 'ip_name' => 'jtag_wb',
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'parameters' => {
+ 'AW' => {
+ 'info' => 'Parameter',
+ 'deafult' => '32',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'SELw' => {
+ 'info' => 'Parameter',
+ 'deafult' => ' 4',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'TAGw' => {
+ 'info' => 'Parameter',
+ 'deafult' => ' 3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'VJTAG_INDEX' => {
+ 'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.',
+ 'deafult' => 'CORE_ID',
+ 'global_param' => 'Parameter',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Entry'
+ },
+ 'DW' => {
+ 'info' => 'Parameter',
+ 'deafult' => '32',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'S_Aw' => {
+ 'info' => 'Parameter',
+ 'deafult' => ' 7',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'M_Aw' => {
+ 'info' => 'Parameter',
+ 'deafult' => ' 32',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ }
+ },
+ 'plugs' => {
+ 'wb_master' => {
+ 'wb_master' => {},
+ '0' => {
+ 'name' => 'wbm'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ }
+ },
+ 'modules' => {
+ 'wb_if' => {},
+ 'vjtag_wb' => {},
+ 'vjtag_ctrl' => {}
+ },
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 'm_sel_o',
+ 'm_dat_o',
+ 'm_addr_o',
+ 'm_cti_o',
+ 'm_stb_o',
+ 'm_cyc_o',
+ 'm_we_o',
+ 'm_dat_i',
+ 'm_ack_i',
+ 'status_i'
+ ],
+ 'ports' => {
+ 'm_dat_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'DW-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'sel_o',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_addr_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'adr_o',
+ 'range' => 'M_Aw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_dat_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'DW-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_cyc_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cyc_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_cti_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cti_o',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_stb_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'stb_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_we_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'we_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'status_i' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'NC',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_ack_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'ack_i',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'parameters_order' => [
+ 'DW',
+ 'AW',
+ 'S_Aw',
+ 'M_Aw',
+ 'TAGw',
+ 'SELw',
+ 'VJTAG_INDEX'
+ ],
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/jtag/jtag_wb/vjtag_wb.v',
+ 'module_name' => 'vjtag_wb',
+ 'unused' => {
+ 'plug:wb_master[0]' => [
+ 'tag_o',
+ 'bte_o',
+ 'err_i',
+ 'rty_i'
+ ]
+ },
+ 'category' => 'JTAG'
+ }, 'ip_gen' );
JTAG/jtag_wb.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: NoC/ni.IP
===================================================================
--- NoC/ni.IP (nonexistent)
+++ NoC/ni.IP (revision 25)
@@ -0,0 +1,639 @@
+#######################################################################
+## File: ni.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ni = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/ni/ni.v',
+ '/mpsoc/src_noc/arbiter.v',
+ '/mpsoc/src_noc/flit_buffer.v',
+ '/mpsoc/src_noc/inout_ports.v',
+ '/mpsoc/src_noc/main_comp.v',
+ '/mpsoc/src_noc/route_mesh.v',
+ '/mpsoc/src_noc/route_torus.v',
+ '/mpsoc/src_noc/routing.v'
+ ],
+ 'system_h' => ' #define ${IP}_BASE_ADDR ${BASE}
+ #define ${IP}_STATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR )))
+ #define ${IP}_MEM_PCKSIZ (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 )))
+ #define ${IP}_PCKSIZE (*((volatile unsigned int *) (${IP}_BASE_ADDR+8)))
+ #define ${IP}_MEM (*((volatile unsigned int *) (${IP}_BASE_ADDR+12)))
+
+ #define ${IP}_VC_WR_ADDR(v) (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 + (1<<5)+ (v<<6) )))
+ #define ${IP}_VC_RD_ADDR(v) (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 + (v<<6) )))
+
+
+ #define ${IP}_VC_NUM ${V}
+ #define ${IP}_VC_MASK ((1<<${V})-1)
+ #define ${IP}_CLASS_IN_HDR_WIDTH 8
+ #define ${IP}_DEST_IN_HDR_WIDTH 8
+ #define ${IP}_X_Y_IN_HDR_WIDTH 4
+
+/*
+ [14+V : 14+2V-1]rd_vc_not_empty
+ [14 : 14+V-1] wr_vc_not_empty
+ 13 rsv_pck_isr
+ 12 rd_done_isr
+ 11 wr_done_isr
+ 10 rsv_pck_int_en
+ 9 rd_done_int_en
+ 8 wr_done_int_en
+ 7 all_wr_vcs_full
+ 6 any_rd_vc_has_data
+ 5 rd_no_pck_err
+ 4 rd_ovr_size_err
+ 3 rd_done
+ 2 wr_done
+ 1 rd_busy
+ 0 wr_busy
+*/
+ #define ${IP}_WR_BUSY (1<<0)
+ #define ${IP}_RD_BUSY (1<<1)
+ #define ${IP}_WR_DONE (1<<2)
+ #define ${IP}_RD_DONE (1<<3)
+ #define ${IP}_RD_OVR_ERR (1<<4)
+ #define ${IP}_RD_NPCK_ERR (1<<5)
+ #define ${IP}_HAS_PCK (1<<6)
+ #define ${IP}_ALL_VCS_FULL (1<<7)
+ #define ${IP}_WR_DONE_INT_EN (1<<8)
+ #define ${IP}_RD_DONE_INT_EN (1<<9)
+ #define ${IP}_RSV_PCK_INT_EN (1<<10)
+ #define ${IP}_WR_DONE_ISR (1<<11)
+ #define ${IP}_RD_DONE_ISR (1<<12)
+ #define ${IP}_RSV_PCK_ISR (1<<13)
+ #define ${IP}WR_VCS_NO_EMPTY (${IP}_VC_MASK <<14)
+ #define ${IP}RD_VCS_NO_EMPTY (${IP}_VC_MASK << (14+${V}))
+
+ #define ${IP}_PTR_WIDTH 20
+ #define ${IP}_PCK_SIZE_WIDTH 12
+
+
+
+
+ #define ${IP}_HDR_DEST_CORE_ADDR(DES_X, DES_Y) ((DES_X << ${IP}_X_Y_IN_HDR_WIDTH) | DES_Y)<<(2*${IP}_X_Y_IN_HDR_WIDTH)
+ #define ${IP}_HDR_CLASS(pck_class) (pck_class << ( ${IP}_DEST_IN_HDR_WIDTH+ (4* ${IP}_X_Y_IN_HDR_WIDTH)))
+
+
+ #define ${IP}_wait_for_sending_pck() while (!(${IP}_STATUS & ${IP}_WR_DONE))
+ #define ${IP}_wait_for_reading_pck() while (!(${IP}_STATUS & ${IP}_RD_DONE))
+ #define ${IP}_wait_for_getting_pck() while (!(${IP}_STATUS & ${IP}_HAS_PCK))
+
+/*****************************************
+void send_pck (unsigned int * pck_buffer, unsigned int data_size, unsigned int vc_num);
+sending a packet through NoC network;
+(unsigned int des_x,unsigned int des_y : destination core address;
+unsigned int * pck_buffer : the buffer which hold the packet; The data must start from buff[1];
+unsigned int data_size : the size of data which wanted to be sent out in word = packet_size-1;
+unsigned int class
+
+****************************************/
+ inline void ${IP}_send_pck (unsigned int des_x, unsigned int des_y, volatile unsigned int * pck_buffer, unsigned int data_size, unsigned int pck_class, unsigned int vc_num){
+ pck_buffer [0] = ${IP}_HDR_DEST_CORE_ADDR(des_x, des_y) | ${IP}_HDR_CLASS(pck_class);
+ ${IP}_VC_WR_ADDR(vc_num) = (unsigned int) (& pck_buffer [0]) + (data_size<<${IP}_PTR_WIDTH);
+ ${IP}_wait_for_sending_pck();
+ }
+
+/*******************************************
+void save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size);
+save a received packet on pck_buffer
+unsigned int * pck_buffer: the buffer for storing the packet; The read data start from buff[1];
+********************************************/
+ inline void ${IP}_save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size,unsigned int vc_num){
+ ${IP}_wait_for_getting_pck();
+ ${IP}_VC_RD_ADDR(vc_num) = (unsigned int) (& pck_buffer [0]) + (buffer_size<<${IP}_PTR_WIDTH);
+ ${IP}_wait_for_reading_pck();
+ }',
+ 'ip_name' => 'ni',
+ 'parameters_order' => [
+ 'V',
+ 'B',
+ 'NX',
+ 'NY',
+ 'Fpay',
+ 'TOPOLOGY',
+ 'ROUTE_NAME',
+ 'DEBUG_EN',
+ 'COMB_MEM_PTR_W',
+ 'COMB_PCK_SIZE_W',
+ 'Dw',
+ 'S_Aw',
+ 'M_Aw',
+ 'TAGw',
+ 'SELw',
+ 'Yw',
+ 'Fw',
+ 'Xw'
+ ],
+ 'ports_order' => [
+ 'reset',
+ 'clk',
+ 'current_x',
+ 'current_y',
+ 'flit_out',
+ 'flit_out_wr',
+ 'credit_in',
+ 'flit_in',
+ 'flit_in_wr',
+ 'credit_out',
+ 's_dat_i',
+ 's_sel_i',
+ 's_addr_i',
+ 's_cti_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 's_err_o',
+ 's_rty_o',
+ 'm_sel_o',
+ 'm_dat_o',
+ 'm_addr_o',
+ 'm_cti_o',
+ 'm_stb_o',
+ 'm_cyc_o',
+ 'm_we_o',
+ 'm_dat_i',
+ 'm_ack_i',
+ 'm_err_i',
+ 'm_rty_i',
+ 'irq'
+ ],
+ 'sockets' => {
+ 'ni' => {
+ 'connection_num' => 'single connection',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'ni'
+ },
+ 'type' => 'num',
+ 'ni' => {}
+ }
+ },
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ni/ni.v',
+ 'module_name' => 'ni',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'tag_i',
+ 'bte_i'
+ ],
+ 'plug:wb_master[0]' => [
+ 'tag_o',
+ 'bte_o'
+ ]
+ },
+ 'category' => 'NoC',
+ 'description' => 'Network interface',
+ 'parameters' => {
+ 'Dw' => {
+ 'info' => undef,
+ 'deafult' => ' 32',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'NY' => {
+ 'info' => undef,
+ 'deafult' => ' 2',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'DEBUG_EN' => {
+ 'info' => undef,
+ 'deafult' => '0',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'NX' => {
+ 'info' => undef,
+ 'deafult' => ' 2',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'V' => {
+ 'info' => '',
+ 'deafult' => ' 4',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'CONGESTION_INDEX' => {
+ 'info' => undef,
+ 'deafult' => '3',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'Fw' => {
+ 'info' => undef,
+ 'deafult' => '2+V+Fpay',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 0
+ },
+ 'COMB_PCK_SIZE_W' => {
+ 'info' => undef,
+ 'deafult' => '12',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'TAGw' => {
+ 'info' => undef,
+ 'deafult' => '3',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'COMB_MEM_PTR_W' => {
+ 'info' => undef,
+ 'deafult' => '20',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'M_Aw' => {
+ 'info' => undef,
+ 'deafult' => '32',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'ROUTE_NAME' => {
+ 'info' => undef,
+ 'deafult' => '"XY"',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'Xw ' => {
+ 'info' => undef,
+ 'deafult' => 'log2(NX)',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 0,
+ 'type' => 'Fixed'
+ },
+ 'Fpay' => {
+ 'info' => undef,
+ 'deafult' => ' 32',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'ROUTE_TYPE' => {
+ 'info' => undef,
+ 'deafult' => '"DETERMINISTIC"',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'SELw' => {
+ 'info' => undef,
+ 'deafult' => '4 ',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'P' => {
+ 'info' => undef,
+ 'deafult' => ' 5',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'B' => {
+ 'info' => '',
+ 'deafult' => ' 4',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'Xw' => {
+ 'info' => undef,
+ 'deafult' => 'log2(NX)',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 0,
+ 'type' => 'Fixed'
+ },
+ 'TOPOLOGY' => {
+ 'info' => undef,
+ 'deafult' => '"MESH"',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'S_Aw' => {
+ 'info' => undef,
+ 'deafult' => '7',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'Yw' => {
+ 'info' => undef,
+ 'deafult' => 'log2(NY)',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 0
+ },
+ 'Xwj' => {
+ 'info' => undef,
+ 'deafult' => 'fvf',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'SSA_EN' => {
+ 'info' => undef,
+ 'deafult' => '"NO"',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ }
+ },
+ 'plugs' => {
+ 'wb_master' => {
+ 'wb_master' => {},
+ '0' => {
+ 'name' => 'wb_master'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'interrupt_peripheral' => {
+ 'interrupt_peripheral' => {},
+ '0' => {
+ 'name' => 'int_peripheral'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ '0' => {
+ 'width' => 9,
+ 'name' => 'wb_slave',
+ 'addr' => '0xb800_0000 0xbfff_ffff custom devices'
+ },
+ 'value' => 1,
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'modules' => {
+ 'ni' => {}
+ },
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'ports' => {
+ 'm_addr_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'adr_o',
+ 'range' => 'M_Aw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_cyc_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cyc_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 's_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cyc_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_dat_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_we_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'we_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'credit_out' => {
+ 'intfc_name' => 'socket:ni[0]',
+ 'intfc_port' => 'credit_out',
+ 'range' => 'V-1: 0',
+ 'type' => 'output'
+ },
+ 'flit_in_wr' => {
+ 'intfc_name' => 'socket:ni[0]',
+ 'intfc_port' => 'flit_in_wr',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_ack_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'ack_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_addr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'range' => 'S_Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_dat_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_cti_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cti_i',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'current_y' => {
+ 'intfc_name' => 'socket:ni[0]',
+ 'intfc_port' => 'current_y',
+ 'range' => 'Yw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'sel_i',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_we_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'we_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_stb_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'stb_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 's_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'flit_out_wr' => {
+ 'intfc_name' => 'socket:ni[0]',
+ 'intfc_port' => 'flit_out_wr',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_dat_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_dat_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_err_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'err_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_cti_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cti_o',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_ack_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'flit_out' => {
+ 'intfc_name' => 'socket:ni[0]',
+ 'intfc_port' => 'flit_out',
+ 'range' => 'Fw-1 : 0',
+ 'type' => 'output'
+ },
+ 'credit_in' => {
+ 'intfc_name' => 'socket:ni[0]',
+ 'intfc_port' => 'credit_in',
+ 'range' => 'V-1 : 0',
+ 'type' => 'input'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_err_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'err_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_rty_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'rty_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'sel_o',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'output'
+ },
+ 'flit_in' => {
+ 'intfc_name' => 'socket:ni[0]',
+ 'intfc_port' => 'flit_in',
+ 'range' => 'Fw-1 : 0',
+ 'type' => 'input'
+ },
+ 'current_x' => {
+ 'intfc_name' => 'socket:ni[0]',
+ 'intfc_port' => 'current_x',
+ 'range' => 'Xw-1 : 0',
+ 'type' => 'input'
+ },
+ 'irq' => {
+ 'intfc_name' => 'plug:interrupt_peripheral[0]',
+ 'intfc_port' => 'int_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_rty_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'rty_o',
+ 'range' => '',
+ 'type' => 'output'
+ }
+ }
+ }, 'ip_gen' );
NoC/ni.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: NoC/ni_sep.IP
===================================================================
--- NoC/ni_sep.IP (nonexistent)
+++ NoC/ni_sep.IP (revision 25)
@@ -0,0 +1,680 @@
+#######################################################################
+## File: ni_sep.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ni_sep = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/ni/ni_sep.v',
+ '/mpsoc/src_peripheral/ni/sub_ni_rd.v',
+ '/mpsoc/src_peripheral/ni/sub_ni_wr.v',
+ '/mpsoc/src_noc/arbiter.v',
+ '/mpsoc/src_noc/flit_buffer.v',
+ '/mpsoc/src_noc/inout_ports.v',
+ '/mpsoc/src_noc/main_comp.v',
+ '/mpsoc/src_noc/route_mesh.v',
+ '/mpsoc/src_noc/route_torus.v',
+ '/mpsoc/src_noc/routing.v'
+ ],
+ 'system_h' => '#define ${IP}_BASE_ADDR ${BASE}
+ #define ${IP}_STATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR )))
+ #define ${IP}_MEM_PCKSIZ (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 )))
+ #define ${IP}_PCKSIZE (*((volatile unsigned int *) (${IP}_BASE_ADDR+8)))
+ #define ${IP}_MEM (*((volatile unsigned int *) (${IP}_BASE_ADDR+12)))
+
+ #define ${IP}_VC_WR_ADDR(v) (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 + (1<<5)+ (v<<6) )))
+ #define ${IP}_VC_RD_ADDR(v) (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 + (v<<6) )))
+
+
+ #define ${IP}_VC_NUM ${V}
+ #define ${IP}_VC_MASK ((1<<${V})-1)
+ #define ${IP}_CLASS_IN_HDR_WIDTH 8
+ #define ${IP}_DEST_IN_HDR_WIDTH 8
+ #define ${IP}_X_Y_IN_HDR_WIDTH 4
+
+/*
+ [14+V : 14+2V-1]rd_vc_not_empty
+ [14 : 14+V-1] wr_vc_not_empty
+ 13 rsv_pck_isr
+ 12 rd_done_isr
+ 11 wr_done_isr
+ 10 rsv_pck_int_en
+ 9 rd_done_int_en
+ 8 wr_done_int_en
+ 7 all_wr_vcs_full
+ 6 any_rd_vc_has_data
+ 5 rd_no_pck_err
+ 4 rd_ovr_size_err
+ 3 rd_done
+ 2 wr_done
+ 1 rd_busy
+ 0 wr_busy
+*/
+ #define ${IP}_WR_BUSY (1<<0)
+ #define ${IP}_RD_BUSY (1<<1)
+ #define ${IP}_WR_DONE (1<<2)
+ #define ${IP}_RD_DONE (1<<3)
+ #define ${IP}_RD_OVR_ERR (1<<4)
+ #define ${IP}_RD_NPCK_ERR (1<<5)
+ #define ${IP}_HAS_PCK (1<<6)
+ #define ${IP}_ALL_VCS_FULL (1<<7)
+ #define ${IP}_WR_DONE_INT_EN (1<<8)
+ #define ${IP}_RD_DONE_INT_EN (1<<9)
+ #define ${IP}_RSV_PCK_INT_EN (1<<10)
+ #define ${IP}_WR_DONE_ISR (1<<11)
+ #define ${IP}_RD_DONE_ISR (1<<12)
+ #define ${IP}_RSV_PCK_ISR (1<<13)
+ #define ${IP}WR_VCS_NO_EMPTY (${IP}_VC_MASK <<14)
+ #define ${IP}RD_VCS_NO_EMPTY (${IP}_VC_MASK << (14+${V}))
+
+ #define ${IP}_PTR_WIDTH 20
+ #define ${IP}_PCK_SIZE_WIDTH 12
+
+
+
+
+ #define ${IP}_HDR_DEST_CORE_ADDR(DES_X, DES_Y) ((DES_X << ${IP}_X_Y_IN_HDR_WIDTH) | DES_Y)<<(2*${IP}_X_Y_IN_HDR_WIDTH)
+ #define ${IP}_HDR_CLASS(pck_class) (pck_class << ( ${IP}_DEST_IN_HDR_WIDTH+ (4* ${IP}_X_Y_IN_HDR_WIDTH)))
+
+
+ #define ${IP}_wait_for_sending_pck() while (!(${IP}_STATUS & ${IP}_WR_DONE))
+ #define ${IP}_wait_for_reading_pck() while (!(${IP}_STATUS & ${IP}_RD_DONE))
+ #define ${IP}_wait_for_getting_pck() while (!(${IP}_STATUS & ${IP}_HAS_PCK))
+
+/*****************************************
+void send_pck (unsigned int * pck_buffer, unsigned int data_size, unsigned int vc_num);
+sending a packet through NoC network;
+(unsigned int des_x,unsigned int des_y : destination core address;
+unsigned int * pck_buffer : the buffer which hold the packet; The data must start from buff[1];
+unsigned int data_size : the size of data which wanted to be sent out in word = packet_size-1;
+unsigned int class
+
+****************************************/
+ inline void ${IP}_send_pck (unsigned int des_x, unsigned int des_y, volatile unsigned int * pck_buffer, unsigned int data_size, unsigned int pck_class, unsigned int vc_num){
+ pck_buffer [0] = ${IP}_HDR_DEST_CORE_ADDR(des_x, des_y) | ${IP}_HDR_CLASS(pck_class);
+ ${IP}_VC_WR_ADDR(vc_num) = (unsigned int) (& pck_buffer [0]) + (data_size<<${IP}_PTR_WIDTH);
+ ${IP}_wait_for_sending_pck();
+ }
+
+/*******************************************
+void save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size);
+save a received packet on pck_buffer
+unsigned int * pck_buffer: the buffer for storing the packet; The read data start from buff[1];
+********************************************/
+ inline void ${IP}_save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size,unsigned int vc_num){
+ ${IP}_VC_RD_ADDR(vc_num) = (unsigned int) (& pck_buffer [0]) + (buffer_size<<${IP}_PTR_WIDTH);
+ ${IP}_wait_for_reading_pck();
+ }',
+ 'ip_name' => 'ni_sep',
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'parameters' => {
+ 'Dw' => {
+ 'info' => undef,
+ 'deafult' => ' 32',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'DEBUG_EN' => {
+ 'info' => undef,
+ 'deafult' => '0',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'NY' => {
+ 'info' => undef,
+ 'deafult' => ' 2',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'NX' => {
+ 'info' => undef,
+ 'deafult' => ' 2',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'V' => {
+ 'info' => '',
+ 'deafult' => ' 4',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'CONGESTION_INDEX' => {
+ 'info' => undef,
+ 'deafult' => '3',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Fw' => {
+ 'info' => undef,
+ 'deafult' => '2+V+Fpay',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 0,
+ 'type' => 'Fixed'
+ },
+ 'COMB_PCK_SIZE_W' => {
+ 'info' => undef,
+ 'deafult' => '12',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'TAGw' => {
+ 'info' => undef,
+ 'deafult' => '3',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'M_Aw' => {
+ 'info' => undef,
+ 'deafult' => '32',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'COMB_MEM_PTR_W' => {
+ 'info' => undef,
+ 'deafult' => '20',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'ROUTE_NAME' => {
+ 'info' => undef,
+ 'deafult' => '"XY"',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Xw ' => {
+ 'info' => undef,
+ 'deafult' => 'log2(NX)',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 0
+ },
+ 'Fpay' => {
+ 'info' => undef,
+ 'deafult' => ' 32',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'ROUTE_TYPE' => {
+ 'info' => undef,
+ 'deafult' => '"DETERMINISTIC"',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'SELw' => {
+ 'info' => undef,
+ 'deafult' => '4 ',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'P' => {
+ 'info' => undef,
+ 'deafult' => ' 5',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'B' => {
+ 'info' => '',
+ 'deafult' => ' 4',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'S_Aw' => {
+ 'info' => undef,
+ 'deafult' => ' 3',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'TOPOLOGY' => {
+ 'info' => undef,
+ 'deafult' => '"MESH"',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Xw' => {
+ 'info' => undef,
+ 'deafult' => 'log2(NX)',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 0
+ },
+ 'Yw' => {
+ 'info' => undef,
+ 'deafult' => 'log2(NY)',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 0,
+ 'type' => 'Fixed'
+ },
+ 'SSA_EN' => {
+ 'info' => undef,
+ 'deafult' => '"NO"',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Xwj' => {
+ 'info' => undef,
+ 'deafult' => 'fvf',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ }
+ },
+ 'modules' => {
+ 'ni_sep' => {}
+ },
+ 'plugs' => {
+ 'wb_master' => {
+ 'wb_master' => {},
+ '1' => {
+ 'name' => 'wb_wr'
+ },
+ '0' => {
+ 'name' => 'wb_rd'
+ },
+ 'value' => 2,
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'interrupt_peripheral' => {
+ 'interrupt_peripheral' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'intrpt_prhl'
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ '1' => {
+ 'width' => 1,
+ 'name' => 'wb_slave_1',
+ 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
+ },
+ '0' => {
+ 'width' => 5,
+ 'name' => 'wb_slave',
+ 'addr' => '0xb800_0000 0xbfff_ffff custom devices'
+ },
+ 'value' => 1,
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'ports_order' => [
+ 'reset',
+ 'clk',
+ 'current_x',
+ 'current_y',
+ 'flit_out',
+ 'flit_out_wr',
+ 'credit_in',
+ 'flit_in',
+ 'flit_in_wr',
+ 'credit_out',
+ 's_dat_i',
+ 's_sel_i',
+ 's_addr_i',
+ 's_cti_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 'm_rd_sel_o',
+ 'm_rd_dat_o',
+ 'm_rd_addr_o',
+ 'm_rd_cti_o',
+ 'm_rd_stb_o',
+ 'm_rd_cyc_o',
+ 'm_rd_we_o',
+ 'm_rd_ack_i',
+ 'm_wr_sel_o',
+ 'm_wr_addr_o',
+ 'm_wr_cti_o',
+ 'm_wr_stb_o',
+ 'm_wr_cyc_o',
+ 'm_wr_we_o',
+ 'm_wr_dat_i',
+ 'm_wr_ack_i',
+ 'irq'
+ ],
+ 'parameters_order' => [
+ 'V',
+ 'B',
+ 'NX',
+ 'NY',
+ 'Fpay',
+ 'TOPOLOGY',
+ 'ROUTE_NAME',
+ 'DEBUG_EN',
+ 'COMB_MEM_PTR_W',
+ 'COMB_PCK_SIZE_W',
+ 'Dw',
+ 'S_Aw',
+ 'M_Aw',
+ 'TAGw',
+ 'SELw',
+ 'Yw',
+ 'Fw',
+ 'Xw'
+ ],
+ 'ports' => {
+ 'm_rd_cyc_o' => {
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 's_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_cyc_i' => {
+ 'intfc_port' => 'cyc_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_wr_sel_o' => {
+ 'intfc_port' => 'sel_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_wr_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_wr_addr_o' => {
+ 'intfc_port' => 'adr_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => 'M_Aw-1 : 0',
+ 'type' => 'output'
+ },
+ 'credit_out' => {
+ 'intfc_port' => 'credit_out',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'V-1 : 0',
+ 'type' => 'output'
+ },
+ 'flit_in_wr' => {
+ 'intfc_port' => 'flit_in_wr',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_addr_i' => {
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'S_Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_cti_i' => {
+ 'intfc_port' => 'cti_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'current_y' => {
+ 'intfc_port' => 'current_y',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'Yw-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_wr_cti_o' => {
+ 'intfc_port' => 'cti_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_rd_ack_i' => {
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_sel_i' => {
+ 'intfc_port' => 'sel_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_we_i' => {
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_rd_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_stb_i' => {
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_wr_stb_o' => {
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'flit_out_wr' => {
+ 'intfc_port' => 'flit_out_wr',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_rd_sel_o' => {
+ 'intfc_port' => 'sel_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_rd_addr_o' => {
+ 'intfc_port' => 'adr_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'M_Aw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_wr_ack_i' => {
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_rd_we_o' => {
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'flit_out' => {
+ 'intfc_port' => 'flit_out',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'Fw-1 : 0',
+ 'type' => 'output'
+ },
+ 'credit_in' => {
+ 'intfc_port' => 'credit_in',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'V-1 : 0',
+ 'type' => 'input'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_rd_stb_o' => {
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'flit_in' => {
+ 'intfc_port' => 'flit_in',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'Fw-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_rd_cti_o' => {
+ 'intfc_port' => 'cti_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_wr_we_o' => {
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'current_x' => {
+ 'intfc_port' => 'current_x',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'Xw-1 : 0',
+ 'type' => 'input'
+ },
+ 'irq' => {
+ 'intfc_port' => 'int_o',
+ 'intfc_name' => 'plug:interrupt_peripheral[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_wr_cyc_o' => {
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ }
+ },
+ 'sockets' => {
+ 'ni' => {
+ 'connection_num' => 'single connection',
+ '0' => {
+ 'name' => 'ni'
+ },
+ 'value' => 1,
+ 'type' => 'num',
+ 'ni' => {}
+ }
+ },
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ni/ni_sep.v',
+ 'module_name' => 'ni_sep',
+ 'unused' => {
+ 'plug:wb_master[1]' => [
+ 'tag_o',
+ 'bte_o',
+ 'dat_o',
+ 'err_i',
+ 'rty_i'
+ ],
+ 'plug:wb_slave[0]' => [
+ 'err_o',
+ 'rty_o',
+ 'tag_i',
+ 'bte_i'
+ ],
+ 'plug:wb_master[0]' => [
+ 'tag_o',
+ 'dat_i',
+ 'bte_o',
+ 'err_i',
+ 'rty_i'
+ ]
+ },
+ 'category' => 'NoC'
+ }, 'ip_gen' );
NoC/ni_sep.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Processor/Altor.IP
===================================================================
--- Processor/Altor.IP (nonexistent)
+++ Processor/Altor.IP (revision 25)
@@ -0,0 +1,350 @@
+#######################################################################
+## File: Altor.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$altor = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_alu.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_dcache.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_dcache_mem_if.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_defs.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_dfu.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_exec.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_fetch.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_funcs.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_icache.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_lfu.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_lsu.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_noicache.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_ram_dp.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_ram_sp.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_regfile_alt.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_regfile_sim.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_regfile_xil.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_wb_fetch.v',
+ '/mpsoc/src_processor/altor32/rtl/cpu/altor32_writeback.v'
+ ],
+ 'system_h' => '
+inline void nop (void) {
+ asm volatile ("l.nop");
+}',
+ 'ip_name' => 'Altor',
+ 'ports_order' => [
+ 'clk_i',
+ 'rst_i',
+ 'en_i',
+ 'intr_i',
+ 'nmi_i',
+ 'fault_o',
+ 'break_o',
+ 'imem_addr_o',
+ 'imem_dat_i',
+ 'imem_cti_o',
+ 'imem_cyc_o',
+ 'imem_stb_o',
+ 'imem_ack_i',
+ 'dmem_addr_o',
+ 'dmem_dat_o',
+ 'dmem_dat_i',
+ 'dmem_sel_o',
+ 'dmem_cti_o',
+ 'dmem_cyc_o',
+ 'dmem_we_o',
+ 'dmem_stb_o',
+ 'dmem_ack_i'
+ ],
+ 'parameters_order' => [
+ 'BOOT_VECTOR',
+ 'ISR_VECTOR',
+ 'ENABLE_ICACHE',
+ 'ENABLE_DCACHE',
+ 'REGISTER_FILE_TYPE',
+ 'SUPPORT_32REGS',
+ 'PIPELINED_FETCH'
+ ],
+ 'sockets' => {},
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/altor32/rtl/cpu/altor.v',
+ 'module_name' => 'altor',
+ 'category' => 'Processor',
+ 'unused' => {
+ 'plug:wb_master[1]' => [
+ 'tag_o',
+ 'bte_o',
+ 'err_i',
+ 'rty_i'
+ ],
+ 'plug:wb_master[0]' => [
+ 'tag_o',
+ 'bte_o',
+ 'dat_o',
+ 'err_i',
+ 'we_o',
+ 'rty_i',
+ 'sel_o'
+ ]
+ },
+ 'sw_files' => [
+ '/mpsoc/src_processor/altor32/sw/boot.S',
+ '/mpsoc/src_processor/altor32/sw/exception.inc',
+ '/mpsoc/src_processor/altor32/sw/linker_script',
+ '/mpsoc/src_processor/altor32/sw/makefile',
+ '/mpsoc/src_processor/altor32/sw/program',
+ '/mpsoc/src_processor/program.sh'
+ ],
+ 'modules' => {
+ 'altor' => {}
+ },
+ 'parameters' => {
+ 'BOOT_VECTOR' => {
+ 'info' => undef,
+ 'deafult' => '32\'h00000000',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Entry'
+ },
+ 'ENABLE_DCACHE' => {
+ 'info' => undef,
+ 'deafult' => '"DISABLED"',
+ 'global_param' => 'Localparam',
+ 'content' => '"DISABLED","ENABLED"',
+ 'redefine_param' => 1,
+ 'type' => 'Combo-box'
+ },
+ 'SUPPORT_32REGS' => {
+ 'info' => undef,
+ 'deafult' => '"ENABLED"',
+ 'global_param' => 'Localparam',
+ 'content' => '"DISABLED","ENABLED"',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 1
+ },
+ 'ISR_VECTOR' => {
+ 'info' => undef,
+ 'deafult' => '32\'h00000000',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Entry'
+ },
+ 'REGISTER_FILE_TYPE' => {
+ 'info' => undef,
+ 'deafult' => '"ALTERA"',
+ 'global_param' => 'Localparam',
+ 'content' => '"SIMULATION","ALTERA","XILINX"',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 1
+ },
+ 'ENABLE_ICACHE' => {
+ 'info' => undef,
+ 'deafult' => '"ENABLED"',
+ 'global_param' => 'Localparam',
+ 'content' => '"DISABLED","ENABLED"',
+ 'redefine_param' => 1,
+ 'type' => 'Combo-box'
+ },
+ 'PIPELINED_FETCH' => {
+ 'info' => undef,
+ 'deafult' => '"ENABLED"',
+ 'global_param' => 'Localparam',
+ 'content' => '"DISABLED","ENABLED"',
+ 'redefine_param' => 1,
+ 'type' => 'Combo-box'
+ }
+ },
+ 'plugs' => {
+ 'wb_master' => {
+ 'wb_master' => {},
+ '1' => {
+ 'name' => 'd_wb'
+ },
+ 'value' => 2,
+ '0' => {
+ 'name' => 'i_wb'
+ },
+ 'type' => 'num'
+ },
+ 'interrupt_cpu' => {
+ 'interrupt_cpu' => {},
+ '1' => {
+ 'name' => 'nmi'
+ },
+ '0' => {
+ 'name' => 'intr'
+ },
+ 'value' => 2,
+ 'type' => 'num'
+ },
+ 'enable' => {
+ 'enable' => {},
+ '0' => {
+ 'name' => 'enable'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ }
+ },
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'ports' => {
+ 'imem_addr_o' => {
+ 'intfc_port' => 'adr_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'dmem_dat_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'dat_o',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'nmi_i' => {
+ 'intfc_name' => 'plug:interrupt_cpu[1]',
+ 'intfc_port' => 'int_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'imem_ack_i' => {
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'fault_o' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'break_o' => {
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'dmem_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'sel_o',
+ 'range' => '3:0',
+ 'type' => 'output'
+ },
+ 'dmem_dat_i' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'dat_i',
+ 'range' => '31:0',
+ 'type' => 'input'
+ },
+ 'dmem_ack_i' => {
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'dmem_cti_o' => {
+ 'intfc_port' => 'cti_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '2:0',
+ 'type' => 'output'
+ },
+ 'dmem_we_o' => {
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'imem_cyc_o' => {
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'dmem_stb_o' => {
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'en_i' => {
+ 'intfc_port' => 'enable_i',
+ 'intfc_name' => 'plug:enable[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'rst_i' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'imem_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '31:0',
+ 'type' => 'input'
+ },
+ 'dmem_addr_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'adr_o',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'intr_i' => {
+ 'intfc_name' => 'plug:interrupt_cpu[0]',
+ 'intfc_port' => 'int_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'dmem_cyc_o' => {
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'imem_stb_o' => {
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk_i' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'imem_cti_o' => {
+ 'intfc_port' => 'cti_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '2:0',
+ 'type' => 'output'
+ }
+ }
+ }, 'ip_gen' );
Processor/Altor.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Processor/aeMB.IP
===================================================================
--- Processor/aeMB.IP (nonexistent)
+++ Processor/aeMB.IP (revision 25)
@@ -0,0 +1,420 @@
+#######################################################################
+## File: aeMB.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$aeMB_top = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_processor/aeMB/verilog/aemb.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_core.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_xecu.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_sim.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_bpcu.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_edk32.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_xslif.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_ctrl.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_ibuf.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_tpsram.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_regf.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_exec.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_sparam.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_intu.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_regs.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_spsram.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_memif.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_mult.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_gprf.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_pipe.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_brcc.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_dparam.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_edk63.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_bsft.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_ctrl.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_dwbif.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_edk62.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_sim.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iche.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iwbif.v'
+ ],
+ 'system_h' => ' #include
+ #include
+ #include "aemb/core.hh"
+ #define printf xil_printf
+ inline void nop (void) {
+ asm volatile ("nop");
+ }',
+ 'ip_name' => 'aeMB',
+ 'parameters_order' => [
+ 'AEMB_IWB',
+ 'AEMB_DWB',
+ 'AEMB_XWB',
+ 'AEMB_ICH',
+ 'AEMB_IDX',
+ 'AEMB_BSF',
+ 'AEMB_MUL',
+ 'STACK_SIZE',
+ 'HEAP_SIZE'
+ ],
+ 'ports_order' => [
+ 'dwb_adr_o',
+ 'dwb_cyc_o',
+ 'dwb_dat_o',
+ 'dwb_sel_o',
+ 'dwb_stb_o',
+ 'dwb_tag_o',
+ 'dwb_wre_o',
+ 'dwb_cti_o',
+ 'dwb_bte_o',
+ 'dwb_ack_i',
+ 'dwb_dat_i',
+ 'dwb_err_i',
+ 'dwb_rty_i',
+ 'iwb_adr_o',
+ 'iwb_cyc_o',
+ 'iwb_sel_o',
+ 'iwb_stb_o',
+ 'iwb_tag_o',
+ 'iwb_wre_o',
+ 'iwb_dat_o',
+ 'iwb_cti_o',
+ 'iwb_bte_o',
+ 'iwb_ack_i',
+ 'iwb_dat_i',
+ 'iwb_err_i',
+ 'iwb_rty_i',
+ 'clk',
+ 'reset',
+ 'sys_int_i',
+ 'sys_ena_i'
+ ],
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/aeMB/verilog/aemb.v',
+ 'module_name' => 'aeMB_top',
+ 'gen_sw_files' => [
+ '/mpsoc/src_processor/aeMB/sw/compile/gccromfrename_sep_tcompile/gccrom',
+ '/mpsoc/src_processor/aeMB/sw/Makefilefrename_sep_tMakefile'
+ ],
+ 'unused' => undef,
+ 'category' => 'Processor',
+ 'sw_files' => [
+ '/mpsoc/src_processor/aeMB/sw/aemb',
+ '/mpsoc/src_processor/aeMB/sw/compile',
+ '/mpsoc/src_processor/aeMB/sw/program',
+ '/mpsoc/src_processor/program.sh'
+ ],
+ 'description' => 'AEMB 32-bit Microprocessor Core
+For more information check http://opencores.org/project,aemb',
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'modules' => {
+ 'aeMB_top' => {}
+ },
+ 'plugs' => {
+ 'interrupt_cpu' => {
+ 'interrupt_cpu' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'intrp'
+ },
+ 'type' => 'num'
+ },
+ 'wb_master' => {
+ 'wb_master' => {},
+ '1' => {
+ 'name' => 'dwb'
+ },
+ 'value' => 2,
+ '0' => {
+ 'name' => 'iwb'
+ },
+ 'type' => 'num'
+ },
+ 'enable' => {
+ 'enable' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'enable'
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ }
+ },
+ 'parameters' => {
+ 'STACK_SIZE' => {
+ 'info' => 'The stack size in hex',
+ 'deafult' => '0x400',
+ 'global_param' => 'Don\'t include',
+ 'content' => '',
+ 'type' => 'Entry',
+ 'redefine_param' => 0
+ },
+ 'HEAP_SIZE' => {
+ 'info' => undef,
+ 'deafult' => '0x400',
+ 'global_param' => 'Don\'t include',
+ 'content' => '',
+ 'redefine_param' => 0,
+ 'type' => 'Entry'
+ },
+ 'AEMB_IWB' => {
+ 'info' => undef,
+ 'deafult' => ' 32',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'AEMB_BSF' => {
+ 'info' => undef,
+ 'deafult' => ' 1',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'AEMB_ICH' => {
+ 'info' => undef,
+ 'deafult' => ' 11',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'AEMB_DWB' => {
+ 'info' => undef,
+ 'deafult' => ' 32',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'AEMB_XWB' => {
+ 'info' => undef,
+ 'deafult' => ' 7',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'AEMB_IDX' => {
+ 'info' => undef,
+ 'deafult' => ' 6',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'AEMB_MUL' => {
+ 'info' => undef,
+ 'deafult' => ' 1',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ }
+ },
+ 'ports' => {
+ 'iwb_err_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'err_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'dwb_ack_i' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'ack_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'iwb_cyc_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cyc_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'iwb_dat_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'dwb_wre_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'we_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'dwb_cyc_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'cyc_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'dwb_stb_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'stb_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'iwb_adr_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'adr_o',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'iwb_bte_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'bte_o',
+ 'range' => '1:0',
+ 'type' => 'output'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'iwb_rty_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'rty_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sys_int_i' => {
+ 'intfc_name' => 'plug:interrupt_cpu[0]',
+ 'intfc_port' => 'int_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'dwb_err_i' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'err_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'iwb_tag_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'tag_o',
+ 'range' => '2:0',
+ 'type' => 'output'
+ },
+ 'iwb_ack_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'ack_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'iwb_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'sel_o',
+ 'range' => '3:0',
+ 'type' => 'output'
+ },
+ 'dwb_tag_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'tag_o',
+ 'range' => '2:0',
+ 'type' => 'output'
+ },
+ 'dwb_adr_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'adr_o',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'dwb_bte_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'bte_o',
+ 'range' => '1:0',
+ 'type' => 'output'
+ },
+ 'dwb_dat_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'dat_o',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'dwb_cti_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'cti_o',
+ 'range' => '2:0',
+ 'type' => 'output'
+ },
+ 'iwb_cti_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cti_o',
+ 'range' => '2:0',
+ 'type' => 'output'
+ },
+ 'iwb_stb_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'stb_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'dwb_rty_i' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'rty_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'dwb_dat_i' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'dat_i',
+ 'range' => '31:0',
+ 'type' => 'input'
+ },
+ 'iwb_dat_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => '31:0',
+ 'type' => 'input'
+ },
+ 'dwb_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'sel_o',
+ 'range' => '3:0',
+ 'type' => 'output'
+ },
+ 'iwb_wre_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'we_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sys_ena_i' => {
+ 'intfc_name' => 'plug:enable[0]',
+ 'intfc_port' => 'enable_i',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ }
+ }, 'ip_gen' );
Processor/aeMB.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Processor/lm32.IP
===================================================================
--- Processor/lm32.IP (nonexistent)
+++ Processor/lm32.IP (revision 25)
@@ -0,0 +1,378 @@
+#######################################################################
+## File: lm32.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$lm32 = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_processor/lm32/verilog/src/er1.v',
+ '/mpsoc/src_processor/lm32/verilog/src/JTAGB.v',
+ '/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_include.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v',
+ '/mpsoc/src_processor/lm32/verilog/src/lm32_top.v',
+ '/mpsoc/src_processor/lm32/verilog/src/spiprog.v',
+ '/mpsoc/src_processor/lm32/verilog/src/system_conf.v',
+ '/mpsoc/src_processor/lm32/verilog/src/typea.v',
+ '/mpsoc/src_processor/lm32/verilog/src/typeb.v'
+ ],
+ 'system_h' => '#include "lm32_system.h"
+inline void nop (void) {
+ asm volatile ("nop");
+}',
+ 'ip_name' => 'lm32',
+ 'parameters_order' => [
+ 'INTR_NUM',
+ 'CFG_PL_MULTIPLY',
+ 'CFG_PL_BARREL_SHIFT',
+ 'CFG_SIGN_EXTEND',
+ 'CFG_MC_DIVIDE'
+ ],
+ 'ports_order' => [
+ 'clk_i',
+ 'rst_i',
+ 'en_i',
+ 'interrupt',
+ 'I_DAT_I',
+ 'I_ACK_I',
+ 'I_ERR_I',
+ 'I_RTY_I',
+ 'I_DAT_O',
+ 'I_ADR_O',
+ 'I_CYC_O',
+ 'I_SEL_O',
+ 'I_STB_O',
+ 'I_WE_O',
+ 'I_CTI_O',
+ 'I_BTE_O',
+ 'D_DAT_I',
+ 'D_ACK_I',
+ 'D_ERR_I',
+ 'D_RTY_I',
+ 'D_DAT_O',
+ 'D_ADR_O',
+ 'D_CYC_O',
+ 'D_SEL_O',
+ 'D_STB_O',
+ 'D_WE_O',
+ 'D_CTI_O',
+ 'D_BTE_O'
+ ],
+ 'sockets' => {
+ 'interrupt_peripheral' => {
+ 'interrupt_peripheral' => {},
+ 'connection_num' => 'single connection',
+ 'value' => 'INTR_NUM',
+ '0' => {
+ 'name' => 'interrupt_peripheral'
+ },
+ 'type' => 'param'
+ }
+ },
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v',
+ 'module_name' => 'lm32',
+ 'unused' => {
+ 'plug:wb_master[1]' => [
+ 'tag_o'
+ ],
+ 'plug:wb_master[0]' => [
+ 'tag_o'
+ ]
+ },
+ 'category' => 'Processor',
+ 'sw_files' => [
+ '/mpsoc/src_processor/lm32/sw/crt0ram.S',
+ '/mpsoc/src_processor/lm32/sw/linker.ld',
+ '/mpsoc/src_processor/lm32/sw/lm32_system.h',
+ '/mpsoc/src_processor/lm32/sw/Makefile',
+ '/mpsoc/src_processor/lm32/sw/program',
+ '/mpsoc/src_processor/program.sh'
+ ],
+ 'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement.
+
+for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx',
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'plugs' => {
+ 'wb_master' => {
+ 'wb_master' => {},
+ '1' => {
+ 'name' => 'dwb'
+ },
+ 'value' => 2,
+ '0' => {
+ 'name' => 'iwb'
+ },
+ 'type' => 'num'
+ },
+ 'enable' => {
+ 'enable' => {},
+ '0' => {
+ 'name' => 'enable'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'reset' => {
+ '1' => {
+ 'name' => 'reset_1'
+ },
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ }
+ },
+ 'modules' => {
+ 'lm32' => {}
+ },
+ 'parameters' => {
+ 'CFG_PL_BARREL_SHIFT' => {
+ 'info' => undef,
+ 'deafult' => '"ENABLED"',
+ 'global_param' => 0,
+ 'content' => '"ENABLED","DISABLED"',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'CFG_SIGN_EXTEND' => {
+ 'info' => undef,
+ 'deafult' => '"ENABLED"',
+ 'global_param' => 0,
+ 'content' => '"ENABLED","DISABLED"',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'CFG_PL_MULTIPLY' => {
+ 'info' => undef,
+ 'deafult' => '"ENABLED"',
+ 'global_param' => 0,
+ 'content' => '"ENABLED","DISABLED"',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'INTR_NUM' => {
+ 'info' => undef,
+ 'deafult' => '32',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'CFG_MC_DIVIDE' => {
+ 'info' => undef,
+ 'deafult' => '"DISABLED"',
+ 'global_param' => 0,
+ 'content' => '"ENABLED","DISABLED"',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ }
+ },
+ 'ports' => {
+ 'I_SEL_O' => {
+ 'intfc_port' => 'sel_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '(4-1):0',
+ 'type' => 'output'
+ },
+ 'I_DAT_I' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '(32-1):0',
+ 'type' => 'input'
+ },
+ 'I_CTI_O' => {
+ 'intfc_port' => 'cti_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '(3-1):0',
+ 'type' => 'output'
+ },
+ 'D_WE_O' => {
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'I_ERR_I' => {
+ 'intfc_port' => 'err_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'D_ADR_O' => {
+ 'intfc_port' => 'adr_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '(32-1):0',
+ 'type' => 'output'
+ },
+ 'D_CTI_O' => {
+ 'intfc_port' => 'cti_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '(3-1):0',
+ 'type' => 'output'
+ },
+ 'D_STB_O' => {
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'en_i' => {
+ 'intfc_port' => 'enable_i',
+ 'intfc_name' => 'plug:enable[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'I_CYC_O' => {
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'D_DAT_I' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '(32-1):0',
+ 'type' => 'input'
+ },
+ 'D_ACK_I' => {
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'D_DAT_O' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '(32-1):0',
+ 'type' => 'output'
+ },
+ 'I_ADR_O' => {
+ 'intfc_port' => 'adr_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '(32-1):0',
+ 'type' => 'output'
+ },
+ 'I_WE_O' => {
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'I_BTE_O' => {
+ 'intfc_port' => 'bte_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '(2-1):0',
+ 'type' => 'output'
+ },
+ 'rst_i' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'interrupt' => {
+ 'intfc_port' => 'int_i',
+ 'intfc_name' => 'socket:interrupt_peripheral[array]',
+ 'range' => '(32-1):0',
+ 'type' => 'input'
+ },
+ 'D_BTE_O' => {
+ 'intfc_port' => 'bte_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '(2-1):0',
+ 'type' => 'output'
+ },
+ 'D_CYC_O' => {
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'I_STB_O' => {
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'D_SEL_O' => {
+ 'intfc_port' => 'sel_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '(4-1):0',
+ 'type' => 'output'
+ },
+ 'I_DAT_O' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '(32-1):0',
+ 'type' => 'output'
+ },
+ 'D_ERR_I' => {
+ 'intfc_port' => 'err_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'D_RTY_I' => {
+ 'intfc_port' => 'rty_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'I_ACK_I' => {
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'I_RTY_I' => {
+ 'intfc_port' => 'rty_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'clk_i' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ }
+ }, 'ip_gen' );
Processor/lm32.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: RAM/dual_port_ram.IP
===================================================================
--- RAM/dual_port_ram.IP (nonexistent)
+++ RAM/dual_port_ram.IP (revision 25)
@@ -0,0 +1,379 @@
+#######################################################################
+## File: dual_port_ram.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$wb_dual_port_ram = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/ram/generic_ram.v',
+ '/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',
+ '/mpsoc/src_peripheral/ram/wb_dual_port_ram.v',
+ '/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'
+ ],
+ 'description' => 'Dual port ram.',
+ 'ip_name' => 'dual_port_ram',
+ 'parameters' => {
+ 'SELw' => {
+ 'info' => 'Parameter',
+ 'deafult' => 'Dw/8',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Dw' => {
+ 'info' => 'Ram data width in Bits',
+ 'deafult' => '32',
+ 'global_param' => 'Localparam',
+ 'content' => '4,1024,1',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1
+ },
+ 'PORT_B_BURST_MODE' => {
+ 'info' => 'wisbone bus burst mode ebable/disable on port B',
+ 'deafult' => '"DISABLED"',
+ 'global_param' => 'Don\'t include',
+ 'content' => '"DISABLED","ENABLED" ',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 1
+ },
+ 'BTEw' => {
+ 'info' => 'Parameter',
+ 'deafult' => '2',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'WB_Aw' => {
+ 'info' => 'Wishbone bus address width in byte',
+ 'deafult' => 'Aw+2',
+ 'global_param' => 'Don\'t include',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 0
+ },
+ 'RAM_INDEX' => {
+ 'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only.
+
+',
+ 'deafult' => 'CORE_ID',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Entry',
+ 'redefine_param' => 1
+ },
+ 'Aw' => {
+ 'info' => 'Ram address width',
+ 'deafult' => '12',
+ 'global_param' => 'Localparam',
+ 'content' => '2,31,1',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1
+ },
+ 'TAGw' => {
+ 'info' => 'Parameter',
+ 'deafult' => '3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'BYTE_WR_EN' => {
+ 'info' => 'Parameter',
+ 'deafult' => '"YES"',
+ 'global_param' => 'Localparam',
+ 'content' => '"YES","NO"',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 1
+ },
+ 'PORT_A_BURST_MODE' => {
+ 'info' => ' wisbone bus burst mode enable/disable on port A',
+ 'deafult' => '"DISABLED"',
+ 'global_param' => 'Localparam',
+ 'content' => '"DISABLED","ENABLED"',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 1
+ },
+ 'CTIw' => {
+ 'info' => 'Parameter',
+ 'deafult' => '3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'FPGA_VENDOR' => {
+ 'info' => 'Parameter',
+ 'deafult' => '"ALTERA"',
+ 'global_param' => 'Localparam',
+ 'content' => '"ALTERA","GENERIC"',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 1
+ }
+ },
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'plugs' => {
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ '1' => {
+ 'width' => 'WB_Aw',
+ 'name' => 'wb_b',
+ 'addr' => '0x0000_0000 0x3fff_ffff RAM'
+ },
+ '0' => {
+ 'width' => 'WB_Aw',
+ 'name' => 'wb_a',
+ 'addr' => '0x0000_0000 0x3fff_ffff RAM'
+ },
+ 'value' => 2,
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'modules' => {
+ 'wb_dual_port_ram' => {}
+ },
+ 'ports' => {
+ 'sa_tag_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'tag_i',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sb_addr_i' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'adr_i',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_rty_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'rty_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_cti_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cti_i',
+ 'range' => 'CTIw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'sel_i',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_bte_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'bte_i',
+ 'range' => 'BTEw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cyc_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sb_err_o' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'err_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_err_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'err_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_ack_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sb_dat_o' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 'sb_cti_i' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'cti_i',
+ 'range' => 'CTIw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sb_bte_i' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'bte_i',
+ 'range' => 'BTEw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_addr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sb_ack_o' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'ack_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sb_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'cyc_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sb_rty_o' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'rty_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sb_dat_i' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_dat_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 'sb_we_i' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'we_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_dat_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_i',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sb_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'sel_i',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_we_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'we_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sb_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sb_tag_i' => {
+ 'intfc_name' => 'plug:wb_slave[1]',
+ 'intfc_port' => 'tag_i',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'parameters_order' => [
+ 'Dw',
+ 'Aw',
+ 'BYTE_WR_EN',
+ 'FPGA_VENDOR',
+ 'TAGw',
+ 'SELw',
+ 'CTIw',
+ 'BTEw',
+ 'WB_Aw',
+ 'RAM_INDEX',
+ 'PORT_A_BURST_MODE',
+ 'PORT_B_BURST_MODE'
+ ],
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 'sa_dat_i',
+ 'sa_sel_i',
+ 'sa_addr_i',
+ 'sa_tag_i',
+ 'sa_cti_i',
+ 'sa_bte_i',
+ 'sa_stb_i',
+ 'sa_cyc_i',
+ 'sa_we_i',
+ 'sa_dat_o',
+ 'sa_ack_o',
+ 'sa_err_o',
+ 'sa_rty_o',
+ 'sb_dat_i',
+ 'sb_sel_i',
+ 'sb_addr_i',
+ 'sb_tag_i',
+ 'sb_cti_i',
+ 'sb_bte_i',
+ 'sb_stb_i',
+ 'sb_cyc_i',
+ 'sb_we_i',
+ 'sb_dat_o',
+ 'sb_ack_o',
+ 'sb_err_o',
+ 'sb_rty_o'
+ ],
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_dual_port_ram.v',
+ 'module_name' => 'wb_dual_port_ram',
+ 'unused' => undef,
+ 'category' => 'RAM'
+ }, 'ip_gen' );
RAM/dual_port_ram.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: RAM/single_port_ram.IP
===================================================================
--- RAM/single_port_ram.IP (nonexistent)
+++ RAM/single_port_ram.IP (revision 25)
@@ -0,0 +1,288 @@
+#######################################################################
+## File: single_port_ram.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$wb_single_port_ram = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
+ '/mpsoc/src_peripheral/ram/generic_ram.v',
+ '/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',
+ '/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'
+ ],
+ 'ip_name' => 'single_port_ram',
+ 'description' => 'Single port ram with wishbone bus interface.',
+ 'modules' => {
+ 'wb_single_port_ram' => {}
+ },
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'plugs' => {
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ '0' => {
+ 'width' => 'WB_Aw',
+ 'name' => 'wb',
+ 'addr' => '0x0000_0000 0x3fff_ffff RAM'
+ },
+ 'value' => 1,
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'parameters' => {
+ 'SELw' => {
+ 'info' => 'Parameter',
+ 'deafult' => 'Dw/8',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Dw' => {
+ 'info' => 'Memory data width in Bits.',
+ 'deafult' => '32',
+ 'global_param' => 'Parameter',
+ 'content' => '8,1024,1',
+ 'redefine_param' => 1,
+ 'type' => 'Spin-button'
+ },
+ 'BTEw' => {
+ 'info' => 'Parameter',
+ 'deafult' => '2',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'WB_Aw' => {
+ 'info' => undef,
+ 'deafult' => 'Aw+2',
+ 'global_param' => 'Don\'t include',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Aw' => {
+ 'info' => 'Memory address width',
+ 'deafult' => '12',
+ 'global_param' => 'Parameter',
+ 'content' => '4,31,1',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1
+ },
+ 'BURST_MODE' => {
+ 'info' => 'Wishbone bus burst read/write mode enable/disable. ',
+ 'deafult' => '"DISABLED"',
+ 'global_param' => 'Localparam',
+ 'content' => '"DISABLED","ENABLED"',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 1
+ },
+ 'TAGw' => {
+ 'info' => 'Parameter',
+ 'deafult' => '3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'JTAG_INDEX' => {
+ 'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
+
+ In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
+
+ You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
+
+',
+ 'deafult' => 'CORE_ID',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Entry'
+ },
+ 'JTAG_CONNECT' => {
+ 'info' => 'JTAG_CONNECT:
+if it is not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb ',
+ 'deafult' => '"DISABLED"',
+ 'global_param' => 'Localparam',
+ 'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 1
+ },
+ 'BYTE_WR_EN' => {
+ 'info' => '',
+ 'deafult' => '"YES"',
+ 'global_param' => 'Localparam',
+ 'content' => '"YES","NO"',
+ 'redefine_param' => 1,
+ 'type' => 'Combo-box'
+ },
+ 'CTIw' => {
+ 'info' => 'Parameter',
+ 'deafult' => '3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'FPGA_VENDOR' => {
+ 'info' => '',
+ 'deafult' => '"ALTERA"',
+ 'global_param' => 'Localparam',
+ 'content' => '"ALTERA","GENERIC"',
+ 'redefine_param' => 1,
+ 'type' => 'Combo-box'
+ }
+ },
+ 'parameters_order' => [
+ 'Dw',
+ 'Aw',
+ 'BYTE_WR_EN',
+ 'FPGA_VENDOR',
+ 'JTAG_CONNECT',
+ 'JTAG_INDEX',
+ 'TAGw',
+ 'SELw',
+ 'CTIw',
+ 'BTEw',
+ 'WB_Aw',
+ 'BURST_MODE'
+ ],
+ 'ports' => {
+ 'sa_tag_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'tag_i',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_rty_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'rty_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 'sa_cti_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cti_i',
+ 'range' => 'CTIw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'sel_i',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_bte_i' => {
+ 'intfc_port' => 'bte_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'BTEw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_we_i' => {
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_err_o' => {
+ 'intfc_port' => 'err_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_cyc_i' => {
+ 'intfc_port' => 'cyc_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_addr_i' => {
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_stb_i' => {
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 'sa_dat_i',
+ 'sa_sel_i',
+ 'sa_addr_i',
+ 'sa_tag_i',
+ 'sa_cti_i',
+ 'sa_bte_i',
+ 'sa_stb_i',
+ 'sa_cyc_i',
+ 'sa_we_i',
+ 'sa_dat_o',
+ 'sa_ack_o',
+ 'sa_err_o',
+ 'sa_rty_o'
+ ],
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
+ 'module_name' => 'wb_single_port_ram',
+ 'unused' => undef,
+ 'category' => 'RAM'
+ }, 'ip_gen' );
RAM/single_port_ram.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Source/clk_source.IP
===================================================================
--- Source/clk_source.IP (nonexistent)
+++ Source/clk_source.IP (revision 25)
@@ -0,0 +1,94 @@
+#######################################################################
+## File: clk_source.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$clk_source = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/reset_sync/altera_reset_synchronizer.v',
+ '/mpsoc/src_peripheral/reset_sync/clk_source.v'
+ ],
+ 'ip_name' => 'clk_source',
+ 'description' => 'clk source. This module provides the clk and reset (socket) interfaces for all other IPs. It also synchronizes the reset signal.',
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'modules' => {
+ 'clk_source' => {}
+ },
+ 'plugs' => {
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ }
+ },
+ 'ports' => {
+ 'clk_out' => {
+ 'intfc_port' => 'clk_o',
+ 'intfc_name' => 'socket:clk[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'reset_out' => {
+ 'intfc_port' => 'reset_o',
+ 'intfc_name' => 'socket:reset[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk_in' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'reset_in' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/reset_sync/clk_source.v',
+ 'sockets' => {
+ 'clk' => {
+ 'clk' => {},
+ 'connection_num' => 'multi connection',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ 'connection_num' => 'multi connection',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ }
+ },
+ 'module_name' => 'clk_source',
+ 'unused' => undef,
+ 'category' => 'Source'
+ }, 'ip_gen' );
Source/clk_source.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Timer/timer.IP
===================================================================
--- Timer/timer.IP (nonexistent)
+++ Timer/timer.IP (revision 25)
@@ -0,0 +1,224 @@
+#######################################################################
+## File: timer.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$timer = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/timer/timer.v'
+ ],
+ 'system_h' => '#define ${IP}_TCSR0 (*((volatile unsigned int *) ($BASE )))
+
+/*
+//timer control register
+TCSR0
+bit
+6-3 : clk_dev_ctrl
+3 : timer_isr
+2 : rst_on_cmp_value
+1 : int_enble_on_cmp_value
+0 : timer enable
+*/
+ #define ${IP}_TLR0 (*((volatile unsigned int *) ($BASE+4 )))
+ #define ${IP}_TCMP0 (*((volatile unsigned int *) ($BASE+8 )))
+ #define ${IP}_EN (1 << 0)
+ #define ${IP}_INT_EN (1 << 1)
+ #define ${IP}_RST_ON_CMP (1 << 2)
+',
+ 'ip_name' => 'timer',
+ 'description' => '32 bit timer ',
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'parameters' => {
+ 'Aw' => {
+ 'info' => undef,
+ 'deafult' => '3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'TAGw' => {
+ 'info' => undef,
+ 'deafult' => '3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'SELw' => {
+ 'info' => undef,
+ 'deafult' => '4',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'Dw' => {
+ 'info' => undef,
+ 'deafult' => '32',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'CNTw' => {
+ 'info' => undef,
+ 'deafult' => '32 ',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ }
+ },
+ 'modules' => {
+ 'timer' => {}
+ },
+ 'plugs' => {
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ },
+ 'interrupt_peripheral' => {
+ 'interrupt_peripheral' => {},
+ '0' => {
+ 'name' => 'intrp'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ '0' => {
+ 'width' => 5,
+ 'name' => 'wb',
+ 'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl'
+ },
+ 'value' => 1,
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'parameters_order' => [
+ 'CNTw',
+ 'Dw',
+ 'Aw',
+ 'TAGw',
+ 'SELw'
+ ],
+ 'ports' => {
+ 'sa_tag_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'tag_i',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_dat_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 'sa_rty_o' => {
+ 'intfc_port' => 'rty_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'sel_i',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_we_i' => {
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'irq' => {
+ 'intfc_port' => 'int_o',
+ 'intfc_name' => 'plug:interrupt_peripheral[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_err_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'err_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_cyc_i' => {
+ 'intfc_port' => 'cyc_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'sa_ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'sa_addr_i' => {
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 'sa_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/timer/timer.v',
+ 'sockets' => {},
+ 'module_name' => 'timer',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'cti_i',
+ 'bte_i'
+ ]
+ },
+ 'category' => 'Timer'
+ }, 'ip_gen' );
Timer/timer.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property