URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip
- from Rev 34 to Rev 38
- ↔ Reverse comparison
Rev 34 → Rev 38
/Eth/ethmac_100.IP
File deleted
Eth/ethmac_100.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: JTAG/altera_jtag_uart.IP
===================================================================
--- JTAG/altera_jtag_uart.IP (revision 34)
+++ JTAG/altera_jtag_uart.IP (nonexistent)
@@ -1,205 +0,0 @@
-#######################################################################
-## File: altera_jtag_uart.IP
-##
-## Copyright (C) 2014-2016 Alireza Monemi
-##
-## This file is part of ProNoC 1.5.0
-##
-## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
-## MAY CAUSE UNEXPECTED BEHAIVOR.
-################################################################################
-
-$altera_jtag_uart_wb = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/jtag/altera_jtag_uart_wb.v'
- ],
- 'system_h' => '#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE)))
-#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4)))
-#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000
-#define ${IP}_DATA_RVALID_MSK 0x00008000
-#define ${IP}_DATA_DATA_MSK 0x000000FF
-
-//////////////////////////////*basic function for jtag_uart*////////////////////////////////////////
-void jtag_putchar(char ch);
-char jtag_getchar(void);
-void outbyte(char c){jtag_putchar(c);} //called in printf();
-char inbyte(){return jtag_getchar();}
-
-void jtag_putchar(char ch){ //print one char from jtag_uart
- while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0);
- ${IP}_DATA_REG=ch;
-}
-
-char jtag_getchar(void){ //get one char from jtag_uart
- unsigned int data;
- data=${IP}_DATA_REG;
- while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input
- data=${IP}_DATA_REG;
- return (data & ${IP}_DATA_DATA_MSK);
-}
-
-int jtag_scanstr(char* buf){ //scan string until to buf, return str length
- char ch; unsigned int i=0;
- while(1){
- ch=jtag_getchar();
- if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER
- else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace
- else { jtag_putchar(ch); buf[i]=ch; i++; } //valid
- }
- return i;
-}
-
-int jtag_scanint(int *num){ //return the scanned integer
- unsigned int curr_num,strlen,i=0;
- char str[11];
- strlen=jtag_scanstr(str); //scan str
- if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow
- *num=0;
- for(i=0;i9); //not integer: do nothing
- else *num=*num*10+curr_num; //is integer
- }
- return 0;
-}
-
-
-
-/////////////////////////////*END: basic function for jtag_uart*////////////////////////////////////',
- 'ip_name' => 'altera_jtag_uart',
- 'gui_status' => {
- 'timeout' => 0,
- 'status' => 'ideal'
- },
- 'modules' => {
- 'qsys_jtag_uart_0_scfifo_w' => {},
- 'qsys_jtag_uart_0_scfifo_r' => {},
- 'qsys_jtag_uart_0_sim_scfifo_r' => {},
- 'qsys_jtag_uart_0' => {},
- 'altera_jtag_uart_wb' => {},
- 'qsys_jtag_uart_0_sim_scfifo_w' => {}
- },
- 'plugs' => {
- 'interrupt_peripheral' => {
- 'interrupt_peripheral' => {},
- '0' => {
- 'name' => 'intrpt'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- '0' => {
- 'name' => 'reset'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- '0' => {
- 'name' => 'clk'
- },
- 'value' => 1,
- 'type' => 'num'
- },
- 'wb_slave' => {
- '0' => {
- 'width' => 5,
- 'name' => 'wb_slave',
- 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'
- },
- 'value' => 1,
- 'type' => 'num',
- 'wb_slave' => {}
- }
- },
- 'ports' => {
- 'wb_irq' => {
- 'intfc_port' => 'int_o',
- 'intfc_name' => 'plug:interrupt_peripheral[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'stb_i' => {
- 'intfc_port' => 'stb_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'cyc_i' => {
- 'intfc_port' => 'cyc_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'dat_i' => {
- 'intfc_port' => 'dat_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => ' 31: 0',
- 'type' => 'input'
- },
- 'rst' => {
- 'intfc_port' => 'reset_i',
- 'intfc_name' => 'plug:reset[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'ack_o' => {
- 'intfc_port' => 'ack_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 'readyfordata' => {
- 'intfc_port' => 'NC',
- 'intfc_name' => 'IO',
- 'range' => '',
- 'type' => 'output'
- },
- 'adr_i' => {
- 'intfc_port' => 'adr_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'dat_o' => {
- 'intfc_port' => 'dat_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => ' 31: 0',
- 'type' => 'output'
- },
- 'clk' => {
- 'intfc_port' => 'clk_i',
- 'intfc_name' => 'plug:clk[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'we_i' => {
- 'intfc_port' => 'we_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'dataavailable' => {
- 'intfc_port' => 'NC',
- 'intfc_name' => 'IO',
- 'range' => '',
- 'type' => 'output'
- }
- },
- 'file_name' => '/home/jaytang/Desktop/alisoc/mpsoc/src_peripheral/jtag/altera_jtag_uart_wb.v',
- 'module_name' => 'altera_jtag_uart_wb',
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'err_o',
- 'rty_o',
- 'tag_i',
- 'cti_i',
- 'sel_i',
- 'bte_i'
- ]
- },
- 'category' => 'JTAG'
- }, 'ip_gen' );
JTAG/altera_jtag_uart.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: JTAG/jtag_wb.IP
===================================================================
--- JTAG/jtag_wb.IP (revision 34)
+++ JTAG/jtag_wb.IP (nonexistent)
@@ -1,219 +0,0 @@
-#######################################################################
-## File: jtag_wb.IP
-##
-## Copyright (C) 2014-2016 Alireza Monemi
-##
-## This file is part of ProNoC 1.5.1
-##
-## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
-## MAY CAUSE UNEXPECTED BEHAIVOR.
-################################################################################
-
-$vjtag_wb = bless( {
- 'plugs' => {
- 'wb_master' => {
- 'wb_master' => {},
- 'value' => 1,
- 'type' => 'num',
- '0' => {
- 'name' => 'wbm'
- }
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- 'type' => 'num',
- '0' => {
- 'name' => 'reset'
- }
- },
- 'clk' => {
- 'type' => 'num',
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'clk' => {}
- }
- },
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/jtag/jtag_wb/vjtag_wb.v',
- 'parameters_order' => [
- 'DW',
- 'AW',
- 'S_Aw',
- 'M_Aw',
- 'TAGw',
- 'SELw',
- 'VJTAG_INDEX'
- ],
- 'modules' => {
- 'vjtag_wb' => {},
- 'wb_if' => {},
- 'vjtag_ctrl' => {}
- },
- 'description' => 'A jtag to wishbone interface',
- 'module_name' => 'vjtag_wb',
- 'parameters' => {
- 'SELw' => {
- 'info' => 'Parameter',
- 'content' => '',
- 'type' => 'Fixed',
- 'deafult' => ' 4',
- 'redefine_param' => 1,
- 'global_param' => 'Localparam'
- },
- 'TAGw' => {
- 'global_param' => 'Localparam',
- 'info' => 'Parameter',
- 'content' => '',
- 'deafult' => ' 3',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'S_Aw' => {
- 'global_param' => 'Localparam',
- 'type' => 'Fixed',
- 'deafult' => ' 7',
- 'redefine_param' => 1,
- 'info' => 'Parameter',
- 'content' => ''
- },
- 'M_Aw' => {
- 'global_param' => 'Localparam',
- 'content' => '',
- 'info' => 'Parameter',
- 'redefine_param' => 1,
- 'type' => 'Fixed',
- 'deafult' => ' 32'
- },
- 'DW' => {
- 'global_param' => 'Localparam',
- 'deafult' => '32',
- 'type' => 'Spin-button',
- 'redefine_param' => 1,
- 'info' => 'Parameter',
- 'content' => '4,1024,8'
- },
- 'AW' => {
- 'global_param' => 'Localparam',
- 'info' => 'Parameter',
- 'content' => '',
- 'type' => 'Fixed',
- 'deafult' => '32',
- 'redefine_param' => 1
- },
- 'VJTAG_INDEX' => {
- 'content' => '',
- 'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.',
- 'redefine_param' => 1,
- 'deafult' => 'CORE_ID',
- 'type' => 'Entry',
- 'global_param' => 'Localparam'
- }
- },
- 'ports' => {
- 'm_we_o' => {
- 'range' => '',
- 'intfc_port' => 'we_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'type' => 'output'
- },
- 'm_dat_i' => {
- 'range' => 'DW-1 : 0',
- 'intfc_port' => 'dat_i',
- 'type' => 'input',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'clk' => {
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'intfc_name' => 'plug:clk[0]',
- 'type' => 'input'
- },
- 'm_addr_o' => {
- 'range' => 'M_Aw-1 : 0',
- 'intfc_port' => 'adr_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'type' => 'output'
- },
- 'm_cyc_o' => {
- 'intfc_port' => 'cyc_o',
- 'range' => '',
- 'type' => 'output',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'm_dat_o' => {
- 'type' => 'output',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => 'DW-1 : 0',
- 'intfc_port' => 'dat_o'
- },
- 'm_sel_o' => {
- 'type' => 'output',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => 'SELw-1 : 0',
- 'intfc_port' => 'sel_o'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'type' => 'input',
- 'range' => '',
- 'intfc_port' => 'reset_i'
- },
- 'm_ack_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'type' => 'input',
- 'range' => '',
- 'intfc_port' => 'ack_i'
- },
- 'status_i' => {
- 'range' => '',
- 'intfc_port' => 'NC',
- 'intfc_name' => 'IO',
- 'type' => 'input'
- },
- 'm_cti_o' => {
- 'intfc_port' => 'cti_o',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'output',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'm_stb_o' => {
- 'type' => 'output',
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'stb_o',
- 'range' => ''
- }
- },
- 'hdl_files' => [
- '/mpsoc/src_peripheral/jtag/jtag_wb'
- ],
- 'ip_name' => 'jtag_wb',
- 'gui_status' => {
- 'timeout' => 0,
- 'status' => 'ideal'
- },
- 'unused' => {
- 'plug:wb_master[0]' => [
- 'bte_o',
- 'tag_o',
- 'rty_i',
- 'err_i'
- ]
- },
- 'category' => 'JTAG',
- 'ports_order' => [
- 'clk',
- 'reset',
- 'm_sel_o',
- 'm_dat_o',
- 'm_addr_o',
- 'm_cti_o',
- 'm_stb_o',
- 'm_cyc_o',
- 'm_we_o',
- 'm_dat_i',
- 'm_ack_i',
- 'status_i'
- ]
- }, 'ip_gen' );
JTAG/jtag_wb.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: Bus/wishbone_bus.IP
===================================================================
--- Bus/wishbone_bus.IP (revision 34)
+++ Bus/wishbone_bus.IP (revision 38)
@@ -117,7 +117,7 @@
'content' => '4,128,1',
'info' => 'The wishbone Bus address width',
'type' => 'Spin-button',
- 'deafult' => '32'
+ 'default' => '32'
},
'M' => {
'global_param' => 'Localparam',
@@ -125,10 +125,10 @@
'redefine_param' => 1,
'type' => 'Spin-button',
'info' => 'Number of wishbone master interface',
- 'deafult' => ' 4'
+ 'default' => ' 4'
},
'TAGw' => {
- 'deafult' => '3',
+ 'default' => '3',
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
@@ -141,13 +141,13 @@
'redefine_param' => 1,
'type' => 'Fixed',
'info' => undef,
- 'deafult' => '2 '
+ 'default' => '2 '
},
'S' => {
'content' => '1,256,1',
'redefine_param' => 1,
'global_param' => 'Localparam',
- 'deafult' => '4',
+ 'default' => '4',
'info' => 'Number of wishbone slave interface',
'type' => 'Spin-button'
},
@@ -155,7 +155,7 @@
'content' => '8,512,8',
'redefine_param' => 1,
'global_param' => 'Localparam',
- 'deafult' => '32',
+ 'default' => '32',
'type' => 'Spin-button',
'info' => 'The wishbone Bus data width in bits.'
},
@@ -162,7 +162,7 @@
'CTIw' => {
'type' => 'Fixed',
'info' => undef,
- 'deafult' => '3',
+ 'default' => '3',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
@@ -173,7 +173,7 @@
'content' => '',
'type' => 'Fixed',
'info' => undef,
- 'deafult' => 'Dw/8'
+ 'default' => 'Dw/8'
}
},
'hdl_files' => [
Index: Communication/ethmac_100.IP
===================================================================
--- Communication/ethmac_100.IP (nonexistent)
+++ Communication/ethmac_100.IP (revision 38)
@@ -0,0 +1,468 @@
+#######################################################################
+## File: ethmac_100.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.7.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ethtop = bless( {
+ 'version' => 1,
+ 'module_name' => 'ethtop',
+ 'unused' => {
+ 'plug:wb_master[0]' => [
+ 'bte_o',
+ 'rty_i',
+ 'cti_o',
+ 'tag_o'
+ ],
+ 'plug:wb_slave[0]' => [
+ 'cti_i',
+ 'bte_i',
+ 'tag_i',
+ 'rty_o'
+ ]
+ },
+ 'plugs' => {
+ 'wb_master' => {
+ 'wb_master' => {},
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'wb_master'
+ }
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ 'wb_slave' => {},
+ 'type' => 'num',
+ '0' => {
+ 'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller',
+ 'width' => 11,
+ 'name' => 'wb_slave'
+ }
+ },
+ 'clk' => {
+ 'value' => 1,
+ 'clk' => {},
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'clk'
+ }
+ },
+ 'interrupt_peripheral' => {
+ 'value' => 1,
+ 'interrupt_peripheral' => {},
+ '0' => {
+ 'name' => 'interrupt_peripheral'
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num',
+ 'reset' => {}
+ }
+ },
+ 'custom_file_num' => 1,
+ 'ports' => {
+ 'wb_clk_i' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i',
+ 'type' => 'input'
+ },
+ 'm_wb_adr_o' => {
+ 'intfc_port' => 'adr_o',
+ 'type' => 'output',
+ 'range' => '31:0',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'mtxd_pad_o' => {
+ 'intfc_port' => 'IO',
+ 'type' => 'output',
+ 'range' => '3:0',
+ 'intfc_name' => 'IO'
+ },
+ 'int_o' => {
+ 'intfc_port' => 'int_o',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_name' => 'plug:interrupt_peripheral[0]'
+ },
+ 'mdc_pad_o' => {
+ 'intfc_port' => 'IO',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_name' => 'IO'
+ },
+ 'wb_ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'mtxen_pad_o' => {
+ 'intfc_port' => 'IO',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_name' => 'IO'
+ },
+ 'wb_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'type' => 'input',
+ 'range' => '31:0',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'wb_stb_i' => {
+ 'type' => 'input',
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => ''
+ },
+ 'mcrs_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'IO'
+ },
+ 'wb_rst_i' => {
+ 'type' => 'input',
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => ''
+ },
+ 'm_wb_dat_i' => {
+ 'range' => '31:0',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'dat_i',
+ 'type' => 'input'
+ },
+ 'md_pad_o' => {
+ 'range' => '',
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'type' => 'output'
+ },
+ 'mcoll_pad_i' => {
+ 'range' => '',
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'type' => 'input'
+ },
+ 'm_wb_stb_o' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'stb_o',
+ 'type' => 'output'
+ },
+ 'm_wb_err_i' => {
+ 'type' => 'input',
+ 'intfc_port' => 'err_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => ''
+ },
+ 'm_wb_cyc_o' => {
+ 'intfc_port' => 'cyc_o',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'mtx_clk_pad_i' => {
+ 'intfc_port' => 'IO',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'IO'
+ },
+ 'wb_err_o' => {
+ 'intfc_port' => 'err_o',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'wb_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'cyc_i'
+ },
+ 'm_wb_dat_o' => {
+ 'range' => '31:0',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'dat_o',
+ 'type' => 'output'
+ },
+ 'mrxdv_pad_i' => {
+ 'intfc_port' => 'IO',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'IO'
+ },
+ 'md_padoe_o' => {
+ 'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_port' => 'IO'
+ },
+ 'wb_dat_o' => {
+ 'range' => '31:0',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'type' => 'output'
+ },
+ 'm_wb_ack_i' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'ack_i',
+ 'type' => 'input'
+ },
+ 'm_wb_we_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_port' => 'we_o'
+ },
+ 'mrx_clk_pad_i' => {
+ 'intfc_port' => 'IO',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'IO'
+ },
+ 'wb_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '3:0',
+ 'type' => 'input',
+ 'intfc_port' => 'sel_i'
+ },
+ 'm_wb_sel_o' => {
+ 'type' => 'output',
+ 'intfc_port' => 'sel_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '3:0'
+ },
+ 'mtxerr_pad_o' => {
+ 'range' => '',
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO',
+ 'type' => 'output'
+ },
+ 'wb_we_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'we_i'
+ },
+ 'mrxerr_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'IO'
+ },
+ 'wb_adr_i' => {
+ 'type' => 'input',
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '9:0'
+ },
+ 'mrxd_pad_i' => {
+ 'type' => 'input',
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'range' => '3:0'
+ },
+ 'md_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'IO'
+ }
+ },
+ 'system_h' => '
+
+void ${IP}_init();
+void ${IP}_interrupt();
+void ${IP}_recv_ack(void);
+int ${IP}_send(int length); //return (-1) or length (still processing previous) or asserted
+
+#define ${IP}_BASE_ADDR $BASE
+#define ${IP}_MODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x00 )))
+#define ${IP}_INT_SOURCE (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x04 )))
+#define ${IP}_INT_MASK (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x08 )))
+#define ${IP}_IPGT (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x0C )))
+#define ${IP}_IPGR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x10 )))
+#define ${IP}_IPGR2 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x14 )))
+#define ${IP}_PACKETLEN (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x18 )))
+#define ${IP}_COLLCONF (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x1C )))
+#define ${IP}_TX_BD_NUM (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x20 )))
+#define ${IP}_CTRLMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x24 )))
+#define ${IP}_MIIMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x28 )))
+#define ${IP}_MIICOMMAND (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x2C )))
+#define ${IP}_MIIADDR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x30 )))
+#define ${IP}_MIITX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x34 )))
+#define ${IP}_MIIRX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x38 )))
+#define ${IP}_MIISTATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x3C )))
+#define ${IP}_MAC_ADDR0 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x40 )))
+#define ${IP}_MAC_ADDR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x44 )))
+#define ${IP}_HASH0_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x48 )))
+#define ${IP}_HASH1_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x4C )))
+#define ${IP}_TXCTRL (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x50 )))
+#define ${IP}_TXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x404 )))
+#define ${IP}_TXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x400 )))
+#define ${IP}_RXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value
+#define ${IP}_RXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value
+
+
+#include "${IP}.h"',
+ 'ip_name' => 'ethmac_100',
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ethmac/ethtop.v',
+ 'ports_order' => [
+ 'wb_clk_i',
+ 'wb_rst_i',
+ 'wb_dat_i',
+ 'wb_dat_o',
+ 'wb_adr_i',
+ 'wb_sel_i',
+ 'wb_we_i',
+ 'wb_cyc_i',
+ 'wb_stb_i',
+ 'wb_ack_o',
+ 'wb_err_o',
+ 'm_wb_adr_o',
+ 'm_wb_sel_o',
+ 'm_wb_we_o',
+ 'm_wb_dat_o',
+ 'm_wb_dat_i',
+ 'm_wb_cyc_o',
+ 'm_wb_stb_o',
+ 'm_wb_ack_i',
+ 'm_wb_err_i',
+ 'mtx_clk_pad_i',
+ 'mtxd_pad_o',
+ 'mtxen_pad_o',
+ 'mtxerr_pad_o',
+ 'mrx_clk_pad_i',
+ 'mrxd_pad_i',
+ 'mrxdv_pad_i',
+ 'mrxerr_pad_i',
+ 'mcoll_pad_i',
+ 'mcrs_pad_i',
+ 'mdc_pad_o',
+ 'md_pad_i',
+ 'md_pad_o',
+ 'md_padoe_o',
+ 'int_o'
+ ],
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_clockgen.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_cop.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_crc.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/ethmac.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_maccontrol.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/ethmac_defines.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_macstatus.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_miim.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_outputcontrol.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_random.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_receivecontrol.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_register.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_registers.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_rxaddrcheck.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_rxcounters.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_rxethmac.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_rxstatem.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_shiftreg.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_spram_256x32.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_top.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_transmitcontrol.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_txcounters.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_txethmac.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_txstatem.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/eth_wishbone.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/timescale.v',
+ '/mpsoc/src_peripheral/ethmac/rtl/xilinx_dist_ram_16x32.v',
+ '/mpsoc/src_peripheral/ethmac/ethtop.v',
+ '/mpsoc/src_peripheral/ethmac/eth_generic_ram.v'
+ ],
+ 'parameters_order' => [
+ 'TX_FIFO_DATA_WIDTH',
+ 'TX_FIFO_DEPTH',
+ 'TX_FIFO_CNT_WIDTH',
+ 'RX_FIFO_DATA_WIDTH',
+ 'RX_FIFO_DEPTH',
+ 'RX_FIFO_CNT_WIDTH'
+ ],
+ 'description' => 'The Ethernet MAC 10/100 Mbps.
+For more information please check: https://opencores.org/project,ethmac',
+ 'gen_sw_files' => [
+ '/mpsoc/src_peripheral/ethmac/ethfrename_sep_t${IP}.h'
+ ],
+ 'parameters' => {
+ 'RX_FIFO_DEPTH' => {
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'default' => ' 16',
+ 'info' => undef,
+ 'type' => 'Fixed',
+ 'global_param' => 0
+ },
+ 'TX_FIFO_DEPTH' => {
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'default' => ' 16',
+ 'info' => undef,
+ 'global_param' => 0,
+ 'type' => 'Fixed'
+ },
+ 'RX_FIFO_DATA_WIDTH' => {
+ 'type' => 'Fixed',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'info' => undef,
+ 'default' => ' 32'
+ },
+ 'TX_FIFO_DATA_WIDTH' => {
+ 'redefine_param' => 1,
+ 'content' => '',
+ 'default' => ' 32',
+ 'info' => undef,
+ 'type' => 'Fixed',
+ 'global_param' => 0
+ },
+ 'RX_FIFO_CNT_WIDTH' => {
+ 'default' => ' 5',
+ 'redefine_param' => 1,
+ 'content' => '',
+ 'info' => undef,
+ 'global_param' => 0,
+ 'type' => 'Fixed'
+ },
+ 'TX_FIFO_CNT_WIDTH' => {
+ 'type' => 'Fixed',
+ 'global_param' => 0,
+ 'info' => undef,
+ 'redefine_param' => 1,
+ 'content' => '',
+ 'default' => ' 5'
+ }
+ },
+ 'sw_files' => [],
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'custom_file' => {
+ '0' => {}
+ },
+ 'category' => 'Communication',
+ 'modules' => {
+ 'ethtop' => {}
+ }
+ }, 'ip_gen' );
Communication/ethmac_100.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Communication/jtag_uart.IP
===================================================================
--- Communication/jtag_uart.IP (nonexistent)
+++ Communication/jtag_uart.IP (revision 38)
@@ -0,0 +1,279 @@
+#######################################################################
+## File: jtag_uart.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.8.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ipgen = bless( {
+ 'plugs' => {
+ 'reset' => {
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ },
+ 'interrupt_peripheral' => {
+ '0' => {
+ 'name' => 'interrupt_peripheral'
+ },
+ 'type' => 'num',
+ 'value' => 1
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ '0' => {
+ 'name' => 'wb_slave',
+ 'width' => 5,
+ 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'clk'
+ }
+ }
+ },
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/jtag/jtag_uart/altera_jtag_uart_wb.v',
+ '/mpsoc/src_peripheral/jtag/jtag_uart/jtag_uart_wb.v',
+ '/mpsoc/src_peripheral/jtag/jtag_uart/altera_simulator_UART.v'
+ ],
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'parameters_order' => [
+ 'FPGA_VENDOR',
+ 'SIM_BUFFER_SIZE',
+ 'SIM_WAIT_COUNT'
+ ],
+ 'description' => 'The Altera JTAG UART core with Wishbone bus interface.',
+ 'system_h' => '#include "define_printf.h" // This file must be available in processor folder which define the printf function
+
+#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE)))
+#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000
+#define ${IP}_DATA_RVALID_MSK 0x00008000
+#define ${IP}_DATA_DATA_MSK 0x000000FF
+
+//////////////////////////////*basic function for jtag_uart*////////////////////////////////////////
+void jtag_putchar(char ch);
+char jtag_getchar(void);
+void outbyte(char c){jtag_putchar(c);} //called in printf();
+char inbyte(){return jtag_getchar();}
+
+void jtag_putchar(char ch){ //print one char from jtag_uart
+ while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0);
+ ${IP}_DATA_REG=ch;
+}
+
+char jtag_getchar(void){ //get one char from jtag_uart
+ unsigned int data;
+ data=${IP}_DATA_REG;
+ while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input
+ data=${IP}_DATA_REG;
+ return (data & ${IP}_DATA_DATA_MSK);
+}
+
+int jtag_scanstr(char* buf){ //scan string until to buf, return str length
+ char ch; unsigned int i=0;
+ while(1){
+ ch=jtag_getchar();
+ if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER
+ else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace
+ else { jtag_putchar(ch); buf[i]=ch; i++; } //valid
+ }
+ return i;
+}
+
+int jtag_scanint(int *num){ //return the scanned integer
+ unsigned int curr_num,strlen,i=0;
+ char str[11];
+ strlen=jtag_scanstr(str); //scan str
+ if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow
+ *num=0;
+ for(i=0;i9); //not integer: do nothing
+ else *num=*num*10+curr_num; //is integer
+ }
+ return 0;
+}
+
+
+
+/////////////////////////////*END: basic function for jtag_uart*////////////////////////////////////',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'rty_o',
+ 'bte_i',
+ 'err_o',
+ 'tag_i'
+ ]
+ },
+ 'version' => 14,
+ 'parameters' => {
+ 'SIM_WAIT_COUNT' => {
+ 'global_param' => 'Localparam',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1,
+ 'content' => '2,100000,1',
+ 'default' => '1000',
+ 'info' => 'This parameter is valid only in simulation.
+If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.'
+ },
+ 'SIM_BUFFER_SIZE' => {
+ 'global_param' => 'Localparam',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1,
+ 'content' => '10,10000,1',
+ 'info' => 'Internal buffer size.
+This parameter is valid only in simulation.
+If internal buffer overflows, the buffer content are displayed on simulator terminal.',
+ 'default' => '100'
+ },
+ 'FPGA_VENDOR' => {
+ 'default' => ' "ALTERA"',
+ 'info' => 'FPGA VENDOR name. Only Altera FPGA is supported. Currently the Generic serial port is not supported. ',
+ 'content' => ' "ALTERA"',
+ 'redefine_param' => 1,
+ 'type' => 'Combo-box',
+ 'global_param' => 'Localparam'
+ }
+ },
+ 'ports_order' => [
+ 'reset',
+ 'clk',
+ 'irq',
+ 's_dat_i',
+ 's_sel_i',
+ 's_addr_i',
+ 's_cti_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 'RxD_din_sim',
+ 'RxD_wr_sim',
+ 'RxD_ready_sim'
+ ],
+ 'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/jtag/jtag_uart/jtag_uart_wb.v',
+ 'category' => 'Communication',
+ 'module_name' => 'jtag_uart_wb',
+ 'modules' => {
+ 'jtag_uart_wb' => {}
+ },
+ 'ip_name' => 'jtag_uart',
+ 'ports' => {
+ 's_dat_i' => {
+ 'range' => '31 : 0',
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'input'
+ },
+ 'RxD_din_sim' => {
+ 'type' => 'input',
+ 'range' => '7:0 ',
+ 'intfc_port' => 'RxD_din_sim',
+ 'intfc_name' => 'socket:RxD_sim[0]'
+ },
+ 's_stb_i' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 's_addr_i' => {
+ 'type' => 'input',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'intfc_port' => 'adr_i'
+ },
+ 's_cti_i' => {
+ 'type' => 'input',
+ 'range' => '2 : 0',
+ 'intfc_port' => 'cti_i',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'irq' => {
+ 'type' => 'output',
+ 'intfc_name' => 'plug:interrupt_peripheral[0]',
+ 'intfc_port' => 'int_o',
+ 'range' => ''
+ },
+ 'RxD_ready_sim' => {
+ 'type' => 'output',
+ 'intfc_name' => 'socket:RxD_sim[0]',
+ 'intfc_port' => 'RxD_ready_sim',
+ 'range' => ''
+ },
+ 's_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'intfc_port' => 'cyc_i',
+ 'type' => 'input'
+ },
+ 's_dat_o' => {
+ 'type' => 'output',
+ 'range' => '31 : 0',
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'intfc_port' => 'clk_i',
+ 'type' => 'input'
+ },
+ 'RxD_wr_sim' => {
+ 'type' => 'input',
+ 'intfc_port' => 'RxD_wr_sim',
+ 'range' => '',
+ 'intfc_name' => 'socket:RxD_sim[0]'
+ },
+ 's_ack_o' => {
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_port' => 'ack_o',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 's_sel_i' => {
+ 'range' => '3 : 0',
+ 'intfc_port' => 'sel_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'input'
+ },
+ 's_we_i' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'sockets' => {
+ 'RxD_sim' => {
+ '0' => {
+ 'name' => 'RxD_sim'
+ },
+ 'type' => 'num',
+ 'value' => 1,
+ 'connection_num' => 'single connection'
+ }
+ }
+ }, 'ip_gen' );
Communication/jtag_uart.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Communication/jtag_wb.IP
===================================================================
--- Communication/jtag_wb.IP (nonexistent)
+++ Communication/jtag_wb.IP (revision 38)
@@ -0,0 +1,220 @@
+#######################################################################
+## File: jtag_wb.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.8.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ipgen = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/jtag/jtag_wb'
+ ],
+ 'modules' => {
+ 'vjtag_wb' => {},
+ 'vjtag_ctrl' => {},
+ 'wb_if' => {}
+ },
+ 'unused' => {
+ 'plug:wb_master[0]' => [
+ 'rty_i',
+ 'tag_o',
+ 'err_i',
+ 'bte_o'
+ ]
+ },
+ 'parameters_order' => [
+ 'DW',
+ 'AW',
+ 'S_Aw',
+ 'M_Aw',
+ 'TAGw',
+ 'SELw',
+ 'VJTAG_INDEX'
+ ],
+ 'category' => 'Communication',
+ 'module_name' => 'vjtag_wb',
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/jtag/jtag_wb/vjtag_wb.v',
+ 'version' => 1,
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 'm_sel_o',
+ 'm_dat_o',
+ 'm_addr_o',
+ 'm_cti_o',
+ 'm_stb_o',
+ 'm_cyc_o',
+ 'm_we_o',
+ 'm_dat_i',
+ 'm_ack_i',
+ 'status_i'
+ ],
+ 'plugs' => {
+ 'clk' => {
+ 'clk' => {},
+ 'type' => 'num',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ }
+ },
+ 'reset' => {
+ 'type' => 'num',
+ 'value' => 1,
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ }
+ },
+ 'wb_master' => {
+ 'type' => 'num',
+ 'value' => 1,
+ 'wb_master' => {},
+ '0' => {
+ 'name' => 'wbm'
+ }
+ }
+ },
+ 'ip_name' => 'jtag_wb',
+ 'parameters' => {
+ 'DW' => {
+ 'default' => '32',
+ 'info' => 'Parameter',
+ 'content' => '4,1024,8',
+ 'redefine_param' => 1,
+ 'global_param' => 'Localparam',
+ 'type' => 'Spin-button'
+ },
+ 'VJTAG_INDEX' => {
+ 'global_param' => 'Localparam',
+ 'redefine_param' => 1,
+ 'type' => 'Entry',
+ 'default' => 'CORE_ID',
+ 'content' => '',
+ 'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.'
+ },
+ 'S_Aw' => {
+ 'global_param' => 'Localparam',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed',
+ 'default' => ' 7',
+ 'content' => '',
+ 'info' => 'Parameter'
+ },
+ 'SELw' => {
+ 'content' => '',
+ 'info' => 'Parameter',
+ 'default' => ' 4',
+ 'type' => 'Fixed',
+ 'global_param' => 'Localparam',
+ 'redefine_param' => 1
+ },
+ 'TAGw' => {
+ 'default' => ' 3',
+ 'content' => '',
+ 'info' => 'Parameter',
+ 'redefine_param' => 1,
+ 'global_param' => 'Localparam',
+ 'type' => 'Fixed'
+ },
+ 'AW' => {
+ 'type' => 'Fixed',
+ 'global_param' => 'Localparam',
+ 'redefine_param' => 1,
+ 'content' => '',
+ 'info' => 'Parameter',
+ 'default' => '32'
+ },
+ 'M_Aw' => {
+ 'type' => 'Fixed',
+ 'global_param' => 'Localparam',
+ 'redefine_param' => 1,
+ 'info' => 'Parameter',
+ 'content' => '',
+ 'default' => ' 32'
+ }
+ },
+ 'description' => 'A jtag to wishbone bus interface.',
+ 'ports' => {
+ 'm_stb_o' => {
+ 'intfc_port' => 'stb_o',
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'm_cyc_o' => {
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'm_addr_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'output',
+ 'range' => 'M_Aw-1 : 0',
+ 'intfc_port' => 'adr_o'
+ },
+ 'm_dat_o' => {
+ 'type' => 'output',
+ 'range' => 'DW-1 : 0',
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'status_i' => {
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'NC',
+ 'intfc_name' => 'IO'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:clk[0]'
+ },
+ 'm_ack_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_port' => 'ack_i'
+ },
+ 'm_dat_i' => {
+ 'type' => 'input',
+ 'range' => 'DW-1 : 0',
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'm_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'output',
+ 'intfc_port' => 'sel_o'
+ },
+ 'm_cti_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'output',
+ 'intfc_port' => 'cti_o'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:reset[0]'
+ },
+ 'm_we_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_port' => 'we_o'
+ }
+ },
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ }
+ }, 'ip_gen' );
Communication/jtag_wb.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: DMA/dma.IP
===================================================================
--- DMA/dma.IP (revision 34)
+++ DMA/dma.IP (revision 38)
@@ -3,403 +3,382 @@
##
## Copyright (C) 2014-2016 Alireza Monemi
##
-## This file is part of ProNoC 1.7.0
+## This file is part of ProNoC 1.8.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
-$dma_multi_chan_wb = bless( {
- 'parameters_order' => [
- 'CHANNEL',
- 'MAX_TRANSACTION_WIDTH',
- 'MAX_BURST_SIZE',
- 'FIFO_B',
- 'DEBUG_EN',
- 'Dw',
- 'S_Aw',
- 'M_Aw',
- 'TAGw',
- 'SELw'
- ],
- 'ports_order' => [
- 'reset',
- 'clk',
- 's_dat_i',
- 's_sel_i',
- 's_addr_i',
- 's_cti_i',
- 's_stb_i',
- 's_cyc_i',
- 's_we_i',
- 's_dat_o',
- 's_ack_o',
- 'm_rd_sel_o',
- 'm_rd_addr_o',
- 'm_rd_cti_o',
- 'm_rd_stb_o',
- 'm_rd_cyc_o',
- 'm_rd_we_o',
- 'm_rd_dat_i',
- 'm_rd_ack_i',
- 'm_wr_sel_o',
- 'm_wr_dat_o',
- 'm_wr_addr_o',
- 'm_wr_cti_o',
- 'm_wr_stb_o',
- 'm_wr_cyc_o',
- 'm_wr_we_o',
- 'm_wr_ack_i',
- 'irq'
- ],
- 'module_name' => 'dma_multi_chan_wb',
- 'unused' => {
- 'plug:wb_master[0]' => [
- 'dat_o',
- 'bte_o',
- 'rty_i',
- 'err_i',
- 'tag_o'
- ],
- 'plug:wb_master[1]' => [
- 'bte_o',
- 'rty_i',
- 'err_i',
- 'tag_o',
- 'dat_i'
- ],
- 'plug:wb_slave[0]' => [
- 'bte_i',
- 'rty_o',
- 'tag_i',
- 'err_o'
- ]
- },
- 'hdl_files' => [
- '/mpsoc/src_noc/main_comp.v',
- '/mpsoc/src_noc/arbiter.v',
- '/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',
- '/mpsoc/src_noc/flit_buffer.v'
- ],
- 'modules' => {
- 'shared_mem_fifos' => {},
- 'dma_single_wb' => {},
- 'dma_multi_chan_wb' => {}
- },
- 'gui_status' => {
- 'status' => 'ideal',
- 'timeout' => 0
+$ipgen = bless( {
+ 'description' => 'A wishbone bus round robin-based multi channel DMA (no byte enable is supported yet). The DMA supports burst data transaction.',
+ 'modules' => {
+ 'dma_multi_chan_wb' => {},
+ 'shared_mem_fifos' => {},
+ 'dma_single_wb' => {}
+ },
+ 'plugs' => {
+ 'clk' => {
+ 'type' => 'num',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'clk' => {}
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ 'wb_slave' => {},
+ 'type' => 'num',
+ '0' => {
+ 'width' => 10,
+ 'addr' => '0x9300_0000 0x93ff_ffff Memory Controller',
+ 'name' => 'wb_slave'
+ }
+ },
+ 'interrupt_peripheral' => {
+ 'value' => 1,
+ 'interrupt_peripheral' => {},
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'interrupt_peripheral'
+ }
+ },
+ 'wb_master' => {
+ '1' => {
+ 'name' => 'wb_wr'
+ },
+ 'wb_master' => {},
+ 'value' => 2,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'wb_rd'
+ }
},
- 'ports' => {
- 's_cti_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'cti_i',
- 'type' => 'input',
- 'range' => 'TAGw-1 : 0'
- },
- 's_we_i' => {
- 'range' => '',
- 'intfc_port' => 'we_i',
- 'type' => 'input',
- 'intfc_name' => 'plug:wb_slave[0]'
- },
- 's_cyc_i' => {
- 'range' => '',
- 'intfc_port' => 'cyc_i',
- 'type' => 'input',
- 'intfc_name' => 'plug:wb_slave[0]'
- },
- 's_dat_o' => {
- 'range' => 'Dw-1 : 0',
- 'intfc_port' => 'dat_o',
- 'type' => 'output',
- 'intfc_name' => 'plug:wb_slave[0]'
- },
- 's_addr_i' => {
- 'range' => 'S_Aw-1 : 0',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'type' => 'input',
- 'intfc_port' => 'adr_i'
- },
- 'm_wr_cyc_o' => {
- 'type' => 'output',
- 'intfc_port' => 'cyc_o',
- 'intfc_name' => 'plug:wb_master[1]',
- 'range' => ''
- },
- 'm_rd_dat_i' => {
- 'range' => 'Dw-1 : 0',
- 'type' => 'input',
- 'intfc_port' => 'dat_i',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'm_rd_cti_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'cti_o',
- 'type' => 'output',
- 'range' => 'TAGw-1 : 0'
- },
- 's_ack_o' => {
- 'range' => '',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'ack_o',
- 'type' => 'output'
- },
- 'clk' => {
- 'range' => '',
- 'intfc_name' => 'plug:clk[0]',
- 'type' => 'input',
- 'intfc_port' => 'clk_i'
- },
- 'm_wr_cti_o' => {
- 'range' => 'TAGw-1 : 0',
- 'intfc_name' => 'plug:wb_master[1]',
- 'type' => 'output',
- 'intfc_port' => 'cti_o'
- },
- 's_dat_i' => {
- 'range' => 'Dw-1 : 0',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'type' => 'input',
- 'intfc_port' => 'dat_i'
- },
- 'm_rd_stb_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'stb_o',
- 'type' => 'output',
- 'range' => ''
- },
- 's_sel_i' => {
- 'type' => 'input',
- 'intfc_port' => 'sel_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'SELw-1 : 0'
- },
- 'm_rd_we_o' => {
- 'type' => 'output',
- 'intfc_port' => 'we_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => ''
- },
- 'm_wr_dat_o' => {
- 'range' => 'Dw-1 : 0',
- 'intfc_name' => 'plug:wb_master[1]',
- 'type' => 'output',
- 'intfc_port' => 'dat_o'
- },
- 'm_wr_stb_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'type' => 'output',
- 'intfc_port' => 'stb_o',
- 'range' => ''
- },
- 'reset' => {
- 'range' => '',
- 'intfc_name' => 'plug:reset[0]',
- 'type' => 'input',
- 'intfc_port' => 'reset_i'
- },
- 'm_wr_addr_o' => {
- 'range' => 'M_Aw-1 : 0',
- 'intfc_port' => 'adr_o',
- 'type' => 'output',
- 'intfc_name' => 'plug:wb_master[1]'
- },
- 'm_rd_addr_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'type' => 'output',
- 'intfc_port' => 'adr_o',
- 'range' => 'M_Aw-1 : 0'
- },
- 'm_wr_sel_o' => {
- 'range' => 'SELw-1 : 0',
- 'intfc_name' => 'plug:wb_master[1]',
- 'type' => 'output',
- 'intfc_port' => 'sel_o'
- },
- 'm_wr_ack_i' => {
- 'range' => '',
- 'intfc_port' => 'ack_i',
- 'type' => 'input',
- 'intfc_name' => 'plug:wb_master[1]'
- },
- 's_stb_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'type' => 'input',
- 'range' => ''
- },
- 'm_wr_we_o' => {
- 'range' => '',
- 'intfc_name' => 'plug:wb_master[1]',
- 'type' => 'output',
- 'intfc_port' => 'we_o'
- },
- 'm_rd_cyc_o' => {
- 'range' => '',
- 'intfc_port' => 'cyc_o',
- 'type' => 'output',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'm_rd_sel_o' => {
- 'range' => 'SELw-1 : 0',
- 'intfc_port' => 'sel_o',
- 'type' => 'output',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'irq' => {
- 'type' => 'output',
- 'intfc_port' => 'int_o',
- 'intfc_name' => 'plug:interrupt_peripheral[0]',
- 'range' => ''
- },
- 'm_rd_ack_i' => {
- 'range' => '',
- 'type' => 'input',
- 'intfc_port' => 'ack_i',
- 'intfc_name' => 'plug:wb_master[0]'
- }
- },
- 'parameters' => {
- 'DEBUG_EN' => {
- 'info' => 'Parameter',
- 'content' => '',
- 'type' => 'Fixed',
- 'deafult' => '1',
- 'global_param' => 'Parameter',
- 'redefine_param' => 1
- },
- 'MAX_BURST_SIZE' => {
- 'redefine_param' => 1,
- 'type' => 'Combo-box',
- 'content' => '\'2,4,8,16,32,64,128,256,512,1024,2048\'',
- 'info' => 'Maximum burst size in words.
-The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active channels, another active channel will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ',
- 'global_param' => 'Parameter',
- 'deafult' => '256'
- },
- 'MAX_TRANSACTION_WIDTH' => {
- 'global_param' => 'Parameter',
- 'deafult' => '10',
- 'content' => '2,32,1',
- 'info' => 'The width of maximum transaction size in words.
-The maximum data that can be sent via one DMA channel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
- 'type' => 'Spin-button',
- 'redefine_param' => 1
- },
- 'FIFO_B' => {
- 'redefine_param' => 1,
- 'global_param' => 'Parameter',
- 'deafult' => '4',
- 'info' => 'Channel FIFO size in words.
+ 'reset' => {
+ 'type' => 'num',
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ }
+ }
+ },
+ 'ports_order' => [
+ 'reset',
+ 'clk',
+ 's_dat_i',
+ 's_sel_i',
+ 's_addr_i',
+ 's_cti_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 'm_rd_sel_o',
+ 'm_rd_addr_o',
+ 'm_rd_cti_o',
+ 'm_rd_stb_o',
+ 'm_rd_cyc_o',
+ 'm_rd_we_o',
+ 'm_rd_dat_i',
+ 'm_rd_ack_i',
+ 'm_wr_sel_o',
+ 'm_wr_dat_o',
+ 'm_wr_addr_o',
+ 'm_wr_cti_o',
+ 'm_wr_stb_o',
+ 'm_wr_cyc_o',
+ 'm_wr_we_o',
+ 'm_wr_ack_i',
+ 'irq'
+ ],
+ 'parameters_order' => [
+ 'CHANNEL',
+ 'MAX_TRANSACTION_WIDTH',
+ 'MAX_BURST_SIZE',
+ 'FIFO_B',
+ 'DEBUG_EN',
+ 'Dw',
+ 'S_Aw',
+ 'M_Aw',
+ 'TAGw',
+ 'SELw'
+ ],
+ 'ip_name' => 'dma',
+ 'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',
+ 'hdl_files' => [
+ '/mpsoc/src_noc/main_comp.v',
+ '/mpsoc/src_noc/arbiter.v',
+ '/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',
+ '/mpsoc/src_noc/flit_buffer.v'
+ ],
+ 'version' => 4,
+ 'category' => 'DMA',
+ 'module_name' => 'dma_multi_chan_wb',
+ 'parameters' => {
+ 'M_Aw' => {
+ 'redefine_param' => 1,
+ 'type' => 'Fixed',
+ 'default' => '32',
+ 'content' => '',
+ 'info' => 'Parameter',
+ 'global_param' => 'Parameter'
+ },
+ 'CHANNEL' => {
+ 'global_param' => 'Parameter',
+ 'info' => 'Number of DMA channels.
+In case there are multiple active DMA channels, Each time one single active DMA channel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter channel until its FIFO is not full and the number of sent data is smaller than the burst size.',
+ 'redefine_param' => 1,
+ 'type' => 'Spin-button',
+ 'default' => '1',
+ 'content' => '1,32,1'
+ },
+ 'SELw' => {
+ 'info' => 'Parameter',
+ 'global_param' => 'Parameter',
+ 'redefine_param' => 1,
+ 'default' => '4',
+ 'type' => 'Fixed',
+ 'content' => ''
+ },
+ 'Dw' => {
+ 'global_param' => 'Parameter',
+ 'info' => 'Wishbone bus Data size in bit',
+ 'redefine_param' => 1,
+ 'type' => 'Spin-button',
+ 'default' => '32',
+ 'content' => '8,1024,8'
+ },
+ 'FIFO_B' => {
+ 'global_param' => 'Parameter',
+ 'info' => 'Channel FIFO size in words.
All channels will share same FPGA block RAM. Hence, the total needed Block RAM words is the multiplication of channel num in channel FIFO size.
',
- 'content' => '\'2,4,8,16,32,64,128,256,512,1024,2048\'',
- 'type' => 'Combo-box'
- },
- 'Dw' => {
+ 'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
+ 'default' => '4',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 1
+ },
+ 'MAX_BURST_SIZE' => {
+ 'global_param' => 'Parameter',
+ 'info' => 'Maximum burst size in words.
+The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active channels, another active channel will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ',
+ 'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1,
- 'deafult' => '32',
- 'global_param' => 'Parameter',
- 'info' => 'Wishbone bus Data size in bit',
- 'content' => '8,1024,8',
- 'type' => 'Spin-button'
+ 'type' => 'Combo-box',
+ 'default' => '256'
},
- 'TAGw' => {
- 'redefine_param' => 1,
- 'content' => '',
- 'info' => 'Parameter',
- 'type' => 'Fixed',
- 'deafult' => '3',
- 'global_param' => 'Parameter'
- },
- 'M_Aw' => {
- 'type' => 'Fixed',
- 'info' => 'Parameter',
- 'content' => '',
- 'global_param' => 'Parameter',
- 'deafult' => '32',
- 'redefine_param' => 1
- },
- 'CHANNEL' => {
- 'redefine_param' => 1,
- 'info' => 'Number of DMA channels.
-In case there are multiple active DMA channels, Each time one single active DMA channel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter channel until its FIFO is not full and the number od sent data is smaller than the burst size.',
- 'content' => '1,32,1',
- 'type' => 'Spin-button',
- 'global_param' => 'Parameter',
- 'deafult' => '1'
- },
- 'S_Aw' => {
- 'redefine_param' => 1,
- 'content' => '',
- 'info' => 'Parameter',
- 'type' => 'Fixed',
- 'global_param' => 'Parameter',
- 'deafult' => '8'
- },
- 'SELw' => {
- 'type' => 'Fixed',
- 'content' => '',
- 'info' => 'Parameter',
- 'global_param' => 'Parameter',
- 'deafult' => '4',
- 'redefine_param' => 1
- }
+ 'DEBUG_EN' => {
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed',
+ 'default' => '1',
+ 'global_param' => 'Parameter',
+ 'info' => 'Parameter'
+ },
+ 'TAGw' => {
+ 'default' => '3',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1,
+ 'content' => '',
+ 'info' => 'Parameter',
+ 'global_param' => 'Parameter'
},
- 'plugs' => {
- 'clk' => {
- 'clk' => {},
- 'type' => 'num',
- '0' => {
- 'name' => 'clk'
- },
- 'value' => 1
- },
- 'wb_master' => {
- 'value' => 2,
- '0' => {
- 'name' => 'wb_rd'
- },
- '1' => {
- 'name' => 'wb_wr'
- },
- 'wb_master' => {},
- 'type' => 'num'
- },
- 'interrupt_peripheral' => {
- 'type' => 'num',
- 'interrupt_peripheral' => {},
- '0' => {
- 'name' => 'interrupt_peripheral'
- },
- 'value' => 1
- },
- 'wb_slave' => {
- 'type' => 'num',
- 'value' => 1,
- 'wb_slave' => {},
- '0' => {
- 'addr' => '0x9300_0000 0x93ff_ffff Memory Controller',
- 'name' => 'wb_slave',
- 'width' => 10
- }
- },
- 'reset' => {
- '0' => {
- 'name' => 'reset'
- },
- 'value' => 1,
- 'reset' => {},
- 'type' => 'num'
- }
- },
- 'description' => 'A round robin based multi channel DMA (no byte enable). support burst data transaction.',
- 'ip_name' => 'dma',
- 'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',
- 'category' => 'DMA',
- 'system_h' => '#define ${IP}_STATUS_REG (*((volatile unsigned int *) ($BASE)))
+ 'S_Aw' => {
+ 'info' => 'Parameter',
+ 'global_param' => 'Parameter',
+ 'type' => 'Fixed',
+ 'default' => '8',
+ 'redefine_param' => 1,
+ 'content' => ''
+ },
+ 'MAX_TRANSACTION_WIDTH' => {
+ 'default' => '10',
+ 'type' => 'Spin-button',
+ 'redefine_param' => 1,
+ 'content' => '2,32,1',
+ 'info' => 'The width of maximum transaction size in words.
+The maximum data that can be sent via one DMA channel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
+ 'global_param' => 'Parameter'
+ }
+ },
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'ports' => {
+ 'm_rd_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'sel_o',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_rd_stb_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'stb_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'irq' => {
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_port' => 'int_o',
+ 'intfc_name' => 'plug:interrupt_peripheral[0]'
+ },
+ 'm_rd_ack_i' => {
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'ack_i'
+ },
+ 's_cti_i' => {
+ 'intfc_port' => 'cti_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'input',
+ 'range' => 'TAGw-1 : 0'
+ },
+ 'm_wr_we_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'we_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_rd_cyc_o' => {
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cyc_o'
+ },
+ 'm_wr_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'type' => 'output',
+ 'range' => 'Dw-1 : 0'
+ },
+ 's_cyc_i' => {
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cyc_i'
+ },
+ 'm_wr_ack_i' => {
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'ack_i'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'type' => 'input',
+ 'range' => ''
+ },
+ 'm_rd_cti_o' => {
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cti_o'
+ },
+ 's_dat_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'sel_i',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_we_i' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'm_wr_cyc_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'cyc_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_wr_cti_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'cti_o',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'output'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'type' => 'input',
+ 'range' => ''
+ },
+ 'm_rd_dat_i' => {
+ 'type' => 'input',
+ 'range' => 'Dw-1 : 0',
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 's_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_addr_i' => {
+ 'type' => 'input',
+ 'range' => 'S_Aw-1 : 0',
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'm_rd_addr_o' => {
+ 'range' => 'M_Aw-1 : 0',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'adr_o'
+ },
+ 's_dat_i' => {
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_i'
+ },
+ 'm_wr_stb_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'stb_o',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_wr_addr_o' => {
+ 'intfc_port' => 'adr_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'type' => 'output',
+ 'range' => 'M_Aw-1 : 0'
+ },
+ 'm_rd_we_o' => {
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 's_ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'output',
+ 'range' => ''
+ },
+ 'm_wr_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'sel_o',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'output'
+ }
+ },
+ 'system_h' => '#define ${IP}_STATUS_REG (*((volatile unsigned int *) ($BASE)))
#define ${IP}_BURST_SIZE_ADDR_REG (*((volatile unsigned int *) ($BASE+4)))
@@ -424,5 +403,28 @@
${IP}_RD_START_ADDR_REG(channel) = read_start_addr;
${IP}_DATA_SIZE_ADDR_REG(channel) = data_size;
${IP}_WR_START_ADDR_REG(channel) = write_start_addr;
-}'
- }, 'ip_gen' );
+}',
+ 'description_pdf' => '/mpsoc/src_peripheral/DMA/DMA.pdf',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'rty_o',
+ 'bte_i',
+ 'err_o',
+ 'tag_i'
+ ],
+ 'plug:wb_master[0]' => [
+ 'err_i',
+ 'dat_o',
+ 'rty_i',
+ 'bte_o',
+ 'tag_o'
+ ],
+ 'plug:wb_master[1]' => [
+ 'err_i',
+ 'dat_i',
+ 'rty_i',
+ 'bte_o',
+ 'tag_o'
+ ]
+ }
+ }, 'ip_gen' );
/Display/lcd_2x16.IP
3,17 → 3,15
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$lcd_2x16 = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v' |
], |
'system_h' => '#define ${IP}_WR_CMD (*((volatile unsigned int *) ($BASE))) |
$ipgen = bless( { |
'sw_params_list' => [], |
'system_h' => '#define ${IP}_WR_CMD (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_RD_CMD (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_WR_DATA (*((volatile unsigned int *) ($BASE+8))) |
#define ${IP}_RD_DATA (*((volatile unsigned int *) ($BASE+16))) |
21,185 → 19,188
#define ${IP}_CLK_MHZ $CLK_MHZ |
|
#include "$IP.h"', |
'ip_name' => 'lcd_2x16', |
'sw_params_list' => [], |
'parameters_order' => [ |
'Dw', |
'Aw', |
'CLK_MHZ' |
], |
'ports_order' => [ |
'clk', |
'reset', |
's_dat_i', |
's_addr_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
'lcd_en', |
'lcd_rs', |
'lcd_rw', |
'lcd_data' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v', |
'module_name' => 'lcd_2x16', |
'gen_sw_files' => [ |
'/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16frename_sep_t${IP}.h' |
], |
'unused' => { |
'plug:wb_slave[0]' => [ |
'err_o', |
'rty_o', |
'tag_i', |
'cti_i', |
'sel_i', |
'bte_i' |
] |
}, |
'category' => 'Display', |
'sw_files' => [], |
'description' => 'Alphabet Display LCD 2x16', |
'modules' => { |
'lcd_2x16' => {} |
'parameters_order' => [ |
'Dw', |
'Aw', |
'CLK_MHZ' |
], |
'module_name' => 'lcd_2x16', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'plugs' => { |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
'ip_name' => 'lcd_2x16', |
'ports' => { |
'lcd_rw' => { |
'type' => 'output', |
'intfc_name' => 'IO', |
'range' => '', |
'intfc_port' => 'IO' |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'lcd_en' => { |
'intfc_name' => 'IO', |
'range' => '', |
'intfc_port' => 'IO', |
'type' => 'output' |
}, |
's_we_i' => { |
'type' => 'input', |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
's_dat_o' => { |
'type' => 'output', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o' |
}, |
'clk' => { |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'intfc_port' => 'clk_i' |
}, |
's_ack_o' => { |
'type' => 'output', |
'intfc_port' => 'ack_o', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
's_stb_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i' |
}, |
'lcd_rs' => { |
'range' => '', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'type' => 'output' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
}, |
's_dat_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i' |
}, |
's_cyc_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'cyc_i' |
}, |
's_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'intfc_port' => 'adr_i', |
'type' => 'input' |
}, |
'lcd_data' => { |
'range' => ' 7: 0', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'type' => 'inout' |
} |
}, |
'ports_order' => [ |
'clk', |
'reset', |
's_dat_i', |
's_addr_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
'lcd_en', |
'lcd_rs', |
'lcd_rw', |
'lcd_data' |
], |
'version' => 1, |
'gen_sw_files' => [ |
'/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16frename_sep_t${IP}.h' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'sel_i', |
'tag_i', |
'bte_i', |
'err_o', |
'rty_o', |
'cti_i' |
] |
}, |
'plugs' => { |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num', |
'value' => 1, |
'clk' => {} |
}, |
'wb_slave' => { |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O', |
'name' => 'wb', |
'width' => 5 |
}, |
'type' => 'num' |
'value' => 1, |
'wb_slave' => {} |
}, |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
}, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'parameters' => { |
'Aw' => { |
'info' => undef, |
'deafult' => ' 2', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'Dw' => { |
'info' => undef, |
'deafult' => ' 8', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'CLK_MHZ' => { |
'info' => 'The LCD controller clock speed in MHZ. It will be used for measuring the lcd enable delay. You can define a larger value than the actual clk speed but not smaller.', |
'deafult' => '100', |
'global_param' => 0, |
'content' => '2,1000,2', |
'type' => 'Spin-button', |
'redefine_param' => 1 |
} |
}, |
'ports' => { |
's_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'type' => 'input' |
}, |
's_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
}, |
'lcd_en' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
's_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
's_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'range' => '', |
'type' => 'input' |
}, |
's_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
}, |
'lcd_data' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => ' 7: 0', |
'type' => 'inout' |
}, |
'lcd_rs' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'input' |
}, |
'lcd_rw' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
's_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
's_dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
} |
} |
}, 'ip_gen' ); |
'reset' => { |
'type' => 'num', |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1 |
} |
}, |
'modules' => { |
'lcd_2x16' => {} |
}, |
'category' => 'Display', |
'description' => '2x16 Character Alphabet Liquid Crystal Display (LCD) driver module ', |
'parameters' => { |
'CLK_MHZ' => { |
'content' => '2,1000,2', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'global_param' => 0, |
'default' => '100', |
'info' => 'The LCD controller clock speed in MHZ. It will be used for measuring the lcd enable delay. You can define a larger value than the actual clk speed but not smaller.' |
}, |
'Aw' => { |
'global_param' => 0, |
'default' => ' 2', |
'info' => undef, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'Dw' => { |
'type' => 'Fixed', |
'redefine_param' => 1, |
'content' => '', |
'info' => undef, |
'default' => ' 8', |
'global_param' => 0 |
} |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v' |
], |
'sw_files' => [] |
}, 'ip_gen' ); |
/GPIO/gpi.IP
3,200 → 3,201
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.6.0 |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$gpi = bless( { |
'parameters_order' => [ |
'PORT_WIDTH', |
'Dw', |
'Aw', |
'TAGw', |
'SELw' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v', |
'ports' => { |
'sa_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_addr_i' => { |
'range' => 'Aw-1 : 0', |
'intfc_port' => 'adr_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
$ipgen = bless( { |
'modules' => { |
'gpo' => {}, |
'gpi' => {}, |
'gpio' => {} |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/gpio/gpio.v' |
], |
'module_name' => 'gpi', |
'category' => 'GPIO', |
'sockets' => {}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'bte_i', |
'cti_i' |
] |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'parameters_order' => [ |
'PORT_WIDTH', |
'Dw', |
'Aw', |
'TAGw', |
'SELw' |
], |
'parameters' => { |
'PORT_WIDTH' => { |
'default' => ' 1', |
'redefine_param' => 1, |
'content' => '1,32,1', |
'info' => 'Input port width ', |
'global_param' => 'Parameter', |
'type' => 'Spin-button' |
}, |
'Dw' => { |
'info' => undef, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => 'PORT_WIDTH', |
'redefine_param' => 1, |
'content' => '' |
}, |
'port_i' => { |
'intfc_name' => 'IO', |
'type' => 'input', |
'intfc_port' => 'IO', |
'range' => 'PORT_WIDTH-1 : 0' |
}, |
'sa_dat_i' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'ack_o', |
'range' => '' |
}, |
'sa_stb_i' => { |
'intfc_port' => 'stb_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
'sa_we_i' => { |
'TAGw' => { |
'global_param' => 'Localparam', |
'info' => undef, |
'type' => 'Fixed', |
'redefine_param' => 1, |
'default' => ' 3', |
'content' => '' |
}, |
'Aw' => { |
'redefine_param' => 1, |
'default' => ' 2', |
'content' => '', |
'global_param' => 'Localparam', |
'info' => undef, |
'type' => 'Fixed' |
}, |
'SELw' => { |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'content' => '', |
'default' => ' 4', |
'redefine_param' => 1 |
} |
}, |
'description' => 'General purpose Wishbone bus-based input port', |
'version' => 2, |
'ports' => { |
'sa_dat_i' => { |
'range' => 'Dw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_tag_i' => { |
'range' => 'TAGw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'tag_i' |
}, |
'sa_cyc_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'we_i' |
'range' => '' |
}, |
'sa_err_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'err_o' |
}, |
'sa_sel_i' => { |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_err_o' => { |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o' |
}, |
'sa_sel_i' => { |
'type' => 'input', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i' |
}, |
'sa_rty_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o' |
}, |
'port_i' => { |
'range' => 'PORT_WIDTH-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i' |
'intfc_port' => 'IO', |
'intfc_name' => 'IO' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'range' => '' |
}, |
'sa_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'cyc_i', |
'range' => '' |
}, |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'rty_o', |
'range' => '' |
}, |
'reset' => { |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'sa_dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
'clk' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'intfc_port' => 'reset_i' |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]' |
}, |
'sa_tag_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0' |
} |
}, |
'modules' => { |
'gpio' => {}, |
'gpo' => {}, |
'gpi' => {} |
'sa_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '' |
} |
}, |
'ip_name' => 'gpi', |
'category' => 'GPIO', |
'sockets' => {}, |
'plugs' => { |
'wb_slave' => { |
'wb_slave' => {}, |
'type' => 'num', |
'value' => 1, |
'0' => { |
'width' => 5, |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O', |
'name' => 'wb' |
} |
}, |
'reset' => { |
'plugs' => { |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num', |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
} |
'clk' => {} |
}, |
'clk' => { |
'value' => 1, |
'type' => 'num', |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
} |
} |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/gpio/gpio.v' |
], |
'description' => 'General inout port', |
'system_h' => '#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8))) |
#define ${IP}_READ() ${IP}_READ_REG ', |
'parameters' => { |
'TAGw' => { |
'deafult' => ' 3', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'info' => undef, |
'content' => '' |
}, |
'Dw' => { |
'redefine_param' => 1, |
'deafult' => 'PORT_WIDTH', |
'global_param' => 'Localparam', |
'info' => undef, |
'type' => 'Fixed', |
'content' => '' |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'reset' => {}, |
'value' => 1, |
'type' => 'num' |
}, |
'SELw' => { |
'global_param' => 'Localparam', |
'deafult' => ' 4', |
'redefine_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'info' => undef |
}, |
'PORT_WIDTH' => { |
'info' => 'Input port width ', |
'type' => 'Spin-button', |
'content' => '1,32,1', |
'deafult' => ' 1', |
'redefine_param' => 1, |
'global_param' => 'Parameter' |
}, |
'Aw' => { |
'content' => '', |
'info' => undef, |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'deafult' => ' 2', |
'redefine_param' => 1 |
} |
}, |
'module_name' => 'gpi', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'bte_i' |
] |
} |
}, 'ip_gen' ); |
'wb_slave' => { |
'wb_slave' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'wb', |
'width' => 5, |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
}, |
'value' => 1 |
} |
}, |
'ip_name' => 'gpi', |
'system_h' => '#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8))) |
#define ${IP}_READ() ${IP}_READ_REG ' |
}, 'ip_gen' ); |
/GPIO/gpio.IP
3,164 → 3,144
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.6.0 |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$gpio = bless( { |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v', |
'module_name' => 'gpio', |
'modules' => { |
'gpo' => {}, |
'gpi' => {}, |
'gpio' => {} |
$ipgen = bless( { |
'module_name' => 'gpio', |
'category' => 'GPIO', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cyc_i', |
'bte_i', |
'tag_i', |
'cti_i' |
] |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'sockets' => {}, |
'category' => 'GPIO', |
'ports' => { |
'sa_dat_o' => { |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]' |
'hdl_files' => [ |
'/mpsoc/src_peripheral/gpio/gpio.v' |
], |
'ip_name' => 'gpio', |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v', |
'version' => 1, |
'modules' => { |
'gpo' => {}, |
'gpio' => {}, |
'gpi' => {} |
}, |
'parameters' => { |
'Dw' => { |
'content' => '', |
'info' => undef, |
'redefine_param' => 1, |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'default' => 'PORT_WIDTH' |
}, |
'sa_dat_i' => { |
'PORT_WIDTH' => { |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '1,32,1', |
'info' => undef, |
'default' => '1', |
'global_param' => 'Parameter' |
}, |
'SELw' => { |
'default' => '4', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => undef, |
'content' => '' |
}, |
'Aw' => { |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => undef, |
'content' => '', |
'global_param' => 'Localparam', |
'default' => '2' |
} |
}, |
'description' => 'General purpose Wishbone bus-based input/output port', |
'ports' => { |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'dat_i' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'ack_o' |
}, |
'sa_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o', |
'type' => 'output', |
'range' => '' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'reset_i' |
}, |
'sa_stb_i' => { |
'intfc_port' => 'stb_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
'reset' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]' |
}, |
'port_io' => { |
'type' => 'inout', |
'range' => 'PORT_WIDTH-1 : 0', |
'intfc_port' => 'IO', |
'intfc_name' => 'IO' |
}, |
'port_io' => { |
'intfc_port' => 'IO', |
'type' => 'inout', |
'range' => 'PORT_WIDTH-1 : 0', |
'intfc_name' => 'IO' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'sa_dat_o' => { |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o' |
}, |
'sa_dat_i' => { |
'type' => 'input', |
'range' => 'Aw-1 : 0', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_err_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
} |
}, |
'plugs' => { |
'reset' => { |
'type' => 'num', |
'value' => 1, |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
} |
}, |
'wb_slave' => { |
'value' => 1, |
'type' => 'num', |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
}, |
'wb_slave' => {} |
}, |
'clk' => { |
'type' => 'num', |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
} |
} |
}, |
'description' => 'General inout port', |
'parameters' => { |
'Dw' => { |
'global_param' => 'Localparam', |
'info' => undef, |
'content' => '', |
'deafult' => 'PORT_WIDTH', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'SELw' => { |
'global_param' => 'Localparam', |
'info' => undef, |
'deafult' => '4', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'PORT_WIDTH' => { |
'info' => undef, |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '1,32,1', |
'deafult' => '1' |
}, |
'Aw' => { |
'deafult' => '2', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => undef, |
'global_param' => 'Localparam' |
} |
}, |
'system_h' => '#define ${IP}_DIR_REG (*((volatile unsigned int *) ($BASE))) |
'sa_err_o' => { |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '' |
}, |
'sa_stb_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_sel_i' => { |
'range' => 'SELw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input', |
'range' => '' |
}, |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
} |
}, |
'system_h' => '#define ${IP}_DIR_REG (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8))) |
|
167,23 → 147,44
#define ${IP}_DIR_SET(value) ${IP}_DIR_REG=value |
#define ${IP}_WRITE(value) ${IP}_WRITE _REG=value |
#define ${IP}_READ() ${IP}_READ_REG ', |
'hdl_files' => [ |
'/mpsoc/src_peripheral/gpio/gpio.v' |
], |
'ip_name' => 'gpio', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'tag_i', |
'cyc_i', |
'bte_i', |
'cti_i' |
] |
'sockets' => {}, |
'parameters_order' => [ |
'PORT_WIDTH', |
'Dw', |
'Aw', |
'SELw', |
'Dw' |
], |
'plugs' => { |
'clk' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'clk' => {} |
}, |
'reset' => { |
'type' => 'num', |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
} |
}, |
'wb_slave' => { |
'0' => { |
'width' => 5, |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O', |
'name' => 'wb' |
}, |
'type' => 'num', |
'value' => 1, |
'wb_slave' => {} |
} |
}, |
'parameters_order' => [ |
'PORT_WIDTH', |
'Dw', |
'Aw', |
'SELw', |
'Dw' |
] |
}, 'ip_gen' ); |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
} |
}, 'ip_gen' ); |
/GPIO/gpo.IP
3,203 → 3,203
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.6.0 |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$gpo = bless( { |
'version' => 1, |
'description' => 'General output port', |
'hdl_files' => [ |
'/mpsoc/src_peripheral/gpio/gpio.v' |
], |
'parameters' => { |
'SELw' => { |
$ipgen = bless( { |
'unused' => { |
'plug:wb_slave[0]' => [ |
'bte_i', |
'cti_i' |
] |
}, |
'parameters_order' => [ |
'PORT_WIDTH', |
'Aw', |
'TAGw', |
'SELw', |
'Dw' |
], |
'module_name' => 'gpo', |
'system_h' => '#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_WRITE(value) ${IP}_WRITE_REG=value |
|
', |
'sockets' => {}, |
'category' => 'GPIO', |
'version' => 2, |
'modules' => { |
'gpo' => {}, |
'gpi' => {}, |
'gpio' => {} |
}, |
'plugs' => { |
'clk' => { |
'type' => 'num', |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
} |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_slave' => { |
'type' => 'num', |
'value' => 1, |
'wb_slave' => {}, |
'0' => { |
'name' => 'wb', |
'width' => 5, |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
} |
} |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/gpio/gpio.v' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v', |
'ports' => { |
'sa_sel_i' => { |
'type' => 'input', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_cyc_i' => { |
'type' => 'input', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'port_o' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => 'PORT_WIDTH-1 : 0', |
'type' => 'output' |
}, |
'sa_ack_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '' |
}, |
'sa_err_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_we_i' => { |
'type' => 'input', |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_stb_i' => { |
'range' => '', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_tag_i' => { |
'type' => 'input', |
'range' => 'TAGw-1 : 0', |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output' |
}, |
'sa_dat_i' => { |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'ip_name' => 'gpo', |
'parameters' => { |
'Dw' => { |
'content' => '', |
'type' => 'Fixed', |
'default' => 'PORT_WIDTH', |
'global_param' => 'Localparam', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'PORT_WIDTH' => { |
'type' => 'Spin-button', |
'content' => '1,32,1', |
'global_param' => 'Parameter', |
'default' => ' 1', |
'redefine_param' => 1, |
'info' => 'output port width' |
}, |
'SELw' => { |
'type' => 'Fixed', |
'content' => '', |
'global_param' => 'Localparam', |
'default' => ' 4', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'Aw' => { |
'redefine_param' => 1, |
'deafult' => ' 4', |
'content' => '' |
}, |
'Aw' => { |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'deafult' => ' 2', |
'content' => '', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'Dw' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'content' => '', |
'deafult' => 'PORT_WIDTH', |
'redefine_param' => 1, |
'info' => undef |
}, |
'TAGw' => { |
'info' => undef, |
'redefine_param' => 1, |
'deafult' => ' 3', |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed' |
'type' => 'Fixed', |
'default' => ' 2', |
'global_param' => 'Localparam' |
}, |
'PORT_WIDTH' => { |
'deafult' => ' 1', |
'content' => '1,32,1', |
'info' => 'output port width', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'global_param' => 'Parameter' |
} |
}, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'bte_i', |
'cti_i' |
] |
}, |
'modules' => { |
'gpo' => {}, |
'gpi' => {}, |
'gpio' => {} |
}, |
'ports' => { |
'sa_tag_i' => { |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'TAGw-1 : 0', |
'type' => 'input' |
}, |
'reset' => { |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'intfc_port' => 'reset_i' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'ack_o' |
}, |
'sa_stb_i' => { |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'sa_sel_i' => { |
'type' => 'input', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:clk[0]' |
}, |
'sa_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '' |
}, |
'sa_dat_i' => { |
'intfc_port' => 'dat_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0' |
}, |
'port_o' => { |
'intfc_port' => 'IO', |
'type' => 'output', |
'intfc_name' => 'IO', |
'range' => 'PORT_WIDTH-1 : 0' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'we_i' |
}, |
'sa_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'dat_o' |
}, |
'sa_rty_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'rty_o' |
}, |
'sa_err_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o' |
} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'category' => 'GPIO', |
'ip_name' => 'gpo', |
'system_h' => '#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_WRITE(value) ${IP}_WRITE_REG=value |
|
', |
'parameters_order' => [ |
'PORT_WIDTH', |
'Aw', |
'TAGw', |
'SELw', |
'Dw' |
], |
'plugs' => { |
'reset' => { |
'reset' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1 |
}, |
'wb_slave' => { |
'value' => 1, |
'wb_slave' => {}, |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'value' => 1, |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
} |
}, |
'sockets' => {}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v', |
'module_name' => 'gpo' |
}, 'ip_gen' ); |
'TAGw' => { |
'content' => '', |
'type' => 'Fixed', |
'default' => ' 3', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => undef |
} |
}, |
'description' => 'General purpose Wishbone bus-based output port' |
}, 'ip_gen' ); |
/Interrupt/ext_int.IP
3,210 → 3,212
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ext_int = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ext_int/ext_int.v' |
], |
'system_h' => ' |
#define ${IP}_GER (*((volatile unsigned int *) ($BASE ))) |
#define ${IP}_IER_RISE (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_IER_FALL (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_ISR (*((volatile unsigned int *) ($BASE+12 ))) |
#define ${IP}_RD (*((volatile unsigned int *) ($BASE+16 )))', |
'ip_name' => 'ext_int', |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'plugs' => { |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'interrupt' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
$ipgen = bless( { |
'sockets' => {}, |
'version' => 1, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ext_int/ext_int.v', |
'parameters' => { |
'TAGw' => { |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 0, |
'content' => '', |
'default' => '3' |
}, |
'SELw' => { |
'default' => '4', |
'content' => '', |
'global_param' => 0, |
'info' => undef, |
'type' => 'Fixed' |
}, |
'Dw' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'content' => '', |
'global_param' => 0 |
}, |
'EXT_INT_NUM' => { |
'type' => 'Spin-button', |
'info' => 'number of external interrupt pins.', |
'global_param' => 0, |
'content' => '1,32,1', |
'default' => '3' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'Aw' => { |
'default' => '3', |
'global_param' => 0, |
'content' => '', |
'info' => undef, |
'type' => 'Fixed' |
} |
}, |
'plugs' => { |
'reset' => { |
'value' => 1, |
'reset' => {}, |
'0' => { |
'name' => 'clk' |
'name' => 'reset' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller' |
}, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'modules' => { |
'ext_int' => {} |
}, |
'parameters' => { |
'Aw' => { |
'info' => undef, |
'deafult' => '3', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
'wb_slave' => { |
'wb_slave' => {}, |
'value' => 1, |
'0' => { |
'name' => 'wb', |
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller', |
'width' => 5 |
}, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'value' => 1, |
'interrupt_peripheral' => {}, |
'0' => { |
'name' => 'interrupt' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num', |
'clk' => {} |
} |
}, |
'ports' => { |
'ext_int_i' => { |
'intfc_port' => 'IO', |
'type' => 'input', |
'intfc_name' => 'IO', |
'range' => 'EXT_INT_NUM-1 : 0' |
}, |
'SELw' => { |
'info' => undef, |
'deafult' => '4', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
}, |
'TAGw' => { |
'info' => undef, |
'deafult' => '3', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
}, |
'Dw' => { |
'info' => undef, |
'deafult' => '32', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
'sa_stb_i' => { |
'type' => 'input', |
'intfc_port' => 'stb_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0' |
}, |
'EXT_INT_NUM' => { |
'info' => 'number of external interrupt pins.', |
'deafult' => '3', |
'global_param' => 0, |
'content' => '1,32,1', |
'type' => 'Spin-button' |
} |
}, |
'parameters_order' => [ |
'Dw', |
'Aw', |
'TAGw', |
'SELw', |
'EXT_INT_NUM' |
], |
'ports' => { |
'sa_tag_i' => { |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'TAGw-1 : 0', |
'type' => 'input' |
}, |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
'sa_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
'sa_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
}, |
'ext_int_o' => { |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'intfc_port' => 'int_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'ext_int_o' => { |
'range' => '', |
'type' => 'input' |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'type' => 'output', |
'intfc_port' => 'int_o' |
}, |
'sa_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'sa_err_o' => { |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'ext_int_i' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => 'EXT_INT_NUM-1 : 0', |
'type' => 'input' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'sa_ack_o' => { |
'type' => 'output', |
'intfc_port' => 'ack_o', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'we_i', |
'type' => 'input' |
}, |
'sa_err_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'err_o', |
'type' => 'output' |
}, |
'sa_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'dat_o' |
}, |
'sa_dat_i' => { |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_cyc_i' => { |
'type' => 'input', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => '' |
}, |
'sa_sel_i' => { |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'sel_i' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'intfc_port' => 'reset_i', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'type' => 'input' |
}, |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
} |
}, |
'sockets' => {}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ext_int/ext_int.v', |
'module_name' => 'ext_int', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'bte_i' |
] |
}, |
'category' => 'Interrupt' |
}, 'ip_gen' ); |
'sa_tag_i' => { |
'type' => 'input', |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
} |
}, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'bte_i' |
] |
}, |
'parameters_order' => [ |
'Dw', |
'Aw', |
'TAGw', |
'SELw', |
'EXT_INT_NUM' |
], |
'description' => 'external interrupt', |
'module_name' => 'ext_int', |
'system_h' => ' |
#define ${IP}_GER (*((volatile unsigned int *) ($BASE ))) |
#define ${IP}_IER_RISE (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_IER_FALL (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_ISR (*((volatile unsigned int *) ($BASE+12 ))) |
#define ${IP}_RD (*((volatile unsigned int *) ($BASE+16 )))', |
'ip_name' => 'ext_int', |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ext_int/ext_int.v' |
], |
'category' => 'Interrupt', |
'modules' => { |
'ext_int' => {} |
} |
}, 'ip_gen' ); |
/Interrupt/int_ctrl.IP
3,203 → 3,202
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## This file is part of ProNoC 1.7.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$int_ctrl = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/int_ctrl/int_ctrl.v' |
], |
'system_h' => ' |
#define ${IP}_MER (*((volatile unsigned int *) ($BASE ))) |
#define ${IP}_IER (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_IAR (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_IPR (*((volatile unsigned int *) ($BASE+12 )))', |
'ip_name' => 'int_ctrl', |
'description' => 'interrupt controller', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'modules' => { |
'int_ctrl' => {} |
}, |
'plugs' => { |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
$ipgen = bless( { |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/int_ctrl/int_ctrl.v', |
'sockets' => { |
'interrupt_peripheral' => { |
'connection_num' => 'single connection', |
'value' => 'INT_NUM', |
'0' => { |
'name' => 'int_periph' |
}, |
'interrupt_peripheral' => {}, |
'type' => 'param' |
} |
}, |
'parameters_order' => [ |
'INT_NUM', |
'Dw', |
'Aw', |
'SELw' |
], |
'ip_name' => 'int_ctrl', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'tag_i', |
'cyc_i', |
'bte_i', |
'cti_i' |
] |
}, |
'ports' => { |
'sa_dat_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0' |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'parameters' => { |
'Aw' => { |
'info' => undef, |
'deafult' => ' 3', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
}, |
'SELw' => { |
'info' => undef, |
'deafult' => ' 4 ', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
}, |
'Dw' => { |
'info' => undef, |
'deafult' => ' 32', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
}, |
'INT_NUM' => { |
'info' => 'number of inerrupt.', |
'deafult' => ' 3', |
'global_param' => 0, |
'content' => '1,32,1', |
'type' => 'Spin-button' |
} |
}, |
'ports' => { |
'sa_dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
'sa_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
}, |
'sa_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_err_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'sa_err_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '' |
}, |
'clk' => { |
'range' => '', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input' |
}, |
'int_o' => { |
'intfc_name' => 'plug:interrupt_cpu[0]', |
'intfc_port' => 'int_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_stb_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
'intfc_port' => 'stb_i' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'int_o' => { |
'intfc_name' => 'socket:interrupt_cpu[0]', |
'intfc_port' => 'int_o', |
'sa_rty_o' => { |
'type' => 'output', |
'range' => '', |
'type' => 'output' |
'intfc_port' => 'rty_o', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
'int_i' => { |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'intfc_port' => 'int_i', |
'range' => 'INT_NUM-1 : 0', |
'sa_sel_i' => { |
'type' => 'input', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_ack_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'range' => '', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
}, |
'sa_dat_i' => { |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
'sa_addr_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'intfc_port' => 'adr_i' |
}, |
'int_i' => { |
'intfc_port' => 'int_i', |
'range' => 'INT_NUM-1 : 0', |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'type' => 'input' |
} |
}, |
'version' => 1, |
'plugs' => { |
'wb_slave' => { |
'0' => { |
'width' => 5, |
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller', |
'name' => 'wb' |
}, |
'type' => 'num', |
'value' => 1, |
'wb_slave' => {} |
}, |
'reset' => { |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'reset' => {} |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
} |
}, |
'interrupt_cpu' => { |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'interrupt_cpu' |
} |
} |
}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'modules' => { |
'int_ctrl' => {} |
}, |
'category' => 'Interrupt', |
'module_name' => 'int_ctrl', |
'description' => 'interrupt controller', |
'parameters' => { |
'INT_NUM' => { |
'global_param' => 0, |
'info' => 'number of inerrupt.', |
'content' => '1,32,1', |
'type' => 'Spin-button', |
'default' => ' 3' |
}, |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
} |
}, |
'parameters_order' => [ |
'INT_NUM', |
'Dw', |
'Aw', |
'SELw' |
], |
'sockets' => { |
'interrupt_cpu' => { |
'interrupt_cpu' => {}, |
'connection_num' => 'single connection', |
'value' => 1, |
'0' => { |
'name' => 'int_cpu' |
}, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'connection_num' => 'single connection', |
'interrupt_peripheral' => {}, |
'0' => { |
'name' => 'int_periph' |
}, |
'value' => 'INT_NUM', |
'type' => 'param' |
} |
'SELw' => { |
'type' => 'Fixed', |
'default' => ' 4 ', |
'global_param' => 0, |
'content' => '', |
'info' => undef |
}, |
'Aw' => { |
'type' => 'Fixed', |
'default' => ' 3', |
'global_param' => 0, |
'info' => undef, |
'content' => '' |
}, |
'Dw' => { |
'content' => '', |
'info' => undef, |
'global_param' => 0, |
'type' => 'Fixed', |
'default' => ' 32' |
} |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/int_ctrl/int_ctrl.v', |
'module_name' => 'int_ctrl', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cyc_i', |
'tag_i', |
'cti_i', |
'bte_i' |
] |
}, |
'category' => 'Interrupt' |
}, 'ip_gen' ); |
'system_h' => ' |
#define ${IP}_MER (*((volatile unsigned int *) ($BASE ))) |
#define ${IP}_IER (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_IAR (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_IPR (*((volatile unsigned int *) ($BASE+12 )))', |
'hdl_files' => [ |
'/mpsoc/src_peripheral/int_ctrl/int_ctrl.v' |
] |
}, 'ip_gen' ); |
/NoC/ni_master.IP
3,554 → 3,551
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.6.0 |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ni_master = bless( { |
'plugs' => { |
'interrupt_peripheral' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'interrupt' |
}, |
'interrupt_peripheral' => {} |
}, |
'wb_slave' => { |
'wb_slave' => {}, |
'type' => 'num', |
'value' => 1, |
'0' => { |
'addr' => '0xb800_0000 0xbfff_ffff custom devices', |
'name' => 'wb_slave', |
'width' => 10 |
} |
}, |
'reset' => { |
'reset' => {}, |
$ipgen = bless( { |
'description' => '', |
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_master.v', |
'plugs' => { |
'wb_master' => { |
'value' => 2, |
'1' => { |
'name' => 'wb_receive' |
}, |
'wb_master' => {}, |
'0' => { |
'name' => 'reset' |
'name' => 'wb_send' |
}, |
'type' => 'num', |
'value' => 1 |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_master' => { |
'1' => { |
'name' => 'wb_receive' |
}, |
'type' => 'num', |
'wb_master' => {}, |
'value' => 2, |
'0' => { |
'name' => 'wb_send' |
} |
} |
}, |
'sockets' => { |
'ni' => { |
'connection_num' => 'single connection', |
'interrupt_peripheral' => { |
'value' => 1, |
'interrupt_peripheral' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'interrupt' |
} |
}, |
'wb_slave' => { |
'wb_slave' => {}, |
'value' => 1, |
'type' => 'num', |
'ni' => {}, |
'0' => { |
'name' => 'ni' |
} |
} |
}, |
'unused' => { |
'plug:wb_master[1]' => [ |
'bte_o', |
'dat_i', |
'err_i', |
'tag_o', |
'rty_i' |
], |
'plug:wb_slave[0]' => [ |
'tag_i', |
'err_o', |
'rty_o', |
'bte_i' |
], |
'plug:wb_master[0]' => [ |
'bte_o', |
'err_i', |
'tag_o', |
'dat_o', |
'rty_i' |
] |
}, |
'ip_name' => 'ni_master', |
'description' => '', |
'hdl_files' => [ |
'/mpsoc/src_noc/arbiter.v', |
'/mpsoc/src_noc/flit_buffer.v', |
'/mpsoc/src_noc/input_ports.v', |
'/mpsoc/src_noc/main_comp.v', |
'/mpsoc/src_noc/route_mesh.v', |
'/mpsoc/src_noc/route_torus.v', |
'/mpsoc/src_noc/routing.v', |
'/mpsoc/src_peripheral/ni/ni_vc_dma.v', |
'/mpsoc/src_peripheral/ni/ni_vc_wb_slave_regs.v', |
'/mpsoc/src_peripheral/ni/ni_master.v', |
'/mpsoc/src_peripheral/ni/ni_crc32.v' |
], |
'parameters' => { |
'B' => { |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'content' => '', |
'deafult' => ' 4', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'CRC_EN' => { |
'redefine_param' => 1, |
'deafult' => '"NO"', |
'content' => '"YES","NO"', |
'info' => 'The parameter can be selected as "YES" or "NO". |
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ', |
'global_param' => 'Localparam', |
'type' => 'Combo-box' |
}, |
'DEBUG_EN' => { |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'info' => 'Parameter', |
'deafult' => ' 1', |
'content' => '', |
'redefine_param' => 1 |
'name' => 'wb_slave', |
'width' => 10, |
'addr' => '0xb800_0000 0xbfff_ffff custom devices' |
}, |
'Yw' => { |
'info' => undef, |
'redefine_param' => 0, |
'content' => '', |
'deafult' => 'log2(NY)', |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'NY' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'deafult' => ' 4', |
'content' => '', |
'type' => 'Fixed', |
'global_param' => 'Parameter' |
}, |
'C' => { |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'info' => 'Parameter', |
'content' => '', |
'deafult' => ' 4', |
'redefine_param' => 1 |
}, |
'SELw' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'type' => 'num' |
}, |
'clk' => { |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num', |
'clk' => {} |
}, |
'reset' => { |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
}, |
'reset' => {}, |
'value' => 1 |
} |
}, |
'ports_order' => [ |
'reset', |
'clk', |
'current_x', |
'current_y', |
'flit_out', |
'flit_out_wr', |
'credit_in', |
'flit_in', |
'flit_in_wr', |
'credit_out', |
's_dat_i', |
's_sel_i', |
's_addr_i', |
's_cti_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
'm_send_sel_o', |
'm_send_addr_o', |
'm_send_cti_o', |
'm_send_stb_o', |
'm_send_cyc_o', |
'm_send_we_o', |
'm_send_dat_i', |
'm_send_ack_i', |
'm_receive_sel_o', |
'm_receive_dat_o', |
'm_receive_addr_o', |
'm_receive_cti_o', |
'm_receive_stb_o', |
'm_receive_cyc_o', |
'm_receive_we_o', |
'm_receive_ack_i', |
'irq' |
], |
'hdl_files' => [ |
'/mpsoc/src_noc/arbiter.v', |
'/mpsoc/src_noc/flit_buffer.v', |
'/mpsoc/src_noc/input_ports.v', |
'/mpsoc/src_noc/main_comp.v', |
'/mpsoc/src_noc/route_mesh.v', |
'/mpsoc/src_noc/route_torus.v', |
'/mpsoc/src_noc/routing.v', |
'/mpsoc/src_peripheral/ni/ni_vc_dma.v', |
'/mpsoc/src_peripheral/ni/ni_vc_wb_slave_regs.v', |
'/mpsoc/src_peripheral/ni/ni_master.v', |
'/mpsoc/src_peripheral/ni/ni_crc32.v' |
], |
'parameters' => { |
'TOPOLOGY' => { |
'default' => '"MESH"', |
'redefine_param' => 1, |
'content' => '', |
'deafult' => '4', |
'info' => 'Parameter' |
}, |
'Fpay' => { |
'redefine_param' => 1, |
'deafult' => ' 32', |
'content' => '', |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'type' => 'Fixed' |
'type' => 'Fixed', |
'content' => '' |
}, |
'MAX_TRANSACTION_WIDTH' => { |
'info' => 'maximum packet size width in words. |
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.', |
'content' => '4,32,1', |
'deafult' => '13', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'global_param' => 'Localparam' |
}, |
'SRC_ADR_HDR_WIDTH' => { |
'redefine_param' => 1, |
'content' => '', |
'deafult' => '8', |
'info' => 'Parameter', |
'global_param' => 'Localparam', |
'type' => 'Fixed' |
}, |
'ROUTING_HDR_WIDTH' => { |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'content' => '', |
'deafult' => '8', |
'redefine_param' => 1 |
}, |
'Fw' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'redefine_param' => 0, |
'deafult' => '2+V+Fpay', |
'content' => '', |
'info' => undef |
}, |
'DST_ADR_HDR_WIDTH' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'deafult' => '8', |
'content' => '', |
'info' => 'Parameter' |
}, |
'Xw' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'deafult' => 'log2(NX)', |
'content' => '', |
'redefine_param' => 0, |
'info' => undef |
}, |
'M_Aw' => { |
'redefine_param' => 1, |
'deafult' => '32', |
'content' => 'Dw', |
'info' => 'Parameter', |
'global_param' => 'Localparam', |
'type' => 'Fixed' |
}, |
'P' => { |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'deafult' => '5', |
'content' => '', |
'info' => 'Parameter' |
}, |
'ROUTE_TYPE' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'deafult' => ' ', |
'content' => '', |
'type' => 'Fixed', |
'global_param' => 'Parameter' |
}, |
'MAX_BURST_SIZE' => { |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'info' => 'Maximum burst size in words. |
'MAX_BURST_SIZE' => { |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'type' => 'Combo-box', |
'info' => 'Maximum burst size in words. |
The NI release wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ', |
'redefine_param' => 1, |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'deafult' => '16' |
}, |
'Dw' => { |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'info' => 'wishbone_bus data width in bits.', |
'redefine_param' => 1, |
'content' => '32,256,8', |
'deafult' => '32' |
}, |
'ROUTE_NAME' => { |
'deafult' => '"XY" ', |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'type' => 'Fixed' |
'default' => '16' |
}, |
'NX' => { |
'content' => '', |
'deafult' => ' 4', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'type' => 'Fixed' |
}, |
'CLASS_HDR_WIDTH' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'deafult' => '8', |
'content' => '', |
'info' => 'Parameter' |
}, |
'TOPOLOGY' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'content' => '', |
'deafult' => '"MESH"', |
'type' => 'Fixed', |
'global_param' => 'Parameter' |
}, |
'S_Aw' => { |
'global_param' => 'Localparam', |
'ROUTING_HDR_WIDTH' => { |
'content' => '', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '8' |
}, |
'CLASS_HDR_WIDTH' => { |
'redefine_param' => 1, |
'default' => '8', |
'content' => '', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'global_param' => 'Localparam' |
}, |
'S_Aw' => { |
'content' => '', |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'default' => '8' |
}, |
'ROUTE_TYPE' => { |
'redefine_param' => 1, |
'default' => ' ', |
'content' => '', |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'type' => 'Fixed' |
}, |
'DST_ADR_HDR_WIDTH' => { |
'content' => '', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '8' |
}, |
'NX' => { |
'default' => ' 4', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'content' => '' |
}, |
'SRC_ADR_HDR_WIDTH' => { |
'default' => '8', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'info' => 'Parameter', |
'global_param' => 'Localparam', |
'content' => '' |
}, |
'ROUTE_NAME' => { |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'content' => '', |
'default' => '"XY" ', |
'redefine_param' => 1 |
}, |
'Xw' => { |
'redefine_param' => 0, |
'default' => 'log2(NX)', |
'content' => '', |
'info' => undef, |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'TAGw' => { |
'type' => 'Fixed', |
'info' => 'Parameter', |
'global_param' => 'Localparam', |
'content' => '', |
'default' => '3', |
'redefine_param' => 1 |
}, |
'DEBUG_EN' => { |
'content' => '', |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'content' => '', |
'deafult' => '8', |
'info' => 'Parameter' |
'default' => ' 1' |
}, |
'V' => { |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'content' => '', |
'deafult' => '4', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'TAGw' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'deafult' => '3', |
'content' => '', |
'redefine_param' => 1, |
'info' => 'Parameter' |
} |
}, |
'version' => 37, |
'category' => 'NoC', |
'description_pdf' => '/mpsoc/src_peripheral/ni/NI_master.pdf', |
'ports' => { |
's_addr_i' => { |
'range' => 'S_Aw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i' |
}, |
'm_send_cti_o' => { |
'intfc_port' => 'cti_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => 'TAGw-1 : 0' |
}, |
'm_send_sel_o' => { |
'type' => 'output', |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => 'SELw-1 : 0' |
}, |
'm_receive_ack_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'ack_i' |
}, |
'm_send_cyc_o' => { |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'cyc_o', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'm_receive_sel_o' => { |
'range' => 'SELw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
's_dat_i' => { |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0' |
'B' => { |
'redefine_param' => 1, |
'default' => ' 4', |
'content' => '', |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'type' => 'Fixed' |
}, |
'Dw' => { |
'redefine_param' => 1, |
'default' => '32', |
'content' => '32,256,8', |
'info' => 'wishbone_bus data width in bits.', |
'global_param' => 'Localparam', |
'type' => 'Spin-button' |
}, |
'Fpay' => { |
'default' => ' 32', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'content' => '' |
}, |
'NY' => { |
'redefine_param' => 1, |
'default' => ' 4', |
'content' => '', |
'global_param' => 'Parameter', |
'info' => 'Parameter', |
'type' => 'Fixed' |
}, |
'P' => { |
'global_param' => 'Parameter', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'content' => '', |
'default' => '5', |
'redefine_param' => 1 |
}, |
'SELw' => { |
'redefine_param' => 1, |
'default' => '4', |
'content' => '', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'V' => { |
'redefine_param' => 1, |
'default' => '4', |
'content' => '', |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'type' => 'Fixed' |
}, |
'CRC_EN' => { |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'info' => 'The parameter can be selected as "YES" or "NO". |
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ', |
'content' => '"YES","NO"', |
'default' => '"NO"', |
'redefine_param' => 1 |
}, |
'flit_out' => { |
'range' => 'Fw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_out' |
}, |
'm_receive_cyc_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'cyc_o', |
'type' => 'output', |
'range' => '' |
}, |
'current_x' => { |
'range' => 'Xw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'current_x', |
'intfc_name' => 'socket:ni[0]' |
}, |
'm_receive_we_o' => { |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => '' |
}, |
'flit_out_wr' => { |
'Yw' => { |
'default' => 'log2(NY)', |
'redefine_param' => 0, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'info' => undef, |
'content' => '' |
}, |
'M_Aw' => { |
'redefine_param' => 1, |
'default' => '32', |
'content' => 'Dw', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'Fw' => { |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'content' => '', |
'default' => '2+V+Fpay', |
'redefine_param' => 0 |
}, |
'MAX_TRANSACTION_WIDTH' => { |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'info' => 'maximum packet size width in words. |
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.', |
'content' => '4,32,1', |
'default' => '13', |
'redefine_param' => 1 |
}, |
'C' => { |
'default' => ' 4', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'content' => '' |
} |
}, |
'ports' => { |
's_dat_o' => { |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output' |
}, |
's_stb_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'stb_i' |
}, |
'm_receive_sel_o' => { |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'intfc_port' => 'sel_o' |
}, |
'm_receive_ack_i' => { |
'intfc_port' => 'ack_i', |
'range' => '', |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_out_wr', |
'type' => 'output' |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input' |
}, |
's_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => '' |
's_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '' |
}, |
'm_send_addr_o' => { |
'intfc_port' => 'adr_o', |
'range' => 'M_Aw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'm_send_we_o' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'we_o' |
}, |
'm_receive_addr_o' => { |
'range' => 'M_Aw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'adr_o' |
}, |
's_sel_i' => { |
'range' => 'SELw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i' |
}, |
'm_send_ack_i' => { |
'type' => 'input', |
'intfc_port' => 'ack_i', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '' |
}, |
'reset' => { |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'range' => '' |
'current_x' => { |
'intfc_port' => 'current_x', |
'range' => 'Xw-1 : 0', |
'intfc_name' => 'socket:ni[0]', |
'type' => 'input' |
}, |
'm_send_stb_o' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'stb_o', |
'type' => 'output' |
'clk' => { |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'intfc_port' => 'clk_i' |
}, |
'm_receive_addr_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => 'M_Aw-1 : 0', |
'intfc_port' => 'adr_o' |
}, |
'm_send_dat_i' => { |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input', |
'range' => 'Dw-1 : 0' |
}, |
'credit_in' => { |
'type' => 'input', |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'credit_in', |
'range' => 'V-1 : 0' |
}, |
'irq' => { |
's_dat_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i' |
}, |
'm_receive_dat_o' => { |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
's_sel_i' => { |
'intfc_port' => 'sel_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'SELw-1 : 0' |
}, |
's_ack_o' => { |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'int_o', |
'intfc_name' => 'plug:interrupt_peripheral[0]' |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
's_stb_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'm_send_we_o' => { |
'm_receive_stb_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'we_o', |
'type' => 'output' |
'intfc_port' => 'stb_o' |
}, |
'flit_in' => { |
'range' => 'Fw-1 : 0', |
'type' => 'input', |
'flit_out_wr' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_in' |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'flit_out_wr' |
}, |
'm_send_addr_o' => { |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => 'M_Aw-1 : 0' |
}, |
'credit_out' => { |
'range' => 'V-1 : 0', |
'current_y' => { |
'intfc_port' => 'current_y', |
'intfc_name' => 'socket:ni[0]', |
'type' => 'input', |
'range' => 'Yw-1 : 0' |
}, |
'm_send_cti_o' => { |
'range' => 'TAGw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cti_o' |
}, |
'm_receive_we_o' => { |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'credit_out', |
'intfc_name' => 'socket:ni[0]' |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'we_o' |
}, |
'm_receive_stb_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'stb_o', |
'type' => 'output', |
'range' => '' |
}, |
'clk' => { |
'range' => '', |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'flit_in' => { |
'range' => 'Fw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_in' |
}, |
'flit_out' => { |
'range' => 'Fw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_out' |
}, |
's_addr_i' => { |
'intfc_port' => 'adr_i', |
'range' => 'S_Aw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
'm_send_stb_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'intfc_port' => 'stb_o' |
}, |
's_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => '' |
}, |
'm_receive_cti_o' => { |
'intfc_port' => 'cti_o', |
'range' => 'TAGw-1 : 0', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
}, |
's_cti_i' => { |
'intfc_port' => 'cti_i', |
'range' => 'TAGw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
's_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'm_send_cyc_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'intfc_port' => 'cyc_o' |
}, |
'm_send_sel_o' => { |
'intfc_port' => 'sel_o', |
'range' => 'SELw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'reset' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i' |
}, |
'credit_in' => { |
'type' => 'input', |
'intfc_name' => 'socket:ni[0]', |
'range' => 'V-1 : 0', |
'intfc_port' => 'credit_in' |
}, |
'm_send_dat_i' => { |
'intfc_port' => 'dat_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => 'Dw-1 : 0' |
}, |
'credit_out' => { |
'range' => 'V-1 : 0', |
'intfc_name' => 'socket:ni[0]', |
'type' => 'output', |
'intfc_port' => 'credit_out' |
}, |
'm_receive_cyc_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'cyc_o' |
}, |
'm_send_ack_i' => { |
'intfc_port' => 'ack_i', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input', |
'range' => '' |
}, |
'irq' => { |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'intfc_port' => 'int_o' |
}, |
'flit_in_wr' => { |
'range' => '', |
'type' => 'input', |
'range' => '' |
}, |
's_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '' |
}, |
'm_receive_cti_o' => { |
'range' => 'TAGw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'cti_o', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
's_cti_i' => { |
'range' => 'TAGw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cti_i' |
}, |
'current_y' => { |
'range' => 'Yw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'current_y', |
'intfc_name' => 'socket:ni[0]' |
}, |
's_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output' |
}, |
'flit_in_wr' => { |
'type' => 'input', |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_in_wr', |
'range' => '' |
}, |
'm_receive_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
} |
}, |
'modules' => { |
'ni_vc_dma' => {}, |
'header_flit_generator' => {}, |
'ni_master' => {}, |
'ovc_status' => {}, |
'vc_wb_slave_registers' => {} |
}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'system_h' => ' /* NI wb registers addresses |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_in_wr' |
} |
}, |
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf', |
'category' => 'NoC', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'system_h' => ' /* NI wb registers addresses |
0 : STATUS1_WB_ADDR // status1: {send_enable_binarry,receive_enable_binarry,send_vc_is_busy,receive_vc_is_busy,receive_vc_got_packet} |
1 : STATUS2_WB_ADDR // status2: |
2 : BURST_SIZE_WB_ADDR // The busrt size in words |
624,70 → 621,73
|
|
}', |
'ports_order' => [ |
'reset', |
'clk', |
'current_x', |
'current_y', |
'flit_out', |
'flit_out_wr', |
'credit_in', |
'flit_in', |
'flit_in_wr', |
'credit_out', |
's_dat_i', |
's_sel_i', |
's_addr_i', |
's_cti_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
'm_send_sel_o', |
'm_send_addr_o', |
'm_send_cti_o', |
'm_send_stb_o', |
'm_send_cyc_o', |
'm_send_we_o', |
'm_send_dat_i', |
'm_send_ack_i', |
'm_receive_sel_o', |
'm_receive_dat_o', |
'm_receive_addr_o', |
'm_receive_cti_o', |
'm_receive_stb_o', |
'm_receive_cyc_o', |
'm_receive_we_o', |
'm_receive_ack_i', |
'irq' |
], |
'module_name' => 'ni_master', |
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_master.v', |
'parameters_order' => [ |
'CLASS_HDR_WIDTH', |
'ROUTING_HDR_WIDTH', |
'DST_ADR_HDR_WIDTH', |
'SRC_ADR_HDR_WIDTH', |
'TOPOLOGY', |
'ROUTE_NAME', |
'NX', |
'NY', |
'C', |
'V', |
'B', |
'Fpay', |
'MAX_TRANSACTION_WIDTH', |
'MAX_BURST_SIZE', |
'DEBUG_EN', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'Xw', |
'Yw', |
'Fw', |
'CRC_EN' |
] |
}, 'ip_gen' ); |
'modules' => { |
'header_flit_generator' => {}, |
'vc_wb_slave_registers' => {}, |
'ni_vc_dma' => {}, |
'ovc_status' => {}, |
'ni_master' => {} |
}, |
'version' => 38, |
'parameters_order' => [ |
'CLASS_HDR_WIDTH', |
'ROUTING_HDR_WIDTH', |
'DST_ADR_HDR_WIDTH', |
'SRC_ADR_HDR_WIDTH', |
'TOPOLOGY', |
'ROUTE_NAME', |
'NX', |
'NY', |
'C', |
'V', |
'B', |
'Fpay', |
'MAX_TRANSACTION_WIDTH', |
'MAX_BURST_SIZE', |
'DEBUG_EN', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'Xw', |
'Yw', |
'Fw', |
'CRC_EN' |
], |
'unused' => { |
'plug:wb_master[0]' => [ |
'dat_o', |
'err_i', |
'bte_o', |
'rty_i', |
'tag_o' |
], |
'plug:wb_slave[0]' => [ |
'rty_o', |
'bte_i', |
'err_o', |
'tag_i' |
], |
'plug:wb_master[1]' => [ |
'err_i', |
'bte_o', |
'rty_i', |
'dat_i', |
'tag_o' |
] |
}, |
'sockets' => { |
'ni' => { |
'value' => 1, |
'ni' => {}, |
'type' => 'num', |
'connection_num' => 'single connection', |
'0' => { |
'name' => 'ni' |
} |
} |
}, |
'module_name' => 'ni_master', |
'ip_name' => 'ni_master' |
}, 'ip_gen' ); |
/NoC/ni_slave.IP
0,0 → 1,756
####################################################################### |
## File: ni_slave.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ipgen = bless( { |
'category' => 'NoC', |
'plugs' => { |
'wb_slave' => { |
'0' => { |
'width' => 10, |
'addr' => '0xb800_0000 0xbfff_ffff custom devices', |
'name' => 'wb_ctrl' |
}, |
'type' => 'num', |
'1' => { |
'width' => 'IN_MEM_BYTEw', |
'addr' => '0xb800_0000 0xbfff_ffff custom devices', |
'name' => 'wb_in' |
}, |
'wb_slave' => {}, |
'value' => 3, |
'2' => { |
'name' => 'wb_out', |
'addr' => '0xb800_0000 0xbfff_ffff custom devices', |
'width' => 'OUT_MEM_BYTEw' |
} |
}, |
'reset' => { |
'reset' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1 |
}, |
'interrupt_peripheral' => { |
'0' => { |
'name' => 'interrupt' |
}, |
'type' => 'num', |
'interrupt_peripheral' => {}, |
'value' => 1 |
}, |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num', |
'clk' => {}, |
'value' => 1 |
} |
}, |
'parameters_order' => [ |
'INPUT_MEM_Aw', |
'OUTPUT_MEM_Aw', |
'MAX_TRANSACTION_WIDTH', |
'MAX_BURST_SIZE', |
'DEBUG_EN', |
'CLASS_HDR_WIDTH', |
'ROUTING_HDR_WIDTH', |
'DST_ADR_HDR_WIDTH', |
'SRC_ADR_HDR_WIDTH', |
'TOPOLOGY', |
'ROUTE_NAME', |
'NX', |
'NY', |
'C', |
'V', |
'B', |
'Fpay', |
'CRC_EN', |
'SWA_ARBITER_TYPE', |
'WEIGHTw', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'IN_MEM_BYTEw', |
'OUT_MEM_BYTEw' |
], |
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf', |
'ports' => { |
'ctrl_cti_i' => { |
'range' => 'TAGw-1 : 0', |
'intfc_port' => 'cti_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'ctrl_dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0' |
}, |
'ctrl_addr_i' => { |
'intfc_port' => 'adr_i', |
'range' => 'S_Aw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'current_x' => { |
'type' => 'input', |
'intfc_port' => 'current_x', |
'range' => 'Xw-1 : 0', |
'intfc_name' => 'socket:ni[0]' |
}, |
'out_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[2]' |
}, |
'in_sel_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
'in_cti_i' => { |
'intfc_port' => 'cti_i', |
'range' => 'TAGw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'flit_in_wr' => { |
'intfc_name' => 'socket:ni[0]', |
'range' => '', |
'intfc_port' => 'flit_in_wr', |
'type' => 'input' |
}, |
'in_dat_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i' |
}, |
'out_we_i' => { |
'type' => 'input', |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[2]' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'intfc_port' => 'clk_i', |
'type' => 'input' |
}, |
'in_dat_o' => { |
'type' => 'output', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'out_sel_i' => { |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[2]' |
}, |
'out_dat_i' => { |
'intfc_name' => 'plug:wb_slave[2]', |
'type' => 'input', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i' |
}, |
'flit_out_wr' => { |
'intfc_name' => 'socket:ni[0]', |
'range' => '', |
'intfc_port' => 'flit_out_wr', |
'type' => 'output' |
}, |
'ctrl_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'ack_o', |
'type' => 'output' |
}, |
'ctrl_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0' |
}, |
'ctrl_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
'out_cti_i' => { |
'intfc_name' => 'plug:wb_slave[2]', |
'range' => 'TAGw-1 : 0', |
'intfc_port' => 'cti_i', |
'type' => 'input' |
}, |
'credit_out' => { |
'intfc_name' => 'socket:ni[0]', |
'range' => 'V-1 : 0', |
'intfc_port' => 'credit_out', |
'type' => 'output' |
}, |
'out_stb_i' => { |
'intfc_name' => 'plug:wb_slave[2]', |
'type' => 'input', |
'intfc_port' => 'stb_i', |
'range' => '' |
}, |
'in_addr_i' => { |
'intfc_port' => 'adr_i', |
'range' => 'S_Aw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'in_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input', |
'intfc_port' => 'cyc_i', |
'range' => '' |
}, |
'flit_out' => { |
'range' => 'Fw-1 : 0', |
'intfc_port' => 'flit_out', |
'type' => 'output', |
'intfc_name' => 'socket:ni[0]' |
}, |
'ctrl_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'type' => 'input' |
}, |
'in_ack_o' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'output', |
'intfc_port' => 'ack_o', |
'range' => '' |
}, |
'out_dat_o' => { |
'intfc_name' => 'plug:wb_slave[2]', |
'type' => 'output', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o' |
}, |
'in_stb_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => '', |
'intfc_port' => 'stb_i', |
'type' => 'input' |
}, |
'out_addr_i' => { |
'type' => 'input', |
'range' => 'S_Aw-1 : 0', |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[2]' |
}, |
'in_we_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => '', |
'intfc_port' => 'we_i', |
'type' => 'input' |
}, |
'flit_in' => { |
'intfc_name' => 'socket:ni[0]', |
'type' => 'input', |
'range' => 'Fw-1 : 0', |
'intfc_port' => 'flit_in' |
}, |
'credit_in' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'credit_in', |
'range' => 'V-1 : 0', |
'type' => 'input' |
}, |
'current_y' => { |
'intfc_name' => 'socket:ni[0]', |
'range' => 'Yw-1 : 0', |
'intfc_port' => 'current_y', |
'type' => 'input' |
}, |
'ctrl_we_i' => { |
'type' => 'input', |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'reset' => { |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'range' => '', |
'intfc_name' => 'plug:reset[0]' |
}, |
'out_ack_o' => { |
'intfc_name' => 'plug:wb_slave[2]', |
'type' => 'output', |
'intfc_port' => 'ack_o', |
'range' => '' |
}, |
'ctrl_stb_i' => { |
'range' => '', |
'intfc_port' => 'stb_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'irq' => { |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'intfc_port' => 'int_o', |
'range' => '', |
'type' => 'output' |
} |
}, |
'module_name' => 'ni_slave', |
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_slave.v', |
'system_h' => ' /* NI wb registers addresses |
0 : STATUS1_WB_ADDR // status1: {send_enable_binarry,receive_enable_binarry,send_vc_is_busy,receive_vc_is_busy,receive_vc_got_packet} |
1 : STATUS2_WB_ADDR // status2: |
2 : BURST_SIZE_WB_ADDR // The busrt size in words |
|
3 : SEND_DATA_SIZE_WB_ADDR, // The size of data to be sent in byte |
4 : SEND_STRT_WB_ADDR, // The address of data to be sent in byte |
5 : SEND_DEST_WB_ADDR // The destination router address |
6 : SEND_CTRL_WB_ADDR |
|
7 : RECEIVE_DATA_SIZE_WB_ADDR // The size of recieved data in byte |
8 : RECEIVE_STRT_WB_ADDR // The address pointer of reciever memory in byte |
9 : RECEIVE_SRC_WB_ADDR // The source router (the router which is sent this packet). |
10 : RECEIVE_CTRL_WB_ADDR // The NI reciever control register |
11 : RECEIVE_MAX_BUFF_SIZ // The receiver\'s allocated buffer size in words. If the packet size is bigger tha the buffer size the rest of will be discarred |
|
*/ |
|
|
|
#define ${IP}_STATUS1_REG (*((volatile unsigned int *) ($BASE))) //0 |
#define ${IP}_STATUS2_REG (*((volatile unsigned int *) ($BASE+4))) //1 |
#define ${IP}_BURST_SIZE_REG (*((volatile unsigned int *) ($BASE+8))) //2 |
|
|
#define ${IP}_NUM_VCs ${V} |
|
#define ${IP}_SEND_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+12+(v<<6)))) //3 |
#define ${IP}_SEND_START_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+16+(v<<6)))) //4 |
#define ${IP}_SEND_DEST_REG(v) (*((volatile unsigned int *) ($BASE+20+(v<<6)))) //5 |
#define ${IP}_SEND_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+24+(v<<6)))) //6 |
|
#define ${IP}_RECEIVE_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+28+(v<<6)))) //7 |
#define ${IP}_RECEIVE_STRT_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+32+(v<<6)))) //8 |
#define ${IP}_RECEIVE_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+36+(v<<6)))) //9 |
#define ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) (*((volatile unsigned int *) ($BASE+40+(v<<6)))) //10 |
#define ${IP}_RECEIVE_CRC_MATCH_REG(v) (*((volatile unsigned int *) ($BASE+44+(v<<6)))) //11 |
|
|
|
// assign status1= {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet}; |
// assign status2= {send_enable_binarry,receive_enable_binarry,crc_miss_match,got_pck_isr, save_done_isr,send_done_isr,got_pck_int_en, save_done_int_en,send_done_int_en}; |
|
|
#define ${IP}_got_packet(v) ((${IP}_STATUS1_REG >> (v)) & 0x1) |
#define ${IP}_packet_is_saved(v) ((${IP}_STATUS1_REG >> (${V}+v)) & 0x1) |
#define ${IP}_receive_is_busy(v) ((${IP}_STATUS1_REG >> (2*${V}+v)) & 0x1) |
#define ${IP}_send_is_busy(v) ((${IP}_STATUS1_REG >> (3*${V}+v)) & 0x1) |
|
|
|
void ${IP}_initial (unsigned int burst_size) { |
${IP}_BURST_SIZE_REG = burst_size; |
} |
|
|
void ${IP}_transfer (unsigned int v, unsigned int class_num, unsigned int data_start_addr, unsigned int data_size, unsigned int dest_x,unsigned int dest_y){ |
while (${IP}_send_is_busy(v)); // wait until VC is busy sending previous packet |
|
${IP}_SEND_DATA_SIZE_REG(v) = data_size; |
${IP}_SEND_START_ADDR_REG(v) = data_start_addr; |
${IP}_SEND_DEST_REG(v) = dest_x | (dest_y<<4)| (class_num<<8) ; |
|
} |
|
void ${IP}_receive (unsigned int v, unsigned int data_start_addr, unsigned int max_buffer_size){ |
while (${IP}_receive_is_busy(v)); // wait until VC is busy saving previous packet |
|
${IP}_RECEIVE_STRT_ADDR_REG(v) = data_start_addr; |
${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) = max_buffer_size; |
${IP}_RECEIVE_CTRL_REG(v) = 1; |
|
|
}', |
'ip_name' => 'ni_slave', |
'description' => '', |
'sockets' => { |
'ni' => { |
'connection_num' => 'single connection', |
'ni' => {}, |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'ni' |
} |
} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'version' => 45, |
'ports_order' => [ |
'reset', |
'clk', |
'current_x', |
'current_y', |
'flit_out', |
'flit_out_wr', |
'credit_in', |
'flit_in', |
'flit_in_wr', |
'credit_out', |
'ctrl_dat_i', |
'ctrl_sel_i', |
'ctrl_addr_i', |
'ctrl_cti_i', |
'ctrl_stb_i', |
'ctrl_cyc_i', |
'ctrl_we_i', |
'ctrl_dat_o', |
'ctrl_ack_o', |
'in_dat_i', |
'in_sel_i', |
'in_addr_i', |
'in_cti_i', |
'in_stb_i', |
'in_cyc_i', |
'in_we_i', |
'in_dat_o', |
'in_ack_o', |
'out_dat_i', |
'out_sel_i', |
'out_addr_i', |
'out_cti_i', |
'out_stb_i', |
'out_cyc_i', |
'out_we_i', |
'out_dat_o', |
'out_ack_o', |
'irq' |
], |
'hdl_files' => [ |
'/mpsoc/src_noc/arbiter.v', |
'/mpsoc/src_noc/flit_buffer.v', |
'/mpsoc/src_noc/input_ports.v', |
'/mpsoc/src_noc/main_comp.v', |
'/mpsoc/src_noc/route_mesh.v', |
'/mpsoc/src_noc/route_torus.v', |
'/mpsoc/src_noc/routing.v', |
'/mpsoc/src_peripheral/ni/ni_vc_dma.v', |
'/mpsoc/src_peripheral/ni/ni_vc_wb_slave_regs.v', |
'/mpsoc/src_peripheral/ni/ni_slave.v', |
'/mpsoc/src_peripheral/ni/ni_crc32.v', |
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv', |
'/mpsoc/src_peripheral/ram/generic_ram.v', |
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v', |
'/mpsoc/src_peripheral/ram/wb_dual_port_ram.v', |
'/mpsoc/src_peripheral/ram/wb_single_port_ram.v' |
], |
'unused' => { |
'plug:wb_slave[0]' => [ |
'rty_o', |
'tag_i', |
'bte_i', |
'err_o' |
], |
'plug:wb_slave[1]' => [ |
'rty_o', |
'tag_i', |
'bte_i', |
'err_o' |
], |
'plug:wb_slave[2]' => [ |
'rty_o', |
'tag_i', |
'bte_i', |
'err_o' |
] |
}, |
'parameters' => { |
'S_Aw' => { |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'content' => '', |
'default' => '8', |
'info' => 'Parameter', |
'redefine_param' => 1 |
}, |
'SELw' => { |
'type' => 'Fixed', |
'default' => '4', |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'Fw' => { |
'info' => undef, |
'redefine_param' => 0, |
'global_param' => 'Localparam', |
'content' => '', |
'default' => '2+V+Fpay', |
'type' => 'Fixed' |
}, |
'V' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'default' => '4', |
'type' => 'Fixed' |
}, |
'INPUT_MEM_Aw' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'default' => ' 10', |
'content' => '4,32,1', |
'global_param' => 'Parameter', |
'type' => 'Spin-button' |
}, |
'B' => { |
'global_param' => 'Parameter', |
'content' => '', |
'default' => ' 4', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'redefine_param' => 1 |
}, |
'MAX_TRANSACTION_WIDTH' => { |
'type' => 'Spin-button', |
'content' => '4,32,1', |
'global_param' => 'Localparam', |
'default' => '13', |
'info' => 'maximum packet size width in words. |
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.', |
'redefine_param' => 1 |
}, |
'Xw' => { |
'redefine_param' => 0, |
'info' => undef, |
'default' => 'log2(NX)', |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed' |
}, |
'ROUTE_NAME' => { |
'type' => 'Fixed', |
'default' => '"XY" ', |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'OUT_MEM_BYTEw' => { |
'type' => 'Fixed', |
'default' => 'OUTPUT_MEM_Aw+(Dw/8)', |
'content' => '', |
'global_param' => 'Don\'t include', |
'redefine_param' => 1, |
'info' => undef |
}, |
'Dw' => { |
'global_param' => 'Localparam', |
'content' => '32,256,8', |
'default' => '32', |
'type' => 'Spin-button', |
'info' => 'wishbone_bus data width in bits.', |
'redefine_param' => 1 |
}, |
'SRC_ADR_HDR_WIDTH' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'type' => 'Fixed', |
'default' => '8', |
'content' => '', |
'global_param' => 'Localparam' |
}, |
'M_Aw' => { |
'global_param' => 'Localparam', |
'content' => 'Dw', |
'default' => '32', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'redefine_param' => 1 |
}, |
'C' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'content' => '', |
'global_param' => 'Parameter', |
'default' => ' 4' |
}, |
'CRC_EN' => { |
'info' => 'The parameter can be selected as "YES" or "NO". |
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'content' => '"YES","NO"', |
'global_param' => 'Localparam', |
'default' => '"NO"' |
}, |
'NX' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'default' => ' 4', |
'type' => 'Fixed' |
}, |
'MAX_BURST_SIZE' => { |
'type' => 'Combo-box', |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'global_param' => 'Localparam', |
'default' => '16', |
'info' => 'Maximum burst size in words. |
The NI release wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ', |
'redefine_param' => 1 |
}, |
'CLASS_HDR_WIDTH' => { |
'default' => '8', |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'Fpay' => { |
'default' => ' 32', |
'global_param' => 'Parameter', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'ROUTE_TYPE' => { |
'type' => 'Fixed', |
'default' => ' ', |
'content' => '', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'IN_MEM_BYTEw' => { |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => 'INPUT_MEM_Aw+(Dw/8)', |
'global_param' => 'Don\'t include', |
'content' => '' |
}, |
'SWA_ARBITER_TYPE' => { |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"RRA"', |
'content' => '', |
'global_param' => 'Parameter' |
}, |
'WEIGHTw' => { |
'default' => '4', |
'global_param' => 'Parameter', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => undef |
}, |
'OUTPUT_MEM_Aw' => { |
'type' => 'Spin-button', |
'default' => ' 10', |
'content' => '4,32,1', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'DEBUG_EN' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'default' => ' 1', |
'content' => '', |
'global_param' => 'Parameter', |
'type' => 'Fixed' |
}, |
'TOPOLOGY' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'content' => '', |
'default' => '"MESH"' |
}, |
'DST_ADR_HDR_WIDTH' => { |
'type' => 'Fixed', |
'default' => '8', |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'ROUTING_HDR_WIDTH' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'default' => '8', |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed' |
}, |
'P' => { |
'default' => '5', |
'content' => '', |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'TAGw' => { |
'default' => '3', |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'Yw' => { |
'content' => '', |
'global_param' => 'Localparam', |
'default' => 'log2(NY)', |
'type' => 'Fixed', |
'info' => undef, |
'redefine_param' => 0 |
}, |
'NY' => { |
'type' => 'Fixed', |
'content' => '', |
'global_param' => 'Parameter', |
'default' => ' 4', |
'info' => 'Parameter', |
'redefine_param' => 1 |
} |
}, |
'modules' => { |
'ni_slave' => {} |
} |
}, 'ip_gen' ); |
/NoC/old/ni.IP
0,0 → 1,639
####################################################################### |
## File: ni.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ni = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ni/ni.v', |
'/mpsoc/src_noc/arbiter.v', |
'/mpsoc/src_noc/flit_buffer.v', |
'/mpsoc/src_noc/inout_ports.v', |
'/mpsoc/src_noc/main_comp.v', |
'/mpsoc/src_noc/route_mesh.v', |
'/mpsoc/src_noc/route_torus.v', |
'/mpsoc/src_noc/routing.v' |
], |
'system_h' => ' #define ${IP}_BASE_ADDR ${BASE} |
#define ${IP}_STATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR ))) |
#define ${IP}_MEM_PCKSIZ (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 ))) |
#define ${IP}_PCKSIZE (*((volatile unsigned int *) (${IP}_BASE_ADDR+8))) |
#define ${IP}_MEM (*((volatile unsigned int *) (${IP}_BASE_ADDR+12))) |
|
#define ${IP}_VC_WR_ADDR(v) (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 + (1<<5)+ (v<<6) ))) |
#define ${IP}_VC_RD_ADDR(v) (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 + (v<<6) ))) |
|
|
#define ${IP}_VC_NUM ${V} |
#define ${IP}_VC_MASK ((1<<${V})-1) |
#define ${IP}_CLASS_IN_HDR_WIDTH 8 |
#define ${IP}_DEST_IN_HDR_WIDTH 8 |
#define ${IP}_X_Y_IN_HDR_WIDTH 4 |
|
/* |
[14+V : 14+2V-1]rd_vc_not_empty |
[14 : 14+V-1] wr_vc_not_empty |
13 rsv_pck_isr |
12 rd_done_isr |
11 wr_done_isr |
10 rsv_pck_int_en |
9 rd_done_int_en |
8 wr_done_int_en |
7 all_wr_vcs_full |
6 any_rd_vc_has_data |
5 rd_no_pck_err |
4 rd_ovr_size_err |
3 rd_done |
2 wr_done |
1 rd_busy |
0 wr_busy |
*/ |
#define ${IP}_WR_BUSY (1<<0) |
#define ${IP}_RD_BUSY (1<<1) |
#define ${IP}_WR_DONE (1<<2) |
#define ${IP}_RD_DONE (1<<3) |
#define ${IP}_RD_OVR_ERR (1<<4) |
#define ${IP}_RD_NPCK_ERR (1<<5) |
#define ${IP}_HAS_PCK (1<<6) |
#define ${IP}_ALL_VCS_FULL (1<<7) |
#define ${IP}_WR_DONE_INT_EN (1<<8) |
#define ${IP}_RD_DONE_INT_EN (1<<9) |
#define ${IP}_RSV_PCK_INT_EN (1<<10) |
#define ${IP}_WR_DONE_ISR (1<<11) |
#define ${IP}_RD_DONE_ISR (1<<12) |
#define ${IP}_RSV_PCK_ISR (1<<13) |
#define ${IP}WR_VCS_NO_EMPTY (${IP}_VC_MASK <<14) |
#define ${IP}RD_VCS_NO_EMPTY (${IP}_VC_MASK << (14+${V})) |
|
#define ${IP}_PTR_WIDTH 20 |
#define ${IP}_PCK_SIZE_WIDTH 12 |
|
|
|
|
#define ${IP}_HDR_DEST_CORE_ADDR(DES_X, DES_Y) ((DES_X << ${IP}_X_Y_IN_HDR_WIDTH) | DES_Y)<<(2*${IP}_X_Y_IN_HDR_WIDTH) |
#define ${IP}_HDR_CLASS(pck_class) (pck_class << ( ${IP}_DEST_IN_HDR_WIDTH+ (4* ${IP}_X_Y_IN_HDR_WIDTH))) |
|
|
#define ${IP}_wait_for_sending_pck() while (!(${IP}_STATUS & ${IP}_WR_DONE)) |
#define ${IP}_wait_for_reading_pck() while (!(${IP}_STATUS & ${IP}_RD_DONE)) |
#define ${IP}_wait_for_getting_pck() while (!(${IP}_STATUS & ${IP}_HAS_PCK)) |
|
/***************************************** |
void send_pck (unsigned int * pck_buffer, unsigned int data_size, unsigned int vc_num); |
sending a packet through NoC network; |
(unsigned int des_x,unsigned int des_y : destination core address; |
unsigned int * pck_buffer : the buffer which hold the packet; The data must start from buff[1]; |
unsigned int data_size : the size of data which wanted to be sent out in word = packet_size-1; |
unsigned int class |
|
****************************************/ |
inline void ${IP}_send_pck (unsigned int des_x, unsigned int des_y, volatile unsigned int * pck_buffer, unsigned int data_size, unsigned int pck_class, unsigned int vc_num){ |
pck_buffer [0] = ${IP}_HDR_DEST_CORE_ADDR(des_x, des_y) | ${IP}_HDR_CLASS(pck_class); |
${IP}_VC_WR_ADDR(vc_num) = (unsigned int) (& pck_buffer [0]) + (data_size<<${IP}_PTR_WIDTH); |
${IP}_wait_for_sending_pck(); |
} |
|
/******************************************* |
void save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size); |
save a received packet on pck_buffer |
unsigned int * pck_buffer: the buffer for storing the packet; The read data start from buff[1]; |
********************************************/ |
inline void ${IP}_save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size,unsigned int vc_num){ |
${IP}_wait_for_getting_pck(); |
${IP}_VC_RD_ADDR(vc_num) = (unsigned int) (& pck_buffer [0]) + (buffer_size<<${IP}_PTR_WIDTH); |
${IP}_wait_for_reading_pck(); |
}', |
'ip_name' => 'ni', |
'parameters_order' => [ |
'V', |
'B', |
'NX', |
'NY', |
'Fpay', |
'TOPOLOGY', |
'ROUTE_NAME', |
'DEBUG_EN', |
'COMB_MEM_PTR_W', |
'COMB_PCK_SIZE_W', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'Yw', |
'Fw', |
'Xw' |
], |
'ports_order' => [ |
'reset', |
'clk', |
'current_x', |
'current_y', |
'flit_out', |
'flit_out_wr', |
'credit_in', |
'flit_in', |
'flit_in_wr', |
'credit_out', |
's_dat_i', |
's_sel_i', |
's_addr_i', |
's_cti_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
's_err_o', |
's_rty_o', |
'm_sel_o', |
'm_dat_o', |
'm_addr_o', |
'm_cti_o', |
'm_stb_o', |
'm_cyc_o', |
'm_we_o', |
'm_dat_i', |
'm_ack_i', |
'm_err_i', |
'm_rty_i', |
'irq' |
], |
'sockets' => { |
'ni' => { |
'connection_num' => 'single connection', |
'value' => 1, |
'0' => { |
'name' => 'ni' |
}, |
'type' => 'num', |
'ni' => {} |
} |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ni/ni.v', |
'module_name' => 'ni', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'tag_i', |
'bte_i' |
], |
'plug:wb_master[0]' => [ |
'tag_o', |
'bte_o' |
] |
}, |
'category' => 'NoC', |
'description' => 'Network interface', |
'parameters' => { |
'Dw' => { |
'info' => undef, |
'default' => ' 32', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'NY' => { |
'info' => undef, |
'default' => ' 2', |
'global_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'DEBUG_EN' => { |
'info' => undef, |
'default' => '0', |
'global_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'NX' => { |
'info' => undef, |
'default' => ' 2', |
'global_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'V' => { |
'info' => '', |
'default' => ' 4', |
'global_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'CONGESTION_INDEX' => { |
'info' => undef, |
'default' => '3', |
'global_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'Fw' => { |
'info' => undef, |
'default' => '2+V+Fpay', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 0 |
}, |
'COMB_PCK_SIZE_W' => { |
'info' => undef, |
'default' => '12', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'TAGw' => { |
'info' => undef, |
'default' => '3', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'COMB_MEM_PTR_W' => { |
'info' => undef, |
'default' => '20', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'M_Aw' => { |
'info' => undef, |
'default' => '32', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'ROUTE_NAME' => { |
'info' => undef, |
'default' => '"XY"', |
'global_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'Xw ' => { |
'info' => undef, |
'default' => 'log2(NX)', |
'global_param' => 0, |
'content' => '', |
'redefine_param' => 0, |
'type' => 'Fixed' |
}, |
'Fpay' => { |
'info' => undef, |
'default' => ' 32', |
'global_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'ROUTE_TYPE' => { |
'info' => undef, |
'default' => '"DETERMINISTIC"', |
'global_param' => 1, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'SELw' => { |
'info' => undef, |
'default' => '4 ', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'P' => { |
'info' => undef, |
'default' => ' 5', |
'global_param' => 1, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'B' => { |
'info' => '', |
'default' => ' 4', |
'global_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'Xw' => { |
'info' => undef, |
'default' => 'log2(NX)', |
'global_param' => 0, |
'content' => '', |
'redefine_param' => 0, |
'type' => 'Fixed' |
}, |
'TOPOLOGY' => { |
'info' => undef, |
'default' => '"MESH"', |
'global_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'S_Aw' => { |
'info' => undef, |
'default' => '7', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'Yw' => { |
'info' => undef, |
'default' => 'log2(NY)', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 0 |
}, |
'Xwj' => { |
'info' => undef, |
'default' => 'fvf', |
'global_param' => 0, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'SSA_EN' => { |
'info' => undef, |
'default' => '"NO"', |
'global_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
} |
}, |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'0' => { |
'name' => 'wb_master' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'0' => { |
'name' => 'int_peripheral' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_slave' => { |
'0' => { |
'width' => 9, |
'name' => 'wb_slave', |
'addr' => '0xb800_0000 0xbfff_ffff custom devices' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'modules' => { |
'ni' => {} |
}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'ports' => { |
'm_addr_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'adr_o', |
'range' => 'M_Aw-1 : 0', |
'type' => 'output' |
}, |
'm_cyc_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cyc_o', |
'range' => '', |
'type' => 'output' |
}, |
's_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'type' => 'input' |
}, |
's_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
}, |
'm_we_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'we_o', |
'range' => '', |
'type' => 'output' |
}, |
'credit_out' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'credit_out', |
'range' => 'V-1: 0', |
'type' => 'output' |
}, |
'flit_in_wr' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_in_wr', |
'range' => '', |
'type' => 'input' |
}, |
'm_ack_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'ack_i', |
'range' => '', |
'type' => 'input' |
}, |
's_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => 'S_Aw-1 : 0', |
'type' => 'input' |
}, |
's_dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
's_cti_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cti_i', |
'range' => 'TAGw-1 : 0', |
'type' => 'input' |
}, |
'current_y' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'current_y', |
'range' => 'Yw-1 : 0', |
'type' => 'input' |
}, |
's_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
's_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'range' => '', |
'type' => 'input' |
}, |
'm_stb_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'stb_o', |
'range' => '', |
'type' => 'output' |
}, |
's_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
}, |
'flit_out_wr' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_out_wr', |
'range' => '', |
'type' => 'output' |
}, |
'm_dat_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
}, |
'm_dat_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
's_err_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output' |
}, |
'm_cti_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cti_o', |
'range' => 'TAGw-1 : 0', |
'type' => 'output' |
}, |
's_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'flit_out' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_out', |
'range' => 'Fw-1 : 0', |
'type' => 'output' |
}, |
'credit_in' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'credit_in', |
'range' => 'V-1 : 0', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'input' |
}, |
'm_err_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'err_i', |
'range' => '', |
'type' => 'input' |
}, |
'm_rty_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'rty_i', |
'range' => '', |
'type' => 'input' |
}, |
'm_sel_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'sel_o', |
'range' => 'SELw-1 : 0', |
'type' => 'output' |
}, |
'flit_in' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_in', |
'range' => 'Fw-1 : 0', |
'type' => 'input' |
}, |
'current_x' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'current_x', |
'range' => 'Xw-1 : 0', |
'type' => 'input' |
}, |
'irq' => { |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'intfc_port' => 'int_o', |
'range' => '', |
'type' => 'output' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
's_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o', |
'range' => '', |
'type' => 'output' |
} |
} |
}, 'ip_gen' ); |
NoC/old/ni.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: NoC/old/ni_sep.IP
===================================================================
--- NoC/old/ni_sep.IP (nonexistent)
+++ NoC/old/ni_sep.IP (revision 38)
@@ -0,0 +1,680 @@
+#######################################################################
+## File: ni_sep.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.1
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ni_sep = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/ni/ni_sep.v',
+ '/mpsoc/src_peripheral/ni/sub_ni_rd.v',
+ '/mpsoc/src_peripheral/ni/sub_ni_wr.v',
+ '/mpsoc/src_noc/arbiter.v',
+ '/mpsoc/src_noc/flit_buffer.v',
+ '/mpsoc/src_noc/inout_ports.v',
+ '/mpsoc/src_noc/main_comp.v',
+ '/mpsoc/src_noc/route_mesh.v',
+ '/mpsoc/src_noc/route_torus.v',
+ '/mpsoc/src_noc/routing.v'
+ ],
+ 'system_h' => '#define ${IP}_BASE_ADDR ${BASE}
+ #define ${IP}_STATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR )))
+ #define ${IP}_MEM_PCKSIZ (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 )))
+ #define ${IP}_PCKSIZE (*((volatile unsigned int *) (${IP}_BASE_ADDR+8)))
+ #define ${IP}_MEM (*((volatile unsigned int *) (${IP}_BASE_ADDR+12)))
+
+ #define ${IP}_VC_WR_ADDR(v) (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 + (1<<5)+ (v<<6) )))
+ #define ${IP}_VC_RD_ADDR(v) (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 + (v<<6) )))
+
+
+ #define ${IP}_VC_NUM ${V}
+ #define ${IP}_VC_MASK ((1<<${V})-1)
+ #define ${IP}_CLASS_IN_HDR_WIDTH 8
+ #define ${IP}_DEST_IN_HDR_WIDTH 8
+ #define ${IP}_X_Y_IN_HDR_WIDTH 4
+
+/*
+ [14+V : 14+2V-1]rd_vc_not_empty
+ [14 : 14+V-1] wr_vc_not_empty
+ 13 rsv_pck_isr
+ 12 rd_done_isr
+ 11 wr_done_isr
+ 10 rsv_pck_int_en
+ 9 rd_done_int_en
+ 8 wr_done_int_en
+ 7 all_wr_vcs_full
+ 6 any_rd_vc_has_data
+ 5 rd_no_pck_err
+ 4 rd_ovr_size_err
+ 3 rd_done
+ 2 wr_done
+ 1 rd_busy
+ 0 wr_busy
+*/
+ #define ${IP}_WR_BUSY (1<<0)
+ #define ${IP}_RD_BUSY (1<<1)
+ #define ${IP}_WR_DONE (1<<2)
+ #define ${IP}_RD_DONE (1<<3)
+ #define ${IP}_RD_OVR_ERR (1<<4)
+ #define ${IP}_RD_NPCK_ERR (1<<5)
+ #define ${IP}_HAS_PCK (1<<6)
+ #define ${IP}_ALL_VCS_FULL (1<<7)
+ #define ${IP}_WR_DONE_INT_EN (1<<8)
+ #define ${IP}_RD_DONE_INT_EN (1<<9)
+ #define ${IP}_RSV_PCK_INT_EN (1<<10)
+ #define ${IP}_WR_DONE_ISR (1<<11)
+ #define ${IP}_RD_DONE_ISR (1<<12)
+ #define ${IP}_RSV_PCK_ISR (1<<13)
+ #define ${IP}WR_VCS_NO_EMPTY (${IP}_VC_MASK <<14)
+ #define ${IP}RD_VCS_NO_EMPTY (${IP}_VC_MASK << (14+${V}))
+
+ #define ${IP}_PTR_WIDTH 20
+ #define ${IP}_PCK_SIZE_WIDTH 12
+
+
+
+
+ #define ${IP}_HDR_DEST_CORE_ADDR(DES_X, DES_Y) ((DES_X << ${IP}_X_Y_IN_HDR_WIDTH) | DES_Y)<<(2*${IP}_X_Y_IN_HDR_WIDTH)
+ #define ${IP}_HDR_CLASS(pck_class) (pck_class << ( ${IP}_DEST_IN_HDR_WIDTH+ (4* ${IP}_X_Y_IN_HDR_WIDTH)))
+
+
+ #define ${IP}_wait_for_sending_pck() while (!(${IP}_STATUS & ${IP}_WR_DONE))
+ #define ${IP}_wait_for_reading_pck() while (!(${IP}_STATUS & ${IP}_RD_DONE))
+ #define ${IP}_wait_for_getting_pck() while (!(${IP}_STATUS & ${IP}_HAS_PCK))
+
+/*****************************************
+void send_pck (unsigned int * pck_buffer, unsigned int data_size, unsigned int vc_num);
+sending a packet through NoC network;
+(unsigned int des_x,unsigned int des_y : destination core address;
+unsigned int * pck_buffer : the buffer which hold the packet; The data must start from buff[1];
+unsigned int data_size : the size of data which wanted to be sent out in word = packet_size-1;
+unsigned int class
+
+****************************************/
+ inline void ${IP}_send_pck (unsigned int des_x, unsigned int des_y, volatile unsigned int * pck_buffer, unsigned int data_size, unsigned int pck_class, unsigned int vc_num){
+ pck_buffer [0] = ${IP}_HDR_DEST_CORE_ADDR(des_x, des_y) | ${IP}_HDR_CLASS(pck_class);
+ ${IP}_VC_WR_ADDR(vc_num) = (unsigned int) (& pck_buffer [0]) + (data_size<<${IP}_PTR_WIDTH);
+ ${IP}_wait_for_sending_pck();
+ }
+
+/*******************************************
+void save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size);
+save a received packet on pck_buffer
+unsigned int * pck_buffer: the buffer for storing the packet; The read data start from buff[1];
+********************************************/
+ inline void ${IP}_save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size,unsigned int vc_num){
+ ${IP}_VC_RD_ADDR(vc_num) = (unsigned int) (& pck_buffer [0]) + (buffer_size<<${IP}_PTR_WIDTH);
+ ${IP}_wait_for_reading_pck();
+ }',
+ 'ip_name' => 'ni_sep',
+ 'parameters_order' => [
+ 'V',
+ 'B',
+ 'NX',
+ 'NY',
+ 'Fpay',
+ 'TOPOLOGY',
+ 'ROUTE_NAME',
+ 'DEBUG_EN',
+ 'COMB_MEM_PTR_W',
+ 'COMB_PCK_SIZE_W',
+ 'Dw',
+ 'S_Aw',
+ 'M_Aw',
+ 'TAGw',
+ 'SELw',
+ 'Yw',
+ 'Fw',
+ 'Xw'
+ ],
+ 'ports_order' => [
+ 'reset',
+ 'clk',
+ 'current_x',
+ 'current_y',
+ 'flit_out',
+ 'flit_out_wr',
+ 'credit_in',
+ 'flit_in',
+ 'flit_in_wr',
+ 'credit_out',
+ 's_dat_i',
+ 's_sel_i',
+ 's_addr_i',
+ 's_cti_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 'm_rd_sel_o',
+ 'm_rd_dat_o',
+ 'm_rd_addr_o',
+ 'm_rd_cti_o',
+ 'm_rd_stb_o',
+ 'm_rd_cyc_o',
+ 'm_rd_we_o',
+ 'm_rd_ack_i',
+ 'm_wr_sel_o',
+ 'm_wr_addr_o',
+ 'm_wr_cti_o',
+ 'm_wr_stb_o',
+ 'm_wr_cyc_o',
+ 'm_wr_we_o',
+ 'm_wr_dat_i',
+ 'm_wr_ack_i',
+ 'irq'
+ ],
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ni/ni_sep.v',
+ 'sockets' => {
+ 'ni' => {
+ 'connection_num' => 'single connection',
+ '0' => {
+ 'name' => 'ni'
+ },
+ 'value' => 1,
+ 'type' => 'num',
+ 'ni' => {}
+ }
+ },
+ 'module_name' => 'ni_sep',
+ 'unused' => {
+ 'plug:wb_master[1]' => [
+ 'tag_o',
+ 'bte_o',
+ 'dat_o',
+ 'err_i',
+ 'rty_i'
+ ],
+ 'plug:wb_slave[0]' => [
+ 'err_o',
+ 'rty_o',
+ 'tag_i',
+ 'bte_i'
+ ],
+ 'plug:wb_master[0]' => [
+ 'tag_o',
+ 'dat_i',
+ 'bte_o',
+ 'err_i',
+ 'rty_i'
+ ]
+ },
+ 'category' => 'NoC',
+ 'plugs' => {
+ 'wb_master' => {
+ 'wb_master' => {},
+ '1' => {
+ 'name' => 'wb_wr'
+ },
+ '0' => {
+ 'name' => 'wb_rd'
+ },
+ 'value' => 2,
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'interrupt_peripheral' => {
+ 'interrupt_peripheral' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'intrpt_prhl'
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ '1' => {
+ 'width' => 1,
+ 'name' => 'wb_slave_1',
+ 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
+ },
+ '0' => {
+ 'width' => 9,
+ 'name' => 'wb_slave',
+ 'addr' => '0xb800_0000 0xbfff_ffff custom devices'
+ },
+ 'value' => 1,
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'modules' => {
+ 'ni_sep' => {}
+ },
+ 'parameters' => {
+ 'Dw' => {
+ 'info' => undef,
+ 'default' => ' 32',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'DEBUG_EN' => {
+ 'info' => undef,
+ 'default' => '0',
+ 'global_param' => 'Parameter',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'NY' => {
+ 'info' => undef,
+ 'default' => ' 2',
+ 'global_param' => 'Parameter',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'NX' => {
+ 'info' => undef,
+ 'default' => ' 2',
+ 'global_param' => 'Parameter',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'V' => {
+ 'info' => '',
+ 'default' => ' 4',
+ 'global_param' => 'Parameter',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'CONGESTION_INDEX' => {
+ 'info' => undef,
+ 'default' => '3',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Fw' => {
+ 'info' => undef,
+ 'default' => '2+V+Fpay',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 0,
+ 'type' => 'Fixed'
+ },
+ 'COMB_PCK_SIZE_W' => {
+ 'info' => undef,
+ 'default' => '12',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'TAGw' => {
+ 'info' => undef,
+ 'default' => '3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'M_Aw' => {
+ 'info' => undef,
+ 'default' => '32',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'COMB_MEM_PTR_W' => {
+ 'info' => undef,
+ 'default' => '20',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'ROUTE_NAME' => {
+ 'info' => undef,
+ 'default' => '"XY"',
+ 'global_param' => 'Parameter',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Xw ' => {
+ 'info' => undef,
+ 'default' => 'log2(NX)',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 0
+ },
+ 'Fpay' => {
+ 'info' => undef,
+ 'default' => ' 32',
+ 'global_param' => 'Parameter',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'ROUTE_TYPE' => {
+ 'info' => undef,
+ 'default' => '"DETERMINISTIC"',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'SELw' => {
+ 'info' => undef,
+ 'default' => '4 ',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'P' => {
+ 'info' => undef,
+ 'default' => ' 5',
+ 'global_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ },
+ 'B' => {
+ 'info' => '',
+ 'default' => ' 4',
+ 'global_param' => 'Parameter',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'S_Aw' => {
+ 'info' => undef,
+ 'default' => '7',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'TOPOLOGY' => {
+ 'info' => undef,
+ 'default' => '"MESH"',
+ 'global_param' => 'Parameter',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Xw' => {
+ 'info' => undef,
+ 'default' => 'log2(NX)',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 0
+ },
+ 'Yw' => {
+ 'info' => undef,
+ 'default' => 'log2(NY)',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 0,
+ 'type' => 'Fixed'
+ },
+ 'SSA_EN' => {
+ 'info' => undef,
+ 'default' => '"NO"',
+ 'global_param' => 1,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Xwj' => {
+ 'info' => undef,
+ 'default' => 'fvf',
+ 'global_param' => 0,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1
+ }
+ },
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'ports' => {
+ 'm_rd_cyc_o' => {
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 's_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_cyc_i' => {
+ 'intfc_port' => 'cyc_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_wr_sel_o' => {
+ 'intfc_port' => 'sel_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_wr_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_wr_addr_o' => {
+ 'intfc_port' => 'adr_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => 'M_Aw-1 : 0',
+ 'type' => 'output'
+ },
+ 'credit_out' => {
+ 'intfc_port' => 'credit_out',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'V-1 : 0',
+ 'type' => 'output'
+ },
+ 'flit_in_wr' => {
+ 'intfc_port' => 'flit_in_wr',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_addr_i' => {
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'S_Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_cti_i' => {
+ 'intfc_port' => 'cti_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'current_y' => {
+ 'intfc_port' => 'current_y',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'Yw-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_wr_cti_o' => {
+ 'intfc_port' => 'cti_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_rd_ack_i' => {
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_sel_i' => {
+ 'intfc_port' => 'sel_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_we_i' => {
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_rd_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_stb_i' => {
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_wr_stb_o' => {
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'flit_out_wr' => {
+ 'intfc_port' => 'flit_out_wr',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_rd_sel_o' => {
+ 'intfc_port' => 'sel_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_rd_addr_o' => {
+ 'intfc_port' => 'adr_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'M_Aw-1 : 0',
+ 'type' => 'output'
+ },
+ 's_ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'm_wr_ack_i' => {
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_rd_we_o' => {
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'flit_out' => {
+ 'intfc_port' => 'flit_out',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'Fw-1 : 0',
+ 'type' => 'output'
+ },
+ 'credit_in' => {
+ 'intfc_port' => 'credit_in',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'V-1 : 0',
+ 'type' => 'input'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_rd_stb_o' => {
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'flit_in' => {
+ 'intfc_port' => 'flit_in',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'Fw-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_rd_cti_o' => {
+ 'intfc_port' => 'cti_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_wr_we_o' => {
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'current_x' => {
+ 'intfc_port' => 'current_x',
+ 'intfc_name' => 'socket:ni[0]',
+ 'range' => 'Xw-1 : 0',
+ 'type' => 'input'
+ },
+ 'irq' => {
+ 'intfc_port' => 'int_o',
+ 'intfc_name' => 'plug:interrupt_peripheral[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_wr_cyc_o' => {
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '',
+ 'type' => 'output'
+ }
+ }
+ }, 'ip_gen' );
NoC/old/ni_sep.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Other/dummy_module.IP
===================================================================
--- Other/dummy_module.IP (revision 34)
+++ Other/dummy_module.IP (revision 38)
@@ -126,7 +126,7 @@
},
'parameters' => {
'S_Aw' => {
- 'deafult' => ' 7',
+ 'default' => ' 7',
'type' => 'Fixed',
'info' => 'Parameter',
'redefine_param' => 1,
@@ -135,7 +135,7 @@
},
'REQ_LEN_CLK_NUM' => {
'type' => 'Spin-button',
- 'deafult' => ' 10',
+ 'default' => ' 10',
'info' => 'Parameter',
'content' => '1,100000,1',
'global_param' => 'Parameter',
@@ -144,7 +144,7 @@
'TAGw' => {
'info' => 'Parameter',
'type' => 'Fixed',
- 'deafult' => ' 3',
+ 'default' => ' 3',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
@@ -153,7 +153,7 @@
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '',
- 'deafult' => ' 32',
+ 'default' => ' 32',
'type' => 'Fixed',
'info' => 'Parameter'
},
@@ -160,7 +160,7 @@
'REQ_WAIT_CLK_NUM' => {
'info' => 'Parameter',
'type' => 'Spin-button',
- 'deafult' => ' 20',
+ 'default' => ' 20',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '1,100000,1'
@@ -168,7 +168,7 @@
'SELw' => {
'info' => 'Parameter',
'type' => 'Fixed',
- 'deafult' => ' 4',
+ 'default' => ' 4',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => ''
@@ -178,7 +178,7 @@
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
- 'deafult' => ' 32',
+ 'default' => ' 32',
'info' => 'Parameter'
}
},
Index: Other/gcd.IP
===================================================================
--- Other/gcd.IP (nonexistent)
+++ Other/gcd.IP (revision 38)
@@ -0,0 +1,222 @@
+#######################################################################
+## File: gcd.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.8.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ipgen = bless( {
+ 'parameters' => {
+ 'SELw' => {
+ 'type' => 'Fixed',
+ 'default' => '4',
+ 'content' => '',
+ 'global_param' => 'Localparam',
+ 'info' => 'Parameter',
+ 'redefine_param' => 1
+ },
+ 'GCDw' => {
+ 'global_param' => 'Parameter',
+ 'default' => '32',
+ 'type' => 'Combo-box',
+ 'content' => '8,16,32',
+ 'info' => 'GCD\'s Input/output width in bits',
+ 'redefine_param' => 1
+ },
+ 'TAGw' => {
+ 'info' => 'Parameter',
+ 'redefine_param' => 1,
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'default' => '3'
+ },
+ 'Dw' => {
+ 'default' => 'GCDw',
+ 'type' => 'Fixed',
+ 'content' => '',
+ 'global_param' => 'Localparam',
+ 'redefine_param' => 1,
+ 'info' => 'Parameter'
+ },
+ 'Aw' => {
+ 'redefine_param' => 1,
+ 'info' => 'Parameter',
+ 'default' => '5',
+ 'type' => 'Fixed',
+ 'content' => '',
+ 'global_param' => 'Localparam'
+ }
+ },
+ 'ports' => {
+ 's_tag_i' => {
+ 'intfc_port' => 'tag_i',
+ 'type' => 'input',
+ 'range' => 'TAGw-1 : 0',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 's_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'stb_i'
+ },
+ 's_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'input',
+ 'range' => 'Dw-1 : 0'
+ },
+ 's_cyc_i' => {
+ 'intfc_port' => 'cyc_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'input',
+ 'range' => ''
+ },
+ 's_sel_i' => {
+ 'intfc_port' => 'sel_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_rty_o' => {
+ 'intfc_port' => 'rty_o',
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'reset' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i'
+ },
+ 's_addr_i' => {
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'input',
+ 'range' => 'Aw-1 : 0'
+ },
+ 's_err_o' => {
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'err_o'
+ },
+ 's_ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 's_we_i' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'we_i'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'output',
+ 'range' => 'Dw-1 : 0'
+ }
+ },
+ 'ip_name' => 'gcd',
+ 'modules' => {
+ 'gcd_ip' => {}
+ },
+ 'file_name' => '/home/alireza/mywork/workshop/files/gcd_ip.v',
+ 'category' => 'Other',
+ 'version' => 3,
+ 'parameters_order' => [
+ 'GCDw',
+ 'Dw',
+ 'Aw',
+ 'TAGw',
+ 'SELw'
+ ],
+ 'plugs' => {
+ 'clk' => {
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1
+ },
+ 'wb_slave' => {
+ 'type' => 'num',
+ 'value' => 1,
+ '0' => {
+ 'width' => 5,
+ 'addr' => '0xb800_0000 0xbfff_ffff custom devices',
+ 'name' => 'wb_slave'
+ }
+ },
+ 'reset' => {
+ 'type' => 'num',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ }
+ }
+ },
+ 'system_h' => '#define ${IP}_DONE_ADDR (*((volatile unsigned int *) ($BASE)))
+#define ${IP}_IN_1_ADDR (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_IN_2_ADDR (*((volatile unsigned int *) ($BASE+8)))
+#define ${IP}_GCD_ADDR (*((volatile unsigned int *) ($BASE+12)))
+
+
+#define ${IP}_IN1_WRITE(value) ${IP}_IN_1_ADDR=value
+#define ${IP}_IN2_WRITE(value) ${IP}_IN_2_ADDR=value
+#define ${IP}_DONE_READ() ${IP}_DONE_ADDR
+#define ${IP}_READ() ${IP}_GCD_ADDR
+
+unsigned int gcd_hardware ( unsigned int p, unsigned int q ){
+ ${IP}_IN1_WRITE(p);
+ ${IP}_IN2_WRITE(q);
+ while (${IP}_DONE_READ()!=1);
+ return ${IP}_READ();
+}',
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'description' => 'gcd module',
+ 'module_name' => 'gcd_ip',
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 's_dat_i',
+ 's_sel_i',
+ 's_addr_i',
+ 's_tag_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 's_err_o',
+ 's_rty_o'
+ ],
+ 'hdl_files' => [
+ '/workshop/files/gcd.v',
+ '/workshop/files/gcd_ip.v'
+ ],
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'bte_i',
+ 'cti_i'
+ ]
+ }
+ }, 'ip_gen' );
Index: Other/gcd.IP.back
===================================================================
--- Other/gcd.IP.back (nonexistent)
+++ Other/gcd.IP.back (revision 38)
@@ -0,0 +1,224 @@
+#######################################################################
+## File: gcd.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.5.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$gcd_ip = bless( {
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/Other/gcd.v',
+ '/mpsoc/src_peripheral/Other/gcd_ip.v'
+ ],
+ 'system_h' => ' #define ${IP}_DONE_ADDR (*((volatile unsigned int *) ($BASE )))
+ #define ${IP}_IN_1_ADDR (*((volatile unsigned int *) ($BASE+4)))
+ #define ${IP}_IN_2_ADDR (*((volatile unsigned int *) ($BASE+8)))
+ #define ${IP}_GCD_ADDR (*((volatile unsigned int *) ($BASE+12)))
+
+ #define ${IP}_IN1_WRITE(value) ${IP}_IN_1_ADDR=value
+ #define ${IP}_IN2_WRITE(value) ${IP}_IN_2_ADDR=value
+
+ #define ${IP}_DONE_READ() ${IP}_DONE_ADDR
+ #define ${IP}_GCD_READ() ${IP}_GCD_ADDR
+
+ unsigned int gcd_hardware ( unsigned int p, unsigned int q ){
+ ${IP}_IN1_WRITE(p) ;
+ ${IP}_IN2_WRITE(q) ;
+ while (${IP}_DONE_READ()!=1);
+ return ${IP}_GCD_READ();
+ }',
+ 'description' => 'Greatest Common Divisor hardware accelerator.',
+ 'ip_name' => 'gcd',
+ 'parameters' => {
+ 'GCDw' => {
+ 'info' => "GCD\x{2019}s Input/output width in bits",
+ 'default' => '32',
+ 'global_param' => 'Localparam',
+ 'content' => '8,16,32',
+ 'redefine_param' => 1,
+ 'type' => 'Combo-box'
+ },
+ 'Aw' => {
+ 'info' => 'Parameter',
+ 'default' => '2',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'TAGw' => {
+ 'info' => 'Parameter',
+ 'default' => '3',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'SELw' => {
+ 'info' => 'Parameter',
+ 'default' => '4',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Dw' => {
+ 'info' => 'Parameter',
+ 'default' => 'GCDw',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ }
+ },
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'plugs' => {
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ '0' => {
+ 'width' => 5,
+ 'name' => 'wb_slave',
+ 'addr' => '0xb800_0000 0xbfff_ffff custom devices'
+ },
+ 'type' => 'num',
+ 'wb_slave' => {}
+ }
+ },
+ 'modules' => {
+ 'gcd_ip' => {}
+ },
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 's_dat_i',
+ 's_sel_i',
+ 's_addr_i',
+ 's_tag_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 's_err_o',
+ 's_rty_o'
+ ],
+ 'parameters_order' => [
+ 'GCDw',
+ 'Dw',
+ 'Aw',
+ 'TAGw',
+ 'SELw'
+ ],
+ 'ports' => {
+ 's_sel_i' => {
+ 'intfc_port' => 'sel_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_err_o' => {
+ 'intfc_port' => 'err_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 's_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_cyc_i' => {
+ 'intfc_port' => 'cyc_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 's_we_i' => {
+ 'intfc_port' => 'we_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_stb_i' => {
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_tag_i' => {
+ 'intfc_port' => 'tag_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'input'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 's_rty_o' => {
+ 'intfc_port' => 'rty_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 's_addr_i' => {
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'input'
+ },
+ 's_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ }
+ },
+ 'file_name' => '/home/alireza/Mywork/mpsoc_doc/usermanual/tutorial2/gcd_ip.v',
+ 'module_name' => 'gcd_ip',
+ 'category' => 'Other',
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'cti_i',
+ 'bte_i'
+ ]
+ }
+ }, 'ip_gen' );
Other/gcd.IP.back
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Other/sim_uart.IP
===================================================================
--- Other/sim_uart.IP (revision 34)
+++ Other/sim_uart.IP (revision 38)
@@ -10,93 +10,177 @@
################################################################################
$simulator_UART = bless( {
+ 'module_name' => 'simulator_UART',
+ 'system_h' => '#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE)))
+
+void ${IP}_putchar(char ch){ //print one char from jtag_uart
+ ${IP}_DATA_REG=ch;
+}
+
+
+void ${IP}_putstring (char * buffer, char sz){
+ while (sz){
+ ${IP}_putchar(*buffer);
+ buffer++;
+ sz--;
+ }
+}
+',
+ 'description' => 'A simple uart that display input characters on simulator terminal using $write command.
+',
+ 'ports_order' => [
+ 'reset',
+ 'clk',
+ 's_dat_i',
+ 's_sel_i',
+ 's_addr_i',
+ 's_cti_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o'
+ ],
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/Other/simulator_UART.v',
- 'gui_status' => {
- 'status' => 'ideal',
- 'timeout' => 0
- },
- 'version' => 6,
+ 'version' => 7,
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'bte_i',
+ 'rty_o',
+ 'tag_i',
+ 'err_o'
+ ]
+ },
'modules' => {
'simulator_UART' => {}
},
+ 'parameters' => {
+ 'S_Aw' => {
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'info' => 'Parameter',
+ 'global_param' => 'Localparam',
+ 'redefine_param' => 1,
+ 'default' => ' 7'
+ },
+ 'M_Aw' => {
+ 'redefine_param' => 1,
+ 'info' => 'Parameter',
+ 'global_param' => 'Localparam',
+ 'default' => ' 32',
+ 'type' => 'Fixed',
+ 'content' => ''
+ },
+ 'BUFFER_SIZE' => {
+ 'default' => '100',
+ 'info' => 'Internal buffer size ',
+ 'global_param' => 'Localparam',
+ 'redefine_param' => 1,
+ 'content' => '2,1000,1',
+ 'type' => 'Spin-button'
+ },
+ 'Dw' => {
+ 'default' => ' 32',
+ 'redefine_param' => 1,
+ 'info' => 'Parameter',
+ 'global_param' => 'Localparam',
+ 'type' => 'Fixed',
+ 'content' => ''
+ },
+ 'WAIT_COUNT' => {
+ 'type' => 'Spin-button',
+ 'content' => '2,100000,1',
+ 'redefine_param' => 1,
+ 'info' => 'If internal buffer has a data, the internal module timer starts counting up in each clock cycle. If Timer reach the WAIT_COUNT value, it writes the buffer vakue on simulator terminal.',
+ 'global_param' => 'Localparam',
+ 'default' => '1000'
+ },
+ 'TAGw' => {
+ 'type' => 'Fixed',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'global_param' => 'Localparam',
+ 'info' => 'Parameter',
+ 'default' => ' 3'
+ },
+ 'SELw' => {
+ 'type' => 'Fixed',
+ 'content' => '',
+ 'default' => ' 4',
+ 'redefine_param' => 1,
+ 'global_param' => 'Localparam',
+ 'info' => 'Parameter'
+ }
+ },
+ 'category' => 'Other',
'ports' => {
- 's_stb_i' => {
+ 's_cti_i' => {
'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
- 'range' => '',
- 'type' => 'input'
- },
- 's_cyc_i' => {
'type' => 'input',
- 'range' => '',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'cyc_i'
+ 'intfc_port' => 'cti_i',
+ 'range' => 'TAGw-1 : 0'
},
's_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'SELw-1 : 0',
'intfc_port' => 'sel_i',
- 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'input'
+ },
+ 's_addr_i' => {
+ 'range' => 'S_Aw-1 : 0',
+ 'type' => 'input',
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 's_dat_o' => {
+ 'range' => 'Dw-1 : 0',
+ 'intfc_port' => 'dat_o',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'clk' => {
+ 'type' => 'input',
+ 'intfc_port' => 'clk_i',
+ 'range' => '',
+ 'intfc_name' => 'plug:clk[0]'
+ },
+ 's_we_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'we_i',
+ 'type' => 'input',
+ 'range' => ''
+ },
+ 's_dat_i' => {
+ 'intfc_port' => 'dat_i',
'type' => 'input',
- 'range' => 'SELw-1 : 0'
+ 'range' => 'Dw-1 : 0',
+ 'intfc_name' => 'plug:wb_slave[0]'
},
'reset' => {
+ 'type' => 'input',
+ 'intfc_port' => 'reset_i',
'range' => '',
- 'type' => 'input',
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i'
+ 'intfc_name' => 'plug:reset[0]'
},
- 's_cti_i' => {
- 'intfc_port' => 'cti_i',
- 'intfc_name' => 'plug:wb_slave[0]',
+ 's_stb_i' => {
'type' => 'input',
- 'range' => 'TAGw-1 : 0'
+ 'intfc_port' => 'stb_i',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]'
},
- 's_dat_i' => {
- 'intfc_port' => 'dat_i',
+ 's_cyc_i' => {
'intfc_name' => 'plug:wb_slave[0]',
- 'type' => 'input',
- 'range' => 'Dw-1 : 0'
+ 'range' => '',
+ 'intfc_port' => 'cyc_i',
+ 'type' => 'input'
},
's_ack_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
- 's_addr_i' => {
- 'intfc_port' => 'adr_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'type' => 'input',
- 'range' => 'S_Aw-1 : 0'
- },
- 's_dat_o' => {
- 'range' => 'Dw-1 : 0',
'type' => 'output',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o'
- },
- 's_we_i' => {
- 'intfc_port' => 'we_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'clk' => {
- 'intfc_port' => 'clk_i',
- 'intfc_name' => 'plug:clk[0]',
- 'range' => '',
- 'type' => 'input'
- }
+ 'range' => ''
+ }
},
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'tag_i',
- 'bte_i',
- 'rty_o',
- 'err_o'
- ]
- },
- 'description' => 'A simple uart that display input characters on simulator terminal using $write command.
-',
'parameters_order' => [
'Dw',
'S_Aw',
@@ -106,124 +190,40 @@
'BUFFER_SIZE',
'WAIT_COUNT'
],
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'ip_name' => 'sim_uart',
+ 'hdl_files' => [
+ '/mpsoc/src_peripheral/Other/simulator_UART.v'
+ ],
'plugs' => {
- 'reset' => {
- 'value' => 1,
- 'reset' => {},
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
'clk' => {
- 'type' => 'num',
'clk' => {},
'0' => {
'name' => 'clk'
},
- 'value' => 1
+ 'value' => 1,
+ 'type' => 'num'
},
'wb_slave' => {
- 'wb_slave' => {},
'type' => 'num',
+ 'value' => 1,
'0' => {
+ 'addr' => '0xa500_0000 0xa5ff_ffff Debug',
'width' => 1,
- 'name' => 'wb_slave',
- 'addr' => '0xa500_0000 0xa5ff_ffff Debug'
+ 'name' => 'wb_slave'
},
- 'value' => 1
- }
- },
- 'ip_name' => 'sim_uart',
- 'ports_order' => [
- 'reset',
- 'clk',
- 's_dat_i',
- 's_sel_i',
- 's_addr_i',
- 's_cti_i',
- 's_stb_i',
- 's_cyc_i',
- 's_we_i',
- 's_dat_o',
- 's_ack_o'
- ],
- 'hdl_files' => [
- '/mpsoc/src_peripheral/Other/simulator_UART.v'
- ],
- 'system_h' => '#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE)))
-
-void ${IP}_putchar(char ch){ //print one char from jtag_uart
- ${IP}_DATA_REG=ch;
-}
-
-
-void ${IP}_putstring (char * buffer, char sz){
- while (sz){
- ${IP}_putchar(*buffer);
- *buffer++;
- sz--;
- }
-}
-',
- 'category' => 'Other',
- 'parameters' => {
- 'SELw' => {
- 'content' => '',
- 'type' => 'Fixed',
- 'global_param' => 'Localparam',
- 'info' => 'Parameter',
- 'redefine_param' => 1,
- 'deafult' => ' 4'
- },
- 'S_Aw' => {
- 'deafult' => ' 7',
- 'redefine_param' => 1,
- 'info' => 'Parameter',
- 'content' => '',
- 'type' => 'Fixed',
- 'global_param' => 'Localparam'
- },
- 'M_Aw' => {
- 'redefine_param' => 1,
- 'global_param' => 'Localparam',
- 'type' => 'Fixed',
- 'content' => '',
- 'info' => 'Parameter',
- 'deafult' => ' 32'
- },
- 'WAIT_COUNT' => {
- 'deafult' => '1000',
- 'info' => 'If internal buffer has a data, the internal module timer starts counting up in each clock cycle. If Timer reach the WAIT_COUNT value, it writes the buffer vakue on simulator terminal.',
- 'global_param' => 'Localparam',
- 'type' => 'Spin-button',
- 'content' => '2,100000,1',
- 'redefine_param' => 1
- },
- 'Dw' => {
- 'redefine_param' => 1,
- 'content' => '',
- 'global_param' => 'Localparam',
- 'type' => 'Fixed',
- 'info' => 'Parameter',
- 'deafult' => ' 32'
- },
- 'BUFFER_SIZE' => {
- 'info' => 'Internal buffer size ',
- 'content' => '2,1000,1',
- 'global_param' => 'Localparam',
- 'type' => 'Spin-button',
- 'redefine_param' => 1,
- 'deafult' => '100'
- },
- 'TAGw' => {
- 'deafult' => ' 3',
- 'redefine_param' => 1,
- 'content' => '',
- 'type' => 'Fixed',
- 'global_param' => 'Localparam',
- 'info' => 'Parameter'
- }
- },
- 'module_name' => 'simulator_UART'
+ 'wb_slave' => {}
+ },
+ 'reset' => {
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'reset' => {}
+ }
+ }
}, 'ip_gen' );
/Processor/Altor.IP
File deleted
Processor/Altor.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: Processor/Or1200.IP
===================================================================
--- Processor/Or1200.IP (nonexistent)
+++ Processor/Or1200.IP (revision 38)
@@ -0,0 +1,567 @@
+#######################################################################
+## File: Or1200.IP
+##
+## Copyright (C) 2014-2016 Alireza Monemi
+##
+## This file is part of ProNoC 1.7.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$or1200 = bless( {
+ 'system_h' => ' #include "or1200/system.h"
+
+
+inline void nop (){
+ __asm__("l.nop 1");
+}',
+ 'category' => 'Processor',
+ 'sw_files' => [
+ '/mpsoc/src_processor/or1200/sw/Makefile',
+ '/mpsoc/src_processor/or1200/sw/or1200',
+ '/mpsoc/src_processor/or1200/sw/link.ld',
+ '/mpsoc/src_processor/or1200/sw/define_printf.h',
+ '/mpsoc/src_processor/src_lib/simple-printf'
+ ],
+ 'file_name' => '/home/alireza/mywork/mpsoc/src_processor/or1200/verilog/or1200.v',
+ 'hdl_files' => [
+ '/mpsoc/src_processor/or1200/verilog/or1200.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_alu.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_amultp2_32x32.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_cfgr.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_cpu.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_ctrl.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_dc_fsm.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_dc_ram.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_dc_tag.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_dc_top.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_tlb.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_top.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_dpram.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_32x32.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_256x32.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_du.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_except.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_addsub.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_arith.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_div.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_fcmp.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv_except.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_mul.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_addsub.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_div.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_intfloat_conv.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_mul.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_addsub.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_div.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_mul.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_freeze.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_genpc.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_gmultp2_32x32.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_ic_fsm.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_ic_ram.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_ic_tag.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_ic_top.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_if.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_immu_tlb.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_immu_top.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_iwb_biu.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_lsu.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_mem2reg.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_mult_mac.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_operandmuxes.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_pic.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_pm.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_qmem_top.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_reg2mem.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_rf.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_rfram_generic.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_sb.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_sb_fifo.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32_bw.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32x24.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x14.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x22.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x24.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_128x32.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_256x21.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_512x20.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x8.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32_bw.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x8.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32_bw.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_sprs.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_top.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_tpram_32x32.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_tt.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_wb_biu.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_wbmux.v',
+ '/mpsoc/src_processor/or1200/verilog/src/or1200_xcv_ram32x8d.v',
+ '/mpsoc/src_processor/or1200/verilog/src/timescale.v'
+ ],
+ 'ip_name' => 'Or1200',
+ 'plugs' => {
+ 'reset' => {
+ 'type' => 'num',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ }
+ },
+ 'enable' => {
+ '0' => {
+ 'name' => 'enable'
+ },
+ 'enable' => {},
+ 'value' => 1,
+ 'type' => 'num'
+ },
+ 'wb_master' => {
+ '0' => {
+ 'name' => 'iwb'
+ },
+ 'type' => 'num',
+ 'value' => 2,
+ '1' => {
+ 'name' => 'dwb'
+ }
+ },
+ 'clk' => {
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num',
+ 'value' => 1
+ }
+ },
+ 'ports' => {
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'type' => 'input'
+ },
+ 'dwb_sel_o' => {
+ 'type' => 'output',
+ 'range' => '3:0',
+ 'intfc_port' => 'sel_o',
+ 'intfc_name' => 'plug:wb_master[1]'
+ },
+ 'dwb_cti_o' => {
+ 'intfc_port' => 'cti_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'type' => 'output',
+ 'range' => '2:0'
+ },
+ 'dwb_bte_o' => {
+ 'type' => 'output',
+ 'range' => '1:0',
+ 'intfc_port' => 'bte_o',
+ 'intfc_name' => 'plug:wb_master[1]'
+ },
+ 'iwb_cyc_o' => {
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'output',
+ 'range' => ''
+ },
+ 'dwb_adr_o' => {
+ 'intfc_port' => 'adr_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => 'aw-1:0',
+ 'type' => 'output'
+ },
+ 'iwb_err_i' => {
+ 'intfc_port' => 'err_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'dwb_we_o' => {
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'we_o'
+ },
+ 'dwb_rty_i' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'rty_i',
+ 'type' => 'input',
+ 'range' => ''
+ },
+ 'dwb_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'type' => 'output',
+ 'range' => 'dw-1:0'
+ },
+ 'iwb_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'output',
+ 'range' => 'dw-1:0'
+ },
+ 'iwb_rty_i' => {
+ 'intfc_port' => 'rty_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'input',
+ 'range' => ''
+ },
+ 'iwb_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'sel_o',
+ 'type' => 'output',
+ 'range' => '3:0'
+ },
+ 'clk' => {
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]'
+ },
+ 'en_i' => {
+ 'intfc_port' => 'enable_i',
+ 'intfc_name' => 'plug:enable[0]',
+ 'type' => 'input',
+ 'range' => ''
+ },
+ 'dwb_cyc_o' => {
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_port' => 'cyc_o',
+ 'intfc_name' => 'plug:wb_master[1]'
+ },
+ 'iwb_dat_i' => {
+ 'range' => 'dw-1:0',
+ 'type' => 'input',
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'iwb_stb_o' => {
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'stb_o'
+ },
+ 'dwb_ack_i' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'ack_i'
+ },
+ 'dwb_dat_i' => {
+ 'type' => 'input',
+ 'range' => 'dw-1:0',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'dat_i'
+ },
+ 'iwb_cti_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cti_o',
+ 'type' => 'output',
+ 'range' => '2:0'
+ },
+ 'iwb_we_o' => {
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'iwb_adr_o' => {
+ 'range' => 'aw-1:0',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'adr_o'
+ },
+ 'dwb_err_i' => {
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'err_i',
+ 'intfc_name' => 'plug:wb_master[1]'
+ },
+ 'iwb_bte_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'bte_o',
+ 'type' => 'output',
+ 'range' => '1:0'
+ },
+ 'dwb_stb_o' => {
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'type' => 'output',
+ 'range' => ''
+ },
+ 'iwb_ack_i' => {
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'pic_ints_i' => {
+ 'intfc_port' => 'int_i',
+ 'intfc_name' => 'socket:interrupt_peripheral[array]',
+ 'range' => 'ppic_ints-1:0',
+ 'type' => 'input'
+ }
+ },
+ 'parameters_order' => [
+ 'dw',
+ 'aw',
+ 'ppic_ints',
+ 'boot_adr',
+ 'Data_cashe_size',
+ 'Instruction_cashe_size',
+ 'Data_cashe_enable',
+ 'Instruction_cashe_enable',
+ 'Data_MMU_enable',
+ 'Instruction_MMU_enable',
+ 'implementation_addc',
+ 'implement_sub',
+ 'implement_cy',
+ 'implement_0v',
+ 'implement_OVE',
+ 'implement_alu_rotate',
+ 'implement_alu_compare',
+ 'implement_alu_ext',
+ 'multiplier_type',
+ 'divider_type'
+ ],
+ 'unused' => {
+ 'plug:wb_master[1]' => [
+ 'tag_o'
+ ],
+ 'plug:wb_master[0]' => [
+ 'tag_o'
+ ]
+ },
+ 'parameters' => {
+ 'implement_0v' => {
+ 'content' => '0V,NO_0V',
+ 'redefine_param' => 0,
+ 'global_param' => 'Don\'t include',
+ 'info' => 'Implement carry bit SR[OV]
+Compiler doesn\'t use this, but other code may like to.',
+ 'default' => '0V',
+ 'type' => 'Combo-box'
+ },
+ 'implement_alu_ext' => {
+ 'global_param' => 'Don\'t include',
+ 'content' => 'EXT,NO_EXT',
+ 'redefine_param' => 0,
+ 'type' => 'Combo-box',
+ 'info' => 'Implement l.extXs and l.extXz instructions',
+ 'default' => 'NO_EXT'
+ },
+ 'Data_MMU_enable' => {
+ 'content' => 'NO,YES',
+ 'redefine_param' => 0,
+ 'global_param' => 'Don\'t include',
+ 'default' => 'YES',
+ 'info' => undef,
+ 'type' => 'Combo-box'
+ },
+ 'aw' => {
+ 'type' => 'Fixed',
+ 'info' => 'Parameter',
+ 'default' => '32',
+ 'global_param' => 'Parameter',
+ 'content' => '',
+ 'redefine_param' => 1
+ },
+ 'Data_cashe_enable' => {
+ 'info' => undef,
+ 'default' => 'YES',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 0,
+ 'content' => 'NO,YES',
+ 'global_param' => 'Don\'t include'
+ },
+ 'implement_OVE' => {
+ 'redefine_param' => 0,
+ 'content' => 'OVE,NO_OVE',
+ 'global_param' => 'Don\'t include',
+ 'info' => 'Implement carry bit SR[OVE]
+Overflow interrupt indicator. When enabled, SR[OV] flag does not remain asserted after exception.',
+ 'default' => 'NO_OVE',
+ 'type' => 'Combo-box'
+ },
+ 'implementation_addc' => {
+ 'global_param' => 'Don\'t include',
+ 'content' => 'ADDC,NO_ADDC',
+ 'redefine_param' => 0,
+ 'type' => 'Combo-box',
+ 'default' => 'ADDC',
+ 'info' => 'Implement l.addc/l.addic instructions
+By default implementation of l.addc/l.addic instructions is enabled in case you need them.
+If you don\'t use them, then disable implementation to save area.'
+ },
+ 'implement_sub' => {
+ 'type' => 'Combo-box',
+ 'default' => 'SUB',
+ 'info' => 'Implement l.sub instruction
+By default implementation of l.sub instructions is enabled to be compliant with the simulator.
+If you don\'t use carry bit, then disable implementation to save area.',
+ 'global_param' => 'Don\'t include',
+ 'content' => 'SUB,NO_SUB',
+ 'redefine_param' => 0
+ },
+ 'divider_type' => {
+ 'type' => 'Combo-box',
+ 'default' => 'SERIAL',
+ 'info' => undef,
+ 'global_param' => 'Don\'t include',
+ 'redefine_param' => 0,
+ 'content' => 'SERIAL,PARALLEL'
+ },
+ 'Instruction_MMU_enable' => {
+ 'global_param' => 'Don\'t include',
+ 'content' => 'NO,YES',
+ 'redefine_param' => 0,
+ 'type' => 'Combo-box',
+ 'default' => 'YES',
+ 'info' => undef
+ },
+ 'implement_alu_rotate' => {
+ 'global_param' => 'Don\'t include',
+ 'redefine_param' => 0,
+ 'content' => 'ROTATE,NO_ROTATE',
+ 'type' => 'Combo-box',
+ 'info' => 'Implement rotate in the ALU
+At the time of writing this, or32 C/C++ compiler doesn\'t generate rotate instructions. However or32 assembler can assemble code that uses rotate insn.
+This means that rotate instructions must be used manually inserted.
+By default implementation of rotate is disabled to save area and increase is disabled to save area and increase clock frequency.',
+ 'default' => 'ROTATE'
+ },
+ 'multiplier_type' => {
+ 'global_param' => 'Don\'t include',
+ 'redefine_param' => 0,
+ 'content' => 'SERIAL,PARALLEL',
+ 'type' => 'Combo-box',
+ 'info' => undef,
+ 'default' => 'SERIAL'
+ },
+ 'boot_adr' => {
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'global_param' => 'Parameter',
+ 'info' => 'Parameter',
+ 'default' => '32\'h00000100',
+ 'type' => 'Fixed'
+ },
+ 'Instruction_cashe_enable' => {
+ 'global_param' => 'Don\'t include',
+ 'redefine_param' => 0,
+ 'content' => 'NO,YES',
+ 'type' => 'Combo-box',
+ 'info' => undef,
+ 'default' => 'YES'
+ },
+ 'ppic_ints' => {
+ 'content' => '3,31,1',
+ 'redefine_param' => 1,
+ 'global_param' => 'Parameter',
+ 'info' => 'Number of interrupts',
+ 'default' => '20',
+ 'type' => 'Spin-button'
+ },
+ 'Data_cashe_size' => {
+ 'content' => '512,4K,8K,16K,32K',
+ 'redefine_param' => 0,
+ 'global_param' => 'Don\'t include',
+ 'info' => 'Data Cashe Size in B',
+ 'default' => '8K',
+ 'type' => 'Combo-box'
+ },
+ 'Instruction_cashe_size' => {
+ 'default' => '8K',
+ 'info' => 'Instruction Cashe Size in B',
+ 'type' => 'Combo-box',
+ 'content' => '512,4K,8K,16K,32K',
+ 'redefine_param' => 0,
+ 'global_param' => 'Don\'t include'
+ },
+ 'implement_alu_compare' => {
+ 'global_param' => 'Don\'t include',
+ 'redefine_param' => 0,
+ 'content' => '1,2,3',
+ 'type' => 'Combo-box',
+ 'default' => '2',
+ 'info' => 'Type of ALU compare to implement
+Try to find which synthesizes with most efficient logic use or highest speed.'
+ },
+ 'dw' => {
+ 'default' => '32',
+ 'info' => 'Parameter',
+ 'type' => 'Fixed',
+ 'redefine_param' => 1,
+ 'content' => '',
+ 'global_param' => 'Parameter'
+ },
+ 'implement_cy' => {
+ 'type' => 'Combo-box',
+ 'info' => 'Implement carry bit SR[CY]
+By default implementation of SR[CY] is enabled to be compliant with the simulator. However SR[CY] is explicitly only used by l.addc/l.addic/l.sub instructions and if these three insns are not implemented there is not much point having SR[CY].',
+ 'default' => 'CY',
+ 'global_param' => 'Don\'t include',
+ 'redefine_param' => 0,
+ 'content' => 'CY,NO_CY'
+ }
+ },
+ 'modules' => {
+ 'or1200' => {}
+ },
+ 'sockets' => {
+ 'interrupt_peripheral' => {
+ 'type' => 'param',
+ 'value' => 'ppic_ints',
+ 'connection_num' => 'single connection',
+ '0' => {
+ 'name' => 'interrupt'
+ }
+ }
+ },
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 'en_i',
+ 'pic_ints_i',
+ 'iwb_ack_i',
+ 'iwb_err_i',
+ 'iwb_rty_i',
+ 'iwb_dat_i',
+ 'iwb_cyc_o',
+ 'iwb_adr_o',
+ 'iwb_stb_o',
+ 'iwb_we_o',
+ 'iwb_sel_o',
+ 'iwb_dat_o',
+ 'iwb_cti_o',
+ 'iwb_bte_o',
+ 'dwb_ack_i',
+ 'dwb_err_i',
+ 'dwb_rty_i',
+ 'dwb_dat_i',
+ 'dwb_cyc_o',
+ 'dwb_adr_o',
+ 'dwb_stb_o',
+ 'dwb_we_o',
+ 'dwb_sel_o',
+ 'dwb_dat_o',
+ 'dwb_cti_o',
+ 'dwb_bte_o'
+ ],
+ 'module_name' => 'or1200',
+ 'gen_hw_files' => [
+ '/mpsoc/src_processor/or1200/verilog/or1200_definesfrename_sep_tlib/or1200_defines.v'
+ ],
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'version' => 32
+ }, 'ip_gen' );
Index: Processor/aeMB.IP
===================================================================
--- Processor/aeMB.IP (revision 34)
+++ Processor/aeMB.IP (revision 38)
@@ -3,418 +3,422 @@
##
## Copyright (C) 2014-2016 Alireza Monemi
##
-## This file is part of ProNoC 1.5.0
+## This file is part of ProNoC 1.7.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
-$aeMB_top = bless( {
- 'hdl_files' => [
- '/mpsoc/src_processor/aeMB/verilog/aemb.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_core.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_xecu.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_sim.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_bpcu.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_edk32.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_xslif.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_ctrl.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_ibuf.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_tpsram.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB_regf.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_exec.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_sparam.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_intu.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_regs.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_spsram.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_memif.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_mult.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_gprf.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_pipe.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_brcc.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_dparam.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_edk63.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_bsft.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_ctrl.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_dwbif.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_edk62.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_sim.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iche.v',
- '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iwbif.v'
+$ipgen = bless( {
+ 'unused' => undef,
+ 'parameters' => {
+ 'AEMB_DWB' => {
+ 'redefine_param' => 1,
+ 'info' => undef,
+ 'default' => ' 32',
+ 'content' => '',
+ 'global_param' => 'Localparam',
+ 'type' => 'Fixed'
+ },
+ 'AEMB_BSF' => {
+ 'default' => ' 1',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'info' => undef,
+ 'global_param' => 'Localparam',
+ 'type' => 'Fixed'
+ },
+ 'AEMB_IWB' => {
+ 'global_param' => 'Localparam',
+ 'type' => 'Fixed',
+ 'content' => '',
+ 'default' => ' 32',
+ 'redefine_param' => 1,
+ 'info' => undef
+ },
+ 'AEMB_XWB' => {
+ 'type' => 'Fixed',
+ 'global_param' => 'Localparam',
+ 'content' => '',
+ 'default' => ' 7',
+ 'info' => undef,
+ 'redefine_param' => 1
+ },
+ 'HEAP_SIZE' => {
+ 'info' => undef,
+ 'redefine_param' => 0,
+ 'content' => '',
+ 'default' => '0x400',
+ 'type' => 'Entry',
+ 'global_param' => 'Don\'t include'
+ },
+ 'AEMB_MUL' => {
+ 'default' => ' 1',
+ 'content' => '',
+ 'info' => undef,
+ 'redefine_param' => 1,
+ 'type' => 'Fixed',
+ 'global_param' => 'Localparam'
+ },
+ 'AEMB_IDX' => {
+ 'info' => undef,
+ 'redefine_param' => 1,
+ 'default' => ' 6',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'global_param' => 'Localparam'
+ },
+ 'AEMB_ICH' => {
+ 'global_param' => 'Localparam',
+ 'type' => 'Fixed',
+ 'content' => '',
+ 'default' => ' 11',
+ 'redefine_param' => 1,
+ 'info' => undef
+ },
+ 'STACK_SIZE' => {
+ 'type' => 'Entry',
+ 'global_param' => 'Don\'t include',
+ 'default' => '0x400',
+ 'content' => '',
+ 'info' => 'The stack size in hex',
+ 'redefine_param' => 0
+ }
+ },
+ 'hdl_files' => [
+ '/mpsoc/src_processor/aeMB/verilog/aemb.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_core.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_xecu.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_sim.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_bpcu.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_edk32.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_xslif.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_ctrl.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_ibuf.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_tpsram.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB_regf.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_exec.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_sparam.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_intu.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_regs.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_spsram.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_memif.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_mult.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_gprf.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_pipe.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_brcc.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_dparam.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_edk63.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_bsft.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_ctrl.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_dwbif.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_edk62.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_sim.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iche.v',
+ '/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iwbif.v'
+ ],
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/aeMB/verilog/aemb.v',
+ 'module_name' => 'aeMB_top',
+ 'sockets' => {
+ 'interrupt_cpu' => {
+ 'connection_num' => 'single connection',
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'interrupt_cpu'
+ },
+ 'value' => 1
+ }
+ },
+ 'version' => 2,
+ 'description' => 'AEMB 32-bit Microprocessor Core
+For more information check http://opencores.org/project,aemb',
+ 'gen_sw_files' => [
+ '/mpsoc/src_processor/aeMB/sw/compile/gccromfrename_sep_tcompile/gccrom',
+ '/mpsoc/src_processor/aeMB/sw/Makefilefrename_sep_tMakefile'
],
- 'system_h' => ' #include
+ 'plugs' => {
+ 'enable' => {
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'enable'
+ },
+ 'value' => 1,
+ 'enable' => {}
+ },
+ 'clk' => {
+ 'clk' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num'
+ },
+ 'wb_master' => {
+ 'wb_master' => {},
+ '1' => {
+ 'name' => 'dwb'
+ },
+ 'value' => 2,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'iwb'
+ }
+ },
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num',
+ 'value' => 1
+ }
+ },
+ 'ports' => {
+ 'iwb_tag_o' => {
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'tag_o',
+ 'range' => '2:0'
+ },
+ 'iwb_adr_o' => {
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'adr_o',
+ 'range' => '31:0'
+ },
+ 'clk' => {
+ 'range' => '',
+ 'intfc_port' => 'clk_i',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:clk[0]'
+ },
+ 'dwb_rty_i' => {
+ 'type' => 'input',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'rty_i',
+ 'range' => ''
+ },
+ 'dwb_stb_o' => {
+ 'range' => '',
+ 'intfc_port' => 'stb_o',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[1]'
+ },
+ 'dwb_wre_o' => {
+ 'range' => '',
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'type' => 'output'
+ },
+ 'iwb_stb_o' => {
+ 'range' => '',
+ 'intfc_port' => 'stb_o',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'type' => 'input',
+ 'intfc_port' => 'reset_i',
+ 'range' => ''
+ },
+ 'dwb_bte_o' => {
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'bte_o',
+ 'range' => '1:0'
+ },
+ 'dwb_dat_i' => {
+ 'range' => '31:0',
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'type' => 'input'
+ },
+ 'dwb_dat_o' => {
+ 'range' => '31:0',
+ 'intfc_port' => 'dat_o',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[1]'
+ },
+ 'iwb_rty_i' => {
+ 'range' => '',
+ 'intfc_port' => 'rty_i',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'iwb_cyc_o' => {
+ 'intfc_port' => 'cyc_o',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'output'
+ },
+ 'dwb_cyc_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_port' => 'cyc_o'
+ },
+ 'dwb_sel_o' => {
+ 'intfc_port' => 'sel_o',
+ 'range' => '3:0',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[1]'
+ },
+ 'sys_int_i' => {
+ 'intfc_port' => 'int_i',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_name' => 'socket:interrupt_cpu[0]'
+ },
+ 'iwb_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'range' => '31:0',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'input'
+ },
+ 'dwb_err_i' => {
+ 'intfc_port' => 'err_i',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:wb_master[1]'
+ },
+ 'iwb_sel_o' => {
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'sel_o',
+ 'range' => '3:0'
+ },
+ 'iwb_wre_o' => {
+ 'intfc_port' => 'we_o',
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'dwb_adr_o' => {
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'type' => 'output',
+ 'intfc_port' => 'adr_o',
+ 'range' => '31:0'
+ },
+ 'iwb_cti_o' => {
+ 'range' => '2:0',
+ 'intfc_port' => 'cti_o',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'iwb_err_i' => {
+ 'intfc_port' => 'err_i',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'input'
+ },
+ 'dwb_tag_o' => {
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'intfc_port' => 'tag_o',
+ 'range' => '2:0'
+ },
+ 'sys_ena_i' => {
+ 'intfc_name' => 'plug:enable[0]',
+ 'type' => 'input',
+ 'intfc_port' => 'enable_i',
+ 'range' => ''
+ },
+ 'dwb_ack_i' => {
+ 'range' => '',
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'type' => 'input'
+ },
+ 'iwb_bte_o' => {
+ 'range' => '1:0',
+ 'intfc_port' => 'bte_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'output'
+ },
+ 'iwb_dat_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'output',
+ 'intfc_port' => 'dat_o',
+ 'range' => '31:0'
+ },
+ 'dwb_cti_o' => {
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[1]',
+ 'range' => '2:0',
+ 'intfc_port' => 'cti_o'
+ },
+ 'iwb_ack_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'input',
+ 'intfc_port' => 'ack_i',
+ 'range' => ''
+ }
+ },
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'modules' => {
+ 'aeMB_top' => {}
+ },
+ 'ip_name' => 'aeMB',
+ 'system_h' => ' #include
#include
#include "aemb/core.hh"
- #define printf xil_printf
+
inline void nop (void) {
asm volatile ("nop");
}',
- 'ip_name' => 'aeMB',
- 'parameters_order' => [
- 'AEMB_IWB',
- 'AEMB_DWB',
- 'AEMB_XWB',
- 'AEMB_ICH',
- 'AEMB_IDX',
- 'AEMB_BSF',
- 'AEMB_MUL',
- 'STACK_SIZE',
- 'HEAP_SIZE'
- ],
- 'ports_order' => [
- 'dwb_adr_o',
- 'dwb_cyc_o',
- 'dwb_dat_o',
- 'dwb_sel_o',
- 'dwb_stb_o',
- 'dwb_tag_o',
- 'dwb_wre_o',
- 'dwb_cti_o',
- 'dwb_bte_o',
- 'dwb_ack_i',
- 'dwb_dat_i',
- 'dwb_err_i',
- 'dwb_rty_i',
- 'iwb_adr_o',
- 'iwb_cyc_o',
- 'iwb_sel_o',
- 'iwb_stb_o',
- 'iwb_tag_o',
- 'iwb_wre_o',
- 'iwb_dat_o',
- 'iwb_cti_o',
- 'iwb_bte_o',
- 'iwb_ack_i',
- 'iwb_dat_i',
- 'iwb_err_i',
- 'iwb_rty_i',
- 'clk',
- 'reset',
- 'sys_int_i',
- 'sys_ena_i'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/aeMB/verilog/aemb.v',
- 'module_name' => 'aeMB_top',
- 'gen_sw_files' => [
- '/mpsoc/src_processor/aeMB/sw/compile/gccromfrename_sep_tcompile/gccrom',
- '/mpsoc/src_processor/aeMB/sw/Makefilefrename_sep_tMakefile'
- ],
- 'unused' => undef,
- 'category' => 'Processor',
- 'sw_files' => [
- '/mpsoc/src_processor/aeMB/sw/aemb',
- '/mpsoc/src_processor/aeMB/sw/compile',
- '/mpsoc/src_processor/aeMB/sw/program',
- '/mpsoc/src_processor/program.sh'
+ 'ports_order' => [
+ 'dwb_adr_o',
+ 'dwb_cyc_o',
+ 'dwb_dat_o',
+ 'dwb_sel_o',
+ 'dwb_stb_o',
+ 'dwb_tag_o',
+ 'dwb_wre_o',
+ 'dwb_cti_o',
+ 'dwb_bte_o',
+ 'dwb_ack_i',
+ 'dwb_dat_i',
+ 'dwb_err_i',
+ 'dwb_rty_i',
+ 'iwb_adr_o',
+ 'iwb_cyc_o',
+ 'iwb_sel_o',
+ 'iwb_stb_o',
+ 'iwb_tag_o',
+ 'iwb_wre_o',
+ 'iwb_dat_o',
+ 'iwb_cti_o',
+ 'iwb_bte_o',
+ 'iwb_ack_i',
+ 'iwb_dat_i',
+ 'iwb_err_i',
+ 'iwb_rty_i',
+ 'clk',
+ 'reset',
+ 'sys_int_i',
+ 'sys_ena_i'
],
- 'description' => 'AEMB 32-bit Microprocessor Core
-For more information check http://opencores.org/project,aemb',
- 'gui_status' => {
- 'status' => 'ideal',
- 'timeout' => 0
- },
- 'modules' => {
- 'aeMB_top' => {}
- },
- 'plugs' => {
- 'interrupt_cpu' => {
- 'interrupt_cpu' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'intrp'
- },
- 'type' => 'num'
- },
- 'wb_master' => {
- 'wb_master' => {},
- '1' => {
- 'name' => 'dwb'
- },
- 'value' => 2,
- '0' => {
- 'name' => 'iwb'
- },
- 'type' => 'num'
- },
- 'enable' => {
- 'enable' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'enable'
- },
- 'type' => 'num'
- },
- 'clk' => {
- 'clk' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- }
- },
- 'parameters' => {
- 'STACK_SIZE' => {
- 'info' => 'The stack size in hex',
- 'deafult' => '0x400',
- 'global_param' => 'Don\'t include',
- 'content' => '',
- 'type' => 'Entry',
- 'redefine_param' => 0
- },
- 'HEAP_SIZE' => {
- 'info' => undef,
- 'deafult' => '0x400',
- 'global_param' => 'Don\'t include',
- 'content' => '',
- 'redefine_param' => 0,
- 'type' => 'Entry'
- },
- 'AEMB_IWB' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => 'Localparam',
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_BSF' => {
- 'info' => undef,
- 'deafult' => ' 1',
- 'global_param' => 'Localparam',
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_ICH' => {
- 'info' => undef,
- 'deafult' => ' 11',
- 'global_param' => 'Localparam',
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_DWB' => {
- 'info' => undef,
- 'deafult' => ' 32',
- 'global_param' => 'Localparam',
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_XWB' => {
- 'info' => undef,
- 'deafult' => ' 7',
- 'global_param' => 'Localparam',
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_IDX' => {
- 'info' => undef,
- 'deafult' => ' 6',
- 'global_param' => 'Localparam',
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'AEMB_MUL' => {
- 'info' => undef,
- 'deafult' => ' 1',
- 'global_param' => 'Localparam',
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- }
- },
- 'ports' => {
- 'iwb_err_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'err_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'dwb_ack_i' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'ack_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'iwb_cyc_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'cyc_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'iwb_dat_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'dat_o',
- 'range' => '31:0',
- 'type' => 'output'
- },
- 'dwb_wre_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'we_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'dwb_cyc_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'cyc_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'dwb_stb_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'stb_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'iwb_adr_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'adr_o',
- 'range' => '31:0',
- 'type' => 'output'
- },
- 'iwb_bte_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'bte_o',
- 'range' => '1:0',
- 'type' => 'output'
- },
- 'reset' => {
- 'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'iwb_rty_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'rty_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'sys_int_i' => {
- 'intfc_name' => 'plug:interrupt_cpu[0]',
- 'intfc_port' => 'int_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'dwb_err_i' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'err_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'iwb_tag_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'tag_o',
- 'range' => '2:0',
- 'type' => 'output'
- },
- 'iwb_ack_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'ack_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'iwb_sel_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'sel_o',
- 'range' => '3:0',
- 'type' => 'output'
- },
- 'dwb_tag_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'tag_o',
- 'range' => '2:0',
- 'type' => 'output'
- },
- 'dwb_adr_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'adr_o',
- 'range' => '31:0',
- 'type' => 'output'
- },
- 'dwb_bte_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'bte_o',
- 'range' => '1:0',
- 'type' => 'output'
- },
- 'dwb_dat_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'dat_o',
- 'range' => '31:0',
- 'type' => 'output'
- },
- 'dwb_cti_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'cti_o',
- 'range' => '2:0',
- 'type' => 'output'
- },
- 'iwb_cti_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'cti_o',
- 'range' => '2:0',
- 'type' => 'output'
- },
- 'iwb_stb_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'stb_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'dwb_rty_i' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'rty_i',
- 'range' => '',
- 'type' => 'input'
- },
- 'dwb_dat_i' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'dat_i',
- 'range' => '31:0',
- 'type' => 'input'
- },
- 'iwb_dat_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'dat_i',
- 'range' => '31:0',
- 'type' => 'input'
- },
- 'dwb_sel_o' => {
- 'intfc_name' => 'plug:wb_master[1]',
- 'intfc_port' => 'sel_o',
- 'range' => '3:0',
- 'type' => 'output'
- },
- 'iwb_wre_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'we_o',
- 'range' => '',
- 'type' => 'output'
- },
- 'sys_ena_i' => {
- 'intfc_name' => 'plug:enable[0]',
- 'intfc_port' => 'enable_i',
- 'range' => '',
- 'type' => 'input'
- }
- }
- }, 'ip_gen' );
+ 'category' => 'Processor',
+ 'sw_files' => [
+ '/mpsoc/src_processor/aeMB/sw/aemb',
+ '/mpsoc/src_processor/aeMB/sw/compile',
+ '/mpsoc/src_processor/aeMB/sw/program',
+ '/mpsoc/src_processor/program.sh',
+ '/mpsoc/src_processor/aeMB/sw/define_printf.h'
+ ],
+ 'parameters_order' => [
+ 'AEMB_IWB',
+ 'AEMB_DWB',
+ 'AEMB_XWB',
+ 'AEMB_ICH',
+ 'AEMB_IDX',
+ 'AEMB_BSF',
+ 'AEMB_MUL',
+ 'STACK_SIZE',
+ 'HEAP_SIZE'
+ ]
+ }, 'ip_gen' );
/Processor/lm32.IP
3,7 → 3,7
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## This file is part of ProNoC 1.7.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
41,70 → 41,18
'/mpsoc/src_processor/lm32/verilog/src/typea.v', |
'/mpsoc/src_processor/lm32/verilog/src/typeb.v' |
], |
'system_h' => '#include "lm32_system.h" |
inline void nop (void) { |
asm volatile ("nop"); |
}', |
'ip_name' => 'lm32', |
'parameters_order' => [ |
'INTR_NUM', |
'CFG_PL_MULTIPLY', |
'CFG_PL_BARREL_SHIFT', |
'CFG_SIGN_EXTEND', |
'CFG_MC_DIVIDE' |
], |
'ports_order' => [ |
'clk_i', |
'rst_i', |
'en_i', |
'interrupt', |
'I_DAT_I', |
'I_ACK_I', |
'I_ERR_I', |
'I_RTY_I', |
'I_DAT_O', |
'I_ADR_O', |
'I_CYC_O', |
'I_SEL_O', |
'I_STB_O', |
'I_WE_O', |
'I_CTI_O', |
'I_BTE_O', |
'D_DAT_I', |
'D_ACK_I', |
'D_ERR_I', |
'D_RTY_I', |
'D_DAT_O', |
'D_ADR_O', |
'D_CYC_O', |
'D_SEL_O', |
'D_STB_O', |
'D_WE_O', |
'D_CTI_O', |
'D_BTE_O' |
], |
'category' => 'Processor', |
'sockets' => { |
'interrupt_peripheral' => { |
'type' => 'param', |
'interrupt_peripheral' => {}, |
'connection_num' => 'single connection', |
'value' => 'INTR_NUM', |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'type' => 'param' |
'value' => 'INTR_NUM', |
'connection_num' => 'single connection' |
} |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v', |
'module_name' => 'lm32', |
'unused' => { |
'plug:wb_master[1]' => [ |
'tag_o' |
], |
'plug:wb_master[0]' => [ |
'tag_o' |
] |
}, |
'category' => 'Processor', |
'sw_files' => [ |
'/mpsoc/src_processor/lm32/sw/crt0ram.S', |
'/mpsoc/src_processor/lm32/sw/linker.ld', |
111,268 → 59,323
'/mpsoc/src_processor/lm32/sw/lm32_system.h', |
'/mpsoc/src_processor/lm32/sw/Makefile', |
'/mpsoc/src_processor/lm32/sw/program', |
'/mpsoc/src_processor/program.sh' |
'/mpsoc/src_processor/program.sh', |
'/mpsoc/src_processor/lm32/sw/define_printf.h', |
'/mpsoc/src_processor/src_lib/simple-printf' |
], |
'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement. |
|
for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'unused' => { |
'plug:wb_master[0]' => [ |
'tag_o' |
], |
'plug:wb_master[1]' => [ |
'tag_o' |
] |
}, |
'module_name' => 'lm32', |
'parameters_order' => [ |
'INTR_NUM', |
'CFG_PL_MULTIPLY', |
'CFG_PL_BARREL_SHIFT', |
'CFG_SIGN_EXTEND', |
'CFG_MC_DIVIDE' |
], |
'system_h' => '#include "lm32_system.h" |
inline void nop (void) { |
asm volatile ("nop"); |
}', |
'modules' => { |
'lm32' => {} |
}, |
'ip_name' => 'lm32', |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'1' => { |
'name' => 'dwb' |
}, |
'value' => 2, |
'0' => { |
'name' => 'iwb' |
}, |
'type' => 'num' |
}, |
'enable' => { |
'enable' => {}, |
'0' => { |
'name' => 'enable' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'reset' => {}, |
'1' => { |
'name' => 'reset_1' |
}, |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
'value' => 1 |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
} |
'type' => 'num', |
'clk' => {}, |
'value' => 1 |
}, |
'enable' => { |
'enable' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'enable' |
}, |
'value' => 1 |
}, |
'wb_master' => { |
'1' => { |
'name' => 'dwb' |
}, |
'value' => 2, |
'0' => { |
'name' => 'iwb' |
}, |
'type' => 'num', |
'wb_master' => {} |
} |
}, |
'modules' => { |
'lm32' => {} |
}, |
'parameters' => { |
'CFG_PL_BARREL_SHIFT' => { |
'info' => undef, |
'deafult' => '"ENABLED"', |
'global_param' => 0, |
'content' => '"ENABLED","DISABLED"', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'CFG_SIGN_EXTEND' => { |
'info' => undef, |
'deafult' => '"ENABLED"', |
'global_param' => 0, |
'content' => '"ENABLED","DISABLED"', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'CFG_PL_MULTIPLY' => { |
'info' => undef, |
'deafult' => '"ENABLED"', |
'global_param' => 0, |
'content' => '"ENABLED","DISABLED"', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'INTR_NUM' => { |
'info' => undef, |
'deafult' => '32', |
'global_param' => 0, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'CFG_MC_DIVIDE' => { |
'info' => undef, |
'deafult' => '"DISABLED"', |
'global_param' => 0, |
'content' => '"ENABLED","DISABLED"', |
'redefine_param' => 1, |
'type' => 'Fixed' |
} |
}, |
'ports' => { |
'I_SEL_O' => { |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(4-1):0', |
'type' => 'output' |
'interrupt' => { |
'intfc_port' => 'int_i', |
'type' => 'input', |
'range' => '(32-1):0', |
'intfc_name' => 'socket:interrupt_peripheral[array]' |
}, |
'D_ACK_I' => { |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'I_DAT_I' => { |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(32-1):0', |
'D_RTY_I' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'rty_i', |
'range' => '', |
'type' => 'input' |
}, |
'I_CTI_O' => { |
'intfc_port' => 'cti_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => '(3-1):0', |
'type' => 'output' |
'intfc_port' => 'cti_o' |
}, |
'D_WE_O' => { |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '', |
'type' => 'output' |
}, |
'I_ERR_I' => { |
'intfc_port' => 'err_i', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'input' |
'I_DAT_O' => { |
'type' => 'output', |
'range' => '(32-1):0', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'D_ADR_O' => { |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[1]', |
'I_DAT_I' => { |
'type' => 'input', |
'range' => '(32-1):0', |
'type' => 'output' |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'D_CTI_O' => { |
'intfc_port' => 'cti_o', |
'D_ADR_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '(3-1):0', |
'type' => 'output' |
'intfc_port' => 'adr_o', |
'type' => 'output', |
'range' => '(32-1):0' |
}, |
'D_STB_O' => { |
'intfc_port' => 'stb_o', |
'intfc_name' => 'plug:wb_master[1]', |
'I_ACK_I' => { |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'range' => '', |
'type' => 'output' |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'en_i' => { |
'intfc_port' => 'enable_i', |
'intfc_name' => 'plug:enable[0]', |
'range' => '', |
'type' => 'input' |
}, |
'I_CYC_O' => { |
'intfc_port' => 'cyc_o', |
'I_BTE_O' => { |
'intfc_port' => 'bte_o', |
'type' => 'output', |
'range' => '(2-1):0', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'I_RTY_I' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output' |
'type' => 'input', |
'intfc_port' => 'rty_i' |
}, |
'D_DAT_I' => { |
'intfc_port' => 'dat_i', |
'clk_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]' |
}, |
'D_CTI_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '(32-1):0', |
'type' => 'input' |
'range' => '(3-1):0', |
'type' => 'output', |
'intfc_port' => 'cti_o' |
}, |
'D_ACK_I' => { |
'intfc_port' => 'ack_i', |
'D_DAT_I' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '', |
'type' => 'input' |
}, |
'D_DAT_O' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input', |
'range' => '(32-1):0', |
'type' => 'output' |
'intfc_port' => 'dat_i' |
}, |
'I_ADR_O' => { |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(32-1):0', |
'type' => 'output' |
}, |
'I_WE_O' => { |
'D_WE_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output' |
}, |
'I_BTE_O' => { |
'intfc_port' => 'bte_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(2-1):0', |
'type' => 'output' |
}, |
'rst_i' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'range' => '', |
'type' => 'input' |
'intfc_port' => 'reset_i' |
}, |
'interrupt' => { |
'intfc_port' => 'int_i', |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'range' => '(32-1):0', |
'type' => 'input' |
}, |
'en_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'enable_i', |
'intfc_name' => 'plug:enable[0]' |
}, |
'D_BTE_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'bte_o', |
'type' => 'output', |
'range' => '(2-1):0' |
}, |
'I_SEL_O' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(4-1):0', |
'type' => 'output', |
'intfc_port' => 'sel_o' |
}, |
'D_DAT_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '(2-1):0', |
'type' => 'output' |
'type' => 'output', |
'range' => '(32-1):0', |
'intfc_port' => 'dat_o' |
}, |
'D_CYC_O' => { |
'intfc_port' => 'cyc_o', |
'D_ERR_I' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'err_i', |
'range' => '', |
'type' => 'output' |
'type' => 'input' |
}, |
'I_STB_O' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'stb_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output' |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'D_SEL_O' => { |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '(4-1):0', |
'type' => 'output' |
}, |
'I_DAT_O' => { |
'intfc_port' => 'dat_o', |
'I_WE_O' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'we_o', |
'range' => '', |
'type' => 'output' |
}, |
'I_ADR_O' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => '(32-1):0', |
'type' => 'output' |
'intfc_port' => 'adr_o' |
}, |
'D_ERR_I' => { |
'intfc_port' => 'err_i', |
'intfc_name' => 'plug:wb_master[1]', |
'I_ERR_I' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input', |
'range' => '', |
'type' => 'input' |
'intfc_port' => 'err_i' |
}, |
'D_RTY_I' => { |
'intfc_port' => 'rty_i', |
'D_STB_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'stb_o', |
'range' => '', |
'type' => 'input' |
'type' => 'output' |
}, |
'I_ACK_I' => { |
'intfc_port' => 'ack_i', |
'intfc_name' => 'plug:wb_master[0]', |
'D_CYC_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'cyc_o', |
'range' => '', |
'type' => 'input' |
'type' => 'output' |
}, |
'I_RTY_I' => { |
'intfc_port' => 'rty_i', |
'D_SEL_O' => { |
'range' => '(4-1):0', |
'type' => 'output', |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'I_CYC_O' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'input' |
}, |
'clk_i' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
} |
} |
'intfc_port' => 'cyc_o', |
'type' => 'output', |
'range' => '' |
} |
}, |
'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement. |
|
for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx', |
'ports_order' => [ |
'clk_i', |
'rst_i', |
'en_i', |
'interrupt', |
'I_DAT_I', |
'I_ACK_I', |
'I_ERR_I', |
'I_RTY_I', |
'I_DAT_O', |
'I_ADR_O', |
'I_CYC_O', |
'I_SEL_O', |
'I_STB_O', |
'I_WE_O', |
'I_CTI_O', |
'I_BTE_O', |
'D_DAT_I', |
'D_ACK_I', |
'D_ERR_I', |
'D_RTY_I', |
'D_DAT_O', |
'D_ADR_O', |
'D_CYC_O', |
'D_SEL_O', |
'D_STB_O', |
'D_WE_O', |
'D_CTI_O', |
'D_BTE_O' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v', |
'version' => 2, |
'parameters' => { |
'CFG_MC_DIVIDE' => { |
'global_param' => 0, |
'content' => '"ENABLED","DISABLED"', |
'info' => undef, |
'redefine_param' => 1, |
'default' => '"DISABLED"', |
'type' => 'Fixed' |
}, |
'INTR_NUM' => { |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'content' => '', |
'global_param' => 0 |
}, |
'CFG_SIGN_EXTEND' => { |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'redefine_param' => 1, |
'info' => undef, |
'content' => '"ENABLED","DISABLED"', |
'global_param' => 0 |
}, |
'CFG_PL_MULTIPLY' => { |
'content' => '"ENABLED","DISABLED"', |
'global_param' => 0, |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"' |
}, |
'CFG_PL_BARREL_SHIFT' => { |
'content' => '"ENABLED","DISABLED"', |
'global_param' => 0, |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'redefine_param' => 1, |
'info' => undef |
} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
} |
}, 'ip_gen' ); |
/Processor/mor1kx.IP
0,0 → 1,378
####################################################################### |
## File: mor1kx.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ipgen = bless( { |
'parameters_order' => [ |
'OPTION_OPERAND_WIDTH', |
'IRQ_NUM' |
], |
'sockets' => { |
'interrupt_peripheral' => { |
'value' => 'IRQ_NUM', |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'connection_num' => 'single connection', |
'type' => 'param' |
} |
}, |
'ports' => { |
'dwbm_dat_i' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '31:0', |
'intfc_port' => 'dat_i', |
'type' => 'input' |
}, |
'dwbm_cyc_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '', |
'intfc_port' => 'cyc_o', |
'type' => 'output' |
}, |
'iwbm_rty_i' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'rty_i', |
'type' => 'input' |
}, |
'iwbm_adr_o' => { |
'intfc_port' => 'adr_o', |
'type' => 'output', |
'range' => '31:0', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'iwbm_dat_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '31:0', |
'type' => 'input', |
'intfc_port' => 'dat_i' |
}, |
'rst' => { |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'intfc_port' => 'reset_i' |
}, |
'irq_i' => { |
'type' => 'input', |
'intfc_port' => 'int_i', |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'range' => '31:0' |
}, |
'iwbm_bte_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '1:0', |
'type' => 'output', |
'intfc_port' => 'bte_o' |
}, |
'dwbm_ack_i' => { |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '' |
}, |
'iwbm_dat_o' => { |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '31:0' |
}, |
'iwbm_cyc_o' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'cyc_o' |
}, |
'iwbm_we_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'we_o' |
}, |
'dwbm_rty_i' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'rty_i' |
}, |
'dwbm_cti_o' => { |
'intfc_port' => 'cti_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '2:0' |
}, |
'dwbm_adr_o' => { |
'intfc_port' => 'adr_o', |
'type' => 'output', |
'range' => '31:0', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'dwbm_err_i' => { |
'type' => 'input', |
'intfc_port' => 'err_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'clk_i' |
}, |
'iwbm_ack_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'ack_i' |
}, |
'dwbm_dat_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '31:0', |
'type' => 'output', |
'intfc_port' => 'dat_o' |
}, |
'iwbm_sel_o' => { |
'range' => '3:0', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'sel_o', |
'type' => 'output' |
}, |
'dwbm_stb_o' => { |
'type' => 'output', |
'intfc_port' => 'stb_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '' |
}, |
'cpu_en' => { |
'range' => '', |
'intfc_name' => 'plug:enable[0]', |
'type' => 'input', |
'intfc_port' => 'enable_i' |
}, |
'dwbm_we_o' => { |
'type' => 'output', |
'intfc_port' => 'we_o', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'iwbm_err_i' => { |
'intfc_port' => 'err_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'iwbm_cti_o' => { |
'intfc_port' => 'cti_o', |
'type' => 'output', |
'range' => '2:0', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'dwbm_sel_o' => { |
'intfc_port' => 'sel_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '3:0' |
}, |
'iwbm_stb_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'stb_o' |
}, |
'dwbm_bte_o' => { |
'type' => 'output', |
'intfc_port' => 'bte_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '1:0' |
} |
}, |
'unused' => { |
'plug:wb_master[1]' => [ |
'tag_o' |
], |
'plug:wb_master[0]' => [ |
'tag_o' |
] |
}, |
'modules' => { |
'mor1k' => {} |
}, |
'parameters' => { |
'IRQ_NUM' => { |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => '32', |
'global_param' => 'Parameter', |
'info' => undef |
}, |
'OPTION_OPERAND_WIDTH' => { |
'redefine_param' => 1, |
'content' => '', |
'info' => 'Parameter', |
'default' => '32', |
'global_param' => 'Parameter', |
'type' => 'Fixed' |
} |
}, |
'category' => 'Processor', |
'plugs' => { |
'reset' => { |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1 |
}, |
'enable' => { |
'value' => 1, |
'0' => { |
'name' => 'enable' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'clk' |
} |
}, |
'wb_master' => { |
'1' => { |
'name' => 'dwb' |
}, |
'0' => { |
'name' => 'iwb' |
}, |
'value' => 2, |
'type' => 'num' |
} |
}, |
'ports_order' => [ |
'clk', |
'rst', |
'cpu_en', |
'iwbm_adr_o', |
'iwbm_stb_o', |
'iwbm_cyc_o', |
'iwbm_sel_o', |
'iwbm_we_o', |
'iwbm_cti_o', |
'iwbm_bte_o', |
'iwbm_dat_o', |
'iwbm_err_i', |
'iwbm_ack_i', |
'iwbm_dat_i', |
'iwbm_rty_i', |
'dwbm_adr_o', |
'dwbm_stb_o', |
'dwbm_cyc_o', |
'dwbm_sel_o', |
'dwbm_we_o', |
'dwbm_cti_o', |
'dwbm_bte_o', |
'dwbm_dat_o', |
'dwbm_err_i', |
'dwbm_ack_i', |
'dwbm_dat_i', |
'dwbm_rty_i', |
'irq_i' |
], |
'ip_name' => 'mor1kx', |
'module_name' => 'mor1k', |
'version' => 13, |
'hdl_files' => [ |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_branch_prediction.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_avalon.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_wb32.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cache_lru.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cfgrs.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dcache.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode_execute_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-defines.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dmmu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_alu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_icache.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_immu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_pic.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_simple_dpram_sclk.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-sprs.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_store_buffer.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ticktimer.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_true_dpram_sclk.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_utils.vh', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v' |
], |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'system_h' => ' #include "mor1kx/system.h" |
|
inline void nop (){ |
__asm__("l.nop 1"); |
} |
/********************* |
//Interrupt template: check mor1kx/int.c for more information |
// interrupt function |
void hw_isr(void){ |
//place your interrupt code here |
|
|
HW_ISR=HW_ISR; //ack the interrupt at the end of isr function |
return; |
} |
|
int main(){ |
|
int_init(); |
//assume hw interrupt pin is connected to 10th cpu intrrupt pin |
int_add(10, hw_isr, 0); |
// Enable this interrupt |
int_enable(10); |
cpu_enable_user_interrupts(); |
hw_init ( ); // hw interrupt enable function |
while(1){ |
//place rest of the code |
|
} |
} |
*******************************/', |
'sw_files' => [ |
'/mpsoc/src_processor/mor1kx-3.1/sw/link.ld', |
'/mpsoc/src_processor/mor1kx-3.1/sw/Makefile', |
'/mpsoc/src_processor/mor1kx-3.1/sw/mor1kx', |
'/mpsoc/src_processor/src_lib/simple-printf', |
'/mpsoc/src_processor/mor1kx-3.1/sw/define_printf.h' |
], |
'file_name' => '/home/alireza/mywork/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v' |
}, 'ip_gen' ); |
/RAM/dual_port_ram.IP
3,247 → 3,192
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.6.0 |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$wb_dual_port_ram = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ram/generic_ram.v', |
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv', |
'/mpsoc/src_peripheral/ram/wb_dual_port_ram.v', |
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v' |
], |
'module_name' => 'wb_dual_port_ram', |
'category' => 'RAM', |
'plugs' => { |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
} |
$ipgen = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ram/generic_ram.v', |
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv', |
'/mpsoc/src_peripheral/ram/wb_dual_port_ram.v', |
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v' |
], |
'ports_order' => [ |
'clk', |
'reset', |
'sa_dat_i', |
'sa_sel_i', |
'sa_addr_i', |
'sa_tag_i', |
'sa_cti_i', |
'sa_bte_i', |
'sa_stb_i', |
'sa_cyc_i', |
'sa_we_i', |
'sa_dat_o', |
'sa_ack_o', |
'sa_err_o', |
'sa_rty_o', |
'sb_dat_i', |
'sb_sel_i', |
'sb_addr_i', |
'sb_tag_i', |
'sb_cti_i', |
'sb_bte_i', |
'sb_stb_i', |
'sb_cyc_i', |
'sb_we_i', |
'sb_dat_o', |
'sb_ack_o', |
'sb_err_o', |
'sb_rty_o' |
], |
'parameters_order' => [ |
'Dw', |
'Aw', |
'BYTE_WR_EN', |
'FPGA_VENDOR', |
'TAGw', |
'SELw', |
'CTIw', |
'BTEw', |
'WB_Aw', |
'RAM_INDEX', |
'PORT_A_BURST_MODE', |
'PORT_B_BURST_MODE', |
'INITIAL_EN', |
'MEM_CONTENT_FILE_NAME', |
'INIT_FILE_PATH' |
], |
'category' => 'RAM', |
'plugs' => { |
'reset' => { |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'value' => 1, |
'reset' => {} |
}, |
'wb_slave' => { |
'value' => 2, |
'1' => { |
'addr' => '0x0000_0000 0x3fff_ffff RAM', |
'width' => 'WB_Aw', |
'name' => 'wb_b' |
}, |
'type' => 'num', |
'wb_slave' => {}, |
'0' => { |
'addr' => '0x0000_0000 0x3fff_ffff RAM', |
'width' => 'WB_Aw', |
'name' => 'wb_a' |
} |
} |
'type' => 'num', |
'reset' => {} |
}, |
'clk' => { |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
}, |
'clk' => {}, |
'value' => 1 |
}, |
'ports' => { |
'sb_err_o' => { |
'range' => '', |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'output' |
}, |
'sa_stb_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '' |
}, |
'sb_addr_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0' |
}, |
'sb_rty_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[1]', |
'intfc_port' => 'rty_o', |
'range' => '' |
}, |
'sb_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
'sb_we_i' => { |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input' |
}, |
'sb_dat_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i' |
}, |
'sa_err_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'err_o' |
}, |
'sb_sel_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i' |
}, |
'sb_ack_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => '', |
'intfc_port' => 'ack_o' |
}, |
'sb_cti_i' => { |
'intfc_port' => 'cti_i', |
'range' => 'CTIw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sb_stb_i' => { |
'intfc_port' => 'stb_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input' |
}, |
'sa_cti_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cti_i', |
'range' => 'CTIw-1 : 0' |
}, |
'sb_bte_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => 'BTEw-1 : 0', |
'intfc_port' => 'bte_i' |
}, |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'rty_o' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]' |
'wb_slave' => { |
'type' => 'num', |
'0' => { |
'addr' => '0x0000_0000 0x3fff_ffff RAM', |
'width' => 'WB_Aw', |
'name' => 'wb_a' |
}, |
'1' => { |
'name' => 'wb_b', |
'width' => 'WB_Aw', |
'addr' => '0x0000_0000 0x3fff_ffff RAM' |
}, |
'wb_slave' => {}, |
'value' => 2 |
} |
}, |
'modules' => { |
'wb_dual_port_ram' => {} |
}, |
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf', |
'version' => 10, |
'description' => 'Dual port ram.', |
'ip_name' => 'dual_port_ram', |
'module_name' => 'wb_dual_port_ram', |
'unused' => undef, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_dual_port_ram.v', |
'parameters' => { |
'RAM_INDEX' => { |
'global_param' => 'Localparam', |
'type' => 'Entry', |
'content' => '', |
'default' => 'CORE_ID', |
'redefine_param' => 1, |
'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only. |
|
' |
}, |
'sa_dat_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o' |
}, |
'sa_dat_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0' |
}, |
'sa_bte_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'bte_i', |
'range' => 'BTEw-1 : 0' |
}, |
'sa_ack_o' => { |
'range' => '', |
'intfc_port' => 'ack_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_sel_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'reset_i' |
'SELw' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'default' => 'Dw/8', |
'global_param' => 'Localparam' |
}, |
'BYTE_WR_EN' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'type' => 'Combo-box', |
'content' => '"YES","NO"', |
'default' => '"YES"', |
'global_param' => 'Localparam' |
}, |
'INITIAL_EN' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'If selected as "YES", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', |
'default' => '"NO"', |
'content' => '"YES","NO"', |
'type' => 'Combo-box' |
}, |
'CTIw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'default' => '3', |
'type' => 'Fixed', |
'content' => '' |
}, |
'Dw' => { |
'redefine_param' => 1, |
'info' => 'Ram data width in Bits', |
'type' => 'Spin-button', |
'default' => '32', |
'content' => '4,1024,1', |
'global_param' => 'Localparam' |
}, |
'FPGA_VENDOR' => { |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'redefine_param' => 1, |
'default' => '"GENERIC"', |
'type' => 'Combo-box', |
'content' => '"ALTERA","GENERIC"' |
}, |
'sa_cyc_i' => { |
'range' => '', |
'intfc_port' => 'cyc_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
'INIT_FILE_PATH' => { |
'global_param' => 'Don\'t include', |
'content' => '', |
'default' => 'SW_LOC', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => undef |
}, |
'sa_tag_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0' |
}, |
'sb_dat_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sb_tag_i' => { |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
} |
}, |
'description' => 'Dual port ram.', |
'parameters' => { |
'WB_Aw' => { |
'type' => 'Fixed', |
'redefine_param' => 0, |
'info' => 'Wishbone bus address width in byte', |
'content' => '', |
'deafult' => 'Aw+2', |
'global_param' => 'Don\'t include' |
}, |
'BTEw' => { |
'info' => 'Parameter', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'deafult' => '2' |
}, |
'MEM_CONTENT_FILE_NAME' => { |
'type' => 'Entry', |
'redefine_param' => 1, |
'content' => '', |
'info' => 'MEM_FILE_NAME: |
'PORT_A_BURST_MODE' => { |
'info' => ' wisbone bus burst mode enable/disable on port A', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'default' => '"ENABLED"', |
'content' => '"DISABLED","ENABLED"', |
'global_param' => 'Localparam' |
}, |
'MEM_CONTENT_FILE_NAME' => { |
'global_param' => 'Localparam', |
'content' => '', |
'default' => '"ram0"', |
'type' => 'Entry', |
'redefine_param' => 1, |
'info' => 'MEM_FILE_NAME: |
The memory file name (without file type extension ) that is used for writting the memory content at initialization time. |
|
File Path: |
252,165 → 197,221
|
file_type: |
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command. |
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ', |
'deafult' => '"ram0"', |
'global_param' => 'Localparam' |
}, |
'TAGw' => { |
'info' => 'Parameter', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'deafult' => '3' |
}, |
'CTIw' => { |
'redefine_param' => 1, |
'type' => 'Fixed', |
'content' => '', |
'info' => 'Parameter', |
'deafult' => '3', |
'global_param' => 'Localparam' |
}, |
'INIT_FILE_PATH' => { |
'redefine_param' => 1, |
'type' => 'Fixed', |
'info' => undef, |
'content' => '', |
'deafult' => 'SW_LOC', |
'global_param' => 'Don\'t include' |
}, |
'Aw' => { |
'deafult' => '12', |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'info' => 'Ram address width', |
'content' => '2,31,1' |
}, |
'INITIAL_EN' => { |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'info' => 'If selected as "YES", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', |
'content' => '"YES","NO"', |
'deafult' => '"NO"', |
'global_param' => 'Localparam' |
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ' |
}, |
'RAM_INDEX' => { |
'deafult' => 'CORE_ID', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Entry', |
'content' => '', |
'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only. |
|
' |
}, |
'SELw' => { |
'deafult' => 'Dw/8', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'info' => 'Parameter', |
'content' => '' |
}, |
'Dw' => { |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '4,1024,1', |
'info' => 'Ram data width in Bits', |
'deafult' => '32', |
'global_param' => 'Localparam' |
}, |
'PORT_B_BURST_MODE' => { |
'info' => 'wisbone bus burst mode ebable/disable on port B', |
'content' => '"DISABLED","ENABLED" ', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'deafult' => '"ENABLED"' |
}, |
'BYTE_WR_EN' => { |
'content' => '"YES","NO"', |
'info' => 'Parameter', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'deafult' => '"YES"' |
}, |
'PORT_A_BURST_MODE' => { |
'deafult' => '"ENABLED"', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'content' => '"DISABLED","ENABLED"', |
'info' => ' wisbone bus burst mode enable/disable on port A' |
}, |
'FPGA_VENDOR' => { |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'content' => '"ALTERA","GENERIC"', |
'info' => 'Parameter', |
'deafult' => '"GENERIC"', |
'global_param' => 'Localparam' |
} |
'TAGw' => { |
'content' => '', |
'type' => 'Fixed', |
'default' => '3', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'global_param' => 'Localparam' |
}, |
'BTEw' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'default' => '2', |
'content' => '', |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'Aw' => { |
'info' => 'Ram address width', |
'redefine_param' => 1, |
'default' => '12', |
'content' => '2,31,1', |
'type' => 'Spin-button', |
'global_param' => 'Localparam' |
}, |
'PORT_B_BURST_MODE' => { |
'redefine_param' => 1, |
'info' => 'wisbone bus burst mode ebable/disable on port B', |
'type' => 'Combo-box', |
'content' => '"DISABLED","ENABLED"', |
'default' => '"ENABLED"', |
'global_param' => 'Localparam' |
}, |
'WB_Aw' => { |
'info' => 'Wishbone bus address width in byte', |
'redefine_param' => 0, |
'content' => '', |
'default' => 'Aw+2', |
'type' => 'Fixed', |
'global_param' => 'Don\'t include' |
} |
}, |
'ports' => { |
'reset' => { |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'range' => '', |
'intfc_name' => 'plug:reset[0]' |
}, |
'sb_we_i' => { |
'type' => 'input', |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sb_err_o' => { |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'ports_order' => [ |
'clk', |
'reset', |
'sa_dat_i', |
'sa_sel_i', |
'sa_addr_i', |
'sa_tag_i', |
'sa_cti_i', |
'sa_bte_i', |
'sa_stb_i', |
'sa_cyc_i', |
'sa_we_i', |
'sa_dat_o', |
'sa_ack_o', |
'sa_err_o', |
'sa_rty_o', |
'sb_dat_i', |
'sb_sel_i', |
'sb_addr_i', |
'sb_tag_i', |
'sb_cti_i', |
'sb_bte_i', |
'sb_stb_i', |
'sb_cyc_i', |
'sb_we_i', |
'sb_dat_o', |
'sb_ack_o', |
'sb_err_o', |
'sb_rty_o' |
], |
'version' => 6, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'rty_o', |
'range' => '' |
}, |
'parameters_order' => [ |
'Dw', |
'Aw', |
'BYTE_WR_EN', |
'FPGA_VENDOR', |
'TAGw', |
'SELw', |
'CTIw', |
'BTEw', |
'WB_Aw', |
'RAM_INDEX', |
'PORT_A_BURST_MODE', |
'PORT_B_BURST_MODE', |
'INITIAL_EN', |
'MEM_CONTENT_FILE_NAME', |
'INIT_FILE_PATH' |
], |
'unused' => undef, |
'ip_name' => 'dual_port_ram', |
'modules' => { |
'wb_dual_port_ram' => {} |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_dual_port_ram.v' |
}, 'ip_gen' ); |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sb_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sa_stb_i' => { |
'range' => '', |
'intfc_port' => 'stb_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_tag_i' => { |
'type' => 'input', |
'range' => 'TAGw-1 : 0', |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_dat_i' => { |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'we_i' |
}, |
'sb_bte_i' => { |
'type' => 'input', |
'range' => 'BTEw-1 : 0', |
'intfc_port' => 'bte_i', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sb_addr_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input', |
'range' => 'Aw-1 : 0', |
'intfc_port' => 'adr_i' |
}, |
'sb_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'cyc_i' |
}, |
'sa_sel_i' => { |
'type' => 'input', |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sb_sel_i' => { |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sb_dat_i' => { |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sb_cti_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input', |
'range' => 'CTIw-1 : 0', |
'intfc_port' => 'cti_i' |
}, |
'sb_ack_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sa_cti_i' => { |
'type' => 'input', |
'range' => 'CTIw-1 : 0', |
'intfc_port' => 'cti_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_err_o' => { |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sb_tag_i' => { |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sb_stb_i' => { |
'type' => 'input', |
'intfc_port' => 'stb_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sa_bte_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'bte_i', |
'range' => 'BTEw-1 : 0' |
}, |
'sa_cyc_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sb_rty_o' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'output', |
'intfc_port' => 'rty_o', |
'range' => '' |
} |
}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
} |
}, 'ip_gen' ); |
/RAM/single_port_ram.IP
3,94 → 3,77
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.6.0 |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$wb_single_port_ram = bless( { |
'modules' => { |
'wb_single_port_ram' => {} |
$ipgen = bless( { |
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf', |
'unused' => undef, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'modules' => { |
'wb_single_port_ram' => {} |
}, |
'parameters' => { |
'Aw' => { |
'global_param' => 'Parameter', |
'info' => 'Memory address width', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'default' => '12', |
'content' => '4,31,1' |
}, |
'module_name' => 'wb_single_port_ram', |
'version' => 19, |
'category' => 'RAM', |
'description' => 'Single port ram with wishbone bus interface.', |
'plugs' => { |
'reset' => { |
'value' => 1, |
'reset' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
} |
}, |
'wb_slave' => { |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'wb', |
'width' => 'WB_Aw', |
'addr' => '0x0000_0000 0x3fff_ffff RAM' |
}, |
'wb_slave' => {} |
}, |
'clk' => { |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'clk' => {} |
} |
}, |
'unused' => undef, |
'ip_name' => 'single_port_ram', |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ram/wb_single_port_ram.v', |
'/mpsoc/src_peripheral/ram/generic_ram.v', |
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv', |
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v' |
], |
'parameters_order' => [ |
'Dw', |
'Aw', |
'BYTE_WR_EN', |
'FPGA_VENDOR', |
'JTAG_CONNECT', |
'JTAG_INDEX', |
'TAGw', |
'SELw', |
'CTIw', |
'BTEw', |
'WB_Aw', |
'BURST_MODE', |
'MEM_CONTENT_FILE_NAME', |
'INITIAL_EN', |
'INIT_FILE_PATH' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
'INITIAL_EN' => { |
'content' => '"YES","NO"', |
'redefine_param' => 1, |
'default' => '"NO"', |
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', |
'type' => 'Combo-box', |
'global_param' => 'Localparam' |
}, |
'WB_Aw' => { |
'global_param' => 'Don\'t include', |
'info' => undef, |
'type' => 'Fixed', |
'redefine_param' => 1, |
'default' => 'Aw+2', |
'content' => '' |
}, |
'parameters' => { |
'SELw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'content' => '', |
'deafult' => 'Dw/8', |
'info' => 'Parameter' |
}, |
|
'MEM_CONTENT_FILE_NAME' => { |
'type' => 'Entry', |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => 'MEM_FILE_NAME: |
'BYTE_WR_EN' => { |
'info' => 'Byte enable', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => '"YES","NO"', |
'default' => '"YES"' |
}, |
'TAGw' => { |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'content' => '', |
'default' => '3', |
'redefine_param' => 1 |
}, |
'FPGA_VENDOR' => { |
'content' => '"ALTERA","GENERIC"', |
'redefine_param' => 1, |
'default' => '"GENERIC"', |
'info' => '', |
'type' => 'Combo-box', |
'global_param' => 'Localparam' |
}, |
'MEM_CONTENT_FILE_NAME' => { |
'default' => '"ram0"', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Entry', |
'info' => 'MEM_FILE_NAME: |
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time. |
|
File Path: |
101,229 → 84,244
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime. |
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command. |
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ', |
'deafult' => '"ram0"' |
}, |
'JTAG_CONNECT' => { |
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'deafult' => '"DISABLED"', |
'info' => 'JTAG_CONNECT: |
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ' |
}, |
'WB_Aw' => { |
'deafult' => 'Aw+2', |
'info' => undef, |
'global_param' => 'Don\'t include', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'content' => '' |
}, |
|
'JTAG_INDEX' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => '', |
'type' => 'Entry', |
'deafult' => 'CORE_ID', |
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory. |
'global_param' => 'Localparam' |
}, |
'Dw' => { |
'content' => '8,1024,1', |
'redefine_param' => 1, |
'default' => '32', |
'global_param' => 'Parameter', |
'info' => 'Memory data width in Bits.', |
'type' => 'Spin-button' |
}, |
'JTAG_INDEX' => { |
'content' => '', |
'default' => 'CORE_ID', |
'redefine_param' => 1, |
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory. |
|
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1). |
|
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units). |
|
' |
}, |
'Aw' => { |
'info' => 'Memory address width', |
'deafult' => '12', |
'content' => '4,31,1', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'global_param' => 'Parameter' |
}, |
'TAGw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'deafult' => '3' |
}, |
'BTEw' => { |
'deafult' => '2', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'FPGA_VENDOR' => { |
'type' => 'Combo-box', |
'content' => '"ALTERA","GENERIC"', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => '', |
'deafult' => '"GENERIC"' |
}, |
'CTIw' => { |
'type' => 'Fixed', |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'deafult' => '3' |
}, |
'Dw' => { |
'type' => 'Spin-button', |
'content' => '8,1024,1', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'info' => 'Memory data width in Bits.', |
'deafult' => '32' |
}, |
'INIT_FILE_PATH' => { |
'info' => undef, |
'deafult' => 'SW_LOC', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'content' => '' |
}, |
|
'INITIAL_EN' => { |
'deafult' => '"NO"', |
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => '"YES","NO"', |
'type' => 'Combo-box' |
}, |
'BURST_MODE' => { |
'deafult' => '"ENABLED"', |
'info' => 'Wishbone bus burst read/write mode enable/disable. ', |
'type' => 'Combo-box', |
'content' => '"DISABLED","ENABLED"', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'BYTE_WR_EN' => { |
'info' => '', |
'deafult' => '"YES"', |
'type' => 'Combo-box', |
'content' => '"YES","NO"', |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
} |
}, |
'ports_order' => [ |
'clk', |
'reset', |
'sa_dat_i', |
'sa_sel_i', |
'sa_addr_i', |
'sa_tag_i', |
'sa_cti_i', |
'sa_bte_i', |
'sa_stb_i', |
'sa_cyc_i', |
'sa_we_i', |
'sa_dat_o', |
'sa_ack_o', |
'sa_err_o', |
'sa_rty_o' |
], |
'ports' => { |
'sa_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => '' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => 'Aw-1 : 0' |
}, |
'sa_tag_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'tag_i', |
'type' => 'input', |
'range' => 'TAGw-1 : 0' |
}, |
'sa_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
}, |
'sa_stb_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i' |
}, |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'sa_sel_i' => { |
'type' => 'input', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i' |
}, |
'sa_cti_i' => { |
'range' => 'CTIw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'cti_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'range' => '' |
}, |
'sa_bte_i' => { |
'intfc_port' => 'bte_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'BTEw-1 : 0', |
'type' => 'input' |
}, |
'reset' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]' |
}, |
'sa_err_o' => { |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
} |
} |
}, 'ip_gen' ); |
', |
'type' => 'Entry', |
'global_param' => 'Localparam' |
}, |
'CTIw' => { |
'content' => '', |
'redefine_param' => 1, |
'default' => '3', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'info' => 'Parameter' |
}, |
'SELw' => { |
'content' => '', |
'redefine_param' => 1, |
'default' => 'Dw/8', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'BURST_MODE' => { |
'default' => '"ENABLED"', |
'content' => '"DISABLED","ENABLED"', |
'redefine_param' => 1, |
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ', |
'type' => 'Combo-box', |
'global_param' => 'Localparam' |
}, |
'BTEw' => { |
'redefine_param' => 1, |
'default' => '2', |
'content' => '', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'global_param' => 'Localparam' |
}, |
'INIT_FILE_PATH' => { |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'content' => '', |
'default' => 'SW_LOC', |
'redefine_param' => 1 |
}, |
'JTAG_CONNECT' => { |
'type' => 'Combo-box', |
'info' => 'JTAG_CONNECT: |
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ', |
'global_param' => 'Localparam', |
'default' => '"DISABLED"', |
'redefine_param' => 1, |
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"' |
} |
}, |
'version' => 22, |
'ports' => { |
'reset' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]' |
}, |
'sa_bte_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'bte_i', |
'type' => 'input', |
'range' => 'BTEw-1 : 0' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_sel_i' => { |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
'sa_err_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o' |
}, |
'sa_tag_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'tag_i', |
'type' => 'input', |
'range' => 'TAGw-1 : 0' |
}, |
'sa_dat_i' => { |
'type' => 'input', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'type' => 'input', |
'range' => '' |
}, |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_cti_i' => { |
'range' => 'CTIw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cti_i' |
}, |
'sa_we_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => 'Dw-1 : 0' |
}, |
'clk' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i' |
}, |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
} |
}, |
'parameters_order' => [ |
'Dw', |
'Aw', |
'BYTE_WR_EN', |
'FPGA_VENDOR', |
'JTAG_CONNECT', |
'JTAG_INDEX', |
'TAGw', |
'SELw', |
'CTIw', |
'BTEw', |
'WB_Aw', |
'BURST_MODE', |
'MEM_CONTENT_FILE_NAME', |
'INITIAL_EN', |
'INIT_FILE_PATH' |
], |
'plugs' => { |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'value' => 1, |
'reset' => {} |
}, |
'wb_slave' => { |
'type' => 'num', |
'0' => { |
'name' => 'wb', |
'addr' => '0x0000_0000 0x3fff_ffff RAM', |
'width' => 'WB_Aw' |
}, |
'wb_slave' => {}, |
'value' => 1 |
}, |
'clk' => { |
'value' => 1, |
'clk' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
} |
} |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ram/wb_single_port_ram.v', |
'/mpsoc/src_peripheral/ram/generic_ram.v', |
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv', |
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v' |
], |
'ip_name' => 'single_port_ram', |
'ports_order' => [ |
'clk', |
'reset', |
'sa_dat_i', |
'sa_sel_i', |
'sa_addr_i', |
'sa_tag_i', |
'sa_cti_i', |
'sa_bte_i', |
'sa_stb_i', |
'sa_cyc_i', |
'sa_we_i', |
'sa_dat_o', |
'sa_ack_o', |
'sa_err_o', |
'sa_rty_o' |
], |
'module_name' => 'wb_single_port_ram', |
'description' => 'Single port ram with wishbone bus interface.', |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v', |
'category' => 'RAM' |
}, 'ip_gen' ); |
/Timer/timer.IP
3,7 → 3,7
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## This file is part of ProNoC 1.7.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
10,79 → 10,124
################################################################################ |
|
$timer = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/timer/timer.v' |
], |
'system_h' => '#define ${IP}_TCSR0 (*((volatile unsigned int *) ($BASE ))) |
'system_h' => '#define ${IP}_TCSR (*((volatile unsigned int *) ($BASE ))) |
|
/* |
//timer control register |
TCSR0 |
TCSR |
bit |
6-3 : clk_dev_ctrl |
3 : timer_isr |
2 : rst_on_cmp_value |
1 : int_enble_on_cmp_value |
0 : timer enable |
PRESCALER WIDTH+3:4 : clk_dev_ctrl |
3 : timer_isr |
2 : rst_on_cmp_value |
1 : int_enble_on_cmp_value |
0 : timer enable |
*/ |
#define ${IP}_TLR0 (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_TCMP0 (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_TLR (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_TCMR (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_EN (1 << 0) |
#define ${IP}_INT_EN (1 << 1) |
#define ${IP}_RST_ON_CMP (1 << 2) |
', |
'ip_name' => 'timer', |
'description' => '32 bit timer ', |
//Initialize the timer. Enable the timer, reset on compare value, and interrupt |
void ${IP}_int_init ( unsigned int compare ){ |
${IP}_TCMR = compare; |
${IP}_TCSR = ( ${IP}_EN | ${IP}_INT_EN | ${IP}_RST_ON_CMP); |
} |
|
#define ${IP}_start() ${IP}_TCSR|=${IP}_EN |
#define ${IP}_stop() ${IP}_TCSR&=~${IP}_EN |
#define ${IP}_reset() ${IP}_TLR=0 |
#define ${IP}_read() ${IP}_TLR', |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'parameters' => { |
'Aw' => { |
'CNTw' => { |
'default' => '32 ', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'content' => '', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'Dw' => { |
'default' => '32', |
'type' => 'Fixed', |
'content' => '', |
'global_param' => 'Localparam', |
'info' => undef, |
'deafult' => '3', |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'TAGw' => { |
'SELw' => { |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => undef, |
'deafult' => '3', |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
'default' => '4' |
}, |
'SELw' => { |
'TAGw' => { |
'redefine_param' => 1, |
'info' => undef, |
'deafult' => '4', |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
'default' => '3' |
}, |
'Dw' => { |
'info' => undef, |
'deafult' => '32', |
'PRESCALER_WIDTH' => { |
'type' => 'Spin-button', |
'default' => '8', |
'redefine_param' => 1, |
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured. |
|
|
', |
'global_param' => 'Parameter', |
'content' => '1,32,1' |
}, |
'Aw' => { |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'CNTw' => { |
'info' => undef, |
'deafult' => '32 ', |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
} |
'default' => '3' |
} |
}, |
'modules' => { |
'timer' => {} |
}, |
'module_name' => 'timer', |
'description' => 'A simple, general purpose, Wishbone bus-based, 32-bit timer.', |
'sockets' => {}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/timer/timer.v' |
], |
'category' => 'Timer', |
'parameters_order' => [ |
'CNTw', |
'Dw', |
'Aw', |
'TAGw', |
'SELw', |
'PRESCALER_WIDTH' |
], |
'plugs' => { |
'interrupt_peripheral' => { |
'type' => 'num', |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'intrp' |
} |
}, |
'wb_slave' => { |
'type' => 'num', |
'wb_slave' => {}, |
'0' => { |
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl', |
'width' => 5, |
'name' => 'wb' |
}, |
'value' => 1 |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
91,134 → 136,112
}, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'0' => { |
'name' => 'intrp' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
'value' => 1 |
} |
}, |
'parameters_order' => [ |
'CNTw', |
'Dw', |
'Aw', |
'TAGw', |
'SELw' |
], |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'bte_i' |
] |
}, |
'ports' => { |
'sa_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'type' => 'input', |
'range' => '' |
}, |
'sa_tag_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0', |
'type' => 'input' |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
'sa_stb_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'type' => 'input', |
'range' => 'Aw-1 : 0' |
}, |
'irq' => { |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'int_o' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'reset_i' |
}, |
'sa_err_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
'type' => 'output', |
'intfc_port' => 'err_o' |
}, |
'sa_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'SELw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'rty_o' |
}, |
'sa_dat_i' => { |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
'intfc_port' => 'dat_i' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'irq' => { |
'intfc_port' => 'int_o', |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'range' => '', |
'type' => 'output' |
}, |
'sa_err_o' => { |
'sa_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
'type' => 'input', |
'range' => '' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_ack_o' => { |
'intfc_port' => 'ack_o', |
'sa_dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'dat_o' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_stb_i' => { |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'type' => 'output', |
'range' => '', |
'type' => 'input' |
'intfc_port' => 'ack_o' |
} |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/timer/timer.v', |
'sockets' => {}, |
'module_name' => 'timer', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'bte_i' |
] |
}, |
'category' => 'Timer' |
'modules' => { |
'timer' => {} |
}, |
'version' => 9, |
'ip_name' => 'timer', |
'description_pdf' => '/mpsoc/src_peripheral/timer/timer.pdf', |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/timer/timer.v' |
}, 'ip_gen' ); |