URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip
- from Rev 43 to Rev 48
- ↔ Reverse comparison
Rev 43 → Rev 48
/Bus/wishbone_bus.IP
234,7 → 234,7
}, |
'module_name' => 'wishbone_bus', |
'version' => 1, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/bus/wishbone_bus.v', |
'file_name' => 'mpsoc/rtl/src_peripheral/bus/wishbone_bus.v', |
'parameters' => { |
'Aw' => { |
'redefine_param' => 1, |
341,9 → 341,9
}, |
'category' => 'Bus', |
'hdl_files' => [ |
'/mpsoc/src_peripheral/bus/wishbone_bus.v', |
'/mpsoc/src_noc/main_comp.v', |
'/mpsoc/src_noc/arbiter.v' |
'/mpsoc/rtl/src_peripheral/bus/wishbone_bus.v', |
'/mpsoc/rtl/main_comp.v', |
'/mpsoc/rtl/arbiter.v' |
], |
'parameters_order' => [ |
'M', |
/Communication/jtag_uart.IP
File deleted
Communication/jtag_uart.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: Communication/jtag_wb.IP
===================================================================
--- Communication/jtag_wb.IP (revision 43)
+++ Communication/jtag_wb.IP (nonexistent)
@@ -1,220 +0,0 @@
-#######################################################################
-## File: jtag_wb.IP
-##
-## Copyright (C) 2014-2016 Alireza Monemi
-##
-## This file is part of ProNoC 1.8.0
-##
-## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
-## MAY CAUSE UNEXPECTED BEHAIVOR.
-################################################################################
-
-$ipgen = bless( {
- 'hdl_files' => [
- '/mpsoc/src_peripheral/jtag/jtag_wb'
- ],
- 'modules' => {
- 'vjtag_wb' => {},
- 'vjtag_ctrl' => {},
- 'wb_if' => {}
- },
- 'unused' => {
- 'plug:wb_master[0]' => [
- 'rty_i',
- 'tag_o',
- 'err_i',
- 'bte_o'
- ]
- },
- 'parameters_order' => [
- 'DW',
- 'AW',
- 'S_Aw',
- 'M_Aw',
- 'TAGw',
- 'SELw',
- 'VJTAG_INDEX'
- ],
- 'category' => 'Communication',
- 'module_name' => 'vjtag_wb',
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/jtag/jtag_wb/vjtag_wb.v',
- 'version' => 1,
- 'ports_order' => [
- 'clk',
- 'reset',
- 'm_sel_o',
- 'm_dat_o',
- 'm_addr_o',
- 'm_cti_o',
- 'm_stb_o',
- 'm_cyc_o',
- 'm_we_o',
- 'm_dat_i',
- 'm_ack_i',
- 'status_i'
- ],
- 'plugs' => {
- 'clk' => {
- 'clk' => {},
- 'type' => 'num',
- 'value' => 1,
- '0' => {
- 'name' => 'clk'
- }
- },
- 'reset' => {
- 'type' => 'num',
- 'value' => 1,
- 'reset' => {},
- '0' => {
- 'name' => 'reset'
- }
- },
- 'wb_master' => {
- 'type' => 'num',
- 'value' => 1,
- 'wb_master' => {},
- '0' => {
- 'name' => 'wbm'
- }
- }
- },
- 'ip_name' => 'jtag_wb',
- 'parameters' => {
- 'DW' => {
- 'default' => '32',
- 'info' => 'Parameter',
- 'content' => '4,1024,8',
- 'redefine_param' => 1,
- 'global_param' => 'Localparam',
- 'type' => 'Spin-button'
- },
- 'VJTAG_INDEX' => {
- 'global_param' => 'Localparam',
- 'redefine_param' => 1,
- 'type' => 'Entry',
- 'default' => 'CORE_ID',
- 'content' => '',
- 'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.'
- },
- 'S_Aw' => {
- 'global_param' => 'Localparam',
- 'redefine_param' => 1,
- 'type' => 'Fixed',
- 'default' => ' 7',
- 'content' => '',
- 'info' => 'Parameter'
- },
- 'SELw' => {
- 'content' => '',
- 'info' => 'Parameter',
- 'default' => ' 4',
- 'type' => 'Fixed',
- 'global_param' => 'Localparam',
- 'redefine_param' => 1
- },
- 'TAGw' => {
- 'default' => ' 3',
- 'content' => '',
- 'info' => 'Parameter',
- 'redefine_param' => 1,
- 'global_param' => 'Localparam',
- 'type' => 'Fixed'
- },
- 'AW' => {
- 'type' => 'Fixed',
- 'global_param' => 'Localparam',
- 'redefine_param' => 1,
- 'content' => '',
- 'info' => 'Parameter',
- 'default' => '32'
- },
- 'M_Aw' => {
- 'type' => 'Fixed',
- 'global_param' => 'Localparam',
- 'redefine_param' => 1,
- 'info' => 'Parameter',
- 'content' => '',
- 'default' => ' 32'
- }
- },
- 'description' => 'A jtag to wishbone bus interface.',
- 'ports' => {
- 'm_stb_o' => {
- 'intfc_port' => 'stb_o',
- 'range' => '',
- 'type' => 'output',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'm_cyc_o' => {
- 'range' => '',
- 'type' => 'output',
- 'intfc_port' => 'cyc_o',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'm_addr_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'type' => 'output',
- 'range' => 'M_Aw-1 : 0',
- 'intfc_port' => 'adr_o'
- },
- 'm_dat_o' => {
- 'type' => 'output',
- 'range' => 'DW-1 : 0',
- 'intfc_port' => 'dat_o',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'status_i' => {
- 'range' => '',
- 'type' => 'input',
- 'intfc_port' => 'NC',
- 'intfc_name' => 'IO'
- },
- 'clk' => {
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input',
- 'intfc_name' => 'plug:clk[0]'
- },
- 'm_ack_i' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'type' => 'input',
- 'range' => '',
- 'intfc_port' => 'ack_i'
- },
- 'm_dat_i' => {
- 'type' => 'input',
- 'range' => 'DW-1 : 0',
- 'intfc_port' => 'dat_i',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'm_sel_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => 'SELw-1 : 0',
- 'type' => 'output',
- 'intfc_port' => 'sel_o'
- },
- 'm_cti_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => 'TAGw-1 : 0',
- 'type' => 'output',
- 'intfc_port' => 'cti_o'
- },
- 'reset' => {
- 'intfc_port' => 'reset_i',
- 'type' => 'input',
- 'range' => '',
- 'intfc_name' => 'plug:reset[0]'
- },
- 'm_we_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
- 'type' => 'output',
- 'range' => '',
- 'intfc_port' => 'we_o'
- }
- },
- 'gui_status' => {
- 'timeout' => 0,
- 'status' => 'ideal'
- }
- }, 'ip_gen' );
Communication/jtag_wb.IP
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: Communication/Altera_jtag_uart.IP
===================================================================
--- Communication/Altera_jtag_uart.IP (nonexistent)
+++ Communication/Altera_jtag_uart.IP (revision 48)
@@ -0,0 +1,313 @@
+#######################################################################
+## File: altera_jtag_uart.IP
+##
+## Copyright (C) 2014-2019 Alireza Monemi
+##
+## This file is part of ProNoC 2.0.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ipgen = bless( {
+ 'parameters_order' => [
+ 'SIM_BUFFER_SIZE',
+ 'SIM_WAIT_COUNT',
+ 'INCLUDE_SIM_PRINTF'
+ ],
+ 'ip_name' => 'altera_jtag_uart',
+ 'modules' => {
+ 'altera_jtag_uart' => {}
+ },
+ 'system_h' => '
+
+#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE)))
+#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000
+#define ${IP}_DATA_RVALID_MSK 0x00008000
+#define ${IP}_DATA_DATA_MSK 0x000000FF
+
+//////////////////////////////*basic function for jtag_uart*////////////////////////////////////////
+void jtag_putchar(char ch);
+char jtag_getchar(void);
+void outbyte(char c); //called in printf();
+char inbyte(void);
+void jtag_putchar(char ch);
+char jtag_getchar(void);
+int jtag_scanstr(char* buf);
+int jtag_scanint(int *num);
+/////////////////////////////*END: basic function for jtag_uart*////////////////////////////////////
+
+#define INCLUDE_${INCLUDE_SIM_PRINTF}
+
+#ifdef INCLUDE_SIMPLE_PRINTF
+ #include "simple-printf/printf.h"
+#endif
+
+#ifdef INCLUDE_SIMPLE_PRINTF_LONG
+ #include "simple-printf/printf.h"
+#endif',
+ 'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_jtag_uart.v',
+ 'module_name' => 'altera_jtag_uart',
+ 'ports' => {
+ 's_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'cyc_i'
+ },
+ 's_cti_i' => {
+ 'range' => '2 : 0',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cti_i',
+ 'type' => 'input'
+ },
+ 's_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'type' => 'input',
+ 'range' => '31 : 0',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'RxD_wr_sim' => {
+ 'intfc_port' => 'RxD_wr_sim',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'socket:RxD_sim[0]'
+ },
+ 's_we_i' => {
+ 'intfc_port' => 'we_i',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'RxD_din_sim' => {
+ 'intfc_port' => 'RxD_din_sim',
+ 'type' => 'input',
+ 'range' => '7:0 ',
+ 'intfc_name' => 'socket:RxD_sim[0]'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:clk[0]'
+ },
+ 's_stb_i' => {
+ 'intfc_port' => 'stb_i',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:reset[0]'
+ },
+ 's_addr_i' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'type' => 'input'
+ },
+ 'irq' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:interrupt_peripheral[0]',
+ 'intfc_port' => 'int_o',
+ 'type' => 'output'
+ },
+ 's_dat_o' => {
+ 'range' => '31 : 0',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'type' => 'output'
+ },
+ 'RxD_ready_sim' => {
+ 'type' => 'output',
+ 'intfc_port' => 'RxD_ready_sim',
+ 'intfc_name' => 'socket:RxD_sim[0]',
+ 'range' => ''
+ },
+ 's_sel_i' => {
+ 'intfc_port' => 'sel_i',
+ 'type' => 'input',
+ 'range' => '3 : 0',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 's_ack_o' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
+ 'type' => 'output'
+ }
+ },
+ 'sw_files' => [
+ '/mpsoc/src_processor/src_lib/simple-printf'
+ ],
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'system_c' => '
+
+void outbyte(char c){jtag_putchar(c);} //called in printf();
+
+char inbyte(){return jtag_getchar();}
+
+void jtag_putchar(char ch){ //print one char from jtag_uart
+ while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0);
+ ${IP}_DATA_REG=ch;
+}
+
+char jtag_getchar(void){ //get one char from jtag_uart
+ unsigned int data;
+ data=${IP}_DATA_REG;
+ while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input
+ data=${IP}_DATA_REG;
+ return (data & ${IP}_DATA_DATA_MSK);
+}
+
+int jtag_scanstr(char* buf){ //scan string until to buf, return str length
+ char ch; unsigned int i=0;
+ while(1){
+ ch=jtag_getchar();
+ if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER
+ else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace
+ else { jtag_putchar(ch); buf[i]=ch; i++; } //valid
+ }
+ return i;
+}
+
+int jtag_scanint(int *num){ //return the scanned integer
+ unsigned int curr_num,strlen,i=0;
+ char str[11];
+ strlen=jtag_scanstr(str); //scan str
+ if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow
+ *num=0;
+ for(i=0;i9); //not integer: do nothing
+ else *num=*num*10+curr_num; //is integer
+ }
+ return 0;
+}
+
+#ifdef INCLUDE_SIMPLE_PRINTF
+ #include "simple-printf/printf.c"
+#endif
+
+#ifdef INCLUDE_SIMPLE_PRINTF_LONG
+ #include "simple-printf/prinf_long.c"
+#endif
+
+
+',
+ 'category' => 'Communication',
+ 'parameters' => {
+ 'SIM_WAIT_COUNT' => {
+ 'global_param' => 'Localparam',
+ 'info' => 'This parameter is valid only in simulation.
+If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.',
+ 'content' => '2,100000,1',
+ 'redefine_param' => 1,
+ 'default' => '1000',
+ 'type' => 'Spin-button'
+ },
+ 'SIM_BUFFER_SIZE' => {
+ 'info' => 'Internal buffer size.
+This parameter is valid only in simulation.
+If internal buffer overflows, the buffer content are displayed on simulator terminal.',
+ 'content' => '10,10000,1',
+ 'global_param' => 'Localparam',
+ 'type' => 'Spin-button',
+ 'default' => '100',
+ 'redefine_param' => 1
+ },
+ 'INCLUDE_SIM_PRINTF' => {
+ 'info' => 'Select source code for printf command:
+ "NONE": Do not include simple_printf source code. Select "NONE" In case printf command is supported in , or it is not needed in the software code.
+ "SIMPLE_PRINTF" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, and %%s. long and floating formats are not supported.
+ "SIMPLE_PRINTF_LONG" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, %%l, and %%s. floating format is not supported.
+ ',
+ 'content' => 'NONE,SIMPLE_PRINTF,SIMPLE_PRINTF_LONG',
+ 'global_param' => 'Don\'t include',
+ 'redefine_param' => 0,
+ 'default' => 'SIMPLE_PRINTF',
+ 'type' => 'Combo-box'
+ },
+
+ },
+ 'ports_order' => [
+ 'reset',
+ 'clk',
+ 'irq',
+ 's_dat_i',
+ 's_sel_i',
+ 's_addr_i',
+ 's_cti_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 'RxD_din_sim',
+ 'RxD_wr_sim',
+ 'RxD_ready_sim'
+ ],
+ 'description' => 'The Altera JTAG UART IP core (qsys_jtag_uart) with Wishbone bus interface.',
+ 'version' => 20,
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'tag_i',
+ 'bte_i',
+ 'rty_o',
+ 'err_o'
+ ]
+ },
+ 'sockets' => {
+ 'RxD_sim' => {
+ 'connection_num' => 'single connection',
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'RxD_sim'
+ }
+ }
+ },
+ 'plugs' => {
+ 'interrupt_peripheral' => {
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'interrupt_peripheral'
+ }
+ },
+ 'reset' => {
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'reset'
+ }
+ },
+ 'clk' => {
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'clk'
+ }
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
+ 'width' => 5,
+ 'name' => 'wb_slave'
+ }
+ }
+ },
+ 'hdl_files' => [
+ '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_jtag_uart.v',
+ '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_uart_simulator.v'
+ ]
+ }, 'ip_gen' );
Index: Communication/ProNoC_jtag_uart.IP
===================================================================
--- Communication/ProNoC_jtag_uart.IP (nonexistent)
+++ Communication/ProNoC_jtag_uart.IP (revision 48)
@@ -0,0 +1,418 @@
+#######################################################################
+## File: ProNoC_jtag_uart.IP
+##
+## Copyright (C) 2014-2019 Alireza Monemi
+##
+## This file is part of ProNoC 1.9.1
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ipgen = bless( {
+ 'system_h' => '
+#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE)))
+#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000
+#define ${IP}_DATA_RVALID_MSK 0x00008000
+#define ${IP}_DATA_DATA_MSK 0x000000FF
+
+//////////////////////////////*basic function for jtag_uart*////////////////////////////////////////
+void jtag_putchar(char ch);
+char jtag_getchar(void);
+void outbyte(char c); //called in printf();
+char inbyte(void);
+void jtag_putchar(char ch);
+char jtag_getchar(void);
+int jtag_scanstr(char* buf);
+int jtag_scanint(int *num);
+/////////////////////////////*END: basic function for jtag_uart*////////////////////////////////////
+
+#define INCLUDE_${INCLUDE_SIM_PRINTF}
+
+#ifdef INCLUDE_SIMPLE_PRINTF
+ #include "simple-printf/printf.h"
+#endif
+
+#ifdef INCLUDE_SIMPLE_PRINTF_LONG
+ #include "simple-printf/printf.h"
+#endif',
+ 'ports' => {
+ 'wb_adr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'adr_i'
+ },
+ 'wb_stb_i' => {
+ 'type' => 'input',
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => ''
+ },
+ 'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'intfc_port' => 'clk_i',
+ 'type' => 'input'
+ },
+ 'wb_we_i' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'we_i',
+ 'type' => 'input'
+ },
+ 'wb_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1: 0'
+ },
+ 'wb_to_jtag' => {
+ 'range' => 'WB2Jw-1 : 0',
+ 'intfc_name' => 'socket:jtag_to_wb[0]',
+ 'intfc_port' => 'jwb_o',
+ 'type' => 'output'
+ },
+ 'reset' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'type' => 'input'
+ },
+ 'wb_ack_o' => {
+ 'intfc_port' => 'ack_o',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => ''
+ },
+ 'wb_cyc_i' => {
+ 'intfc_port' => 'cyc_i',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => ''
+ },
+ 'jtag_to_wb' => {
+ 'range' => 'J2WBw-1 : 0',
+ 'intfc_name' => 'socket:jtag_to_wb[0]',
+ 'intfc_port' => 'jwb_i',
+ 'type' => 'input'
+ },
+'RxD_wr_sim' => {
+ 'intfc_port' => 'RxD_wr_sim',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'socket:RxD_sim[0]'
+ },
+ 'RxD_din_sim' => {
+ 'intfc_port' => 'RxD_din_sim',
+ 'type' => 'input',
+ 'range' => '7:0 ',
+ 'intfc_name' => 'socket:RxD_sim[0]'
+ },
+ 'RxD_ready_sim' => {
+ 'type' => 'output',
+ 'intfc_port' => 'RxD_ready_sim',
+ 'intfc_name' => 'socket:RxD_sim[0]',
+ 'range' => ''
+ },
+ 'wb_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'type' => 'input',
+ 'range' => 'Dw-1: 0',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ }
+ },
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'tag_i',
+ 'err_o',
+ 'cti_i',
+ 'bte_i',
+ 'rty_o',
+ 'sel_i'
+ ]
+ },
+
+ 'category' => 'Communication',
+ 'plugs' => {
+ 'wb_slave' => {
+ 'type' => 'num',
+ '0' => {
+ 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
+ 'width' => 4,
+ 'name' => 'wb_slave'
+ },
+ 'value' => 1
+ },
+ 'clk' => {
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1
+ },
+ 'reset' => {
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num',
+ 'value' => 1
+ }
+ },
+ 'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_uart/pronoc_jtag_uart.v',
+ 'parameters' => {
+ 'JDw' => {
+ 'type' => 'Fixed',
+ 'global_param' => 'Parameter',
+ 'default' => '32',
+ 'info' => 'Parameter',
+ 'redefine_param' => 1,
+ 'content' => ''
+ },
+ 'JINDEXw' => {
+ 'info' => 'Parameter',
+ 'default' => '8',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'global_param' => 'Parameter',
+ 'type' => 'Fixed'
+ },
+ 'J2WBw' => {
+ 'type' => 'Fixed',
+ 'global_param' => 'Parameter',
+ 'redefine_param' => 1,
+ 'content' => '',
+ 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1',
+ 'info' => undef
+ },
+ 'Dw' => {
+ 'default' => '32',
+ 'info' => 'Parameter',
+ 'redefine_param' => 1,
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'global_param' => 'Localparam'
+ },
+ 'JAw' => {
+ 'global_param' => 'Parameter',
+ 'type' => 'Fixed',
+ 'info' => 'Parameter',
+ 'default' => '32',
+ 'content' => '',
+ 'redefine_param' => 1
+ },
+ 'JSTATUSw' => {
+ 'global_param' => 'Parameter',
+ 'type' => 'Fixed',
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'info' => 'Parameter',
+ 'default' => '8'
+ },
+ 'INCLUDE_SIM_PRINTF' => {
+ 'redefine_param' => 0,
+ 'content' => 'NONE,SIMPLE_PRINTF,SIMPLE_PRINTF_LONG',
+ 'default' => 'SIMPLE_PRINTF',
+ 'info' => 'Select source code for printf command:
+ "NONE": Do not include simple_printf source code. Select "NONE" In case printf command is supported in , or it is not needed in the software code.
+ "SIMPLE_PRINTF" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, and %%s. long and floating formats are not supported.
+ "SIMPLE_PRINTF_LONG" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, %%l, and %%s. floating format is not supported.',
+ 'type' => 'Combo-box',
+ 'global_param' => 'Don\'t include'
+ },
+ 'Aw' => {
+ 'type' => 'Fixed',
+ 'global_param' => 'Localparam',
+ 'redefine_param' => 1,
+ 'content' => '',
+ 'default' => '1',
+ 'info' => 'Parameter'
+ },
+ 'JTAG_CONNECT' => {
+ 'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
+ 'redefine_param' => 1,
+ 'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
+
+For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
+ 'default' => '"XILINX_JTAG_WB"',
+ 'global_param' => 'Parameter',
+ 'type' => 'Combo-box'
+ },
+ 'JTAG_INDEX' => {
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
+ 'default' => '126-CORE_ID',
+ 'global_param' => 'Parameter',
+ 'type' => 'Entry'
+ },
+ 'BUFF_Aw' => {
+ 'global_param' => 'Localparam',
+ 'type' => 'Spin-button',
+ 'content' => '2,16,1',
+ 'redefine_param' => 1,
+ 'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
+ 'default' => '6'
+ },
+ 'SELw' => {
+ 'global_param' => 'Localparam',
+ 'type' => 'Fixed',
+ 'info' => 'Parameter',
+ 'default' => '4',
+ 'content' => '',
+ 'redefine_param' => 1
+ },
+ 'JTAG_CHAIN' => {
+ 'global_param' => 'Parameter',
+ 'type' => 'Combo-box',
+ 'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
+ 4: JTAG runtime memory programmers.
+ 3: UART
+ 1,2: reserved',
+ 'default' => '3',
+ 'content' => '1,2,3,4',
+ 'redefine_param' => 0
+ },
+ 'WB2Jw' => {
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'info' => '',
+ 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1',
+ 'global_param' => 'Parameter',
+ 'type' => 'Fixed'
+ },
+ 'TAGw' => {
+ 'type' => 'Fixed',
+ 'global_param' => 'Localparam',
+ 'default' => '3',
+ 'info' => 'Parameter',
+ 'redefine_param' => 1,
+ 'content' => ''
+ }
+ },
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'ip_name' => 'ProNoC_jtag_uart',
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 'wb_dat_o',
+ 'wb_ack_o',
+ 'wb_adr_i',
+ 'wb_stb_i',
+ 'wb_cyc_i',
+ 'wb_we_i',
+ 'wb_dat_i',
+ 'wb_to_jtag',
+ 'jtag_to_wb',
+ 'RxD_din_sim',
+ 'RxD_wr_sim',
+ 'RxD_ready_sim'
+ ],
+ 'version' => 11,
+ 'description' => 'A jtag uart module. Controled using Altera Vjtag or Xilinx BSCANE2.',
+ 'parameters_order' => [
+ 'Aw',
+ 'SELw',
+ 'TAGw',
+ 'Dw',
+ 'BUFF_Aw',
+ 'JTAG_INDEX',
+ 'JDw',
+ 'JAw',
+ 'JINDEXw',
+ 'JSTATUSw',
+ 'JTAG_CHAIN',
+ 'JTAG_CONNECT',
+ 'J2WBw',
+ 'WB2Jw',
+ 'INCLUDE_SIM_PRINTF'
+ ],
+ 'hdl_files' => [
+ '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/pronoc_jtag_uart.v',
+ '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_uart_simulator.v'
+ ],
+ 'sw_files' => [
+ '/mpsoc/src_processor/src_lib/simple-printf'
+ ],
+ 'sockets' => {
+ 'RxD_sim' => {
+ 'connection_num' => 'single connection',
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'RxD_sim'
+ }
+ },
+
+'jtag_to_wb' => {
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'jtag_to_wb'
+ },
+ 'connection_num' => 'single connection'
+ }
+ },
+ 'modules' => {
+ 'uart_dual_port_ram' => {},
+ 'pronoc_jtag_uart' => {}
+ },
+ 'system_c' => '
+void outbyte(char c){jtag_putchar(c);} //called in printf();
+
+char inbyte(){return jtag_getchar();}
+
+void jtag_putchar(char ch){ //print one char from jtag_uart
+ while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0);
+ ${IP}_DATA_REG=ch;
+}
+
+char jtag_getchar(void){ //get one char from jtag_uart
+ unsigned int data;
+ data=${IP}_DATA_REG;
+ while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input
+ data=${IP}_DATA_REG;
+ return (data & ${IP}_DATA_DATA_MSK);
+}
+
+int jtag_scanstr(char* buf){ //scan string until to buf, return str length
+ char ch; unsigned int i=0;
+ while(1){
+ ch=jtag_getchar();
+ if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER
+ else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace
+ else { jtag_putchar(ch); buf[i]=ch; i++; } //valid
+ }
+ return i;
+}
+
+int jtag_scanint(int *num){ //return the scanned integer
+ unsigned int curr_num,strlen,i=0;
+ char str[11];
+ strlen=jtag_scanstr(str); //scan str
+ if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow
+ *num=0;
+ for(i=0;i9); //not integer: do nothing
+ else *num=*num*10+curr_num; //is integer
+ }
+ return 0;
+}
+
+#ifdef INCLUDE_SIMPLE_PRINTF
+ #include "simple-printf/printf.c"
+#endif
+
+#ifdef INCLUDE_SIMPLE_PRINTF_LONG
+ #include "simple-printf/prinf_long.c"
+#endif
+
+
+',
+ 'module_name' => 'pronoc_jtag_uart'
+ }, 'ip_gen' );
Index: Communication/ProNoC_jtag_wb.IP
===================================================================
--- Communication/ProNoC_jtag_wb.IP (nonexistent)
+++ Communication/ProNoC_jtag_wb.IP (revision 48)
@@ -0,0 +1,296 @@
+#######################################################################
+## File: ProNoC_jtag_wb.IP
+##
+## Copyright (C) 2014-2019 Alireza Monemi
+##
+## This file is part of ProNoC 1.9.1
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ipgen = bless( {
+ 'modules' => {
+ 'pronoc_jtag_wb' => {}
+ },
+ 'category' => 'Communication',
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 'status_i',
+ 'm_sel_o',
+ 'm_dat_o',
+ 'm_addr_o',
+ 'm_cti_o',
+ 'm_stb_o',
+ 'm_cyc_o',
+ 'm_we_o',
+ 'm_dat_i',
+ 'm_ack_i',
+ 'jtag_to_wb',
+ 'wb_to_jtag'
+ ],
+ 'parameters' => {
+ 'WB2Jw' => {
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'info' => 'Parameter',
+ 'redefine_param' => 1,
+ 'global_param' => 'Parameter',
+ 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'
+ },
+ 'Dw' => {
+ 'type' => 'Fixed',
+ 'info' => 'Parameter',
+ 'content' => '',
+ 'default' => '32',
+ 'global_param' => 'Localparam',
+ 'redefine_param' => 1
+ },
+ 'J2WBw' => {
+ 'global_param' => 'Parameter',
+ 'redefine_param' => 1,
+ 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1',
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'info' => 'Parameter'
+ },
+ 'JTAG_INDEX' => {
+ 'redefine_param' => 1,
+ 'global_param' => 'Parameter',
+ 'default' => 'CORE_ID',
+ 'content' => '',
+ 'info' => 'The index number id used for communicating with this IP. All modules connected to the same jtag tab should have a unique JTAG index number. The default value is CORE_ID. The core ID is the tile number in MPSoC. So if each tile has one JTAG_TO_WB module, its index would be different. In case there are multiple number of JTAG_TO_WB modules in one tile or the CORE_ID index number has been taken by another module such as RAM you need to manualy set a new value for this parameter.',
+ 'type' => 'Entry'
+ },
+ 'JTAG_CONNECT' => {
+ 'content' => '"ALTERA_JTAG_WB","XILINX_JTAG_WB"',
+ 'type' => 'Combo-box',
+ 'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the Virtual JTAG tap IP core from Altera lib is used to communicate with the Host PC.
+
+For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the BSCANE2 JTAG tap IP core from XILINX lib is used to communicate with the Host PC.',
+ 'redefine_param' => 1,
+ 'global_param' => 'Parameter',
+ 'default' => '"XILINX_JTAG_WB"'
+ },
+ 'JDw' => {
+ 'content' => '',
+ 'info' => 'Parameter',
+ 'type' => 'Fixed',
+ 'global_param' => 'Parameter',
+ 'redefine_param' => 1,
+ 'default' => '32'
+ },
+ 'JINDEXw' => {
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'info' => 'Parameter',
+ 'global_param' => 'Parameter',
+ 'redefine_param' => 1,
+ 'default' => '8'
+ },
+ 'JTAG_CHAIN' => {
+ 'content' => '1,2,3,4',
+ 'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
+ 4: JTAG runtime memory programmers.
+ 3: UART
+ 1,2: reserved',
+ 'type' => 'Combo-box',
+ 'redefine_param' => 0,
+ 'global_param' => 'Parameter',
+ 'default' => '4'
+ },
+ 'JSTATUSw' => {
+ 'info' => 'Parameter',
+ 'type' => 'Fixed',
+ 'content' => '',
+ 'default' => '8',
+ 'redefine_param' => 1,
+ 'global_param' => 'Parameter'
+ },
+ 'JAw' => {
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'info' => 'Parameter',
+ 'redefine_param' => 1,
+ 'global_param' => 'Parameter',
+ 'default' => '32'
+ },
+ 'SELw' => {
+ 'type' => 'Fixed',
+ 'info' => 'Parameter',
+ 'content' => '',
+ 'default' => '4',
+ 'redefine_param' => 1,
+ 'global_param' => 'Localparam'
+ },
+ 'Aw' => {
+ 'content' => '',
+ 'type' => 'Fixed',
+ 'info' => 'Parameter',
+ 'redefine_param' => 1,
+ 'global_param' => 'Localparam',
+ 'default' => '32'
+ },
+ 'TAGw' => {
+ 'redefine_param' => 1,
+ 'global_param' => 'Localparam',
+ 'default' => '3',
+ 'content' => '',
+ 'info' => 'Parameter',
+ 'type' => 'Fixed'
+ }
+ },
+ 'module_name' => 'pronoc_jtag_wb',
+ 'ports' => {
+ 'status_i' => {
+ 'type' => 'input',
+ 'range' => 'JSTATUSw-1 : 0',
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'NC'
+ },
+ 'm_cyc_o' => {
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cyc_o'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'm_sel_o' => {
+ 'intfc_port' => 'sel_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'SELw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_cti_o' => {
+ 'intfc_port' => 'cti_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'TAGw-1 : 0',
+ 'type' => 'output'
+ },
+ 'wb_to_jtag' => {
+ 'range' => 'WB2Jw-1: 0',
+ 'type' => 'output',
+ 'intfc_port' => 'jwb_o',
+ 'intfc_name' => 'socket:jtag_to_wb[0]'
+ },
+ 'm_we_o' => {
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_port' => 'we_o',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'jtag_to_wb' => {
+ 'range' => 'J2WBw-1 : 0',
+ 'type' => 'input',
+ 'intfc_name' => 'socket:jtag_to_wb[0]',
+ 'intfc_port' => 'jwb_i'
+ },
+ 'm_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'input'
+ },
+ 'm_stb_o' => {
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'm_ack_i' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_port' => 'ack_i',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'type' => 'input',
+ 'range' => ''
+ },
+ 'm_addr_o' => {
+ 'intfc_port' => 'adr_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => 'Aw-1 : 0',
+ 'type' => 'output'
+ },
+ 'm_dat_o' => {
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output',
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_master[0]'
+ }
+ },
+ 'parameters_order' => [
+ 'JTAG_CONNECT',
+ 'JTAG_INDEX',
+ 'JDw',
+ 'JAw',
+ 'JINDEXw',
+ 'JSTATUSw',
+ 'J2WBw',
+ 'WB2Jw',
+ 'Dw',
+ 'Aw',
+ 'TAGw',
+ 'SELw',
+ 'JTAG_CHAIN'
+ ],
+ 'sockets' => {
+ 'jtag_to_wb' => {
+ 'connection_num' => 'single connection',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'jtag_to_wb'
+ },
+ 'type' => 'num'
+ }
+ },
+ 'plugs' => {
+ 'reset' => {
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1
+ },
+ 'wb_master' => {
+ 'value' => 1,
+ '0' => {
+ 'name' => 'wb_master'
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ }
+ },
+ 'hdl_files' => [],
+ 'version' => 8,
+ 'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_wb/pronoc_jtag_wb.v',
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'description' => 'JTAG to Wishbone bus interface. This module allows reading/writing data to the IP cores connected to the wishbone bus (e.g. memory cores). ',
+ 'ip_name' => 'ProNoC_jtag_wb',
+ 'unused' => {
+ 'plug:wb_master[0]' => [
+ 'tag_o',
+ 'bte_o',
+ 'err_i',
+ 'rty_i'
+ ]
+ }
+ }, 'ip_gen' );
Index: Communication/altera_jtag_uart.IP
===================================================================
--- Communication/altera_jtag_uart.IP (nonexistent)
+++ Communication/altera_jtag_uart.IP (revision 48)
@@ -0,0 +1,313 @@
+#######################################################################
+## File: altera_jtag_uart.IP
+##
+## Copyright (C) 2014-2019 Alireza Monemi
+##
+## This file is part of ProNoC 2.0.0
+##
+## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
+## MAY CAUSE UNEXPECTED BEHAIVOR.
+################################################################################
+
+$ipgen = bless( {
+ 'parameters_order' => [
+ 'SIM_BUFFER_SIZE',
+ 'SIM_WAIT_COUNT',
+ 'INCLUDE_SIM_PRINTF'
+ ],
+ 'ip_name' => 'altera_jtag_uart',
+ 'modules' => {
+ 'altera_jtag_uart' => {}
+ },
+ 'system_h' => '
+
+#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE)))
+#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000
+#define ${IP}_DATA_RVALID_MSK 0x00008000
+#define ${IP}_DATA_DATA_MSK 0x000000FF
+
+//////////////////////////////*basic function for jtag_uart*////////////////////////////////////////
+void jtag_putchar(char ch);
+char jtag_getchar(void);
+void outbyte(char c); //called in printf();
+char inbyte(void);
+void jtag_putchar(char ch);
+char jtag_getchar(void);
+int jtag_scanstr(char* buf);
+int jtag_scanint(int *num);
+/////////////////////////////*END: basic function for jtag_uart*////////////////////////////////////
+
+#define INCLUDE_${INCLUDE_SIM_PRINTF}
+
+#ifdef INCLUDE_SIMPLE_PRINTF
+ #include "simple-printf/printf.h"
+#endif
+
+#ifdef INCLUDE_SIMPLE_PRINTF_LONG
+ #include "simple-printf/printf.h"
+#endif',
+ 'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_jtag_uart.v',
+ 'module_name' => 'altera_jtag_uart',
+ 'ports' => {
+ 's_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'cyc_i'
+ },
+ 's_cti_i' => {
+ 'range' => '2 : 0',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cti_i',
+ 'type' => 'input'
+ },
+ 's_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'type' => 'input',
+ 'range' => '31 : 0',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'RxD_wr_sim' => {
+ 'intfc_port' => 'RxD_wr_sim',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'socket:RxD_sim[0]'
+ },
+ 's_we_i' => {
+ 'intfc_port' => 'we_i',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'RxD_din_sim' => {
+ 'intfc_port' => 'RxD_din_sim',
+ 'type' => 'input',
+ 'range' => '7:0 ',
+ 'intfc_name' => 'socket:RxD_sim[0]'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:clk[0]'
+ },
+ 's_stb_i' => {
+ 'intfc_port' => 'stb_i',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 'reset' => {
+ 'intfc_port' => 'reset_i',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:reset[0]'
+ },
+ 's_addr_i' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'adr_i',
+ 'type' => 'input'
+ },
+ 'irq' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:interrupt_peripheral[0]',
+ 'intfc_port' => 'int_o',
+ 'type' => 'output'
+ },
+ 's_dat_o' => {
+ 'range' => '31 : 0',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'dat_o',
+ 'type' => 'output'
+ },
+ 'RxD_ready_sim' => {
+ 'type' => 'output',
+ 'intfc_port' => 'RxD_ready_sim',
+ 'intfc_name' => 'socket:RxD_sim[0]',
+ 'range' => ''
+ },
+ 's_sel_i' => {
+ 'intfc_port' => 'sel_i',
+ 'type' => 'input',
+ 'range' => '3 : 0',
+ 'intfc_name' => 'plug:wb_slave[0]'
+ },
+ 's_ack_o' => {
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
+ 'type' => 'output'
+ }
+ },
+ 'sw_files' => [
+ '/mpsoc/src_processor/src_lib/simple-printf'
+ ],
+ 'gui_status' => {
+ 'timeout' => 0,
+ 'status' => 'ideal'
+ },
+ 'system_c' => '
+
+void outbyte(char c){jtag_putchar(c);} //called in printf();
+
+char inbyte(){return jtag_getchar();}
+
+void jtag_putchar(char ch){ //print one char from jtag_uart
+ while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0);
+ ${IP}_DATA_REG=ch;
+}
+
+char jtag_getchar(void){ //get one char from jtag_uart
+ unsigned int data;
+ data=${IP}_DATA_REG;
+ while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input
+ data=${IP}_DATA_REG;
+ return (data & ${IP}_DATA_DATA_MSK);
+}
+
+int jtag_scanstr(char* buf){ //scan string until to buf, return str length
+ char ch; unsigned int i=0;
+ while(1){
+ ch=jtag_getchar();
+ if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER
+ else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace
+ else { jtag_putchar(ch); buf[i]=ch; i++; } //valid
+ }
+ return i;
+}
+
+int jtag_scanint(int *num){ //return the scanned integer
+ unsigned int curr_num,strlen,i=0;
+ char str[11];
+ strlen=jtag_scanstr(str); //scan str
+ if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow
+ *num=0;
+ for(i=0;i9); //not integer: do nothing
+ else *num=*num*10+curr_num; //is integer
+ }
+ return 0;
+}
+
+#ifdef INCLUDE_SIMPLE_PRINTF
+ #include "simple-printf/printf.c"
+#endif
+
+#ifdef INCLUDE_SIMPLE_PRINTF_LONG
+ #include "simple-printf/prinf_long.c"
+#endif
+
+
+',
+ 'category' => 'Communication',
+ 'parameters' => {
+ 'SIM_WAIT_COUNT' => {
+ 'global_param' => 'Localparam',
+ 'info' => 'This parameter is valid only in simulation.
+If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.',
+ 'content' => '2,100000,1',
+ 'redefine_param' => 1,
+ 'default' => '1000',
+ 'type' => 'Spin-button'
+ },
+ 'SIM_BUFFER_SIZE' => {
+ 'info' => 'Internal buffer size.
+This parameter is valid only in simulation.
+If internal buffer overflows, the buffer content are displayed on simulator terminal.',
+ 'content' => '10,10000,1',
+ 'global_param' => 'Localparam',
+ 'type' => 'Spin-button',
+ 'default' => '100',
+ 'redefine_param' => 1
+ },
+ 'INCLUDE_SIM_PRINTF' => {
+ 'info' => 'Select source code for printf command:
+ "NONE": Do not include simple_printf source code. Select "NONE" In case printf command is supported in , or it is not needed in the software code.
+ "SIMPLE_PRINTF" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, and %%s. long and floating formats are not supported.
+ "SIMPLE_PRINTF_LONG" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, %%l, and %%s. floating format is not supported.
+ ',
+ 'content' => 'NONE,SIMPLE_PRINTF,SIMPLE_PRINTF_LONG',
+ 'global_param' => 'Don\'t include',
+ 'redefine_param' => 0,
+ 'default' => 'NONE',
+ 'type' => 'Combo-box'
+ },
+
+ },
+ 'ports_order' => [
+ 'reset',
+ 'clk',
+ 'irq',
+ 's_dat_i',
+ 's_sel_i',
+ 's_addr_i',
+ 's_cti_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 'RxD_din_sim',
+ 'RxD_wr_sim',
+ 'RxD_ready_sim'
+ ],
+ 'description' => 'The Altera JTAG UART IP core (qsys_jtag_uart) with Wishbone bus interface.',
+ 'version' => 20,
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'tag_i',
+ 'bte_i',
+ 'rty_o',
+ 'err_o'
+ ]
+ },
+ 'sockets' => {
+ 'RxD_sim' => {
+ 'connection_num' => 'single connection',
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'RxD_sim'
+ }
+ }
+ },
+ 'plugs' => {
+ 'interrupt_peripheral' => {
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'interrupt_peripheral'
+ }
+ },
+ 'reset' => {
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'reset'
+ }
+ },
+ 'clk' => {
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'name' => 'clk'
+ }
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ 'type' => 'num',
+ '0' => {
+ 'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
+ 'width' => 5,
+ 'name' => 'wb_slave'
+ }
+ }
+ },
+ 'hdl_files' => [
+ '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_jtag_uart.v',
+ '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_uart_simulator.v'
+ ]
+ }, 'ip_gen' );
Index: Communication/ethmac_100.IP
===================================================================
--- Communication/ethmac_100.IP (revision 43)
+++ Communication/ethmac_100.IP (revision 48)
@@ -1,468 +1,527 @@
#######################################################################
## File: ethmac_100.IP
##
-## Copyright (C) 2014-2016 Alireza Monemi
+## Copyright (C) 2014-2019 Alireza Monemi
##
-## This file is part of ProNoC 1.7.0
+## This file is part of ProNoC 1.9.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
-$ethtop = bless( {
- 'version' => 1,
- 'module_name' => 'ethtop',
- 'unused' => {
- 'plug:wb_master[0]' => [
- 'bte_o',
- 'rty_i',
- 'cti_o',
- 'tag_o'
- ],
- 'plug:wb_slave[0]' => [
- 'cti_i',
- 'bte_i',
- 'tag_i',
- 'rty_o'
- ]
- },
- 'plugs' => {
- 'wb_master' => {
- 'wb_master' => {},
- 'value' => 1,
- 'type' => 'num',
- '0' => {
- 'name' => 'wb_master'
- }
- },
- 'wb_slave' => {
+$ipgen = bless( {
+ 'version' => 2,
+ 'parameters' => {
+ 'TX_FIFO_DATA_WIDTH' => {
+ 'type' => 'Fixed',
+ 'global_param' => 0,
+ 'redefine_param' => 1,
+ 'default' => ' 32',
+ 'content' => '',
+ 'info' => undef
+ },
+ 'TX_FIFO_DEPTH' => {
+ 'default' => ' 16',
+ 'content' => '',
+ 'info' => undef,
+ 'type' => 'Fixed',
+ 'redefine_param' => 1,
+ 'global_param' => 0
+ },
+ 'RX_FIFO_CNT_WIDTH' => {
+ 'info' => undef,
+ 'default' => ' 5',
+ 'content' => '',
+ 'global_param' => 0,
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'RX_FIFO_DATA_WIDTH' => {
+ 'default' => ' 32',
+ 'content' => '',
+ 'info' => undef,
+ 'type' => 'Fixed',
+ 'global_param' => 0,
+ 'redefine_param' => 1
+ },
+ 'TX_FIFO_CNT_WIDTH' => {
+ 'content' => '',
+ 'default' => ' 5',
+ 'info' => undef,
+ 'type' => 'Fixed',
+ 'redefine_param' => 1,
+ 'global_param' => 0
+ },
+ 'RX_FIFO_DEPTH' => {
+ 'default' => ' 16',
+ 'content' => '',
+ 'info' => undef,
+ 'type' => 'Fixed',
+ 'global_param' => 0,
+ 'redefine_param' => 1
+ }
+ },
+ 'gen_sw_files' => [
+ '/mpsoc/rtl/src_peripheral/ethmac/ethfrename_sep_t${IP}.h'
+ ],
+ 'system_h' => '
+
+void ${IP}_init();
+void ${IP}_interrupt();
+void ${IP}_recv_ack(void);
+int ${IP}_send(int length); //return (-1) or length (still processing previous) or asserted
+
+#define ${IP}_BASE_ADDR $BASE
+#define ${IP}_MODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x00 )))
+#define ${IP}_INT_SOURCE (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x04 )))
+#define ${IP}_INT_MASK (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x08 )))
+#define ${IP}_IPGT (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x0C )))
+#define ${IP}_IPGR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x10 )))
+#define ${IP}_IPGR2 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x14 )))
+#define ${IP}_PACKETLEN (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x18 )))
+#define ${IP}_COLLCONF (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x1C )))
+#define ${IP}_TX_BD_NUM (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x20 )))
+#define ${IP}_CTRLMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x24 )))
+#define ${IP}_MIIMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x28 )))
+#define ${IP}_MIICOMMAND (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x2C )))
+#define ${IP}_MIIADDR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x30 )))
+#define ${IP}_MIITX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x34 )))
+#define ${IP}_MIIRX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x38 )))
+#define ${IP}_MIISTATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x3C )))
+#define ${IP}_MAC_ADDR0 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x40 )))
+#define ${IP}_MAC_ADDR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x44 )))
+#define ${IP}_HASH0_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x48 )))
+#define ${IP}_HASH1_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x4C )))
+#define ${IP}_TXCTRL (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x50 )))
+#define ${IP}_TXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x404 )))
+#define ${IP}_TXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x400 )))
+#define ${IP}_RXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value
+#define ${IP}_RXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value
+
+
+#include "${IP}.h"',
+ 'plugs' => {
+ 'reset' => {
+ 'reset' => {},
+ 'type' => 'num',
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ }
+ },
+ 'wb_slave' => {
+ 'value' => 1,
+ 'type' => 'num',
+ 'wb_slave' => {},
+ '0' => {
+ 'width' => 11,
+ 'name' => 'wb_slave',
+ 'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller'
+ }
+ },
+ 'interrupt_peripheral' => {
+ '0' => {
+ 'name' => 'interrupt_peripheral'
+ },
+ 'interrupt_peripheral' => {},
+ 'type' => 'num',
+ 'value' => 1
+ },
+ 'clk' => {
+ 'clk' => {},
+ '0' => {
+ 'name' => 'clk'
+ },
+ 'type' => 'num',
+ 'value' => 1
+ },
+ 'wb_master' => {
'value' => 1,
- 'wb_slave' => {},
'type' => 'num',
+ 'wb_master' => {},
'0' => {
- 'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller',
- 'width' => 11,
- 'name' => 'wb_slave'
+ 'name' => 'wb_master'
}
- },
- 'clk' => {
- 'value' => 1,
- 'clk' => {},
- 'type' => 'num',
- '0' => {
- 'name' => 'clk'
- }
- },
- 'interrupt_peripheral' => {
- 'value' => 1,
- 'interrupt_peripheral' => {},
- '0' => {
- 'name' => 'interrupt_peripheral'
- },
- 'type' => 'num'
- },
- 'reset' => {
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num',
- 'reset' => {}
- }
- },
- 'custom_file_num' => 1,
- 'ports' => {
- 'wb_clk_i' => {
- 'range' => '',
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'type' => 'input'
- },
- 'm_wb_adr_o' => {
- 'intfc_port' => 'adr_o',
- 'type' => 'output',
- 'range' => '31:0',
- 'intfc_name' => 'plug:wb_master[0]'
+ }
+ },
+ 'sw_files' => [],
+ 'custom_file' => {
+ '0' => {}
+ },
+ 'file_name' => 'mpsoc/rtl/src_peripheral/ethmac/ethtop.v',
+ 'custom_file_num' => 1,
+ 'parameters_order' => [
+ 'TX_FIFO_DATA_WIDTH',
+ 'TX_FIFO_DEPTH',
+ 'TX_FIFO_CNT_WIDTH',
+ 'RX_FIFO_DATA_WIDTH',
+ 'RX_FIFO_DEPTH',
+ 'RX_FIFO_CNT_WIDTH'
+ ],
+ 'ip_name' => 'ethmac_100',
+ 'description' => 'The Ethernet MAC 10/100 Mbps.
+For more information please check: https://opencores.org/project,ethmac',
+ 'ports' => {
+ 'm_wb_adr_o' => {
+ 'intfc_port' => 'adr_o',
+ 'range' => '31:0',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'wb_err_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_port' => 'err_o'
+ },
+ 'wb_we_i' => {
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'we_i'
+ },
+ 'm_wb_sel_o' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'range' => '3:0',
+ 'type' => 'output',
+ 'intfc_port' => 'sel_o'
+ },
+ 'mrxdv_pad_i' => {
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO'
},
- 'mtxd_pad_o' => {
- 'intfc_port' => 'IO',
- 'type' => 'output',
- 'range' => '3:0',
- 'intfc_name' => 'IO'
- },
- 'int_o' => {
- 'intfc_port' => 'int_o',
- 'type' => 'output',
- 'range' => '',
- 'intfc_name' => 'plug:interrupt_peripheral[0]'
- },
- 'mdc_pad_o' => {
+ 'int_o' => {
+ 'intfc_port' => 'int_o',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_name' => 'plug:interrupt_peripheral[0]'
+ },
+ 'm_wb_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'type' => 'input',
+ 'range' => '31:0',
+ 'intfc_name' => 'plug:wb_master[0]'
+ },
+ 'wb_clk_i' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:clk[0]',
+ 'intfc_port' => 'clk_i'
+ },
+ 'm_wb_ack_i' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'ack_i'
+ },
+ 'wb_rst_i' => {
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_name' => 'plug:reset[0]'
+ },
+ 'mrxd_pad_i' => {
'intfc_port' => 'IO',
- 'type' => 'output',
- 'range' => '',
+ 'range' => '3:0',
+ 'type' => 'input',
'intfc_name' => 'IO'
},
- 'wb_ack_o' => {
- 'intfc_port' => 'ack_o',
- 'type' => 'output',
- 'range' => '',
- 'intfc_name' => 'plug:wb_slave[0]'
- },
- 'mtxen_pad_o' => {
+ 'mtxerr_pad_o' => {
'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
'type' => 'output',
- 'range' => '',
- 'intfc_name' => 'IO'
+ 'range' => ''
},
- 'wb_dat_i' => {
- 'intfc_port' => 'dat_i',
- 'type' => 'input',
- 'range' => '31:0',
- 'intfc_name' => 'plug:wb_slave[0]'
- },
- 'wb_stb_i' => {
- 'type' => 'input',
- 'intfc_port' => 'stb_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => ''
- },
- 'mcrs_pad_i' => {
+ 'md_pad_o' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'type' => 'output',
+ 'range' => ''
+ },
+ 'wb_adr_i' => {
+ 'intfc_port' => 'adr_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'input',
+ 'range' => '9:0'
+ },
+ 'wb_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '31:0',
+ 'type' => 'output'
+ },
+ 'm_wb_err_i' => {
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_port' => 'err_i'
+ },
+ 'mtxen_pad_o' => {
+ 'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => '',
- 'type' => 'input',
- 'intfc_port' => 'IO'
+ 'type' => 'output'
},
- 'wb_rst_i' => {
- 'type' => 'input',
- 'intfc_port' => 'reset_i',
- 'intfc_name' => 'plug:reset[0]',
- 'range' => ''
- },
- 'm_wb_dat_i' => {
- 'range' => '31:0',
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'dat_i',
- 'type' => 'input'
- },
- 'md_pad_o' => {
- 'range' => '',
- 'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
- 'type' => 'output'
- },
- 'mcoll_pad_i' => {
+ 'mrxerr_pad_i' => {
+ 'type' => 'input',
'range' => '',
'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
- 'type' => 'input'
+ 'intfc_port' => 'IO'
},
- 'm_wb_stb_o' => {
- 'range' => '',
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'stb_o',
- 'type' => 'output'
- },
- 'm_wb_err_i' => {
- 'type' => 'input',
- 'intfc_port' => 'err_i',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => ''
- },
- 'm_wb_cyc_o' => {
- 'intfc_port' => 'cyc_o',
- 'type' => 'output',
- 'range' => '',
- 'intfc_name' => 'plug:wb_master[0]'
- },
- 'mtx_clk_pad_i' => {
- 'intfc_port' => 'IO',
- 'type' => 'input',
- 'range' => '',
- 'intfc_name' => 'IO'
- },
- 'wb_err_o' => {
- 'intfc_port' => 'err_o',
+ 'mtx_clk_pad_i' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO'
+ },
+ 'm_wb_stb_o' => {
+ 'intfc_port' => 'stb_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'output',
+ 'range' => ''
+ },
+ 'mcrs_pad_i' => {
+ 'type' => 'input',
+ 'range' => '',
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO'
+ },
+ 'm_wb_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'type' => 'output',
+ 'range' => '31:0'
+ },
+ 'm_wb_we_o' => {
+ 'intfc_port' => 'we_o',
+ 'range' => '',
'type' => 'output',
- 'range' => '',
- 'intfc_name' => 'plug:wb_slave[0]'
+ 'intfc_name' => 'plug:wb_master[0]'
},
- 'wb_cyc_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
+ 'mdc_pad_o' => {
'range' => '',
- 'type' => 'input',
- 'intfc_port' => 'cyc_i'
+ 'type' => 'output',
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO'
},
- 'm_wb_dat_o' => {
- 'range' => '31:0',
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'dat_o',
- 'type' => 'output'
- },
- 'mrxdv_pad_i' => {
- 'intfc_port' => 'IO',
- 'type' => 'input',
- 'range' => '',
- 'intfc_name' => 'IO'
- },
- 'md_padoe_o' => {
+ 'mtxd_pad_o' => {
+ 'type' => 'output',
+ 'range' => '3:0',
+ 'intfc_name' => 'IO',
+ 'intfc_port' => 'IO'
+ },
+ 'wb_stb_i' => {
+ 'intfc_port' => 'stb_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'type' => 'input',
+ 'range' => ''
+ },
+ 'md_pad_i' => {
+ 'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'input',
+ 'intfc_port' => 'IO'
+ },
+ 'wb_ack_o' => {
+ 'range' => '',
+ 'type' => 'output',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o'
+ },
+ 'mcoll_pad_i' => {
'intfc_name' => 'IO',
'range' => '',
- 'type' => 'output',
+ 'type' => 'input',
'intfc_port' => 'IO'
},
- 'wb_dat_o' => {
- 'range' => '31:0',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o',
- 'type' => 'output'
- },
- 'm_wb_ack_i' => {
- 'range' => '',
- 'intfc_name' => 'plug:wb_master[0]',
- 'intfc_port' => 'ack_i',
- 'type' => 'input'
- },
- 'm_wb_we_o' => {
- 'intfc_name' => 'plug:wb_master[0]',
+ 'm_wb_cyc_o' => {
'range' => '',
'type' => 'output',
- 'intfc_port' => 'we_o'
+ 'intfc_name' => 'plug:wb_master[0]',
+ 'intfc_port' => 'cyc_o'
},
- 'mrx_clk_pad_i' => {
- 'intfc_port' => 'IO',
- 'type' => 'input',
- 'range' => '',
- 'intfc_name' => 'IO'
- },
- 'wb_sel_i' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '3:0',
- 'type' => 'input',
- 'intfc_port' => 'sel_i'
- },
- 'm_wb_sel_o' => {
- 'type' => 'output',
- 'intfc_port' => 'sel_o',
- 'intfc_name' => 'plug:wb_master[0]',
- 'range' => '3:0'
- },
- 'mtxerr_pad_o' => {
- 'range' => '',
- 'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
- 'type' => 'output'
- },
- 'wb_we_i' => {
+ 'wb_cyc_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input',
- 'intfc_port' => 'we_i'
+ 'intfc_port' => 'cyc_i'
},
- 'mrxerr_pad_i' => {
+ 'wb_sel_i' => {
+ 'intfc_port' => 'sel_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '3:0',
+ 'type' => 'input'
+ },
+ 'wb_dat_i' => {
+ 'intfc_port' => 'dat_i',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => '31:0',
+ 'type' => 'input'
+ },
+ 'md_padoe_o' => {
+ 'intfc_name' => 'IO',
+ 'type' => 'output',
+ 'range' => '',
+ 'intfc_port' => 'IO'
+ },
+ 'mrx_clk_pad_i' => {
+ 'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => '',
- 'type' => 'input',
- 'intfc_port' => 'IO'
- },
- 'wb_adr_i' => {
- 'type' => 'input',
- 'intfc_port' => 'adr_i',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '9:0'
- },
- 'mrxd_pad_i' => {
- 'type' => 'input',
- 'intfc_port' => 'IO',
- 'intfc_name' => 'IO',
- 'range' => '3:0'
- },
- 'md_pad_i' => {
- 'intfc_name' => 'IO',
- 'range' => '',
- 'type' => 'input',
- 'intfc_port' => 'IO'
- }
+ 'type' => 'input'
+ }
+ },
+ 'module_name' => 'ethtop',
+ 'unused' => {
+ 'plug:wb_master[0]' => [
+ 'tag_o',
+ 'rty_i',
+ 'bte_o',
+ 'cti_o'
+ ],
+ 'plug:wb_slave[0]' => [
+ 'cti_i',
+ 'bte_i',
+ 'rty_o',
+ 'tag_i'
+ ]
},
- 'system_h' => '
+ 'hdl_files' => [
+ '/mpsoc/rtl/src_peripheral/ethmac'
+ ],
+ 'category' => 'Communication',
+ 'modules' => {
+ 'ethtop' => {}
+ },
+ 'gui_status' => {
+ 'status' => 'ideal',
+ 'timeout' => 0
+ },
+ 'ports_order' => [
+ 'wb_clk_i',
+ 'wb_rst_i',
+ 'wb_dat_i',
+ 'wb_dat_o',
+ 'wb_adr_i',
+ 'wb_sel_i',
+ 'wb_we_i',
+ 'wb_cyc_i',
+ 'wb_stb_i',
+ 'wb_ack_o',
+ 'wb_err_o',
+ 'm_wb_adr_o',
+ 'm_wb_sel_o',
+ 'm_wb_we_o',
+ 'm_wb_dat_o',
+ 'm_wb_dat_i',
+ 'm_wb_cyc_o',
+ 'm_wb_stb_o',
+ 'm_wb_ack_i',
+ 'm_wb_err_i',
+ 'mtx_clk_pad_i',
+ 'mtxd_pad_o',
+ 'mtxen_pad_o',
+ 'mtxerr_pad_o',
+ 'mrx_clk_pad_i',
+ 'mrxd_pad_i',
+ 'mrxdv_pad_i',
+ 'mrxerr_pad_i',
+ 'mcoll_pad_i',
+ 'mcrs_pad_i',
+ 'mdc_pad_o',
+ 'md_pad_i',
+ 'md_pad_o',
+ 'md_padoe_o',
+ 'int_o'
+ ],
+ 'system_c' => 'void ${IP}_recv_ack(void)
+{
+ ${IP}_rx_done = 0;
+ ${IP}_rx_len = 0;
+ //accept further data (reset RXBD to empty)
+ ${IP}_RXBD0L = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1
+}
-void ${IP}_init();
-void ${IP}_interrupt();
-void ${IP}_recv_ack(void);
-int ${IP}_send(int length); //return (-1) or length (still processing previous) or asserted
+void ${IP}_init()
+{
+ //TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1
+ ${IP}_MODER = ETH_TXEN | ETH_RXEN | ETH_PAD | ETH_CRCEN | ETH_FULLD;
+ //PHY ADDR = 0x001
+ ${IP}_MIIADDR = 0x00000001;
-#define ${IP}_BASE_ADDR $BASE
-#define ${IP}_MODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x00 )))
-#define ${IP}_INT_SOURCE (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x04 )))
-#define ${IP}_INT_MASK (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x08 )))
-#define ${IP}_IPGT (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x0C )))
-#define ${IP}_IPGR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x10 )))
-#define ${IP}_IPGR2 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x14 )))
-#define ${IP}_PACKETLEN (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x18 )))
-#define ${IP}_COLLCONF (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x1C )))
-#define ${IP}_TX_BD_NUM (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x20 )))
-#define ${IP}_CTRLMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x24 )))
-#define ${IP}_MIIMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x28 )))
-#define ${IP}_MIICOMMAND (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x2C )))
-#define ${IP}_MIIADDR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x30 )))
-#define ${IP}_MIITX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x34 )))
-#define ${IP}_MIIRX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x38 )))
-#define ${IP}_MIISTATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x3C )))
-#define ${IP}_MAC_ADDR0 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x40 )))
-#define ${IP}_MAC_ADDR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x44 )))
-#define ${IP}_HASH0_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x48 )))
-#define ${IP}_HASH1_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x4C )))
-#define ${IP}_TXCTRL (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x50 )))
-#define ${IP}_TXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x404 )))
-#define ${IP}_TXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x400 )))
-#define ${IP}_RXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value
-#define ${IP}_RXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value
+ //enable all interrupts
+ ${IP}_INT_MASK = ETH_RXB | ETH_TXB;
+ //set MAC ADDR
+ ${IP}_MAC_ADDR1 = (${IP}_MAC_ADDR_5 << 8) | ${IP}_MAC_ADDR_4; //low word = mac ADDR high word
+ ${IP}_MAC_ADDR0 = (${IP}_MAC_ADDR_3 << 24) | (${IP}_MAC_ADDR_2 << 16)
+ | (${IP}_MAC_ADDR_1 << 8) | ${IP}_MAC_ADDR_0; //mac ADDR rest
-#include "${IP}.h"',
- 'ip_name' => 'ethmac_100',
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ethmac/ethtop.v',
- 'ports_order' => [
- 'wb_clk_i',
- 'wb_rst_i',
- 'wb_dat_i',
- 'wb_dat_o',
- 'wb_adr_i',
- 'wb_sel_i',
- 'wb_we_i',
- 'wb_cyc_i',
- 'wb_stb_i',
- 'wb_ack_o',
- 'wb_err_o',
- 'm_wb_adr_o',
- 'm_wb_sel_o',
- 'm_wb_we_o',
- 'm_wb_dat_o',
- 'm_wb_dat_i',
- 'm_wb_cyc_o',
- 'm_wb_stb_o',
- 'm_wb_ack_i',
- 'm_wb_err_i',
- 'mtx_clk_pad_i',
- 'mtxd_pad_o',
- 'mtxen_pad_o',
- 'mtxerr_pad_o',
- 'mrx_clk_pad_i',
- 'mrxd_pad_i',
- 'mrxdv_pad_i',
- 'mrxerr_pad_i',
- 'mcoll_pad_i',
- 'mcrs_pad_i',
- 'mdc_pad_o',
- 'md_pad_i',
- 'md_pad_o',
- 'md_padoe_o',
- 'int_o'
- ],
- 'hdl_files' => [
- '/mpsoc/src_peripheral/ethmac/rtl/eth_clockgen.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_cop.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_crc.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v',
- '/mpsoc/src_peripheral/ethmac/rtl/ethmac.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_maccontrol.v',
- '/mpsoc/src_peripheral/ethmac/rtl/ethmac_defines.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_macstatus.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_miim.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_outputcontrol.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_random.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_receivecontrol.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_register.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_registers.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_rxaddrcheck.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_rxcounters.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_rxethmac.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_rxstatem.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_shiftreg.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_spram_256x32.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_top.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_transmitcontrol.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_txcounters.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_txethmac.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_txstatem.v',
- '/mpsoc/src_peripheral/ethmac/rtl/eth_wishbone.v',
- '/mpsoc/src_peripheral/ethmac/rtl/timescale.v',
- '/mpsoc/src_peripheral/ethmac/rtl/xilinx_dist_ram_16x32.v',
- '/mpsoc/src_peripheral/ethmac/ethtop.v',
- '/mpsoc/src_peripheral/ethmac/eth_generic_ram.v'
- ],
- 'parameters_order' => [
- 'TX_FIFO_DATA_WIDTH',
- 'TX_FIFO_DEPTH',
- 'TX_FIFO_CNT_WIDTH',
- 'RX_FIFO_DATA_WIDTH',
- 'RX_FIFO_DEPTH',
- 'RX_FIFO_CNT_WIDTH'
- ],
- 'description' => 'The Ethernet MAC 10/100 Mbps.
-For more information please check: https://opencores.org/project,ethmac',
- 'gen_sw_files' => [
- '/mpsoc/src_peripheral/ethmac/ethfrename_sep_t${IP}.h'
- ],
- 'parameters' => {
- 'RX_FIFO_DEPTH' => {
- 'content' => '',
- 'redefine_param' => 1,
- 'default' => ' 16',
- 'info' => undef,
- 'type' => 'Fixed',
- 'global_param' => 0
- },
- 'TX_FIFO_DEPTH' => {
- 'content' => '',
- 'redefine_param' => 1,
- 'default' => ' 16',
- 'info' => undef,
- 'global_param' => 0,
- 'type' => 'Fixed'
- },
- 'RX_FIFO_DATA_WIDTH' => {
- 'type' => 'Fixed',
- 'global_param' => 0,
- 'content' => '',
- 'redefine_param' => 1,
- 'info' => undef,
- 'default' => ' 32'
- },
- 'TX_FIFO_DATA_WIDTH' => {
- 'redefine_param' => 1,
- 'content' => '',
- 'default' => ' 32',
- 'info' => undef,
- 'type' => 'Fixed',
- 'global_param' => 0
- },
- 'RX_FIFO_CNT_WIDTH' => {
- 'default' => ' 5',
- 'redefine_param' => 1,
- 'content' => '',
- 'info' => undef,
- 'global_param' => 0,
- 'type' => 'Fixed'
- },
- 'TX_FIFO_CNT_WIDTH' => {
- 'type' => 'Fixed',
- 'global_param' => 0,
- 'info' => undef,
- 'redefine_param' => 1,
- 'content' => '',
- 'default' => ' 5'
- }
- },
- 'sw_files' => [],
- 'gui_status' => {
- 'status' => 'ideal',
- 'timeout' => 0
- },
- 'custom_file' => {
- '0' => {}
- },
- 'category' => 'Communication',
- 'modules' => {
- 'ethtop' => {}
- }
- }, 'ip_gen' );
+ //configure TXBD0
+ ${IP}_TXBD0H = (unsigned long) ${IP}_tx_packet; //ADDR used for tx_data
+ ${IP}_TXBD0L = TX_READY; //length = 0 | PAD & CRC = 1 | IRQ & WR = 1
+
+ //configure RXBD0
+ ${IP}_RXBD0H = (unsigned long)${IP}_rx_packet; //ADDR used for tx_data
+ ${IP}_RXBD0L = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1
+
+ //set txdata
+ ${IP}_tx_packet[0] = ${IP}_BROADCAST_ADDR_5;
+ ${IP}_tx_packet[1] = ${IP}_BROADCAST_ADDR_4;
+ ${IP}_tx_packet[2] = ${IP}_BROADCAST_ADDR_3;
+ ${IP}_tx_packet[3] = ${IP}_BROADCAST_ADDR_2;
+ ${IP}_tx_packet[4] = ${IP}_BROADCAST_ADDR_1;
+ ${IP}_tx_packet[5] = ${IP}_BROADCAST_ADDR_0;
+
+ ${IP}_tx_packet[6] = ${IP}_MAC_ADDR_5;
+ ${IP}_tx_packet[7] = ${IP}_MAC_ADDR_4;
+ ${IP}_tx_packet[8] = ${IP}_MAC_ADDR_3;
+ ${IP}_tx_packet[9] = ${IP}_MAC_ADDR_2;
+ ${IP}_tx_packet[10] = ${IP}_MAC_ADDR_1;
+ ${IP}_tx_packet[11] = ${IP}_MAC_ADDR_0;
+
+ //erase interrupts
+ ${IP}_INT_SOURCE = ETH_RXC | ETH_TXC | ETH_BUSY | ETH_RXE | ETH_RXB | ETH_TXE | ETH_TXB;
+
+ ${IP}_tx_done = 1;
+ ${IP}_rx_done = 0;
+ ${IP}_rx_len = 0;
+ ${IP}_tx_data = & ${IP}_tx_packet[HDR_LEN];
+ ${IP}_rx_data = & ${IP}_rx_packet[HDR_LEN];
+}
+
+
+int ${IP}_send(int length)
+{
+ if (!${IP}_tx_done) //if previous command not fully processed, bail out
+ return -1;
+
+ ${IP}_tx_done = 0;
+ ${IP}_tx_packet[12] = length >> 8;
+ ${IP}_tx_packet[13] = length;
+
+ ${IP}_TXBD0L = (( 0x0000FFFF & ( length + HDR_LEN ) ) << 16) | BD_SND;
+
+ return length;
+}
+
+void ${IP}_interrupt()
+{
+ unsigned long source = ${IP}_INT_SOURCE;
+ if ( source & ETH_TXB )
+ {
+ ${IP}_tx_done = 1;
+ //erase interrupt
+ ${IP}_INT_SOURCE |= ETH_TXB;
+ }
+ if ( source & ETH_RXB )
+ {
+ ${IP}_rx_done = 1;
+ ${IP}_rx_len = (${IP}_RXBD0L >> 16) - HDR_LEN - CRC_LEN;
+ //erase interrupt
+ ${IP}_INT_SOURCE |= ETH_RXB;
+ }
+}'
+ }, 'ip_gen' );
/Communication/source_probe.IP
0,0 → 1,194
####################################################################### |
## File: source_probe.IP |
## |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ipgen = bless( { |
'ports_order' => [ |
'reset', |
'clk', |
'source_o', |
'probe_i', |
'jtag_to_wb', |
'wb_to_jtag' |
], |
'unused' => undef, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'ports' => { |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'range' => '' |
}, |
'jtag_to_wb' => { |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'intfc_port' => 'jwb_i', |
'type' => 'input', |
'range' => 'J2WBw-1 : 0' |
}, |
'source_o' => { |
'type' => 'output', |
'range' => 'Dw-1 :0', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO' |
}, |
'probe_i' => { |
'range' => 'Dw-1 :0', |
'type' => 'input', |
'intfc_port' => 'IO', |
'intfc_name' => 'IO' |
}, |
'clk' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]' |
}, |
'wb_to_jtag' => { |
'intfc_port' => 'jwb_o', |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'range' => 'WB2Jw-1: 0', |
'type' => 'output' |
} |
}, |
'ip_name' => 'source_probe', |
'parameters' => { |
'JTAG_CHAIN' => { |
'global_param' => 'Parameter', |
'default' => '3', |
'content' => '1,2,3,4 ', |
'redefine_param' => 0, |
'type' => 'Combo-box', |
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number.' |
}, |
'JAw' => { |
'type' => 'Fixed', |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'default' => '32', |
'redefine_param' => 1, |
'content' => '' |
}, |
'Dw' => { |
'info' => 'probe/probe width in bits ', |
'type' => 'Spin-button', |
'content' => '1,32,1', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => '2' |
}, |
'JTAG_CONNECT' => { |
'info' => 'Parameter', |
'type' => 'Combo-box', |
'content' => '"ALTERA_JTAG_WB","XILINX_JTAG_WB" ', |
'redefine_param' => 1, |
'default' => '"XILINX_JTAG_WB"', |
'global_param' => 'Parameter' |
}, |
'WB2Jw' => { |
'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1', |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'type' => 'Fixed' |
}, |
'JINDEXw' => { |
'default' => '8', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'content' => '', |
'info' => 'Parameter', |
'type' => 'Fixed' |
}, |
'JDw' => { |
'info' => 'Parameter', |
'type' => 'Fixed', |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'default' => '32' |
}, |
'JSTATUSw' => { |
'info' => 'Parameter', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'content' => '', |
'default' => '8', |
'global_param' => 'Parameter' |
}, |
'J2WBw' => { |
'info' => 'Parameter', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Parameter', |
'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1' |
}, |
'JTAG_INDEX' => { |
'global_param' => 'Parameter', |
'default' => ' 0', |
'content' => '0,128,1', |
'redefine_param' => 1, |
'info' => ' A unique index number which will be used for adressing this source probe module.', |
'type' => 'Spin-button' |
} |
}, |
'modules' => { |
'pronoc_jtag_source_probe' => {} |
}, |
'version' => 5, |
'module_name' => 'pronoc_jtag_source_probe', |
'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_wb/pronoc_jtag_source_probe.v', |
'plugs' => { |
'clk' => { |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
} |
}, |
'description' => ' A source/probe that can be controled using xilinx bscan chain or Altera vjtag. ', |
'hdl_files' => [], |
'parameters_order' => [ |
'Dw', |
'JTAG_CONNECT', |
'JTAG_INDEX', |
'JDw', |
'JAw', |
'JINDEXw', |
'JSTATUSw', |
'J2WBw', |
'WB2Jw', |
'JTAG_CHAIN' |
], |
'category' => 'Communication', |
'sockets' => { |
'jtag_to_wb' => { |
'connection_num' => 'single connection', |
'type' => 'num', |
'0' => { |
'name' => 'jtag_to_wb' |
}, |
'value' => 1 |
} |
} |
}, 'ip_gen' ); |
/DMA/dma.IP
1,9 → 1,9
####################################################################### |
## File: dma.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
10,59 → 10,20
################################################################################ |
|
$ipgen = bless( { |
'description' => 'A wishbone bus round robin-based multi channel DMA (no byte enable is supported yet). The DMA supports burst data transaction.', |
'modules' => { |
'dma_multi_chan_wb' => {}, |
'shared_mem_fifos' => {}, |
'dma_single_wb' => {} |
}, |
'plugs' => { |
'clk' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'clk' => {} |
}, |
'wb_slave' => { |
'value' => 1, |
'wb_slave' => {}, |
'type' => 'num', |
'0' => { |
'width' => 10, |
'addr' => '0x9300_0000 0x93ff_ffff Memory Controller', |
'name' => 'wb_slave' |
} |
}, |
'interrupt_peripheral' => { |
'value' => 1, |
'interrupt_peripheral' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'interrupt_peripheral' |
} |
}, |
'wb_master' => { |
'1' => { |
'name' => 'wb_wr' |
}, |
'wb_master' => {}, |
'value' => 2, |
'type' => 'num', |
'0' => { |
'name' => 'wb_rd' |
} |
}, |
'reset' => { |
'type' => 'num', |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
} |
} |
}, |
'system_h' => '#define ${IP}_STATUS_REG (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_BURST_SIZE_ADDR_REG (*((volatile unsigned int *) ($BASE+4))) |
|
#define ${IP}_chanel ${chanel} |
#define ${IP}_DATA_SIZE_ADDR_REG(chanel) (*((volatile unsigned int *) ($BASE+8+(chanel<<5)))) |
#define ${IP}_RD_START_ADDR_REG(chanel) (*((volatile unsigned int *) ($BASE+12+(chanel<<5)))) |
#define ${IP}_WR_START_ADDR_REG(chanel) (*((volatile unsigned int *) ($BASE+16+(chanel<<5)))) |
|
// assign status= {rd_enable_binarry,wr_enable_binarry,chanel_rd_is_active,chanel_wr_is_active}; |
|
#define ${IP}_chanel_is_busy(chanel) ( (${IP}_STATUS_REG >> chanel) & 0x1) |
|
void ${IP}_initial (unsigned int burst_size) ; |
void ${IP}_transfer (unsigned int chanel, unsigned int read_start_addr, unsigned int data_size, unsigned int write_start_addr);', |
'ports_order' => [ |
'reset', |
'clk', |
93,8 → 54,31
'm_wr_ack_i', |
'irq' |
], |
'file_name' => 'mpsoc/rtl/src_peripheral/DMA/dma_multi_chanel_wb.v', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'bte_i', |
'rty_o', |
'err_o', |
'tag_i' |
], |
'plug:wb_master[1]' => [ |
'tag_o', |
'err_i', |
'dat_i', |
'bte_o', |
'rty_i' |
], |
'plug:wb_master[0]' => [ |
'tag_o', |
'err_i', |
'dat_o', |
'bte_o', |
'rty_i' |
] |
}, |
'parameters_order' => [ |
'CHANNEL', |
'chanel', |
'MAX_TRANSACTION_WIDTH', |
'MAX_BURST_SIZE', |
'FIFO_B', |
105,326 → 89,340
'TAGw', |
'SELw' |
], |
'ip_name' => 'dma', |
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v', |
'hdl_files' => [ |
'/mpsoc/src_noc/main_comp.v', |
'/mpsoc/src_noc/arbiter.v', |
'/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v', |
'/mpsoc/src_noc/flit_buffer.v' |
], |
'version' => 4, |
'module_name' => 'dma_multi_chan_wb', |
'description_pdf' => '/mpsoc/rtl/src_peripheral/DMA/DMA.pdf', |
'category' => 'DMA', |
'module_name' => 'dma_multi_chan_wb', |
'parameters' => { |
'M_Aw' => { |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => '32', |
'content' => '', |
'info' => 'Parameter', |
'global_param' => 'Parameter' |
}, |
'CHANNEL' => { |
'global_param' => 'Parameter', |
'info' => 'Number of DMA channels. |
In case there are multiple active DMA channels, Each time one single active DMA channel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter channel until its FIFO is not full and the number of sent data is smaller than the burst size.', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'default' => '1', |
'content' => '1,32,1' |
'plugs' => { |
'interrupt_peripheral' => { |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'interrupt_peripheral' => {} |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'SELw' => { |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'default' => '4', |
'type' => 'Fixed', |
'content' => '' |
'type' => 'num', |
'value' => 1 |
}, |
'reset' => { |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'reset' => {} |
}, |
'wb_master' => { |
'wb_master' => {}, |
'value' => 2, |
'1' => { |
'name' => 'wb_wr' |
}, |
'0' => { |
'name' => 'wb_rd' |
}, |
'type' => 'num' |
}, |
'Dw' => { |
'global_param' => 'Parameter', |
'info' => 'Wishbone bus Data size in bit', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'default' => '32', |
'content' => '8,1024,8' |
}, |
'FIFO_B' => { |
'global_param' => 'Parameter', |
'info' => 'Channel FIFO size in words. |
All channels will share same FPGA block RAM. Hence, the total needed Block RAM words is the multiplication of channel num in channel FIFO size. |
|
', |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'default' => '4', |
'type' => 'Combo-box', |
'redefine_param' => 1 |
'wb_slave' => { |
'wb_slave' => {}, |
'value' => 1, |
'0' => { |
'addr' => '0x9300_0000 0x93ff_ffff Memory Controller', |
'name' => 'wb_slave', |
'width' => 10 |
}, |
'type' => 'num' |
} |
}, |
'modules' => { |
'shared_mem_fifos' => {}, |
'dma_multi_chan_wb' => {}, |
'dma_single_wb' => {} |
}, |
'ports' => { |
'm_wr_addr_o' => { |
'range' => 'M_Aw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'MAX_BURST_SIZE' => { |
'global_param' => 'Parameter', |
'info' => 'Maximum burst size in words. |
The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active channels, another active channel will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ', |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'default' => '256' |
}, |
'DEBUG_EN' => { |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => '1', |
'global_param' => 'Parameter', |
'info' => 'Parameter' |
}, |
'TAGw' => { |
'default' => '3', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'content' => '', |
'info' => 'Parameter', |
'global_param' => 'Parameter' |
}, |
'S_Aw' => { |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => '8', |
'redefine_param' => 1, |
'content' => '' |
}, |
'MAX_TRANSACTION_WIDTH' => { |
'default' => '10', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'content' => '2,32,1', |
'info' => 'The width of maximum transaction size in words. |
The maximum data that can be sent via one DMA channel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.', |
'global_param' => 'Parameter' |
} |
}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'ports' => { |
'm_rd_sel_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'sel_o', |
'range' => 'SELw-1 : 0', |
'type' => 'output' |
}, |
'm_rd_stb_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'stb_o', |
'range' => '', |
'type' => 'output' |
}, |
'irq' => { |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'int_o', |
'intfc_name' => 'plug:interrupt_peripheral[0]' |
'range' => '' |
}, |
's_stb_i' => { |
'range' => '', |
'intfc_port' => 'stb_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'm_rd_ack_i' => { |
'range' => '', |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'ack_i' |
'intfc_name' => 'plug:wb_master[0]' |
}, |
's_cti_i' => { |
'intfc_port' => 'cti_i', |
's_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => 'TAGw-1 : 0' |
}, |
'm_wr_we_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'we_o', |
'range' => '', |
'type' => 'output' |
}, |
'm_rd_cyc_o' => { |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cyc_o' |
}, |
'm_wr_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => 'Dw-1 : 0' |
}, |
's_cyc_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i' |
}, |
'm_wr_ack_i' => { |
'range' => '', |
'm_rd_dat_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'ack_i' |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input', |
'range' => '' |
}, |
's_ack_o' => { |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
's_dat_o' => { |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'm_rd_cti_o' => { |
'range' => 'TAGw-1 : 0', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cti_o' |
'intfc_port' => 'cti_o', |
'range' => 'TAGw-1 : 0' |
}, |
's_dat_o' => { |
's_cti_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
'type' => 'input', |
'intfc_port' => 'cti_i', |
'range' => 'TAGw-1 : 0' |
}, |
's_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'type' => 'input', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
's_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i', |
'type' => 'input' |
}, |
'm_wr_stb_o' => { |
'intfc_port' => 'stb_o', |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
's_we_i' => { |
'type' => 'input', |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'm_wr_cyc_o' => { |
'm_wr_we_o' => { |
'range' => '', |
'intfc_port' => 'we_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'm_wr_dat_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'cyc_o', |
'range' => '', |
'type' => 'output' |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'dat_o' |
}, |
'm_wr_cti_o' => { |
'clk' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]' |
}, |
'm_wr_ack_i' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'cti_o', |
'range' => 'TAGw-1 : 0', |
'type' => 'output' |
'range' => '', |
'intfc_port' => 'ack_i', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'range' => '' |
}, |
'm_rd_dat_i' => { |
'type' => 'input', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i', |
'm_rd_cyc_o' => { |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'cyc_o', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
's_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
}, |
'm_wr_cyc_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'cyc_o', |
'type' => 'output', |
'range' => '' |
}, |
's_addr_i' => { |
'type' => 'input', |
'intfc_port' => 'adr_i', |
'range' => 'S_Aw-1 : 0', |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'm_rd_addr_o' => { |
'range' => 'M_Aw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'adr_o' |
}, |
's_dat_i' => { |
'range' => 'Dw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i' |
}, |
'm_wr_stb_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'stb_o', |
'range' => '', |
'type' => 'output' |
'm_rd_sel_o' => { |
'intfc_port' => 'sel_o', |
'type' => 'output', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'm_wr_addr_o' => { |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => 'M_Aw-1 : 0' |
}, |
'm_wr_sel_o' => { |
'intfc_port' => 'sel_o', |
'type' => 'output', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'm_rd_we_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'we_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
's_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '' |
}, |
'm_wr_sel_o' => { |
'm_wr_cti_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'sel_o', |
'range' => 'SELw-1 : 0', |
'range' => 'TAGw-1 : 0', |
'intfc_port' => 'cti_o', |
'type' => 'output' |
} |
}, |
'm_rd_stb_o' => { |
'range' => '', |
'intfc_port' => 'stb_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'intfc_port' => 'reset_i', |
'type' => 'input' |
}, |
'm_rd_addr_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => 'M_Aw-1 : 0', |
'intfc_port' => 'adr_o', |
'type' => 'output' |
} |
}, |
'system_h' => '#define ${IP}_STATUS_REG (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_BURST_SIZE_ADDR_REG (*((volatile unsigned int *) ($BASE+4))) |
'version' => 6, |
'hdl_files' => [ |
'/mpsoc/rtl/main_comp.v', |
'/mpsoc/rtl/arbiter.v', |
'/mpsoc/rtl/src_peripheral/DMA/dma_multi_chanel_wb.v' |
], |
'ip_name' => 'dma', |
'parameters' => { |
'TAGw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'default' => '3', |
'type' => 'Fixed', |
'content' => '' |
}, |
'M_Aw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'default' => '32', |
'content' => '', |
'type' => 'Fixed' |
}, |
'FIFO_B' => { |
'default' => '4', |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => 'chanel FIFO size in words. |
All chanels will share same FPGA block RAM. Hence, the total needed Block RAM words is the multiplication of chanel num in chanel FIFO size. |
|
|
#define ${IP}_CHANNEL ${CHANNEL} |
#define ${IP}_DATA_SIZE_ADDR_REG(channel) (*((volatile unsigned int *) ($BASE+8+(channel<<5)))) |
#define ${IP}_RD_START_ADDR_REG(channel) (*((volatile unsigned int *) ($BASE+12+(channel<<5)))) |
#define ${IP}_WR_START_ADDR_REG(channel) (*((volatile unsigned int *) ($BASE+16+(channel<<5)))) |
|
|
// assign status= {rd_enable_binarry,wr_enable_binarry,channel_rd_is_active,channel_wr_is_active}; |
|
#define ${IP}_channel_is_busy(channel) ( (${IP}_STATUS_REG >> channel) & 0x1) |
|
|
void ${IP}_initial (unsigned int burst_size) { |
' |
}, |
'MAX_BURST_SIZE' => { |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'type' => 'Combo-box', |
'default' => '256', |
'info' => 'Maximum burst size in words. |
The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active chanels, another active chanel will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ', |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'S_Aw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'default' => '8', |
'type' => 'Fixed', |
'content' => '' |
}, |
'MAX_TRANSACTION_WIDTH' => { |
'info' => 'The width of maximum transaction size in words. |
The maximum data that can be sent via one DMA chanel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '2,32,1', |
'default' => '10' |
}, |
'DEBUG_EN' => { |
'default' => '1', |
'type' => 'Fixed', |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'chanel' => { |
'content' => '1,32,1', |
'type' => 'Spin-button', |
'default' => '1', |
'info' => 'Number of DMA chanels. |
In case there are multiple active DMA chanels, Each time one single active DMA chanel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter chanel until its FIFO is not full and the number of sent data is smaller than the burst size.', |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'SELw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'default' => '4', |
'type' => 'Fixed', |
'content' => '' |
}, |
'Dw' => { |
'info' => 'Wishbone bus Data size in bit', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '8,1024,8', |
'type' => 'Spin-button', |
'default' => '32' |
} |
}, |
'system_c' => 'void ${IP}_initial (unsigned int burst_size) { |
${IP}_BURST_SIZE_ADDR_REG = burst_size; |
} |
|
|
void ${IP}_transfer (unsigned int channel, unsigned int read_start_addr, unsigned int data_size, unsigned int write_start_addr){ |
while ( ${IP}_channel_is_busy(channel)); // wait until DMA channel is busy |
${IP}_RD_START_ADDR_REG(channel) = read_start_addr; |
${IP}_DATA_SIZE_ADDR_REG(channel) = data_size; |
${IP}_WR_START_ADDR_REG(channel) = write_start_addr; |
void ${IP}_transfer (unsigned int chanel, unsigned int read_start_addr, unsigned int data_size, unsigned int write_start_addr){ |
while ( ${IP}_chanel_is_busy(chanel)); // wait until DMA chanel is busy |
${IP}_RD_START_ADDR_REG(chanel) = read_start_addr; |
${IP}_DATA_SIZE_ADDR_REG(chanel) = data_size; |
${IP}_WR_START_ADDR_REG(chanel) = write_start_addr; |
}', |
'description_pdf' => '/mpsoc/src_peripheral/DMA/DMA.pdf', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'rty_o', |
'bte_i', |
'err_o', |
'tag_i' |
], |
'plug:wb_master[0]' => [ |
'err_i', |
'dat_o', |
'rty_i', |
'bte_o', |
'tag_o' |
], |
'plug:wb_master[1]' => [ |
'err_i', |
'dat_i', |
'rty_i', |
'bte_o', |
'tag_o' |
] |
} |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'description' => 'A wishbone bus round robin-based multi chanel DMA (no byte enable is supported yet). The DMA supports burst data transaction.' |
}, 'ip_gen' ); |
/Display/lcd_2x16.IP
1,9 → 1,9
####################################################################### |
## File: lcd_2x16.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
10,197 → 10,289
################################################################################ |
|
$ipgen = bless( { |
'sw_params_list' => [], |
'system_h' => '#define ${IP}_WR_CMD (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_RD_CMD (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_WR_DATA (*((volatile unsigned int *) ($BASE+8))) |
#define ${IP}_RD_DATA (*((volatile unsigned int *) ($BASE+16))) |
'ports_order' => [ |
'clk', |
'reset', |
's_dat_i', |
's_addr_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
'lcd_en', |
'lcd_rs', |
'lcd_rw', |
'lcd_data' |
], |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'description' => '2x16 Character Alphabet Liquid Crystal Display (LCD) driver module ', |
'sw_files' => [], |
'modules' => { |
'lcd_2x16' => {} |
}, |
'plugs' => { |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'name' => 'wb', |
'width' => 5, |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
}, |
'type' => 'num', |
'wb_slave' => {} |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
} |
}, |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'reset' => {}, |
'value' => 1 |
} |
}, |
'system_h' => '#define ${IP}_WR_CMD (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_RD_CMD (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_WR_DATA (*((volatile unsigned int *) ($BASE+8))) |
#define ${IP}_RD_DATA (*((volatile unsigned int *) ($BASE+16))) |
#define ${IP}_CLK_MHZ $CLK_MHZ |
#define ${IP}_WAIT_CNT (${IP}_CLK_MHZ*100) |
#define ${IP}_COLUMN_NUM 16 |
#define ${IP}_ROW_NUM 2 |
|
#define ${IP}_CLK_MHZ $CLK_MHZ |
const char base_y[4]={0x80,0xc0,${IP}_COLUMN_NUM+0x80,${IP}_COLUMN_NUM+0xc0}; |
|
#include "$IP.h"', |
#define ${IP}_set_8_bit_1_line() ${IP}_wr_cmd_func(0x30) |
#define ${IP}_set_8_bit_2_line() ${IP}_wr_cmd_func(0x38) |
#define ${IP}_set_4_bit_1_line() ${IP}_wr_cmd_func(0x20) |
#define ${IP}_set_4_bit_3_line() ${IP}_wr_cmd_func(0x28) |
#define ${IP}_entry_mode() ${IP}_wr_cmd_func(0x06) |
|
//(clearing display without clearing ddram content) |
#define ${IP}_dsply_off_cursor_off() ${IP}_wr_cmd_func(0x08) |
#define ${IP}_dsply_on_cursor_on() ${IP}_wr_cmd_func(0x0e) |
#define ${IP}_dsply_on_cursor_off() ${IP}_wr_cmd_func(0x0c) |
#define ${IP}_dsply_on_cursor_blink() ${IP}_wr_cmd_func(0x0f) |
#define ${IP}_shift_dsply_left() ${IP}_wr_cmd_func(0x18) |
#define ${IP}_shift_dsply_right() ${IP}_wr_cmd_func(0x1c) |
#define ${IP}_shift_cursor_left() ${IP}_wr_cmd_func(0x10) |
#define ${IP}_shift_cursor_right() ${IP}_wr_cmd_func(0x14) |
|
//(also clear ddram content) |
#define ${IP}_clr_dsply() ${IP}_wr_cmd_func(0x01) |
#define ${IP}_goto_line(line_num) ${IP}_wr_cmd_func(base_y[line_num-1]) // 1<= lines num <= ${IP}_ROW_NUM |
#define ${IP}_gotoxy(x,y) ${IP}_wr_cmd_func(base_y[y]+x)// 0<= x< ${IP}_COLUMN_NUM; 0<= y < ${IP}_ROW_NUM |
#define ${IP}_show_character(c) ${IP}_wr_data_func(c); |
|
|
void ${IP}_wait(unsigned int volatile num); |
|
static inline void ${IP}_wr_cmd_func( char data){ |
${IP}_WR_CMD= data; |
${IP}_wait(${IP}_WAIT_CNT); |
} |
|
static inline void ${IP}_wr_data_func( char data){ |
${IP}_WR_DATA=data; |
${IP}_wait(${IP}_WAIT_CNT); |
} |
|
void ${IP}_init(void); |
void ${IP}_show_text(char* Text, unsigned char length); |
', |
'parameters_order' => [ |
'Dw', |
'Aw', |
'CLK_MHZ' |
], |
'module_name' => 'lcd_2x16', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'ip_name' => 'lcd_2x16', |
'category' => 'Display', |
'ports' => { |
'lcd_rw' => { |
'type' => 'output', |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'intfc_port' => 'IO' |
'type' => 'output' |
}, |
'lcd_en' => { |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'IO', |
'range' => '', |
'intfc_port' => 'IO', |
'type' => 'output' |
'intfc_port' => 'IO' |
}, |
's_we_i' => { |
'type' => 'input', |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
's_dat_o' => { |
'type' => 'output', |
's_dat_i' => { |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o' |
'type' => 'input', |
'intfc_port' => 'dat_i' |
}, |
'clk' => { |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'intfc_port' => 'clk_i' |
}, |
's_ack_o' => { |
'type' => 'output', |
'intfc_port' => 'ack_o', |
's_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
'type' => 'input' |
}, |
's_stb_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]', |
'range' => '' |
}, |
'lcd_data' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => ' 7: 0', |
'type' => 'inout' |
}, |
's_addr_i' => { |
'type' => 'input', |
'range' => 'Aw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i' |
}, |
'lcd_rs' => { |
'intfc_port' => 'IO', |
'range' => '', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'type' => 'output' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
}, |
's_dat_i' => { |
'type' => 'input', |
's_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => '' |
}, |
's_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i' |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'dat_o' |
}, |
's_cyc_i' => { |
's_stb_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'cyc_i' |
'intfc_port' => 'stb_i' |
}, |
's_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'intfc_port' => 'adr_i', |
'type' => 'input' |
}, |
'lcd_data' => { |
'range' => ' 7: 0', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'type' => 'inout' |
} |
's_we_i' => { |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'we_i' |
} |
}, |
'ports_order' => [ |
'clk', |
'reset', |
's_dat_i', |
's_addr_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
'lcd_en', |
'lcd_rs', |
'lcd_rw', |
'lcd_data' |
], |
'version' => 1, |
'gen_sw_files' => [ |
'/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16frename_sep_t${IP}.h' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'sel_i', |
'tag_i', |
'bte_i', |
'err_o', |
'rty_o', |
'cti_i' |
] |
}, |
'plugs' => { |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num', |
'value' => 1, |
'clk' => {} |
}, |
'wb_slave' => { |
'type' => 'num', |
'0' => { |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O', |
'name' => 'wb', |
'width' => 5 |
}, |
'value' => 1, |
'wb_slave' => {} |
}, |
'reset' => { |
'type' => 'num', |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1 |
} |
}, |
'modules' => { |
'lcd_2x16' => {} |
}, |
'category' => 'Display', |
'description' => '2x16 Character Alphabet Liquid Crystal Display (LCD) driver module ', |
'sw_params_list' => [], |
'module_name' => 'lcd_2x16', |
'ip_name' => 'lcd_2x16', |
'file_name' => 'mpsoc/rtl/src_peripheral/display/lcd_2x16/lcd_2x16.v', |
'system_c' => ' |
void ${IP}_wait(unsigned int volatile num){ |
while (num>0){ |
num--; |
asm volatile ("nop"); |
} |
return; |
} |
|
|
void ${IP}_init(void) |
{ |
${IP}_set_8_bit_2_line(); |
${IP}_dsply_on_cursor_off(); |
${IP}_clr_dsply(); |
${IP}_entry_mode(); |
${IP}_goto_line(1); |
} |
|
void ${IP}_show_text(char* Text, unsigned char length){ |
int i; |
for(i=0;i<length;i++) ${IP}_show_character(Text[i]); |
} |
|
#ifdef ${IP}_TEST_ENABLE |
//------------------------------------------------------------------------- |
|
void ${IP}_test(){ |
unsigned int x,y; |
|
// Initial ${IP} |
${IP}_init(); |
// Show Text to ${IP} |
for(y=1;y<=${IP}_ROW_NUM;y++) { |
${IP}_goto_line(y); |
${IP}_show_text((char*)test_text[y-1],16); |
} |
|
${IP}_wait(1000*${IP}_WAIT_CNT); |
${IP}_clr_dsply(); |
|
for(y=0;y<${IP}_ROW_NUM;y++){ |
for(x=0;x<${IP}_COLUMN_NUM;x++){ |
${IP}_gotoxy(x,y); |
${IP}_show_character(test_text[y][x]); |
${IP}_wait(500*${IP}_WAIT_CNT); |
} |
} |
} |
|
#endif', |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/display/lcd_2x16/lcd_2x16.v' |
], |
'parameters' => { |
'Dw' => { |
'default' => ' 8', |
'content' => '', |
'global_param' => 0, |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed' |
}, |
'CLK_MHZ' => { |
'default' => '100', |
'content' => '2,1000,2', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'global_param' => 0, |
'default' => '100', |
'info' => 'The LCD controller clock speed in MHZ. It will be used for measuring the lcd enable delay. You can define a larger value than the actual clk speed but not smaller.' |
'info' => 'The LCD controller clock speed in MHZ. It will be used for measuring the lcd enable delay. You can define a larger value than the actual clk speed but not smaller.', |
'type' => 'Spin-button' |
}, |
'Aw' => { |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 0, |
'default' => ' 2', |
'info' => undef, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'Dw' => { |
'type' => 'Fixed', |
'redefine_param' => 1, |
'content' => '', |
'info' => undef, |
'default' => ' 8', |
'global_param' => 0 |
'info' => undef |
} |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v' |
], |
'sw_files' => [] |
'version' => 3, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'rty_o', |
'tag_i', |
'err_o', |
'bte_i', |
'sel_i' |
] |
}, |
'gen_sw_files' => [ |
'frename_sep_t' |
] |
}, 'ip_gen' ); |
/GPIO/gpi.IP
1,9 → 1,9
####################################################################### |
## File: gpi.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
10,194 → 10,194
################################################################################ |
|
$ipgen = bless( { |
'modules' => { |
'gpo' => {}, |
'gpi' => {}, |
'gpio' => {} |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/gpio/gpio.v' |
], |
'module_name' => 'gpi', |
'category' => 'GPIO', |
'sockets' => {}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'bte_i', |
'cti_i' |
] |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'parameters_order' => [ |
'PORT_WIDTH', |
'Dw', |
'Aw', |
'TAGw', |
'SELw' |
], |
'file_name' => 'mpsoc/rtl/src_peripheral/gpio/gpio.v', |
'parameters' => { |
'PORT_WIDTH' => { |
'default' => ' 1', |
'redefine_param' => 1, |
'content' => '1,32,1', |
'info' => 'Input port width ', |
'global_param' => 'Parameter', |
'type' => 'Spin-button' |
}, |
'Dw' => { |
'info' => undef, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => 'PORT_WIDTH', |
'redefine_param' => 1, |
'content' => '' |
}, |
'TAGw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => ' 3', |
'content' => '', |
'info' => undef, |
'type' => 'Fixed' |
}, |
'SELw' => { |
'type' => 'Fixed', |
'redefine_param' => 1, |
'default' => ' 3', |
'default' => ' 4', |
'global_param' => 'Localparam', |
'info' => undef, |
'content' => '' |
}, |
'PORT_WIDTH' => { |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'info' => 'Input port width ', |
'content' => '1,32,1', |
'global_param' => 'Localparam', |
'default' => ' 1' |
}, |
'Aw' => { |
'info' => undef, |
'content' => '', |
'default' => ' 2', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => ' 2', |
'type' => 'Fixed' |
}, |
'Dw' => { |
'redefine_param' => 1, |
'content' => '', |
'info' => undef, |
'default' => 'PORT_WIDTH', |
'global_param' => 'Localparam', |
'info' => undef, |
'type' => 'Fixed' |
}, |
'SELw' => { |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'content' => '', |
'default' => ' 4', |
'redefine_param' => 1 |
} |
} |
}, |
'description' => 'General purpose Wishbone bus-based input port', |
'version' => 2, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'bte_i', |
'cti_i' |
] |
}, |
'module_name' => 'gpi', |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/gpio/gpio.v' |
], |
'parameters_order' => [ |
'PORT_WIDTH', |
'Dw', |
'Aw', |
'TAGw', |
'SELw' |
], |
'category' => 'GPIO', |
'sockets' => {}, |
'ip_name' => 'gpi', |
'version' => 3, |
'modules' => { |
'gpio' => {}, |
'gpo' => {}, |
'gpi' => {} |
}, |
'ports' => { |
'sa_dat_i' => { |
'range' => 'Dw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_tag_i' => { |
'range' => 'TAGw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'tag_i' |
}, |
'sa_cyc_i' => { |
'sa_stb_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'range' => '' |
}, |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
'range' => '' |
}, |
'sa_err_o' => { |
'range' => '', |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o' |
'range' => '' |
}, |
'sa_sel_i' => { |
'type' => 'input', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i' |
}, |
'clk' => { |
'range' => '', |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]' |
}, |
'sa_rty_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'rty_o' |
}, |
'sa_dat_i' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'reset' => { |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'intfc_port' => 'reset_i' |
}, |
'sa_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'dat_o' |
}, |
'sa_addr_i' => { |
'range' => 'Aw-1 : 0', |
'intfc_port' => 'adr_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'port_i' => { |
'range' => 'PORT_WIDTH-1 : 0', |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'type' => 'input', |
'intfc_port' => 'IO', |
'intfc_name' => 'IO' |
'range' => 'PORT_WIDTH-1 : 0' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'ack_o', |
'range' => '' |
}, |
'sa_we_i' => { |
'range' => '', |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_dat_o' => { |
'sa_cyc_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
'intfc_port' => 'cyc_i' |
}, |
'clk' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]' |
}, |
'sa_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '' |
'sa_sel_i' => { |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
} |
}, |
'plugs' => { |
'clk' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num', |
'clk' => {} |
}, |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'reset' => {}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_slave' => { |
'type' => 'num', |
'value' => 1, |
'wb_slave' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'wb', |
'width' => 5, |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
}, |
'value' => 1 |
} |
} |
}, |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num', |
'reset' => {} |
} |
}, |
'ip_name' => 'gpi', |
'system_h' => '#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8))) |
#define ${IP}_READ() ${IP}_READ_REG ' |
}, 'ip_gen' ); |
/GPIO/gpio.IP
1,9 → 1,9
####################################################################### |
## File: gpio.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
10,135 → 10,153
################################################################################ |
|
$ipgen = bless( { |
'file_name' => 'mpsoc/rtl/src_peripheral/gpio/gpio.v', |
'module_name' => 'gpio', |
'category' => 'GPIO', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cyc_i', |
'bte_i', |
'tag_i', |
'cti_i' |
] |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/gpio/gpio.v' |
], |
'ip_name' => 'gpio', |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v', |
'version' => 1, |
'modules' => { |
'gpi' => {}, |
'gpo' => {}, |
'gpio' => {}, |
'gpi' => {} |
'gpio' => {} |
}, |
'parameters' => { |
'Dw' => { |
'Aw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'info' => undef, |
'redefine_param' => 1, |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'default' => 'PORT_WIDTH' |
'default' => '2' |
}, |
'PORT_WIDTH' => { |
'redefine_param' => 1, |
'default' => '1', |
'type' => 'Spin-button', |
'content' => '1,32,1', |
'info' => undef, |
'default' => '1', |
'global_param' => 'Parameter' |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => undef |
}, |
'SELw' => { |
'default' => '4', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => undef, |
'content' => '' |
'default' => '4' |
}, |
'Aw' => { |
'Dw' => { |
'default' => 'PORT_WIDTH', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => undef, |
'content' => '', |
'global_param' => 'Localparam', |
'default' => '2' |
'redefine_param' => 1, |
'info' => undef |
} |
}, |
'description' => 'General purpose Wishbone bus-based input/output port', |
'plugs' => { |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'clk' => {}, |
'type' => 'num', |
'value' => 1 |
}, |
'wb_slave' => { |
'wb_slave' => {}, |
'value' => 1, |
'0' => { |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O', |
'name' => 'wb', |
'width' => 5 |
}, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
} |
}, |
'ip_name' => 'gpio', |
'sockets' => {}, |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/gpio/gpio.v' |
], |
'ports' => { |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => '' |
}, |
'reset' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]' |
}, |
'port_io' => { |
'type' => 'inout', |
'range' => 'PORT_WIDTH-1 : 0', |
'intfc_port' => 'IO', |
'intfc_name' => 'IO' |
}, |
'sa_dat_o' => { |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_stb_i' => { |
'intfc_port' => 'stb_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o' |
'range' => '' |
}, |
'sa_dat_i' => { |
'sa_sel_i' => { |
'type' => 'input', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_err_o' => { |
'intfc_port' => 'err_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '' |
}, |
'sa_stb_i' => { |
'range' => '', |
'sa_dat_i' => { |
'type' => 'input', |
'intfc_port' => 'stb_i', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_sel_i' => { |
'range' => 'SELw-1 : 0', |
'type' => 'input', |
'sa_rty_o' => { |
'type' => 'output', |
'intfc_port' => 'rty_o', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0' |
}, |
'sa_err_o' => { |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i' |
'type' => 'output', |
'intfc_port' => 'err_o' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]', |
'range' => '' |
}, |
'port_io' => { |
'intfc_name' => 'IO', |
'range' => 'PORT_WIDTH-1 : 0', |
'intfc_port' => 'IO', |
'type' => 'inout' |
}, |
'clk' => { |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input', |
'range' => '' |
}, |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
} |
'range' => '', |
'intfc_name' => 'plug:clk[0]' |
} |
}, |
'system_h' => '#define ${IP}_DIR_REG (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4))) |
147,7 → 165,15
#define ${IP}_DIR_SET(value) ${IP}_DIR_REG=value |
#define ${IP}_WRITE(value) ${IP}_WRITE _REG=value |
#define ${IP}_READ() ${IP}_READ_REG ', |
'sockets' => {}, |
'version' => 2, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cyc_i', |
'bte_i', |
'tag_i', |
'cti_i' |
] |
}, |
'parameters_order' => [ |
'PORT_WIDTH', |
'Dw', |
155,36 → 181,10
'SELw', |
'Dw' |
], |
'plugs' => { |
'clk' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'clk' => {} |
}, |
'reset' => { |
'type' => 'num', |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
} |
}, |
'wb_slave' => { |
'0' => { |
'width' => 5, |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O', |
'name' => 'wb' |
}, |
'type' => 'num', |
'value' => 1, |
'wb_slave' => {} |
} |
}, |
'description' => 'General purpose Wishbone bus-based input/output port', |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
} |
}, |
'category' => 'GPIO' |
}, 'ip_gen' ); |
/GPIO/gpo.IP
1,9 → 1,9
####################################################################### |
## File: gpo.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
10,196 → 10,196
################################################################################ |
|
$ipgen = bless( { |
'unused' => { |
'plug:wb_slave[0]' => [ |
'bte_i', |
'cti_i' |
] |
}, |
'parameters_order' => [ |
'PORT_WIDTH', |
'Aw', |
'TAGw', |
'SELw', |
'Dw' |
], |
'module_name' => 'gpo', |
'system_h' => '#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_WRITE(value) ${IP}_WRITE_REG=value |
|
', |
'sockets' => {}, |
'category' => 'GPIO', |
'version' => 2, |
'modules' => { |
'gpo' => {}, |
'gpi' => {}, |
'gpio' => {} |
}, |
'ip_name' => 'gpo', |
'version' => 3, |
'plugs' => { |
'clk' => { |
'type' => 'num', |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
} |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'value' => 1, |
'type' => 'num' |
'reset' => {} |
}, |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num', |
'clk' => {} |
}, |
'wb_slave' => { |
'0' => { |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O', |
'name' => 'wb', |
'width' => 5 |
}, |
'type' => 'num', |
'value' => 1, |
'wb_slave' => {}, |
'0' => { |
'name' => 'wb', |
'width' => 5, |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
} |
'value' => 1 |
} |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/gpio/gpio.v' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v', |
'file_name' => 'mpsoc/rtl/src_peripheral/gpio/gpio.v', |
'ports' => { |
'sa_sel_i' => { |
'type' => 'input', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'reset' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i' |
}, |
'sa_we_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
'sa_cyc_i' => { |
'type' => 'input', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i' |
}, |
'port_o' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => 'PORT_WIDTH-1 : 0', |
'type' => 'output' |
}, |
'sa_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'dat_i' |
}, |
'sa_stb_i' => { |
'intfc_port' => 'stb_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '' |
}, |
'sa_ack_o' => { |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'ack_o' |
}, |
'sa_sel_i' => { |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '' |
'type' => 'input' |
}, |
'sa_err_o' => { |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_we_i' => { |
'type' => 'input', |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_stb_i' => { |
'sa_rty_o' => { |
'range' => '', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
'type' => 'output', |
'intfc_port' => 'rty_o' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input' |
}, |
'port_o' => { |
'intfc_name' => 'IO', |
'range' => 'PORT_WIDTH-1 : 0', |
'type' => 'output', |
'intfc_port' => 'IO' |
}, |
'sa_tag_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'TAGw-1 : 0', |
'type' => 'input', |
'range' => 'TAGw-1 : 0', |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]' |
'intfc_port' => 'tag_i' |
}, |
'sa_rty_o' => { |
'sa_err_o' => { |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output' |
}, |
'sa_dat_i' => { |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
} |
} |
}, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'bte_i' |
] |
}, |
'system_h' => '#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_WRITE(value) ${IP}_WRITE_REG=value |
|
', |
'modules' => { |
'gpio' => {}, |
'gpi' => {}, |
'gpo' => {} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'ip_name' => 'gpo', |
'description' => 'General purpose Wishbone bus-based output port', |
'parameters' => { |
'Dw' => { |
'content' => '', |
'type' => 'Fixed', |
'default' => 'PORT_WIDTH', |
'global_param' => 'Localparam', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'PORT_WIDTH' => { |
'type' => 'Spin-button', |
'content' => '1,32,1', |
'global_param' => 'Parameter', |
'global_param' => 'Localparam', |
'default' => ' 1', |
'redefine_param' => 1, |
'info' => 'output port width' |
'info' => 'output port width', |
'content' => '1,32,1' |
}, |
'SELw' => { |
'type' => 'Fixed', |
'default' => ' 4', |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Localparam', |
'default' => ' 4', |
'info' => undef, |
'redefine_param' => 1 |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'Aw' => { |
'Dw' => { |
'content' => '', |
'info' => undef, |
'redefine_param' => 1, |
'info' => undef, |
'content' => '', |
'type' => 'Fixed', |
'default' => ' 2', |
'global_param' => 'Localparam' |
'default' => 'PORT_WIDTH', |
'global_param' => 'Localparam', |
'type' => 'Fixed' |
}, |
'TAGw' => { |
'info' => undef, |
'content' => '', |
'type' => 'Fixed', |
'default' => ' 3', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => undef |
} |
'type' => 'Fixed' |
}, |
'Aw' => { |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'default' => ' 2', |
'redefine_param' => 1, |
'content' => '', |
'info' => undef |
} |
}, |
'description' => 'General purpose Wishbone bus-based output port' |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/gpio/gpio.v' |
], |
'parameters_order' => [ |
'PORT_WIDTH', |
'Aw', |
'TAGw', |
'SELw', |
'Dw' |
], |
'module_name' => 'gpo', |
'sockets' => {}, |
'category' => 'GPIO' |
}, 'ip_gen' ); |
/Interrupt/ext_int.IP
16,10 → 16,11
'timeout' => 0, |
'status' => 'ideal' |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ext_int/ext_int.v', |
'file_name' => 'mpsoc/rtl/src_peripheral/ext_int/ext_int.v', |
'parameters' => { |
'TAGw' => { |
'type' => 'Fixed', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 0, |
'content' => '', |
26,7 → 27,8
'default' => '3' |
}, |
'SELw' => { |
'default' => '4', |
'redefine_param' => 1, |
'default' => '4', |
'content' => '', |
'global_param' => 0, |
'info' => undef, |
33,7 → 35,8
'type' => 'Fixed' |
}, |
'Dw' => { |
'info' => undef, |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'content' => '', |
40,7 → 43,8
'global_param' => 0 |
}, |
'EXT_INT_NUM' => { |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'info' => 'number of external interrupt pins.', |
'global_param' => 0, |
'content' => '1,32,1', |
47,7 → 51,8
'default' => '3' |
}, |
'Aw' => { |
'default' => '3', |
'redefine_param' => 1, |
'default' => '3', |
'global_param' => 0, |
'content' => '', |
'info' => undef, |
205,7 → 210,7
#define ${IP}_RD (*((volatile unsigned int *) ($BASE+16 )))', |
'ip_name' => 'ext_int', |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ext_int/ext_int.v' |
'/mpsoc/rtl/src_peripheral/ext_int/ext_int.v' |
], |
'category' => 'Interrupt', |
'modules' => { |
/Interrupt/int_ctrl.IP
1,133 → 1,268
####################################################################### |
## File: int_ctrl.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.7.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
## MAY CAUSE UNEXPECTED BEHAVIOR. |
################################################################################ |
|
$ipgen = bless( { |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/int_ctrl/int_ctrl.v', |
'sockets' => { |
'interrupt_peripheral' => { |
'connection_num' => 'single connection', |
'value' => 'INT_NUM', |
'0' => { |
'name' => 'int_periph' |
}, |
'interrupt_peripheral' => {}, |
'type' => 'param' |
} |
}, |
'parameters_order' => [ |
'INT_NUM', |
'Dw', |
'Aw', |
'SELw' |
], |
'ip_name' => 'int_ctrl', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'tag_i', |
'cyc_i', |
'bte_i', |
'cti_i' |
] |
}, |
'version' => 6, |
'system_h' => ' |
#define ${IP}_MER (*((volatile unsigned int *) ($BASE ))) |
#define ${IP}_IER (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_IAR (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_IPR (*((volatile unsigned int *) ($BASE+12 ))) |
|
#define ${IP}_INT_NUM ${INT_NUM} |
|
struct ihnd { |
void (*handler)(void); |
void *arg; |
}; |
|
/* Initialize routine */ |
int general_int_init (void); |
|
/* Add interrupt handler */ |
int general_int_add(unsigned long irq, void (* handler)(), void *arg); |
|
/* Disable interrupt */ |
int general_int_disable (unsigned long irq); |
|
/* Enable interrupt */ |
int general_int_enable(unsigned long irq); |
|
/* Main interrupt handler */ |
void general_int_main(); |
', |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/int_ctrl/int_ctrl.v' |
], |
'ports' => { |
'sa_dat_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0' |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_err_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '' |
'sa_dat_i' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'clk' => { |
'range' => '', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input' |
}, |
'int_o' => { |
'intfc_name' => 'plug:interrupt_cpu[0]', |
'intfc_port' => 'int_o', |
'reset' => { |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'output' |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]' |
}, |
'sa_stb_i' => { |
'sa_sel_i' => { |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_err_o' => { |
'range' => '', |
'intfc_port' => 'stb_i' |
}, |
'sa_rty_o' => { |
'intfc_port' => 'err_o', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'rty_o', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_sel_i' => { |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
'intfc_port' => 'stb_i', |
'range' => '' |
}, |
'sa_ack_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'we_i', |
'range' => '', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'int_o' => { |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
'intfc_port' => 'int_o', |
'type' => 'output', |
'intfc_name' => 'plug:interrupt_cpu[0]' |
}, |
'sa_dat_i' => { |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'intfc_port' => 'adr_i' |
}, |
'int_i' => { |
'type' => 'input', |
'range' => 'INT_NUM-1 : 0', |
'intfc_port' => 'int_i', |
'range' => 'INT_NUM-1 : 0', |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'type' => 'input' |
} |
'intfc_name' => 'socket:interrupt_peripheral[array]' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
} |
}, |
'version' => 1, |
'system_c' => '/* Interrupt handlers table */ |
struct ihnd int_handlers[${IP}_INT_NUM ]; |
|
/* Initialize routine */ |
int general_int_init (void) |
{ |
int i; |
for(i = 0; i <${IP}_INT_NUM; i++) { |
int_handlers[i].handler = 0; |
int_handlers[i].arg = 0; |
} |
${IP}_IER=0; |
${IP}_MER=0x3; |
return 0; |
} |
|
|
/* Add interrupt handler */ |
int general_int_add(unsigned long irq, void (* handler)(void), void *arg) |
{ |
if(irq >= ${IP}_INT_NUM) return -1; |
int_handlers[irq].handler = handler; |
int_handlers[irq].arg = arg; |
return 0; |
} |
|
|
|
/* Disable interrupt */ |
int general_int_disable (unsigned long irq) |
{ |
if(irq >=${IP}_INT_NUM) return -1; |
${IP}_IER &= ~(0x00000001L << irq); |
return 0; |
} |
|
/* Enable interrupt */ |
int general_int_enable(unsigned long irq) |
{ |
if(irq >= ${IP}_INT_NUM) return -1; |
${IP}_IER |= (0x00000001L << irq); |
return 0; |
} |
|
|
/* Main interrupt handler */ |
void general_int_main() |
{ |
unsigned long i = 0; |
unsigned long ipr =${IP}_IPR; |
while(i < 32) { |
if((ipr & (0x01L << i)) && (int_handlers[i].handler != 0)) { |
(*int_handlers[i].handler)( ); //(int_handlers[i].arg); |
} |
i++; |
} |
${IP}_IAR = ipr; // Acknowledge all Interrupts |
} |
|
', |
'modules' => { |
'int_ctrl' => {} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'sockets' => { |
'interrupt_peripheral' => { |
'type' => 'param', |
'0' => { |
'name' => 'int_periph' |
}, |
'interrupt_peripheral' => {}, |
'connection_num' => 'single connection', |
'value' => 'INT_NUM' |
} |
}, |
'description' => 'interrupt controller', |
'ip_name' => 'int_ctrl', |
'module_name' => 'int_ctrl', |
'category' => 'Interrupt', |
'parameters' => { |
'Dw' => { |
'content' => '', |
'default' => ' 32', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => undef |
}, |
'INT_NUM' => { |
'content' => '1,32,1', |
'default' => ' 3', |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'number of inerrupt.' |
}, |
'SELw' => { |
'content' => '', |
'default' => ' 4 ', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => undef |
}, |
'Aw' => { |
'content' => '', |
'info' => undef, |
'redefine_param' => 1, |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'default' => ' 3' |
} |
}, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'bte_i', |
'cti_i', |
'tag_i', |
'cyc_i' |
] |
}, |
'file_name' => 'mpsoc/rtl/src_peripheral/int_ctrl/int_ctrl.v', |
'parameters_order' => [ |
'INT_NUM', |
'Dw', |
'Aw', |
'SELw' |
], |
'plugs' => { |
'wb_slave' => { |
'wb_slave' => {}, |
'value' => 1, |
'type' => 'num', |
'0' => { |
'width' => 5, |
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller', |
'name' => 'wb' |
}, |
'type' => 'num', |
'value' => 1, |
'wb_slave' => {} |
'name' => 'wb', |
'width' => 5 |
} |
}, |
'reset' => { |
'type' => 'num', |
134,13 → 269,13
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'reset' => {} |
'reset' => {}, |
'value' => 1 |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'type' => 'num', |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
} |
147,58 → 282,10
}, |
'interrupt_cpu' => { |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'interrupt_cpu' |
} |
}, |
'type' => 'num' |
} |
}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'modules' => { |
'int_ctrl' => {} |
}, |
'category' => 'Interrupt', |
'module_name' => 'int_ctrl', |
'description' => 'interrupt controller', |
'parameters' => { |
'INT_NUM' => { |
'global_param' => 0, |
'info' => 'number of inerrupt.', |
'content' => '1,32,1', |
'type' => 'Spin-button', |
'default' => ' 3' |
}, |
'SELw' => { |
'type' => 'Fixed', |
'default' => ' 4 ', |
'global_param' => 0, |
'content' => '', |
'info' => undef |
}, |
'Aw' => { |
'type' => 'Fixed', |
'default' => ' 3', |
'global_param' => 0, |
'info' => undef, |
'content' => '' |
}, |
'Dw' => { |
'content' => '', |
'info' => undef, |
'global_param' => 0, |
'type' => 'Fixed', |
'default' => ' 32' |
} |
}, |
'system_h' => ' |
#define ${IP}_MER (*((volatile unsigned int *) ($BASE ))) |
#define ${IP}_IER (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_IAR (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_IPR (*((volatile unsigned int *) ($BASE+12 )))', |
'hdl_files' => [ |
'/mpsoc/src_peripheral/int_ctrl/int_ctrl.v' |
] |
} |
}, 'ip_gen' ); |
/NoC/ni_master.IP
1,352 → 1,634
####################################################################### |
## File: ni_master.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.1 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
## MAY CAUSE UNEXPECTED BEHAVIOR. |
################################################################################ |
|
$ipgen = bless( { |
'ports_order' => [ |
'reset', |
'clk', |
'current_e_addr', |
'current_r_addr', |
'chan_out', |
'chan_in', |
's_dat_i', |
's_sel_i', |
's_addr_i', |
's_cti_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
'm_send_sel_o', |
'm_send_addr_o', |
'm_send_cti_o', |
'm_send_stb_o', |
'm_send_cyc_o', |
'm_send_we_o', |
'm_send_dat_i', |
'm_send_ack_i', |
'm_receive_sel_o', |
'm_receive_dat_o', |
'm_receive_addr_o', |
'm_receive_cti_o', |
'm_receive_stb_o', |
'm_receive_cyc_o', |
'm_receive_we_o', |
'm_receive_ack_i', |
'irq' |
], |
'parameters' => { |
'CRC_EN' => { |
'redefine_param' => 1, |
'default' => '"NO"', |
'global_param' => 'Localparam', |
'info' => 'The parameter can be selected as "YES" or "NO". |
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ', |
'content' => '"YES","NO"', |
'type' => 'Combo-box' |
}, |
'SELw' => { |
'info' => 'Parameter', |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '4', |
'type' => 'Fixed' |
}, |
'MAX_TRANSACTION_WIDTH' => { |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '13', |
'info' => 'maximum packet size width in words. |
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.', |
'content' => '4,32,1' |
}, |
'EAw' => { |
'type' => 'Fixed', |
'default' => '16', |
'redefine_param' => 0, |
'global_param' => 'Parameter', |
'content' => '', |
'info' => undef |
}, |
'S_Aw' => { |
'type' => 'Fixed', |
'content' => '', |
'info' => 'Parameter', |
'default' => '8', |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'TAGw' => { |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '3', |
'info' => 'Parameter', |
'content' => '' |
}, |
'Dw' => { |
'info' => 'wishbone_bus data width in bits.', |
'content' => '32,256,8', |
'global_param' => 'Localparam', |
'default' => '32', |
'redefine_param' => 1, |
'type' => 'Spin-button' |
}, |
'M_Aw' => { |
'type' => 'Fixed', |
'info' => 'Parameter', |
'content' => 'Dw', |
'redefine_param' => 1, |
'default' => '32', |
'global_param' => 'Localparam' |
}, |
'MAX_BURST_SIZE' => { |
'default' => '16', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => 'Maximum burst size in words. |
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ', |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'type' => 'Combo-box' |
}, |
'RAw' => { |
'type' => 'Fixed', |
'redefine_param' => 0, |
'default' => '16', |
'global_param' => 'Parameter', |
'content' => '', |
'info' => undef |
}, |
'HDATA_PRECAPw' => { |
'type' => 'Spin-button', |
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.', |
'content' => '0,8,1', |
'global_param' => 'Localparam', |
'default' => '0', |
'redefine_param' => 1 |
} |
}, |
'plugs' => { |
'reset' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'reset' => {} |
}, |
'wb_slave' => { |
'type' => 'num', |
'0' => { |
'name' => 'wb_slave', |
'addr' => '0xb800_0000 0xbfff_ffff custom devices', |
'width' => 10 |
}, |
'wb_slave' => {}, |
'value' => 1 |
}, |
'wb_master' => { |
'1' => { |
'name' => 'wb_receive' |
}, |
'wb_master' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'wb_send' |
}, |
'value' => 2 |
}, |
'interrupt_peripheral' => { |
'value' => 1, |
'0' => { |
'name' => 'interrupt' |
}, |
'type' => 'num', |
'interrupt_peripheral' => {} |
}, |
'clk' => { |
'clk' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1 |
} |
}, |
'ports' => { |
'm_send_dat_i' => { |
'range' => 'Dw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'm_send_stb_o' => { |
'intfc_port' => 'stb_o', |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
's_addr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'S_Aw-1 : 0', |
'type' => 'input' |
}, |
'm_send_cti_o' => { |
'range' => 'TAGw-1 : 0', |
'intfc_port' => 'cti_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output' |
}, |
'chan_in' => { |
'range' => 'smartflit_chanel_t', |
'intfc_port' => 'chan_in', |
'type' => 'input', |
'intfc_name' => 'socket:ni[0]' |
}, |
'm_receive_sel_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'sel_o' |
}, |
'flit_in_wr' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_in_wr' |
}, |
'm_send_stb_o' => { |
'range' => '', |
'm_send_sel_o' => { |
'intfc_port' => 'sel_o', |
'range' => 'SELw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'stb_o', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
}, |
's_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'type' => 'input', |
'range' => 'SELw-1 : 0' |
}, |
'current_e_addr' => { |
'intfc_name' => 'socket:ni[0]', |
'type' => 'input', |
'intfc_port' => 'current_e_addr', |
'range' => 'EAw-1 : 0' |
}, |
'chan_out' => { |
'type' => 'output', |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'chan_out', |
'range' => 'smartflit_chanel_t' |
}, |
'm_send_we_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'we_o', |
'range' => '' |
}, |
's_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'type' => 'input', |
'range' => '' |
'range' => '', |
'intfc_port' => 'cyc_i' |
}, |
'irq' => { |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'int_o' |
}, |
'm_receive_ack_i' => { |
'intfc_port' => 'ack_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'range' => '' |
'type' => 'input' |
}, |
's_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'reset' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]' |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
}, |
's_dat_i' => { |
'intfc_port' => 'dat_i', |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'range' => '' |
}, |
'm_receive_addr_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'intfc_port' => 'adr_o', |
'range' => 'M_Aw-1 : 0' |
}, |
's_dat_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
'intfc_port' => 'dat_o' |
}, |
'm_send_ack_i' => { |
'intfc_port' => 'ack_i', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'input' |
}, |
'm_receive_cti_o' => { |
'range' => 'TAGw-1 : 0', |
'm_receive_cyc_o' => { |
'type' => 'output', |
'intfc_port' => 'cti_o', |
'intfc_name' => 'plug:wb_master[1]' |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '', |
'intfc_port' => 'cyc_o' |
}, |
'irq' => { |
'intfc_port' => 'int_o', |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'range' => '', |
'type' => 'output' |
}, |
'flit_out_wr' => { |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'flit_out_wr', |
'intfc_name' => 'socket:ni[0]' |
}, |
'credit_out' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'credit_out', |
'type' => 'output', |
'range' => 'V-1 : 0' |
}, |
's_dat_o' => { |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'flit_in' => { |
'type' => 'input', |
'range' => 'Fw-1 : 0', |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'flit_in' |
}, |
's_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'type' => 'input', |
'range' => '' |
}, |
'current_r_addr' => { |
'intfc_port' => 'current_r_addr', |
'intfc_name' => 'socket:ni[0]', |
'range' => 'RAw-1 : 0', |
'type' => 'input' |
}, |
'm_send_addr_o' => { |
'type' => 'output', |
'range' => 'M_Aw-1 : 0', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'adr_o' |
}, |
'm_send_sel_o' => { |
'type' => 'output', |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'sel_o' |
}, |
'm_receive_we_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'we_o' |
'type' => 'output' |
}, |
'm_receive_cyc_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'cyc_o', |
'type' => 'output', |
'range' => '' |
}, |
'm_receive_dat_o' => { |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[1]' |
'range' => 'Dw-1 : 0' |
}, |
'm_send_cti_o' => { |
'type' => 'output', |
'range' => 'TAGw-1 : 0', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cti_o' |
}, |
'm_send_we_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'we_o', |
'type' => 'output', |
'range' => '' |
}, |
's_cti_i' => { |
'range' => 'TAGw-1 : 0', |
's_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'cti_i', |
'intfc_name' => 'plug:wb_slave[0]' |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0' |
}, |
'flit_out' => { |
'range' => 'Fw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'flit_out', |
'intfc_name' => 'socket:ni[0]' |
}, |
'm_send_addr_o' => { |
'range' => 'M_Aw-1 : 0', |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output' |
}, |
's_we_i' => { |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'type' => 'input', |
'range' => '' |
'type' => 'input' |
}, |
'current_e_addr' => { |
'intfc_name' => 'socket:ni[0]', |
'intfc_port' => 'current_e_addr', |
'type' => 'input', |
'range' => 'EAw-1 : 0' |
}, |
's_addr_i' => { |
'range' => 'S_Aw-1 : 0', |
'intfc_port' => 'adr_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
's_ack_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'ack_o' |
}, |
'm_receive_stb_o' => { |
'range' => '', |
'intfc_port' => 'stb_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '', |
'type' => 'output' |
}, |
's_sel_i' => { |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
's_cti_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'cti_i', |
'range' => 'TAGw-1 : 0' |
}, |
'm_send_dat_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i' |
}, |
'm_send_cyc_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'cyc_o', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cyc_o' |
'type' => 'output' |
}, |
'credit_in' => { |
'intfc_port' => 'credit_in', |
'intfc_name' => 'socket:ni[0]', |
'range' => 'V-1 : 0', |
'type' => 'input' |
}, |
'm_receive_addr_o' => { |
'range' => 'M_Aw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[1]' |
} |
'm_receive_cti_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'intfc_port' => 'cti_o', |
'range' => 'TAGw-1 : 0' |
}, |
'm_send_ack_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'ack_i', |
'range' => '' |
}, |
'current_r_addr' => { |
'range' => 'RAw-1 : 0', |
'intfc_port' => 'current_r_addr', |
'type' => 'input', |
'intfc_name' => 'socket:ni[0]' |
}, |
's_stb_i' => { |
'range' => '', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
} |
}, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'tag_i', |
'err_o', |
'bte_i', |
'rty_o' |
], |
'plug:wb_master[0]' => [ |
'rty_i', |
'dat_o', |
'tag_o', |
'err_i', |
'bte_o' |
], |
'plug:wb_master[1]' => [ |
'dat_i', |
'rty_i', |
'tag_o', |
'err_i', |
'bte_o' |
] |
}, |
'parameters_order' => [ |
'TOPOLOGY', |
'ROUTE_NAME', |
'T1', |
'T2', |
'T3', |
'C', |
'V', |
'B', |
'Fpay', |
'MAX_TRANSACTION_WIDTH', |
'MAX_BURST_SIZE', |
'DEBUG_EN', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'Fw', |
'CRC_EN', |
'RAw', |
'EAw' |
'EAw', |
'HDATA_PRECAPw' |
], |
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf', |
'system_v' => '`define INCLUDE_TOPOLOGY_LOCALPARAM |
`include "topology_localparam.v"', |
'modules' => { |
'header_flit_generator' => {}, |
'ni_master' => {}, |
'ni_vc_dma' => {}, |
'vc_wb_slave_registers' => {}, |
'ovc_status' => {} |
}, |
'category' => 'NoC', |
'module_name' => 'ni_master', |
'description' => '', |
'ip_name' => 'ni_master', |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/ni/ni_vc_dma.v', |
'/mpsoc/rtl/src_peripheral/ni/ni_vc_wb_slave_regs.v', |
'/mpsoc/rtl/src_peripheral/ni/ni_master.sv', |
'/mpsoc/rtl/src_peripheral/ni/ni_crc32.v', |
'/mpsoc/rtl/main_comp.v', |
'/mpsoc/rtl/arbiter.v', |
'/mpsoc/rtl/src_topolgy/', |
'/mpsoc/rtl/src_noc/' |
], |
'file_name' => 'mpsoc/rtl/src_peripheral/ni/ni_master.v', |
'system_c' => '/* |
The NI initializing function. |
The burst_size must be <= $MAX_BURST_SIZE |
send_int_en :1: enable the intrrupt when a packet is sent 0 : This intrrupt is disabled |
save_int_en : 1: enable the intrrupt when a recived packet is saved on internal buffer 0 : This intrrupt is disabled |
got_pck_int_en : 1: enable the intrrupt when a packet is recived in NI. 0 : This intrrupt is disabled |
|
*/ |
void ${IP}_initial (unsigned int burst_size, unsigned char errors_int_en, unsigned char send_done_int_en, unsigned char save_done_int_en, unsigned char got_pck_int_en) { |
${IP}_BURST_SIZE_REG = burst_size; |
int i; |
for (i=0; i<${IP}_NUM_VCs;i++){ |
if(send_done_int_en) ${IP}_send_done_int_en(i); else ${IP}_send_done_int_disable(i); |
if(save_done_int_en) ${IP}_save_done_int_en(i); else ${IP}_save_done_int_disable(i); |
if(got_pck_int_en) ${IP}_got_pckt_int_en(i); else ${IP}_got_pckt_int_disable(i); |
if(errors_int_en) ${IP}_error_int_en(i); else ${IP}_error_int_disable(i); |
|
} |
} |
|
/* |
The NI message sent function: |
v: virtual chanel number which this packet should be sent to |
class_num: message class number. Diffrent message classes can be sent via isolated network resources to avoid protocol deadlock |
data_start_addr : The address pointer to the start location of the packet to be sent in the memory |
data_size: the message data size in words |
dest_phy_addr: the destination endpoint physical address. check phy_adr.h file for knowing each endpoint physical address |
|
*/ |
|
void ${IP}_transfer (unsigned int init_weight, unsigned int v, unsigned int class_num, unsigned char hdr_data, unsigned int data_start_addr, unsigned int data_size, unsigned int dest_phy_addr){ |
while (${IP}_send_is_busy(v)); // wait until VC is busy sending previous packet |
${IP}_SEND_HDR_DATA_REG(v) = hdr_data; |
${IP}_SEND_DATA_SIZE_REG(v) = data_size; |
${IP}_SEND_ADDR_POINTER_REG(v) = data_start_addr; |
${IP}_SEND_DEST_REG(v) = dest_phy_addr | (class_num<<16) | (init_weight<<24); |
|
} |
|
/* |
The NI message receiver function: |
v: virtual chanel number of the received packet |
data_start_addr : The address pointer to the start location of the memory where the newly arrived packet must be stored by NI in. |
max_buffer_size : The allocated receive-memory buffer size in words. |
*/ |
|
void ${IP}_receive (unsigned int v, unsigned int data_start_addr, unsigned int max_buffer_size, unsigned int start_index){ |
while (${IP}_receive_is_busy(v)); // wait until VC is busy saving previous packet |
${IP}_RECEIVE_ADDR_POINTER_REG(v) = data_start_addr; |
${IP}_RECEIVE_SATRT_INDEX_REG(v) = start_index ; |
${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) = max_buffer_size; |
${IP}_RECEIVE_CTRL_REG(v) = 1; |
}', |
'system_h' => '#include <stdint.h> |
#include "../phy_addr.h" |
#ifdef MULTI_CORE |
#include "../phy_addr.h" |
#endif |
|
/* NI wb registers addresses |
|
VC specefic registers |
address bits |
[4+Vw:4] [3:0] |
1 : CTRL_FLAGS: {invalid_send_req_err, burst_size_err_isr, send_data_size_err_isr, crc_miss_match_isr, rcive_buff_ovrflw_err_isr,got_packet_isr, |
packet_is_saved_isr, packet_is_sent_isr,got_any_errorint_en,got_packet_int_en, packet_is_saved_int_en, packet_is_sent_int_en, |
receive_is_busy, send_is_busy}; |
2 : SEND_DEST_WB_ADDR The destination router address |
3 : SEND_POINTER_WB_ADDR, The address of data to be sent in byte |
Virtual 4 : SEND_DATA_SIZE_WB_ADDR, The size of data to be sent in byte |
chanel 5 : SEND_HDR_DATA_WB_ADDR The heder data address |
number |
8 : RECEIVE_SRC_WB_ADDR The source router (the router which is sent this packet). |
9 : RECEIVE_POINTER_WB_ADDR The address pointer of reciever memory in byte |
10 : RECEIVE_DATA_SIZE_WB_ADDR The size of recieved data in byte |
11 : RECEIVE_MAX_BUFF_SIZ The reciver allocated buffer size in words. If the packet size is bigger than the buffer size the rest of ot will be discarred |
12 : RECEIVE_SATRT_INDEX_WB_ADDR The recived data is wrriten on RECEIVE_POINTER_WB_ADDR + RECEIVE_SATRT_INDEX_WB_ADDR. |
If the write address reach to the end of buffer pointer, it starts at the RECEIVE_POINTER_WB_ADDR. |
13 : RECEIVE_CTRL_WB_ADDR The NI reciever control register |
14 : RECEIVE_PRECAP_DATA_ADDR The address to the header filit data which can be precaptured befor buffering the actual data. |
|
/* NI wb registers addresses |
0 : STATUS1_WB_ADDR // status1: {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet}; |
1 : STATUS2_WB_ADDR // status2: {send_enable_binary,receive_enable_binary,vc_got_error,aT2_error_isr,got_pck_isr, save_done_isr,send_done_isr,aT2_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en}; |
2 : BURST_SIZE_WB_ADDR // The busrt size in words |
|
3 : SEND_DATA_SIZE_WB_ADDR, // The size of data to be sent in byte |
4 : SEND_STRT_WB_ADDR, // The address of data to be sent in byte |
5 : SEND_DEST_WB_ADDR // The destination router address |
6 : SEND_CTRL_WB_ADDR |
|
7 : RECEIVE_DATA_SIZE_WB_ADDR // The size of recieved data in byte |
8 : RECEIVE_STRT_WB_ADDR // The address pointer of reciever memory in byte |
9 : RECEIVE_SRC_WB_ADDR // The source router (the router which is sent this packet). |
10 : RECEIVE_CTRL_WB_ADDR // The NI reciever control register |
11 : RECEIVE_MAX_BUFF_SIZ // The receiver\'s allocated buffer size in words. If the packet size is bigger tha the buffer size the rest of will be discarred |
12 : ERROR_FLAGS // errors: {crc_miss_match,burst_size_error,send_data_size_error,rcive_buff_ovrflw_err}; |
|
Shared registers for all VCs |
address bits |
[5:0] |
0: STATUS1_WB_ADDR // status1: {send_vc_enable_binary, receive_vc_enable_binary, receive_vc_is_busy, send_vc_is_busy}; |
16: BURST_SIZE_WB_ADDR // The busrt size in words |
32: reserved |
|
*/ |
|
|
|
#define COREID ${CORE_ID} |
#define CORE_PHY_ADDR PHY_ADDR_ENDP_${CORE_ID} |
#define ${IP}_NUM_VCs ${V} |
#define ${IP}_HDATA_PRECAPw ${HDATA_PRECAPw} |
#define ${IP}_BYTE_EN ${BYTE_EN} |
|
//general registers |
#define ${IP}_STATUS1_REG (*((volatile unsigned int *) ($BASE))) //0 |
#define ${IP}_BURST_SIZE_REG (*((volatile unsigned int *) ($BASE+64))) //16 |
|
#define ${IP}_STATUS1_REG (*((volatile unsigned int *) ($BASE))) //0 |
#define ${IP}_STATUS2_REG (*((volatile unsigned int *) ($BASE+4))) //1 |
#define ${IP}_BURST_SIZE_REG (*((volatile unsigned int *) ($BASE+8))) //2 |
//VC contro registerl |
#define ${IP}_CTRL_FLAGS_REG(v) (*((volatile unsigned int *) ($BASE+4+(v<<6)))) //1 |
|
//Send VC registers |
#define ${IP}_SEND_DEST_REG(v) (*((volatile unsigned int *) ($BASE+8+(v<<6)))) //2 |
#define ${IP}_SEND_ADDR_POINTER_REG(v) (*((volatile unsigned int *) ($BASE+12+(v<<6)))) //3 |
#define ${IP}_SEND_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+16+(v<<6)))) //4 |
#define ${IP}_SEND_HDR_DATA_REG(v) (*((volatile unsigned int *) ($BASE+20+(v<<6)))) //5 |
|
#define ${IP}_NUM_VCs ${V} |
//Receives VC registers |
#define ${IP}_RECEIVE_SRC_REG(v) (*((volatile unsigned int *) ($BASE+32+(v<<6)))) //8 |
#define ${IP}_RECEIVE_ADDR_POINTER_REG(v) (*((volatile unsigned int *) ($BASE+36+(v<<6)))) //9 |
#define ${IP}_RECEIVE_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+40+(v<<6)))) //10 |
#define ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) (*((volatile unsigned int *) ($BASE+44+(v<<6)))) //11 |
#define ${IP}_RECEIVE_SATRT_INDEX_REG(v) (*((volatile unsigned int *) ($BASE+48+(v<<6)))) //12 |
#define ${IP}_RECEIVE_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+52+(v<<6)))) //13 |
#define ${IP}_RECEIVE_PRECAP_DATA_REG(v) (*((volatile unsigned int *) ($BASE+56+(v<<6)))) //14 |
|
#define ${IP}_SEND_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+12+(v<<6)))) //3 |
#define ${IP}_SEND_START_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+16+(v<<6)))) //4 |
#define ${IP}_SEND_DEST_REG(v) (*((volatile unsigned int *) ($BASE+20+(v<<6)))) //5 |
#define ${IP}_SEND_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+24+(v<<6)))) //6 |
//STATUS FLGs |
#define ANY_SENT_DONE_ISR_FLG (1<<0) |
#define ANY_SAVE_DONE_ISR_FLG (1<<1) |
#define ANY_GOT_PCK_ISR_FLG (1<<2) |
#define ANY_ERR_ISR_FLG (1<<3) |
|
#define ${IP}_RECEIVE_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+28+(v<<6)))) //7 |
#define ${IP}_RECEIVE_STRT_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+32+(v<<6)))) //8 |
#define ${IP}_RECEIVE_SRC_REG(v) (*((volatile unsigned int *) ($BASE+36+(v<<6)))) //9 |
#define ${IP}_RECEIVE_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+40+(v<<6)))) //10 |
#define ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) (*((volatile unsigned int *) ($BASE+44+(v<<6)))) //11 |
#define ${IP}_ERROR_FLAGS_REG(v) (*((volatile unsigned int *) ($BASE+48+(v<<6)))) //12 |
#define ${IP}_any_sent_done_isr_is_asserted() (( ${IP}_STATUS1_REG & ANY_SENT_DONE_ISR_FLG )!=0) |
#define ${IP}_any_save_done_isr_is_asserted() (( ${IP}_STATUS1_REG & ANY_SAVE_DONE_ISR_FLG )!=0) |
#define ${IP}_any_got_pck_isr_is_asserted() (( ${IP}_STATUS1_REG & ANY_GOT_PCK_ISR_FLG)!=0) |
#define ${IP}_any_err_isr_is_asserted() (( ${IP}_STATUS1_REG & ANY_ERR_ISR_FLG)!=0) |
|
|
|
// assign status1= {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet}; |
// assign status2= {send_enable_binary,receive_enable_binary,vc_got_error,aT2_error_isr,got_pck_isr, save_done_isr,send_done_isr,aT2_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en}; |
|
//CTRL FLGs: |
#define SEND_IS_BUSY_FLG (1<<0) |
#define RCV_IS_BUSY_FLG (1<<1) |
|
#define ${IP}_got_packet(v) ((${IP}_STATUS1_REG >> (v)) & 0x1) |
#define ${IP}_packet_is_saved(v) ((${IP}_STATUS1_REG >> (${V}+v)) & 0x1) |
#define ${IP}_receive_is_busy(v) ((${IP}_STATUS1_REG >> (2*${V}+v)) & 0x1) |
#define ${IP}_send_is_busy(v) ((${IP}_STATUS1_REG >> (3*${V}+v)) & 0x1) |
#define ${IP}_got_aT2_error(v) ((${IP}_STATUS2_REG >> (8+v)) & 0x1) |
#define SEND_DONE_INT_EN_FLG (1<<2) |
#define SAVE_DONE_INT_EN_FLG (1<<3) |
#define GOT_PCK_INT_EN_FLG (1<<4) |
#define ANY_ERR_INT_EN_FLG (1<<5) |
|
#define SEND_DONE_INT_EN (1<<0) |
#define SAVE_DONE_INT_EN (1<<1) |
#define GOT_PCK_INT_EN (1<<2) |
#define ERRORS_INT_EN (1<<3) |
#define ALL_INT_EN (SEND_DONE_INT_EN | SAVE_DONE_INT_EN | GOT_PCK_INT_EN | ERRORS_INT_EN) |
#define SEND_DONE_ISR_FLG (1<<6) |
#define SAVE_DONE_ISR_FLG (1<<7) |
#define GOT_PCK_ISR_FLG (1<<8) |
|
#define SEND_DONE_ISR (1<<4) |
#define SAVE_DONE_ISR (1<<5) |
#define GOT_PCK_ISR (1<<6) |
#define ERRORS_ISR (1<<7) |
#define BUFF_OVFLOW_ERR_ISR_FLG (1<<9) // This error happens when the receiver allocated buffer size is smaller than the received packet size |
#define CRC_MISS_MATCH_ISR_FLG (1<<10) // This error happens when the received packet CRC miss match |
#define SEND_DSIZE_ERR_ISR_FLG (1<<11) // This error happens when the send data size is not set |
#define BURST_SIZE_ERR_ISR_FLG (1<<12) // This error happens when the burst size is not set |
#define INVALID_SEND_REQ_ISR_FLG (1<<13) // This error happens when a new send request is received while the DMA is still busy sending previous packet |
|
#define ALL_INT_EN (SEND_DONE_INT_EN_FLG | SAVE_DONE_INT_EN_FLG | GOT_PCK_INT_EN_FLG | ANY_ERR_INT_EN_FLG) |
|
|
//errors = {crc_miss_match,illegal_send_req,burst_size_error,send_data_size_error,rcive_buff_ovrflw_err}; |
#define BUFF_OVER_FLOW_ERR (1<<0) // This error happens when the receiver allocated buffer size is smaller than the received packet size |
#define SEND_DATA_SIZE_ERR (1<<1) // This error happens when the send data size is not set |
#define BURST_SIZE_ERR (1<<2) // This error happens when the burst size is not set |
#define ILLEGAL_SEND_REQ (1<<3) // This error happens when a new send request is received while the DMA is still busy sending previous packet |
#define CRC_MISS_MATCH (1<<4) // This error happens when the received packet CRC miss match |
#define ${IP}_send_is_busy(v) ((${IP}_CTRL_FLAGS_REG(v) & SEND_IS_BUSY_FLG)!=0) |
#define ${IP}_send_is_free(v) ((${IP}_CTRL_FLAGS_REG(v) & SEND_IS_BUSY_FLG)==0) |
|
//ack intrrupts functions |
#define ${IP}_ack_send_done_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN |SEND_DONE_ISR)) |
#define ${IP}_ack_save_done_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | SAVE_DONE_ISR)) |
#define ${IP}_ack_got_pck_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | GOT_PCK_ISR)) |
#define ${IP}_ack_errors_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | ERRORS_ISR)) |
#define ${IP}_receive_is_busy(v) ((${IP}_CTRL_FLAGS_REG(v) & RCV_IS_BUSY_FLG)!=0) |
#define ${IP}_receive_is_free(v) ((${IP}_CTRL_FLAGS_REG(v) & RCV_IS_BUSY_FLG)==0) |
|
#define ${IP}_ack_all_isr() (${IP}_STATUS2_REG = ${IP}_STATUS2_REG) |
|
|
|
|
#define ${IP}_send_done_int_en(v) (${IP}_CTRL_FLAGS_REG(v) |= SEND_DONE_INT_EN_FLG) |
#define ${IP}_send_done_int_disable(v) (${IP}_CTRL_FLAGS_REG(v) &= ~SEND_DONE_INT_EN_FLG) |
#define ${IP}_save_done_int_en(v) (${IP}_CTRL_FLAGS_REG(v) |= SAVE_DONE_INT_EN_FLG) |
#define ${IP}_save_done_int_disable(v) (${IP}_CTRL_FLAGS_REG(v) &= ~SAVE_DONE_INT_EN_FLG) |
#define ${IP}_got_pckt_int_en(v) (${IP}_CTRL_FLAGS_REG(v) |= GOT_PCK_INT_EN_FLG) |
#define ${IP}_got_pckt_int_disable(v) (${IP}_CTRL_FLAGS_REG(v) &= ~GOT_PCK_INT_EN_FLG) |
#define ${IP}_error_int_en(v) (${IP}_CTRL_FLAGS_REG(v) |= ANY_ERR_INT_EN_FLG) |
#define ${IP}_error_int_disable(v) (${IP}_CTRL_FLAGS_REG(v) &= ~ANY_ERR_INT_EN_FLG) |
|
|
|
#define ${IP}_packet_is_sent(v) ((${IP}_CTRL_FLAGS_REG(v) & SEND_DONE_ISR_FLG)!=0) |
#define ${IP}_packet_is_saved(v) ((${IP}_CTRL_FLAGS_REG(v) & SAVE_DONE_ISR_FLG )!=0) |
#define ${IP}_got_packet(v) ((${IP}_CTRL_FLAGS_REG(v) & GOT_PCK_ISR_FLG)!=0) |
|
#define ${IP}_got_buff_ovf(v) ((${IP}_CTRL_FLAGS_REG(v) & BUFF_OVFLOW_ERR_ISR_FLG)!=0) |
#define ${IP}_got_crc_mismatch(v) ((${IP}_CTRL_FLAGS_REG(v) & CRC_MISS_MATCH_ISR_FLG)!=0) |
#define ${IP}_got_send_dsize_err(v) ((${IP}_CTRL_FLAGS_REG(v) & SEND_DSIZE_ERR_ISR_FLG)!=0) |
#define ${IP}_got_burst_size_err(v) ((${IP}_CTRL_FLAGS_REG(v) & BURST_SIZE_ERR_ISR_FLG)!=0) |
#define ${IP}_got_invalid_send_req(v) ((${IP}_CTRL_FLAGS_REG(v) & INVALID_SEND_REQ_ISR_FLG)!=0) |
|
|
|
//intrrupts ack functions |
#define ${IP}_ack_send_done_isr(v) (${IP}_CTRL_FLAGS_REG(v) &= (ALL_INT_EN | SEND_DONE_ISR_FLG)) |
#define ${IP}_ack_save_done_isr(v) (${IP}_CTRL_FLAGS_REG(v) &= (ALL_INT_EN | SAVE_DONE_ISR_FLG)) |
#define ${IP}_ack_got_pck_isr(v) (${IP}_CTRL_FLAGS_REG(v) &= (ALL_INT_EN | GOT_PCK_ISR_FLG)) |
|
#define ${IP}_ack_buff_ovf_isr(v) (${IP}_CTRL_FLAGS_REG(v) &= (ALL_INT_EN | BUFF_OVFLOW_ERR_ISR_FLG)) |
#define ${IP}_ack_crc_mismatch_isr(v) (${IP}_CTRL_FLAGS_REG(v) &= (ALL_INT_EN | CRC_MISS_MATCH_ISR_FLG)) |
#define ${IP}_ack_send_dsize_err_isr(v) (${IP}_CTRL_FLAGS_REG(v) &= (ALL_INT_EN | SEND_DSIZE_ERR_ISR_FLG)) |
#define ${IP}_ack_burst_size_err_isr(v) (${IP}_CTRL_FLAGS_REG(v) &= (ALL_INT_EN | BURST_SIZE_ERR_ISR_FLG)) |
#define ${IP}_ack_invalid_send_req_isr(v) (${IP}_CTRL_FLAGS_REG(v) &= (ALL_INT_EN | INVALID_SEND_REQ_ISR_FLG)) |
|
|
#define ${IP}_ack_all_isr(v) (${IP}_CTRL_FLAGS_REG(v) = ${IP}_CTRL_FLAGS_REG(v)) |
|
|
struct SRC_INFOS{ |
unsigned char r; // reserved |
unsigned char c; // message class |
353,8 → 635,8
int16_t addr; // phy_addr |
} ; |
|
inline struct SRC_INFOS get_src_info(unsigned char v){ |
struct SRC_INFOS src_info =*(struct SRC_INFOS *) (&ni_RECEIVE_SRC_REG(v)); |
static inline struct SRC_INFOS get_src_info(unsigned char v){ |
struct SRC_INFOS src_info =*(struct SRC_INFOS *) (&${IP}_RECEIVE_SRC_REG(v)); |
return src_info; |
} |
|
366,17 → 648,11
got_pck_int_en : 1: enable the intrrupt when a packet is recived in NI. 0 : This intrrupt is disabled |
|
*/ |
void ${IP}_initial (unsigned int burst_size, unsigned char errors_int_en, unsigned char send_int_en, unsigned char save_int_en, unsigned char got_pck_int_en) { |
${IP}_BURST_SIZE_REG = burst_size; |
if(errors_int_en) ${IP}_STATUS2_REG |= ERRORS_INT_EN; |
if(send_int_en) ${IP}_STATUS2_REG |= SEND_DONE_INT_EN; |
if(save_int_en) ${IP}_STATUS2_REG |= SAVE_DONE_INT_EN; |
if(got_pck_int_en) ${IP}_STATUS2_REG |= GOT_PCK_INT_EN; |
} |
void ${IP}_initial (unsigned int burst_size, unsigned char errors_int_en, unsigned char send_done_int_en, unsigned char save_done_int_en, unsigned char got_pck_int_en) ; |
|
/* |
The NI message sent function: |
v: virtual channel number which this packet should be sent to |
v: virtual chanel number which this packet should be sent to |
class_num: message class number. Diffrent message classes can be sent via isolated network resources to avoid protocol deadlock |
data_start_addr : The address pointer to the start location of the packet to be sent in the memory |
data_size: the message data size in words |
384,343 → 660,41
|
*/ |
|
void ${IP}_transfer (unsigned int init_weight, unsigned int v, unsigned int class_num, unsigned int data_start_addr, unsigned int data_size, unsigned int dest_phy_addr){ |
while (${IP}_send_is_busy(v)); // wait until VC is busy sending previous packet |
void ${IP}_transfer (unsigned int init_weight, unsigned int v, unsigned int class_num, unsigned char hdr_data, unsigned int data_start_addr, unsigned int data_size, unsigned int dest_phy_addr); |
|
${IP}_SEND_DATA_SIZE_REG(v) = data_size; |
${IP}_SEND_START_ADDR_REG(v) = data_start_addr; |
${IP}_SEND_DEST_REG(v) = dest_phy_addr | (class_num<<16) | (init_weight<<24); |
|
} |
|
/* |
The NI message receiver function: |
v: virtual channel number of the received packet |
v: virtual chanel number of the received packet |
data_start_addr : The address pointer to the start location of the memory where the newly arrived packet must be stored by NI in. |
max_buffer_size : The allocated receive-memory buffer size in words. |
*/ |
|
void ${IP}_receive (unsigned int v, unsigned int data_start_addr, unsigned int max_buffer_size){ |
while (${IP}_receive_is_busy(v)); // wait until VC is busy saving previous packet |
|
${IP}_RECEIVE_STRT_ADDR_REG(v) = data_start_addr; |
${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) = max_buffer_size; |
${IP}_RECEIVE_CTRL_REG(v) = 1; |
|
|
}', |
'parameters' => { |
'ROUTE_NAME' => { |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => '"XY" ', |
'redefine_param' => 1, |
'content' => '', |
'info' => 'Parameter' |
}, |
'Fpay' => { |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => ' 32', |
'redefine_param' => 1, |
'content' => '', |
'info' => 'Parameter' |
}, |
'TAGw' => { |
'default' => '3', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'content' => '', |
'info' => 'Parameter', |
'redefine_param' => 1 |
}, |
'S_Aw' => { |
'content' => '', |
'info' => 'Parameter', |
'redefine_param' => 1, |
'default' => '8', |
'global_param' => 'Localparam', |
'type' => 'Fixed' |
}, |
'T3' => { |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'default' => '1', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'content' => '' |
}, |
'MAX_BURST_SIZE' => { |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'info' => 'Maximum burst size in words. |
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ', |
'redefine_param' => 1, |
'default' => '16', |
'global_param' => 'Localparam', |
'type' => 'Combo-box' |
}, |
'M_Aw' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '32', |
'redefine_param' => 1, |
'content' => 'Dw', |
'info' => 'Parameter' |
}, |
'DEBUG_EN' => { |
'info' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'default' => ' 1', |
'type' => 'Fixed', |
'global_param' => 'Parameter' |
}, |
'SELw' => { |
'info' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'default' => '4', |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'Dw' => { |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'default' => '32', |
'redefine_param' => 1, |
'content' => '32,256,8', |
'info' => 'wishbone_bus data width in bits.' |
}, |
'Fw' => { |
'redefine_param' => 0, |
'content' => '', |
'info' => undef, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '2+V+Fpay' |
}, |
'B' => { |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => ' 4', |
'redefine_param' => 1, |
'content' => '', |
'info' => 'Parameter' |
}, |
'CRC_EN' => { |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'default' => '"NO"', |
'redefine_param' => 1, |
'info' => 'The parameter can be selected as "YES" or "NO". |
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ', |
'content' => '"YES","NO"' |
}, |
'V' => { |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'default' => '4', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'content' => '' |
}, |
'RAw' => { |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'default' => '16', |
'redefine_param' => 0, |
'info' => undef, |
'content' => '' |
}, |
'T2' => { |
'content' => '', |
'info' => 'Parameter', |
'redefine_param' => 1, |
'default' => ' 4', |
'global_param' => 'Parameter', |
'type' => 'Fixed' |
}, |
'T1' => { |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => ' 4', |
'redefine_param' => 1, |
'content' => '', |
'info' => 'Parameter' |
}, |
'TOPOLOGY' => { |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => '"MESH"', |
'redefine_param' => 1, |
'content' => '', |
'info' => 'Parameter' |
}, |
'EAw' => { |
'redefine_param' => 0, |
'content' => '', |
'info' => undef, |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => '16' |
}, |
'C' => { |
'default' => ' 4', |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'info' => 'Parameter', |
'content' => '', |
'redefine_param' => 1 |
}, |
'MAX_TRANSACTION_WIDTH' => { |
'default' => '13', |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'info' => 'maximum packet size width in words. |
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.', |
'content' => '4,32,1', |
'redefine_param' => 1 |
} |
void ${IP}_receive (unsigned int v, unsigned int data_start_addr, unsigned int max_buffer_size, unsigned int start_index);', |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'plugs' => { |
'wb_master' => { |
'type' => 'num', |
'0' => { |
'name' => 'wb_send' |
}, |
'value' => 2, |
'1' => { |
'name' => 'wb_receive' |
}, |
'wb_master' => {} |
}, |
'interrupt_peripheral' => { |
'type' => 'num', |
'0' => { |
'name' => 'interrupt' |
}, |
'value' => 1, |
'interrupt_peripheral' => {} |
}, |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num', |
'reset' => {} |
}, |
'wb_slave' => { |
'wb_slave' => {}, |
'value' => 1, |
'0' => { |
'addr' => '0xb800_0000 0xbfff_ffff custom devices', |
'width' => 10, |
'name' => 'wb_slave' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'clk' => {} |
} |
}, |
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_master.v', |
'ip_name' => 'ni_master', |
'system_v' => '`define INCLUDE_TOPOLOGY_LOCALPARAM |
`include "topology_localparam.v"', |
'modules' => { |
'ni_master' => {}, |
'ovc_status' => {}, |
'vc_wb_slave_registers' => {}, |
'ni_vc_dma' => {}, |
'header_flit_generator' => {} |
}, |
'version' => 84, |
'description_pdf' => '/mpsoc/rtl/src_peripheral/ni/NI.pdf', |
'category' => 'NoC', |
'sockets' => { |
'ni' => { |
'connection_num' => 'single connection', |
'ni' => {}, |
'value' => 1, |
'0' => { |
'name' => 'ni' |
}, |
'ni' => {}, |
'value' => 1, |
'connection_num' => 'single connection', |
'type' => 'num' |
} |
}, |
'ports_order' => [ |
'reset', |
'clk', |
'current_e_addr', |
'current_r_addr', |
'flit_out', |
'flit_out_wr', |
'credit_in', |
'flit_in', |
'flit_in_wr', |
'credit_out', |
's_dat_i', |
's_sel_i', |
's_addr_i', |
's_cti_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
'm_send_sel_o', |
'm_send_addr_o', |
'm_send_cti_o', |
'm_send_stb_o', |
'm_send_cyc_o', |
'm_send_we_o', |
'm_send_dat_i', |
'm_send_ack_i', |
'm_receive_sel_o', |
'm_receive_dat_o', |
'm_receive_addr_o', |
'm_receive_cti_o', |
'm_receive_stb_o', |
'm_receive_cyc_o', |
'm_receive_we_o', |
'm_receive_ack_i', |
'irq' |
], |
'description' => '', |
'unused' => { |
'plug:wb_master[1]' => [ |
'tag_o', |
'dat_i', |
'bte_o', |
'err_i', |
'rty_i' |
], |
'plug:wb_master[0]' => [ |
'tag_o', |
'bte_o', |
'err_i', |
'dat_o', |
'rty_i' |
], |
'plug:wb_slave[0]' => [ |
'tag_i', |
'err_o', |
'rty_o', |
'bte_i' |
] |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'hdl_files' => [ |
'/mpsoc/src_noc/arbiter.v', |
'/mpsoc/src_noc/flit_buffer.v', |
'/mpsoc/src_noc/input_ports.v', |
'/mpsoc/src_noc/main_comp.v', |
'/mpsoc/src_noc/route_mesh.v', |
'/mpsoc/src_noc/route_torus.v', |
'/mpsoc/src_noc/routing.v', |
'/mpsoc/src_peripheral/ni/ni_vc_dma.v', |
'/mpsoc/src_peripheral/ni/ni_vc_wb_slave_regs.v', |
'/mpsoc/src_peripheral/ni/ni_master.v', |
'/mpsoc/src_peripheral/ni/ni_crc32.v', |
'/mpsoc/src_noc/topology_localparam.v' |
], |
'module_name' => 'ni_master', |
'version' => 60 |
} |
}, 'ip_gen' ); |
/NoC/ni_slave.IP
375,7 → 375,7
|
/* |
The NI message sent function: |
v: virtual channel number which this packet should be sent to |
v: virtual chanel number which this packet should be sent to |
class_num: message class number. Diffrent message classes can be sent via isolated network resources to avoid protocol deadlock |
data_start_addr : The address pointer to the start location of the packet inside the NI internal buffer |
data_size: the message data size in words |
395,7 → 395,7
|
/* |
The NI message receiver function: |
v: virtual channel number of the received packet |
v: virtual chanel number of the received packet |
data_start_addr : The address pointer to the start location of the memory where the newly arrived packet must be stored by NI in. |
max_buffer_size : The allocated receive-memory buffer size in words. |
*/ |
736,7 → 736,7
], |
'version' => 47, |
'module_name' => 'ni_slave', |
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_slave.v', |
'file_name' => 'mpsoc/src_peripheral/ni/ni_slave.v', |
'plugs' => { |
'reset' => { |
'reset' => {}, |
/Other/dummy_module.IP
11,7 → 11,7
|
$wb_master_dummy_request = bless( { |
'version' => 1, |
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/wb_master_dummy_request.v', |
'file_name' => 'mpsoc/rtl/src_peripheral/DMA/wb_master_dummy_request.v', |
'ip_name' => 'dummy_module', |
'ports' => { |
'clk' => { |
190,7 → 190,7
'status' => 'ideal' |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/Other/wb_master_dummy_request.v' |
'/mpsoc/rtl/src_peripheral/Other/wb_master_dummy_request.v' |
], |
'category' => 'Other', |
'unused' => { |
/Other/fout_sim.IP
0,0 → 1,233
####################################################################### |
## File: fout_sim.IP |
## |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAVIOR. |
################################################################################ |
|
$ipgen = bless( { |
'version' => 29, |
'sw_files' => [ |
'/mpsoc/src_processor/src_lib/simple-printf' |
], |
'modules' => { |
'fout_simulator' => {} |
}, |
'ip_name' => 'fout_sim', |
'module_name' => 'fout_simulator', |
'parameters' => { |
'BUFFER_SIZE' => { |
'content' => '10,1024,1', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'info' => 'Buffer width for getting for getting fle name.', |
'type' => 'Spin-button', |
'default' => '255 ' |
} |
}, |
'hdl_files_ticked' => [], |
'ports' => { |
's_we_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'range' => '' |
}, |
's_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '' |
}, |
's_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '' |
}, |
's_addr_i' => { |
'range' => '2 : 0', |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
's_dat_o' => { |
'range' => '31 : 0', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'range' => '' |
}, |
's_dat_i' => { |
'range' => '31 : 0', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
's_cti_i' => { |
'intfc_port' => 'cti_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => '2 : 0' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'range' => '' |
}, |
's_sel_i' => { |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => '3 : 0' |
}, |
's_stb_i' => { |
'range' => '', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'system_c' => '#define MODE_NOT_SOPPRTED 0 |
#define MODE_CLOSE 1 |
#define MODE_W 2 |
#define MODE_WB 3 |
#define MODE_A 4 |
#define MODE_AB 5 |
|
FILE file_ptr [50]={0}; |
FILE * fopen (const char *filename, const char *mode){ |
//alloacte a new pointer; |
int i=0; |
while(file_ptr [i]!=0 && i<50) i++; |
if(i==50) return ((FILE *)0) ; |
//set file ,ode |
if (mode[0] == \'w\' ){ |
if(mode[1]==\'b\') ${IP}_FILE_MODE = MODE_WB; |
else ${IP}_FILE_MODE = MODE_W; |
}else if (mode[0] == \'a\' ){ |
if(mode[1]==\'b\') ${IP}_FILE_MODE = MODE_AB; |
else ${IP}_FILE_MODE = MODE_A; |
}else { // not supported mode |
//${IP}_FILE_MODE = MODE_NOT_SOPPRTED; |
return ((FILE *)0); |
} |
|
|
file_ptr [i]=i+1; |
//send file pointer |
${IP}_GET_FLE_PTR = file_ptr [i]; |
//send file name |
do{ |
${IP}_GET_FILE_NAME = *filename; |
filename++; |
}while(*filename!=0); |
// activate the Verilog Fwrite command once sending zero |
${IP}_GET_FILE_NAME = 0; |
return (& file_ptr[i]); |
} |
|
|
|
void fclose(FILE * f){ |
//write file pointer |
${IP}_GET_FLE_PTR = *f; |
${IP}_FILE_MODE = MODE_CLOSE; // activate the Verilog fclose |
*f = 0; //set free the pointer |
} |
|
void foutbyte( char c){ |
//write content |
${IP}_GET_FILE_CONTENT = c; |
} |
|
void fout_select (FILE *f){ |
//write file pointer |
${IP}_GET_FLE_PTR = *f; |
} |
|
#include "simple-printf/sim_fprintf.c" |
', |
'category' => 'Other', |
'description' => 'A simple module to replicate the fprintf/fopen instructions in simulator enviremets. ', |
'file_name' => '/home/alireza/work/git/hca_git/ProNoC/mpsoc/rtl/src_peripheral/Other/fout_simulator.v', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'tag_i', |
'rty_o', |
'bte_i', |
'err_o' |
] |
}, |
'ports_order' => [ |
'reset', |
'clk', |
's_dat_i', |
's_sel_i', |
's_addr_i', |
's_cti_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o' |
], |
'plugs' => { |
'reset' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'reset' |
} |
}, |
'wb_slave' => { |
'0' => { |
'name' => 'wb_slave', |
'width' => 5, |
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller' |
}, |
'type' => 'num', |
'value' => 1 |
}, |
'clk' => { |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
} |
} |
}, |
'parameters_order' => [ |
'BUFFER_SIZE' |
], |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/Other/fout_simulator.v' |
], |
'system_h' => '#include "simple-printf/sim_fprintf.h" |
|
#define ${IP}_GET_FLE_PTR (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_GET_FILE_NAME (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_GET_FILE_CONTENT (*((volatile unsigned int *) ($BASE+8))) |
#define ${IP}_FILE_MODE (*((volatile unsigned int *) ($BASE+12))) |
|
#define FILE char |
|
FILE * fopen (const char *filename, const char *mode); |
void fclose(FILE * f); |
void foutbyte(char c); |
void fout_select(FILE * f);' |
}, 'ip_gen' ); |
/Other/gcd.IP
1,199 → 1,148
####################################################################### |
## File: gcd.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
## MAY CAUSE UNEXPECTED BEHAVIOR. |
################################################################################ |
|
$ipgen = bless( { |
'parameters' => { |
'SELw' => { |
'type' => 'Fixed', |
'default' => '4', |
'content' => '', |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'redefine_param' => 1 |
}, |
'GCDw' => { |
'global_param' => 'Parameter', |
'default' => '32', |
'type' => 'Combo-box', |
'content' => '8,16,32', |
'info' => 'GCD\'s Input/output width in bits', |
'redefine_param' => 1 |
}, |
'TAGw' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'default' => '3' |
}, |
'Dw' => { |
'default' => 'GCDw', |
'type' => 'Fixed', |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'Aw' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'default' => '5', |
'type' => 'Fixed', |
'content' => '', |
'global_param' => 'Localparam' |
} |
}, |
'system_h' => '#define ${IP}_DONE_ADDR (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_IN_1_ADDR (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_IN_2_ADDR (*((volatile unsigned int *) ($BASE+8))) |
#define ${IP}_GCD_ADDR (*((volatile unsigned int *) ($BASE+12))) |
|
|
#define ${IP}_IN1_WRITE(value) ${IP}_IN_1_ADDR=value |
#define ${IP}_IN2_WRITE(value) ${IP}_IN_2_ADDR=value |
#define ${IP}_DONE_READ() ${IP}_DONE_ADDR |
#define ${IP}_READ() ${IP}_GCD_ADDR |
|
unsigned int gcd_hardware ( unsigned int p, unsigned int q );', |
'system_c' => 'unsigned int gcd_hardware ( unsigned int p, unsigned int q ){ |
${IP}_IN1_WRITE(p); |
${IP}_IN2_WRITE(q); |
while (${IP}_DONE_READ()!=1); |
return ${IP}_READ(); |
}', |
'ports' => { |
's_tag_i' => { |
'intfc_port' => 'tag_i', |
's_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'type' => 'input', |
'range' => 'TAGw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
'range' => '' |
}, |
's_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'type' => 'output' |
}, |
's_stb_i' => { |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'stb_i' |
'range' => '' |
}, |
's_dat_i' => { |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => 'Dw-1 : 0' |
'type' => 'input' |
}, |
's_cyc_i' => { |
'intfc_port' => 'cyc_i', |
's_rty_o' => { |
'range' => '', |
'intfc_port' => 'rty_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => '' |
'type' => 'output' |
}, |
'clk' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i' |
}, |
's_sel_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
'range' => 'SELw-1 : 0' |
}, |
's_rty_o' => { |
'intfc_port' => 'rty_o', |
's_ack_o' => { |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
's_we_i' => { |
'range' => '', |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input' |
}, |
'reset' => { |
'range' => '', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i' |
}, |
's_tag_i' => { |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => 'TAGw-1 : 0' |
}, |
's_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => 'Aw-1 : 0' |
}, |
's_err_o' => { |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o' |
}, |
's_ack_o' => { |
'intfc_port' => 'ack_o', |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
's_we_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
}, |
's_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => 'Dw-1 : 0' |
'intfc_port' => 'err_o', |
'range' => '' |
} |
}, |
'ip_name' => 'gcd', |
'modules' => { |
'gcd_ip' => {} |
}, |
'file_name' => '/home/alireza/mywork/workshop/files/gcd_ip.v', |
'category' => 'Other', |
'version' => 3, |
'parameters_order' => [ |
'GCDw', |
'Dw', |
'Aw', |
'TAGw', |
'SELw' |
], |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'bte_i' |
] |
}, |
'version' => 4, |
'module_name' => 'gcd_ip', |
'plugs' => { |
'clk' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1 |
'type' => 'num' |
}, |
'wb_slave' => { |
'value' => 1, |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'wb_slave', |
'width' => 5, |
'addr' => '0xb800_0000 0xbfff_ffff custom devices', |
'name' => 'wb_slave' |
'addr' => '0xb800_0000 0xbfff_ffff custom devices' |
} |
}, |
'reset' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'reset' |
} |
}, |
'value' => 1 |
} |
}, |
'system_h' => '#define ${IP}_DONE_ADDR (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_IN_1_ADDR (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_IN_2_ADDR (*((volatile unsigned int *) ($BASE+8))) |
#define ${IP}_GCD_ADDR (*((volatile unsigned int *) ($BASE+12))) |
|
|
#define ${IP}_IN1_WRITE(value) ${IP}_IN_1_ADDR=value |
#define ${IP}_IN2_WRITE(value) ${IP}_IN_2_ADDR=value |
#define ${IP}_DONE_READ() ${IP}_DONE_ADDR |
#define ${IP}_READ() ${IP}_GCD_ADDR |
|
unsigned int gcd_hardware ( unsigned int p, unsigned int q ){ |
${IP}_IN1_WRITE(p); |
${IP}_IN2_WRITE(q); |
while (${IP}_DONE_READ()!=1); |
return ${IP}_READ(); |
}', |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'description' => 'gcd module', |
'module_name' => 'gcd_ip', |
'file_name' => '/home/alireza/mywork/workshop/files/gcd_ip.v', |
'ports_order' => [ |
'clk', |
'reset', |
209,14 → 158,67
's_err_o', |
's_rty_o' |
], |
'parameters_order' => [ |
'GCDw', |
'Dw', |
'Aw', |
'TAGw', |
'SELw' |
], |
'hdl_files_ticked' => [], |
'parameters' => { |
'Aw' => { |
'global_param' => 'Localparam', |
'default' => '5', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'info' => 'Parameter' |
}, |
'Dw' => { |
'info' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'default' => 'GCDw' |
}, |
'GCDw' => { |
'info' => 'GCD\'s Input/output width in bits', |
'global_param' => 'Parameter', |
'default' => '32', |
'content' => '8,16,32', |
'redefine_param' => 1, |
'type' => 'Combo-box' |
}, |
'SELw' => { |
'info' => 'Parameter', |
'global_param' => 'Localparam', |
'default' => '4', |
'redefine_param' => 1, |
'content' => '', |
'type' => 'Fixed' |
}, |
'TAGw' => { |
'info' => 'Parameter', |
'type' => 'Fixed', |
'content' => '', |
'redefine_param' => 1, |
'default' => '3', |
'global_param' => 'Localparam' |
} |
}, |
'category' => 'Other', |
'description' => 'gcd module', |
'hdl_files' => [ |
'/workshop/files/gcd.v', |
'/workshop/files/gcd_ip.v' |
'/mpsoc/rtl/src_peripheral/Other/gcd_ip.v', |
'/mpsoc/rtl/src_peripheral/Other/gcd.v' |
], |
'unused' => { |
'plug:wb_slave[0]' => [ |
'bte_i', |
'cti_i' |
] |
} |
'modules' => { |
'gcd_ip' => {} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
} |
}, 'ip_gen' ); |
/Other/noc_based_mpsoc.IP
0,0 → 1,795
####################################################################### |
## File: noc_based_mpsoc.IP |
## |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ipgen = bless( { |
'hdl_files' => [], |
'version' => 1, |
'sockets' => { |
'jtag_to_wb' => { |
'type' => 'num', |
'0' => { |
'name' => 'jtag_to_wb_0' |
}, |
'2' => { |
'name' => 'jtag_to_wb_2' |
}, |
'1' => { |
'name' => 'jtag_to_wb_1' |
}, |
'value' => 3 |
} |
}, |
'category' => 'Other', |
'unused' => undef, |
'parameters' => { |
'T0_ram_JINDEXw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'default' => '8', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T2_cpu_FEATURE_DMMU' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T0_timer_PRESCALER_WIDTH' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => '8', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T3_ram_JINDEXw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'type' => 'Fixed', |
'default' => '8', |
'info' => undef |
}, |
'T2_cpu_FEATURE_INSTRUCTIONCACHE' => { |
'info' => undef, |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T2_ram_Aw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'type' => 'Fixed', |
'default' => '14', |
'info' => undef |
}, |
'T1_ram_Aw' => { |
'info' => undef, |
'default' => '14', |
'type' => 'Fixed', |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T0_cpu_FEATURE_DMMU' => { |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T1_cpu_FEATURE_DATACACHE' => { |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T1_cpu_FEATURE_IMMU' => { |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T0_ram_FPGA_VENDOR' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'default' => '"XILINX"', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T0_ram_JSTATUSw' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '8' |
}, |
'T2_cpu_IRQ_NUM' => { |
'info' => undef, |
'default' => '32', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T3_timer_PRESCALER_WIDTH' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'default' => '8', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T2_led_PORT_WIDTH' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'type' => 'Fixed', |
'default' => ' 1', |
'info' => undef |
}, |
'T0_ram_JTAG_CONNECT' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"XILINX_JTAG_WB"' |
}, |
'T3_ram_JDw' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => 'T3_ram_Dw', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T3_ram_J2WBw' => { |
'default' => '(T3_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T3_ram_JDw+T3_ram_JAw : 1', |
'type' => 'Fixed', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T3_ram_JTAG_CONNECT' => { |
'type' => 'Fixed', |
'default' => '"XILINX_JTAG_WB"', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T1_cpu_OPTION_DCACHE_SNOOP' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'info' => undef, |
'default' => '"ENABLED"', |
'type' => 'Fixed' |
}, |
'T0_cpu_FEATURE_DATACACHE' => { |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T2_ram_JTAG_CONNECT' => { |
'info' => undef, |
'default' => '"XILINX_JTAG_WB"', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T0_cpu_OPTION_OPERAND_WIDTH' => { |
'info' => undef, |
'default' => '32', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T2_ram_J2WBw' => { |
'default' => '(T2_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T2_ram_JDw+T2_ram_JAw : 1', |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T1_ram_JAw' => { |
'type' => 'Fixed', |
'default' => '32', |
'info' => undef, |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T1_cpu_FEATURE_INSTRUCTIONCACHE' => { |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T1_ram_JDw' => { |
'info' => undef, |
'default' => 'T1_ram_Dw', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T3_cpu_OPTION_DCACHE_SNOOP' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T2_cpu_FEATURE_IMMU' => { |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T0_ram_J2WBw' => { |
'info' => undef, |
'default' => '(T0_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T0_ram_JDw+T0_ram_JAw : 1', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T2_ram_FPGA_VENDOR' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'type' => 'Fixed', |
'default' => '"XILINX"', |
'info' => undef |
}, |
'T2_ram_JSTATUSw' => { |
'default' => '8', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T3_cpu_FEATURE_DATACACHE' => { |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T0_cpu_FEATURE_INSTRUCTIONCACHE' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T2_cpu_FEATURE_DATACACHE' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef |
}, |
'T2_ram_JINDEXw' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => '8', |
'info' => undef |
}, |
'T3_ram_WB2Jw' => { |
'default' => '(T3_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T3_ram_JSTATUSw+T3_ram_JINDEXw+1+T3_ram_JDw : 1', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T1_ram_FPGA_VENDOR' => { |
'info' => undef, |
'default' => '"XILINX"', |
'type' => 'Fixed', |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T1_cpu_IRQ_NUM' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T0_ram_Aw' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '14', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T2_cpu_OPTION_DCACHE_SNOOP' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T1_ram_WB2Jw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'default' => '(T1_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T1_ram_JSTATUSw+T1_ram_JINDEXw+1+T1_ram_JDw : 1', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T1_ram_Dw' => { |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T3_led_PORT_WIDTH' => { |
'type' => 'Fixed', |
'default' => ' 1', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T0_ram_WB2Jw' => { |
'info' => undef, |
'default' => '(T0_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T0_ram_JSTATUSw+T0_ram_JINDEXw+1+T0_ram_JDw : 1', |
'type' => 'Fixed', |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T3_cpu_FEATURE_DMMU' => { |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef, |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T2_cpu_OPTION_OPERAND_WIDTH' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T3_ram_FPGA_VENDOR' => { |
'type' => 'Fixed', |
'default' => '"XILINX"', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T1_cpu_FEATURE_DMMU' => { |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T1_ram_J2WBw' => { |
'type' => 'Fixed', |
'default' => '(T1_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T1_ram_JDw+T1_ram_JAw : 1', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T3_ram_Aw' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => '14', |
'info' => undef |
}, |
'T1_timer_PRESCALER_WIDTH' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'type' => 'Fixed', |
'default' => '8', |
'info' => undef |
}, |
'T2_ram_WB2Jw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'default' => '(T2_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T2_ram_JSTATUSw+T2_ram_JINDEXw+1+T2_ram_JDw : 1', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T1_ram_JINDEXw' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => undef, |
'default' => '8', |
'type' => 'Fixed' |
}, |
'T3_cpu_IRQ_NUM' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '32', |
'info' => undef |
}, |
'T0_ram_JDw' => { |
'info' => undef, |
'default' => 'T0_ram_Dw', |
'type' => 'Fixed', |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T3_ram_JSTATUSw' => { |
'info' => undef, |
'default' => '8', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T0_cpu_FEATURE_IMMU' => { |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T1_ram_JTAG_CONNECT' => { |
'type' => 'Fixed', |
'default' => '"XILINX_JTAG_WB"', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T3_cpu_FEATURE_INSTRUCTIONCACHE' => { |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T0_cpu_IRQ_NUM' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'info' => undef |
}, |
'T0_ram_JAw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T0_ram_Dw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T1_cpu_OPTION_OPERAND_WIDTH' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32' |
}, |
'T0_led_PORT_WIDTH' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => ' 1', |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T3_cpu_FEATURE_IMMU' => { |
'info' => undef, |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T1_ram_JSTATUSw' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => undef, |
'type' => 'Fixed', |
'default' => '8' |
}, |
'T3_ram_Dw' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T2_timer_PRESCALER_WIDTH' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => undef, |
'default' => '8', |
'type' => 'Fixed' |
}, |
'T3_ram_JAw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'info' => undef, |
'default' => '32', |
'type' => 'Fixed' |
}, |
'T1_led_PORT_WIDTH' => { |
'type' => 'Fixed', |
'default' => ' 1', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T0_cpu_OPTION_DCACHE_SNOOP' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"' |
}, |
'T3_cpu_OPTION_OPERAND_WIDTH' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '32', |
'info' => undef |
}, |
'T2_ram_JDw' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => 'T2_ram_Dw', |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T2_ram_JAw' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T2_ram_Dw' => { |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
} |
}, |
'parameters_order' => [ |
'cpu_FEATURE_DATACACHE', |
'cpu_FEATURE_DMMU', |
'cpu_FEATURE_IMMU', |
'cpu_FEATURE_INSTRUCTIONCACHE', |
'cpu_IRQ_NUM', |
'cpu_OPTION_DCACHE_SNOOP', |
'cpu_OPTION_OPERAND_WIDTH', |
'led_PORT_WIDTH', |
'ram_Aw', |
'ram_Dw', |
'ram_FPGA_VENDOR', |
'ram_J2WBw', |
'ram_JAw', |
'ram_JDw', |
'ram_JINDEXw', |
'ram_JSTATUSw', |
'ram_JTAG_CONNECT', |
'ram_WB2Jw', |
'timer_PRESCALER_WIDTH' |
], |
'file_name' => undef, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'ports' => { |
'T0_led_port_o' => { |
'range' => 'T0_led_PORT_WIDTH-1 : 0', |
'intfc_port' => 'IO', |
'type' => 'output', |
'intfc_name' => 'IO' |
}, |
'T2_led_port_o' => { |
'range' => 'T2_led_PORT_WIDTH-1 : 0', |
'intfc_port' => 'IO', |
'type' => 'output', |
'intfc_name' => 'IO' |
}, |
'enable0' => { |
'range' => undef, |
'intfc_port' => 'enable_i', |
'type' => 'input', |
'intfc_name' => 'plug:enable[0]' |
}, |
'T3_ram_jtag_to_wb' => { |
'intfc_name' => 'IO', |
'type' => 'input', |
'intfc_port' => 'jwb_i', |
'range' => 'T3_ram_J2WBw-1 : 0' |
}, |
'hh' => { |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => undef, |
'intfc_port' => 'clk_i' |
}, |
'T2_ram_wb_to_jtag' => { |
'range' => 'T2_ram_WB2Jw-1 : 0', |
'intfc_port' => 'jwb_o', |
'type' => 'output', |
'intfc_name' => 'socket:jtag_to_wb[2]' |
}, |
'T1_led_port_o' => { |
'range' => 'T1_led_PORT_WIDTH-1 : 0', |
'intfc_port' => 'IO', |
'type' => 'output', |
'intfc_name' => 'IO' |
}, |
'T0_ram_wb_to_jtag' => { |
'type' => 'output', |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'range' => 'T0_ram_WB2Jw-1 : 0', |
'intfc_port' => 'jwb_o' |
}, |
'reset0' => { |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]', |
'range' => undef, |
'intfc_port' => 'reset_i' |
}, |
'T1_ram_wb_to_jtag' => { |
'range' => 'T1_ram_WB2Jw-1 : 0', |
'intfc_port' => 'jwb_o', |
'type' => 'output', |
'intfc_name' => 'socket:jtag_to_wb[1]' |
}, |
'T3_led_port_o' => { |
'range' => 'T3_led_PORT_WIDTH-1 : 0', |
'intfc_port' => 'IO', |
'type' => 'output', |
'intfc_name' => 'IO' |
}, |
'clk1' => { |
'intfc_name' => 'plug:clk[1]', |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'range' => undef |
}, |
'T2_ram_jtag_to_wb' => { |
'intfc_port' => 'jwb_i', |
'range' => 'T2_ram_J2WBw-1 : 0', |
'intfc_name' => 'socket:jtag_to_wb[2]', |
'type' => 'input' |
}, |
'T1_ram_jtag_to_wb' => { |
'intfc_name' => 'socket:jtag_to_wb[1]', |
'type' => 'input', |
'intfc_port' => 'jwb_i', |
'range' => 'T1_ram_J2WBw-1 : 0' |
}, |
'T0_ram_jtag_to_wb' => { |
'type' => 'input', |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'range' => 'T0_ram_J2WBw-1 : 0', |
'intfc_port' => 'jwb_i' |
}, |
'T3_ram_wb_to_jtag' => { |
'type' => 'output', |
'intfc_name' => 'IO', |
'range' => 'T3_ram_WB2Jw-1 : 0', |
'intfc_port' => 'jwb_o' |
} |
}, |
'plugs' => { |
'reset' => { |
'value' => 1, |
'0' => { |
'name' => 'reset0' |
}, |
'type' => 'num' |
}, |
'enable' => { |
'0' => { |
'name' => 'enable0' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'value' => '2', |
'1' => { |
'name' => 'clk1' |
}, |
'0' => { |
'name' => 'hh' |
}, |
'type' => 'num' |
} |
}, |
'ports_order' => [], |
'ip_name' => 'noc_based_mpsoc', |
'module_name' => 'noc_based_mpsoc' |
}, 'ip_gen' ); |
/Other/sim_uart.IP
41,7 → 41,7
's_dat_o', |
's_ack_o' |
], |
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/Other/simulator_UART.v', |
'file_name' => 'mpsoc/rtl/src_peripheral/Other/simulator_UART.v', |
'version' => 7, |
'unused' => { |
'plug:wb_slave[0]' => [ |
196,7 → 196,7
}, |
'ip_name' => 'sim_uart', |
'hdl_files' => [ |
'/mpsoc/src_peripheral/Other/simulator_UART.v' |
'/mpsoc/rtl/src_peripheral/Other/simulator_UART.v' |
], |
'plugs' => { |
'clk' => { |
/Other/test.IP
0,0 → 1,790
####################################################################### |
## File: gpo.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ipgen =bless( { |
'sockets' => { |
'jtag_to_wb' => { |
'1' => { |
'name' => 'jtag_to_wb_1' |
}, |
'value' => 3, |
'0' => { |
'name' => 'jtag_to_wb_0' |
}, |
'2' => { |
'name' => 'jtag_to_wb_2' |
}, |
'type' => 'num' |
} |
}, |
'hdl_files' => [], |
'category' => 'Other', |
'parameters' => { |
'T2_ram_Aw' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '14' |
}, |
'T1_ram_Aw' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => undef, |
'default' => '14', |
'type' => 'Fixed' |
}, |
'T3_ram_JINDEXw' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => undef, |
'default' => '8', |
'type' => 'Fixed' |
}, |
'T2_cpu_FEATURE_INSTRUCTIONCACHE' => { |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T0_timer_PRESCALER_WIDTH' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '8', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T2_cpu_FEATURE_DMMU' => { |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef, |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T0_ram_JINDEXw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'default' => '8', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T2_led_PORT_WIDTH' => { |
'default' => ' 1', |
'type' => 'Fixed', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T3_timer_PRESCALER_WIDTH' => { |
'type' => 'Fixed', |
'default' => '8', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T2_cpu_IRQ_NUM' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32' |
}, |
'T1_cpu_FEATURE_IMMU' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef |
}, |
'T0_ram_FPGA_VENDOR' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'type' => 'Fixed', |
'default' => '"XILINX"', |
'info' => undef |
}, |
'T0_ram_JSTATUSw' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => undef, |
'default' => '8', |
'type' => 'Fixed' |
}, |
'T0_cpu_FEATURE_DMMU' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T1_cpu_FEATURE_DATACACHE' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T2_ram_J2WBw' => { |
'default' => '(T2_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T2_ram_JDw+T2_ram_JAw : 1', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T0_cpu_OPTION_OPERAND_WIDTH' => { |
'info' => undef, |
'default' => '32', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T2_ram_JTAG_CONNECT' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => undef, |
'default' => '"XILINX_JTAG_WB"', |
'type' => 'Fixed' |
}, |
'T1_cpu_OPTION_DCACHE_SNOOP' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef |
}, |
'T0_cpu_FEATURE_DATACACHE' => { |
'info' => undef, |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T3_ram_JTAG_CONNECT' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"XILINX_JTAG_WB"', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T3_ram_J2WBw' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '(T3_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T3_ram_JDw+T3_ram_JAw : 1', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T3_ram_JDw' => { |
'default' => 'T3_ram_Dw', |
'type' => 'Fixed', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T0_ram_JTAG_CONNECT' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"XILINX_JTAG_WB"', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T0_ram_J2WBw' => { |
'info' => undef, |
'default' => '(T0_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T0_ram_JDw+T0_ram_JAw : 1', |
'type' => 'Fixed', |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T2_cpu_FEATURE_IMMU' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"' |
}, |
'T1_ram_JDw' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => undef, |
'default' => 'T1_ram_Dw', |
'type' => 'Fixed' |
}, |
'T3_cpu_OPTION_DCACHE_SNOOP' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"' |
}, |
'T1_cpu_FEATURE_INSTRUCTIONCACHE' => { |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T1_ram_JAw' => { |
'type' => 'Fixed', |
'default' => '32', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T3_led_PORT_WIDTH' => { |
'default' => ' 1', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T1_ram_Dw' => { |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T0_ram_WB2Jw' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '(T0_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T0_ram_JSTATUSw+T0_ram_JINDEXw+1+T0_ram_JDw : 1', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T2_cpu_OPTION_DCACHE_SNOOP' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'info' => undef, |
'default' => '"ENABLED"', |
'type' => 'Fixed' |
}, |
'T1_ram_WB2Jw' => { |
'info' => undef, |
'default' => '(T1_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T1_ram_JSTATUSw+T1_ram_JINDEXw+1+T1_ram_JDw : 1', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T0_ram_Aw' => { |
'type' => 'Fixed', |
'default' => '14', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T1_cpu_IRQ_NUM' => { |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T1_ram_FPGA_VENDOR' => { |
'type' => 'Fixed', |
'default' => '"XILINX"', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T3_ram_WB2Jw' => { |
'default' => '(T3_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T3_ram_JSTATUSw+T3_ram_JINDEXw+1+T3_ram_JDw : 1', |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T2_ram_JINDEXw' => { |
'default' => '8', |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T3_cpu_FEATURE_DATACACHE' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef |
}, |
'T0_cpu_FEATURE_INSTRUCTIONCACHE' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"' |
}, |
'T2_cpu_FEATURE_DATACACHE' => { |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T2_ram_FPGA_VENDOR' => { |
'type' => 'Fixed', |
'default' => '"XILINX"', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T2_ram_JSTATUSw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'type' => 'Fixed', |
'default' => '8', |
'info' => undef |
}, |
'T3_ram_Aw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '14' |
}, |
'T1_ram_J2WBw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'type' => 'Fixed', |
'default' => '(T1_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+T1_ram_JDw+T1_ram_JAw : 1', |
'info' => undef |
}, |
'T1_cpu_FEATURE_DMMU' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T3_ram_FPGA_VENDOR' => { |
'type' => 'Fixed', |
'default' => '"XILINX"', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T2_cpu_OPTION_OPERAND_WIDTH' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T3_cpu_FEATURE_DMMU' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '"ENABLED"', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T0_ram_Dw' => { |
'info' => undef, |
'default' => '32', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T0_ram_JAw' => { |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T0_cpu_IRQ_NUM' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => '32', |
'info' => undef |
}, |
'T3_cpu_FEATURE_INSTRUCTIONCACHE' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"' |
}, |
'T1_ram_JTAG_CONNECT' => { |
'type' => 'Fixed', |
'default' => '"XILINX_JTAG_WB"', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T3_ram_JSTATUSw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef, |
'default' => '8', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T0_cpu_FEATURE_IMMU' => { |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef |
}, |
'T0_ram_JDw' => { |
'info' => undef, |
'default' => 'T0_ram_Dw', |
'type' => 'Fixed', |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T3_cpu_IRQ_NUM' => { |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T1_timer_PRESCALER_WIDTH' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '8', |
'info' => undef |
}, |
'T2_ram_WB2Jw' => { |
'default' => '(T2_ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+T2_ram_JSTATUSw+T2_ram_JINDEXw+1+T2_ram_JDw : 1', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T1_ram_JINDEXw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'default' => '8', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T2_ram_Dw' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef |
}, |
'T3_cpu_OPTION_OPERAND_WIDTH' => { |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef, |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T2_ram_JDw' => { |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => 'T2_ram_Dw', |
'info' => undef |
}, |
'T2_ram_JAw' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T0_cpu_OPTION_DCACHE_SNOOP' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => undef |
}, |
'T2_timer_PRESCALER_WIDTH' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '8', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T3_ram_JAw' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef |
}, |
'T1_led_PORT_WIDTH' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'type' => 'Fixed', |
'default' => ' 1', |
'info' => undef |
}, |
'T1_ram_JSTATUSw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '8' |
}, |
'T3_ram_Dw' => { |
'info' => undef, |
'default' => '32', |
'type' => 'Fixed', |
'content' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'T3_cpu_FEATURE_IMMU' => { |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'T0_led_PORT_WIDTH' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => undef, |
'type' => 'Fixed', |
'default' => ' 1', |
'info' => undef |
}, |
'T1_cpu_OPTION_OPERAND_WIDTH' => { |
'type' => 'Fixed', |
'default' => '32', |
'info' => undef, |
'content' => undef, |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
} |
}, |
'parameters_order' => [ |
'cpu_FEATURE_DATACACHE', |
'cpu_FEATURE_DMMU', |
'cpu_FEATURE_IMMU', |
'cpu_FEATURE_INSTRUCTIONCACHE', |
'cpu_IRQ_NUM', |
'cpu_OPTION_DCACHE_SNOOP', |
'cpu_OPTION_OPERAND_WIDTH', |
'led_PORT_WIDTH', |
'ram_Aw', |
'ram_Dw', |
'ram_FPGA_VENDOR', |
'ram_J2WBw', |
'ram_JAw', |
'ram_JDw', |
'ram_JINDEXw', |
'ram_JSTATUSw', |
'ram_JTAG_CONNECT', |
'ram_WB2Jw', |
'timer_PRESCALER_WIDTH' |
], |
'file_name' => undef, |
'ports' => { |
'T0_ram_jtag_to_wb' => { |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'type' => 'input', |
'intfc_port' => 'jwb_i', |
'range' => 'T0_ram_J2WBw-1 : 0' |
}, |
'T1_ram_jtag_to_wb' => { |
'range' => 'T1_ram_J2WBw-1 : 0', |
'intfc_port' => 'jwb_i', |
'type' => 'input', |
'intfc_name' => 'socket:jtag_to_wb[1]' |
}, |
'T2_ram_jtag_to_wb' => { |
'type' => 'input', |
'intfc_name' => 'socket:jtag_to_wb[2]', |
'range' => 'T2_ram_J2WBw-1 : 0', |
'intfc_port' => 'jwb_i' |
}, |
'T3_ram_wb_to_jtag' => { |
'type' => 'output', |
'intfc_name' => 'socket:jtag_to_wb[3]', |
'range' => 'T3_ram_WB2Jw-1 : 0', |
'intfc_port' => 'jwb_o' |
}, |
'T1_ram_wb_to_jtag' => { |
'intfc_port' => 'jwb_o', |
'range' => 'T1_ram_WB2Jw-1 : 0', |
'intfc_name' => 'socket:jtag_to_wb[1]', |
'type' => 'output' |
}, |
'clk1' => { |
'range' => undef, |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'intfc_name' => 'plug:clk[1]' |
}, |
'T3_led_port_o' => { |
'intfc_name' => 'IO', |
'type' => 'output', |
'intfc_port' => 'IO', |
'range' => 'T3_led_PORT_WIDTH-1 : 0' |
}, |
'hh' => { |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => undef, |
'intfc_port' => 'clk_i' |
}, |
'reset0' => { |
'range' => undef, |
'intfc_port' => 'reset_i', |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]' |
}, |
'T0_ram_wb_to_jtag' => { |
'type' => 'output', |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'range' => 'T0_ram_WB2Jw-1 : 0', |
'intfc_port' => 'jwb_o' |
}, |
'T1_led_port_o' => { |
'intfc_name' => 'IO', |
'type' => 'output', |
'intfc_port' => 'IO', |
'range' => 'T1_led_PORT_WIDTH-1 : 0' |
}, |
'T2_ram_wb_to_jtag' => { |
'intfc_port' => 'jwb_o', |
'range' => 'T2_ram_WB2Jw-1 : 0', |
'intfc_name' => 'socket:jtag_to_wb[2]', |
'type' => 'output' |
}, |
'T0_led_port_o' => { |
'type' => 'output', |
'intfc_name' => 'IO', |
'range' => 'T0_led_PORT_WIDTH-1 : 0', |
'intfc_port' => 'IO' |
}, |
'T3_ram_jtag_to_wb' => { |
'intfc_name' => 'socket:jtag_to_wb[3]', |
'type' => 'input', |
'intfc_port' => 'jwb_i', |
'range' => 'T3_ram_J2WBw-1 : 0' |
}, |
'enable0' => { |
'intfc_port' => 'enable_i', |
'range' => undef, |
'intfc_name' => 'plug:enable[0]', |
'type' => 'input' |
}, |
'T2_led_port_o' => { |
'type' => 'output', |
'intfc_name' => 'IO', |
'range' => 'T2_led_PORT_WIDTH-1 : 0', |
'intfc_port' => 'IO' |
} |
}, |
'plugs' => { |
'clk' => { |
'0' => { |
'name' => 'hh' |
}, |
'value' => '2', |
'1' => { |
'name' => 'clk1' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'type' => 'num', |
'0' => { |
'name' => 'reset0' |
}, |
'value' => 1 |
}, |
'enable' => { |
'type' => 'num', |
'0' => { |
'name' => 'enable0' |
}, |
'value' => 1 |
} |
}, |
'ports_order' => [], |
'ip_name' => 'noc_based_mpsoc', |
'module_name' => 'noc_based_mpsoc' |
}, 'ip_gen' ); |
|
/Processor/Or1200.IP
1,567 → 1,567
####################################################################### |
## File: Or1200.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.7.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$or1200 = bless( { |
'system_h' => ' #include "or1200/system.h" |
|
|
inline void nop (){ |
__asm__("l.nop 1"); |
}', |
'category' => 'Processor', |
'sw_files' => [ |
'/mpsoc/src_processor/or1200/sw/Makefile', |
'/mpsoc/src_processor/or1200/sw/or1200', |
'/mpsoc/src_processor/or1200/sw/link.ld', |
'/mpsoc/src_processor/or1200/sw/define_printf.h', |
'/mpsoc/src_processor/src_lib/simple-printf' |
$ipgen = bless( { |
'ip_name' => 'Or1200', |
'parameters_order' => [ |
'dw', |
'aw', |
'ppic_ints', |
'boot_adr', |
'Data_cashe_size', |
'Instruction_cashe_size', |
'Data_cashe_enable', |
'Instruction_cashe_enable', |
'Data_MMU_enable', |
'Instruction_MMU_enable', |
'implementation_addc', |
'implement_sub', |
'implement_cy', |
'implement_0v', |
'implement_OVE', |
'implement_alu_rotate', |
'implement_alu_compare', |
'implement_alu_ext', |
'multiplier_type', |
'divider_type' |
], |
'version' => 34, |
'hdl_files' => [ |
'/mpsoc/src_processor/or1200/verilog/or1200.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_alu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_amultp2_32x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_cfgr.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_cpu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_ctrl.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_fsm.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_ram.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_tag.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_tlb.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_32x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_256x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_du.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_except.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_addsub.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_arith.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_div.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_fcmp.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv_except.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_mul.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_addsub.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_div.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_intfloat_conv.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_mul.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_addsub.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_div.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_mul.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_freeze.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_genpc.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_gmultp2_32x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_fsm.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_ram.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_tag.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_if.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_immu_tlb.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_immu_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_iwb_biu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_lsu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_mem2reg.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_mult_mac.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_operandmuxes.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_pic.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_pm.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_qmem_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_reg2mem.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_rf.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_rfram_generic.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_sb.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_sb_fifo.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32_bw.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32x24.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x14.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x22.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x24.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_128x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_256x21.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_512x20.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x8.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32_bw.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x8.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32_bw.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_sprs.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_tpram_32x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_tt.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_wb_biu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_wbmux.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_xcv_ram32x8d.v', |
'/mpsoc/src_processor/or1200/verilog/src/timescale.v' |
], |
'file_name' => '/home/alireza/mywork/mpsoc/src_processor/or1200/verilog/or1200.v', |
'hdl_files' => [ |
'/mpsoc/src_processor/or1200/verilog/or1200.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_alu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_amultp2_32x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_cfgr.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_cpu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_ctrl.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_fsm.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_ram.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_tag.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_tlb.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_32x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_256x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_du.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_except.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_addsub.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_arith.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_div.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_fcmp.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv_except.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_mul.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_addsub.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_div.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_intfloat_conv.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_mul.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_addsub.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_div.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_mul.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_freeze.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_genpc.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_gmultp2_32x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_fsm.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_ram.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_tag.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_if.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_immu_tlb.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_immu_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_iwb_biu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_lsu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_mem2reg.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_mult_mac.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_operandmuxes.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_pic.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_pm.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_qmem_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_reg2mem.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_rf.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_rfram_generic.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_sb.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_sb_fifo.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32_bw.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32x24.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x14.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x22.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x24.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_128x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_256x21.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_512x20.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x8.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32_bw.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x8.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32_bw.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_sprs.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_top.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_tpram_32x32.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_tt.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_wb_biu.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_wbmux.v', |
'/mpsoc/src_processor/or1200/verilog/src/or1200_xcv_ram32x8d.v', |
'/mpsoc/src_processor/or1200/verilog/src/timescale.v' |
], |
'ip_name' => 'Or1200', |
'plugs' => { |
'reset' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'reset' |
} |
}, |
'enable' => { |
'0' => { |
'name' => 'enable' |
}, |
'enable' => {}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_master' => { |
'0' => { |
'name' => 'iwb' |
}, |
'type' => 'num', |
'value' => 2, |
'1' => { |
'name' => 'dwb' |
} |
}, |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num', |
'value' => 1 |
} |
}, |
'ports' => { |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
}, |
'dwb_sel_o' => { |
'type' => 'output', |
'range' => '3:0', |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'dwb_cti_o' => { |
'intfc_port' => 'cti_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => '2:0' |
}, |
'dwb_bte_o' => { |
'type' => 'output', |
'range' => '1:0', |
'intfc_port' => 'bte_o', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'iwb_cyc_o' => { |
'intfc_port' => 'cyc_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => '' |
}, |
'dwb_adr_o' => { |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => 'aw-1:0', |
'type' => 'output' |
}, |
'iwb_err_i' => { |
'intfc_port' => 'err_i', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'input' |
}, |
'dwb_we_o' => { |
'range' => '', |
'gen_hw_files' => [ |
'/mpsoc/src_processor/or1200/verilog/or1200_definesfrename_sep_tlib/or1200_defines.v' |
], |
'ports' => { |
'iwb_stb_o' => { |
'intfc_port' => 'stb_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'we_o' |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '' |
}, |
'dwb_rty_i' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'rty_i', |
'type' => 'input', |
'range' => '' |
}, |
'dwb_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => 'dw-1:0' |
}, |
'iwb_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => 'dw-1:0' |
}, |
'iwb_rty_i' => { |
'intfc_port' => 'rty_i', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input', |
'range' => '' |
}, |
'iwb_sel_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'sel_o', |
'type' => 'output', |
'range' => '3:0' |
}, |
'clk' => { |
'en_i' => { |
'intfc_name' => 'plug:enable[0]', |
'type' => 'input', |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]' |
'intfc_port' => 'enable_i' |
}, |
'en_i' => { |
'intfc_port' => 'enable_i', |
'intfc_name' => 'plug:enable[0]', |
'type' => 'input', |
'range' => '' |
'iwb_bte_o' => { |
'intfc_port' => 'bte_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => '1:0' |
}, |
'dwb_dat_o' => { |
'intfc_port' => 'dat_o', |
'range' => 'dw-1:0', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
}, |
'iwb_err_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'err_i' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
}, |
'dwb_cyc_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'cyc_o', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'iwb_dat_i' => { |
'range' => 'dw-1:0', |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'iwb_stb_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'stb_o' |
}, |
'dwb_ack_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'ack_i' |
}, |
'dwb_dat_i' => { |
'type' => 'input', |
'range' => 'dw-1:0', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'dat_i' |
}, |
'iwb_cti_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cti_o', |
'type' => 'output', |
'range' => '2:0' |
}, |
'iwb_we_o' => { |
'intfc_port' => 'we_o', |
'dwb_stb_o' => { |
'intfc_port' => 'stb_o', |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'iwb_dat_o' => { |
'intfc_port' => 'dat_o', |
'range' => 'dw-1:0', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output' |
}, |
'iwb_rty_i' => { |
'intfc_port' => 'rty_i', |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'dwb_we_o' => { |
'intfc_port' => 'we_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '' |
}, |
'iwb_dat_i' => { |
'range' => 'dw-1:0', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input', |
'intfc_port' => 'dat_i' |
}, |
'iwb_we_o' => { |
'intfc_port' => 'we_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '' |
}, |
'dwb_cyc_o' => { |
'intfc_port' => 'cyc_o', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
}, |
'iwb_adr_o' => { |
'range' => 'aw-1:0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'adr_o' |
'dwb_cti_o' => { |
'intfc_port' => 'cti_o', |
'range' => '2:0', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
}, |
'iwb_cyc_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'cyc_o' |
}, |
'dwb_err_i' => { |
'intfc_port' => 'err_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input' |
}, |
'pic_ints_i' => { |
'intfc_port' => 'int_i', |
'range' => 'ppic_ints-1:0', |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'type' => 'input' |
}, |
'dwb_err_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'err_i', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'iwb_bte_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'bte_o', |
'type' => 'output', |
'range' => '1:0' |
}, |
'dwb_stb_o' => { |
'intfc_port' => 'stb_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => '' |
}, |
'iwb_ack_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'ack_i', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'pic_ints_i' => { |
'intfc_port' => 'int_i', |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'range' => 'ppic_ints-1:0', |
'type' => 'input' |
} |
'iwb_sel_o' => { |
'intfc_port' => 'sel_o', |
'range' => '3:0', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output' |
}, |
'dwb_rty_i' => { |
'intfc_port' => 'rty_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '' |
}, |
'dwb_adr_o' => { |
'intfc_port' => 'adr_o', |
'range' => 'aw-1:0', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
}, |
'iwb_cti_o' => { |
'intfc_port' => 'cti_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => '2:0' |
}, |
'dwb_sel_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '3:0', |
'intfc_port' => 'sel_o' |
}, |
'iwb_adr_o' => { |
'range' => 'aw-1:0', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'adr_o' |
}, |
'dwb_bte_o' => { |
'intfc_port' => 'bte_o', |
'range' => '1:0', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
}, |
'dwb_dat_i' => { |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input', |
'range' => 'dw-1:0', |
'intfc_port' => 'dat_i' |
}, |
'iwb_ack_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'ack_i' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]' |
}, |
'dwb_ack_i' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input', |
'intfc_port' => 'ack_i' |
} |
}, |
'system_h' => ' #include "or1200/system.h" |
|
|
static inline void nop (){ |
__asm__("l.nop 1"); |
}', |
'plugs' => { |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'value' => 1 |
}, |
'clk' => { |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
} |
}, |
'wb_master' => { |
'type' => 'num', |
'0' => { |
'name' => 'iwb' |
}, |
'1' => { |
'name' => 'dwb' |
}, |
'value' => 2 |
}, |
'enable' => { |
'0' => { |
'name' => 'enable' |
}, |
'type' => 'num', |
'value' => 1, |
'enable' => {} |
} |
}, |
'ports_order' => [ |
'clk', |
'reset', |
'en_i', |
'pic_ints_i', |
'iwb_ack_i', |
'iwb_err_i', |
'iwb_rty_i', |
'iwb_dat_i', |
'iwb_cyc_o', |
'iwb_adr_o', |
'iwb_stb_o', |
'iwb_we_o', |
'iwb_sel_o', |
'iwb_dat_o', |
'iwb_cti_o', |
'iwb_bte_o', |
'dwb_ack_i', |
'dwb_err_i', |
'dwb_rty_i', |
'dwb_dat_i', |
'dwb_cyc_o', |
'dwb_adr_o', |
'dwb_stb_o', |
'dwb_we_o', |
'dwb_sel_o', |
'dwb_dat_o', |
'dwb_cti_o', |
'dwb_bte_o' |
], |
'modules' => { |
'or1200' => {} |
}, |
'unused' => { |
'plug:wb_master[0]' => [ |
'tag_o' |
], |
'plug:wb_master[1]' => [ |
'tag_o' |
] |
}, |
'parameters_order' => [ |
'dw', |
'aw', |
'ppic_ints', |
'boot_adr', |
'Data_cashe_size', |
'Instruction_cashe_size', |
'Data_cashe_enable', |
'Instruction_cashe_enable', |
'Data_MMU_enable', |
'Instruction_MMU_enable', |
'implementation_addc', |
'implement_sub', |
'implement_cy', |
'implement_0v', |
'implement_OVE', |
'implement_alu_rotate', |
'implement_alu_compare', |
'implement_alu_ext', |
'multiplier_type', |
'divider_type' |
], |
'unused' => { |
'plug:wb_master[1]' => [ |
'tag_o' |
], |
'plug:wb_master[0]' => [ |
'tag_o' |
] |
}, |
'parameters' => { |
'implement_0v' => { |
'content' => '0V,NO_0V', |
'parameters' => { |
'implement_alu_ext' => { |
'redefine_param' => 0, |
'info' => 'Implement l.extXs and l.extXz instructions', |
'default' => 'NO_EXT', |
'type' => 'Combo-box', |
'global_param' => 'Don\'t include', |
'content' => 'EXT,NO_EXT' |
}, |
'multiplier_type' => { |
'global_param' => 'Don\'t include', |
'content' => 'SERIAL,PARALLEL', |
'default' => 'SERIAL', |
'redefine_param' => 0, |
'info' => undef, |
'type' => 'Combo-box' |
}, |
'Instruction_cashe_size' => { |
'default' => '8K', |
'redefine_param' => 0, |
'info' => 'Instruction Cashe Size in B', |
'type' => 'Combo-box', |
'global_param' => 'Don\'t include', |
'content' => '512,4K,8K,16K,32K' |
}, |
'divider_type' => { |
'global_param' => 'Don\'t include', |
'content' => 'SERIAL,PARALLEL', |
'info' => undef, |
'redefine_param' => 0, |
'default' => 'SERIAL', |
'type' => 'Combo-box' |
}, |
'dw' => { |
'global_param' => 'Localparam', |
'content' => '', |
'default' => '32', |
'info' => 'Parameter', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'implement_alu_compare' => { |
'default' => '2', |
'redefine_param' => 0, |
'info' => 'Type of ALU compare to implement |
Try to find which synthesizes with most efficient logic use or highest speed.', |
'type' => 'Combo-box', |
'global_param' => 'Don\'t include', |
'content' => '1,2,3' |
}, |
'implement_alu_rotate' => { |
'type' => 'Combo-box', |
'default' => 'ROTATE', |
'info' => 'Implement rotate in the ALU |
At the time of writing this, or32 C/C++ compiler doesn\'t generate rotate instructions. However or32 assembler can assemble code that uses rotate insn. |
This means that rotate instructions must be used manually inserted. |
By default implementation of rotate is disabled to save area and increase is disabled to save area and increase clock frequency.', |
'redefine_param' => 0, |
'content' => 'ROTATE,NO_ROTATE', |
'global_param' => 'Don\'t include' |
}, |
'implement_OVE' => { |
'global_param' => 'Don\'t include', |
'content' => 'OVE,NO_OVE', |
'default' => 'NO_OVE', |
'redefine_param' => 0, |
'global_param' => 'Don\'t include', |
'info' => 'Implement carry bit SR[OV] |
Compiler doesn\'t use this, but other code may like to.', |
'default' => '0V', |
'info' => 'Implement carry bit SR[OVE] |
Overflow interrupt indicator. When enabled, SR[OV] flag does not remain asserted after exception.', |
'type' => 'Combo-box' |
}, |
'implement_alu_ext' => { |
'global_param' => 'Don\'t include', |
'content' => 'EXT,NO_EXT', |
'redefine_param' => 0, |
'type' => 'Combo-box', |
'info' => 'Implement l.extXs and l.extXz instructions', |
'default' => 'NO_EXT' |
}, |
'Data_MMU_enable' => { |
'content' => 'NO,YES', |
'redefine_param' => 0, |
'global_param' => 'Don\'t include', |
'default' => 'YES', |
'info' => undef, |
'type' => 'Combo-box' |
}, |
'aw' => { |
'type' => 'Fixed', |
'info' => 'Parameter', |
'default' => '32', |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1 |
}, |
'Data_cashe_enable' => { |
'info' => undef, |
'default' => 'YES', |
'type' => 'Combo-box', |
'redefine_param' => 0, |
'content' => 'NO,YES', |
'global_param' => 'Don\'t include' |
}, |
'implement_OVE' => { |
'redefine_param' => 0, |
'content' => 'OVE,NO_OVE', |
'global_param' => 'Don\'t include', |
'info' => 'Implement carry bit SR[OVE] |
Overflow interrupt indicator. When enabled, SR[OV] flag does not remain asserted after exception.', |
'default' => 'NO_OVE', |
'type' => 'Combo-box' |
}, |
'implementation_addc' => { |
'global_param' => 'Don\'t include', |
'content' => 'ADDC,NO_ADDC', |
'redefine_param' => 0, |
'type' => 'Combo-box', |
'default' => 'ADDC', |
'info' => 'Implement l.addc/l.addic instructions |
'Data_cashe_enable' => { |
'type' => 'Combo-box', |
'default' => 'YES', |
'info' => undef, |
'redefine_param' => 0, |
'content' => 'NO,YES', |
'global_param' => 'Don\'t include' |
}, |
'ppic_ints' => { |
'default' => '20', |
'redefine_param' => 1, |
'info' => 'Number of interrupts', |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'content' => '3,31,1' |
}, |
'Instruction_cashe_enable' => { |
'info' => undef, |
'redefine_param' => 0, |
'default' => 'YES', |
'type' => 'Combo-box', |
'global_param' => 'Don\'t include', |
'content' => 'NO,YES' |
}, |
'implementation_addc' => { |
'default' => 'ADDC', |
'info' => 'Implement l.addc/l.addic instructions |
By default implementation of l.addc/l.addic instructions is enabled in case you need them. |
If you don\'t use them, then disable implementation to save area.' |
}, |
'implement_sub' => { |
'type' => 'Combo-box', |
'default' => 'SUB', |
'info' => 'Implement l.sub instruction |
If you don\'t use them, then disable implementation to save area.', |
'redefine_param' => 0, |
'type' => 'Combo-box', |
'global_param' => 'Don\'t include', |
'content' => 'ADDC,NO_ADDC' |
}, |
'aw' => { |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'redefine_param' => 1, |
'default' => '32' |
}, |
'implement_sub' => { |
'content' => 'SUB,NO_SUB', |
'global_param' => 'Don\'t include', |
'type' => 'Combo-box', |
'info' => 'Implement l.sub instruction |
By default implementation of l.sub instructions is enabled to be compliant with the simulator. |
If you don\'t use carry bit, then disable implementation to save area.', |
'global_param' => 'Don\'t include', |
'content' => 'SUB,NO_SUB', |
'redefine_param' => 0 |
}, |
'divider_type' => { |
'type' => 'Combo-box', |
'default' => 'SERIAL', |
'info' => undef, |
'global_param' => 'Don\'t include', |
'redefine_param' => 0, |
'content' => 'SERIAL,PARALLEL' |
'default' => 'SUB' |
}, |
'Instruction_MMU_enable' => { |
'global_param' => 'Don\'t include', |
'content' => 'NO,YES', |
'redefine_param' => 0, |
'type' => 'Combo-box', |
'default' => 'YES', |
'info' => undef |
}, |
'implement_alu_rotate' => { |
'global_param' => 'Don\'t include', |
'redefine_param' => 0, |
'content' => 'ROTATE,NO_ROTATE', |
'type' => 'Combo-box', |
'info' => 'Implement rotate in the ALU |
At the time of writing this, or32 C/C++ compiler doesn\'t generate rotate instructions. However or32 assembler can assemble code that uses rotate insn. |
This means that rotate instructions must be used manually inserted. |
By default implementation of rotate is disabled to save area and increase is disabled to save area and increase clock frequency.', |
'default' => 'ROTATE' |
}, |
'multiplier_type' => { |
'global_param' => 'Don\'t include', |
'redefine_param' => 0, |
'content' => 'SERIAL,PARALLEL', |
'type' => 'Combo-box', |
'info' => undef, |
'default' => 'SERIAL' |
}, |
'boot_adr' => { |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'info' => 'Parameter', |
'default' => '32\'h00000100', |
'type' => 'Fixed' |
}, |
'Instruction_cashe_enable' => { |
'global_param' => 'Don\'t include', |
'redefine_param' => 0, |
'content' => 'NO,YES', |
'type' => 'Combo-box', |
'info' => undef, |
'default' => 'YES' |
}, |
'ppic_ints' => { |
'content' => '3,31,1', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'info' => 'Number of interrupts', |
'default' => '20', |
'type' => 'Spin-button' |
}, |
'Data_cashe_size' => { |
'content' => '512,4K,8K,16K,32K', |
'redefine_param' => 0, |
'global_param' => 'Don\'t include', |
'info' => 'Data Cashe Size in B', |
'default' => '8K', |
'type' => 'Combo-box' |
}, |
'Instruction_cashe_size' => { |
'default' => '8K', |
'info' => 'Instruction Cashe Size in B', |
'type' => 'Combo-box', |
'content' => '512,4K,8K,16K,32K', |
'redefine_param' => 0, |
'global_param' => 'Don\'t include' |
}, |
'implement_alu_compare' => { |
'Data_cashe_size' => { |
'global_param' => 'Don\'t include', |
'content' => '512,4K,8K,16K,32K', |
'default' => '8K', |
'redefine_param' => 0, |
'info' => 'Data Cashe Size in B', |
'type' => 'Combo-box' |
}, |
'Data_MMU_enable' => { |
'default' => 'YES', |
'redefine_param' => 0, |
'info' => undef, |
'type' => 'Combo-box', |
'global_param' => 'Don\'t include', |
'content' => 'NO,YES' |
}, |
'boot_adr' => { |
'type' => 'Fixed', |
'default' => '32\'h00000100', |
'info' => 'Parameter', |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Localparam' |
}, |
'implement_0v' => { |
'content' => '0V,NO_0V', |
'global_param' => 'Don\'t include', |
'type' => 'Combo-box', |
'default' => '0V', |
'redefine_param' => 0, |
'info' => 'Implement carry bit SR[OV] |
Compiler doesn\'t use this, but other code may like to.' |
}, |
'implement_cy' => { |
'content' => 'CY,NO_CY', |
'global_param' => 'Don\'t include', |
'type' => 'Combo-box', |
'info' => 'Implement carry bit SR[CY] |
By default implementation of SR[CY] is enabled to be compliant with the simulator. However SR[CY] is explicitly only used by l.addc/l.addic/l.sub instructions and if these three insns are not implemented there is not much point having SR[CY].', |
'redefine_param' => 0, |
'default' => 'CY' |
}, |
'Instruction_MMU_enable' => { |
'global_param' => 'Don\'t include', |
'content' => 'NO,YES', |
'redefine_param' => 0, |
'content' => '1,2,3', |
'type' => 'Combo-box', |
'default' => '2', |
'info' => 'Type of ALU compare to implement |
Try to find which synthesizes with most efficient logic use or highest speed.' |
}, |
'dw' => { |
'default' => '32', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Parameter' |
}, |
'implement_cy' => { |
'type' => 'Combo-box', |
'info' => 'Implement carry bit SR[CY] |
By default implementation of SR[CY] is enabled to be compliant with the simulator. However SR[CY] is explicitly only used by l.addc/l.addic/l.sub instructions and if these three insns are not implemented there is not much point having SR[CY].', |
'default' => 'CY', |
'global_param' => 'Don\'t include', |
'redefine_param' => 0, |
'content' => 'CY,NO_CY' |
} |
}, |
'modules' => { |
'or1200' => {} |
}, |
'sockets' => { |
'interrupt_peripheral' => { |
'type' => 'param', |
'value' => 'ppic_ints', |
'connection_num' => 'single connection', |
'0' => { |
'name' => 'interrupt' |
} |
} |
}, |
'ports_order' => [ |
'clk', |
'reset', |
'en_i', |
'pic_ints_i', |
'iwb_ack_i', |
'iwb_err_i', |
'iwb_rty_i', |
'iwb_dat_i', |
'iwb_cyc_o', |
'iwb_adr_o', |
'iwb_stb_o', |
'iwb_we_o', |
'iwb_sel_o', |
'iwb_dat_o', |
'iwb_cti_o', |
'iwb_bte_o', |
'dwb_ack_i', |
'dwb_err_i', |
'dwb_rty_i', |
'dwb_dat_i', |
'dwb_cyc_o', |
'dwb_adr_o', |
'dwb_stb_o', |
'dwb_we_o', |
'dwb_sel_o', |
'dwb_dat_o', |
'dwb_cti_o', |
'dwb_bte_o' |
], |
'module_name' => 'or1200', |
'gen_hw_files' => [ |
'/mpsoc/src_processor/or1200/verilog/or1200_definesfrename_sep_tlib/or1200_defines.v' |
], |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'version' => 32 |
}, 'ip_gen' ); |
'info' => undef, |
'default' => 'YES', |
'type' => 'Combo-box' |
} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'sockets' => { |
'interrupt_peripheral' => { |
'connection_num' => 'single connection', |
'value' => 'ppic_ints', |
'0' => { |
'name' => 'interrupt' |
}, |
'type' => 'param' |
} |
}, |
'sw_files' => [ |
'/mpsoc/src_processor/or1200/sw/Makefile', |
'/mpsoc/src_processor/or1200/sw/or1200', |
'/mpsoc/src_processor/or1200/sw/link.ld', |
'/mpsoc/src_processor/or1200/sw/define_printf.h', |
'/mpsoc/src_processor/src_lib/simple-printf' |
], |
'category' => 'Processor', |
'module_name' => 'or1200', |
'file_name' => 'mpsoc/src_processor/or1200/verilog/or1200.v' |
}, 'ip_gen' ); |
/Processor/aeMB.IP
1,90 → 1,206
####################################################################### |
## File: aeMB.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.7.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
## MAY CAUSE UNEXPECTED BEHAVIOR. |
################################################################################ |
|
$ipgen = bless( { |
'unused' => undef, |
'plugs' => { |
'enable' => { |
'value' => 1, |
'0' => { |
'name' => 'enable' |
}, |
'enable' => {}, |
'type' => 'num' |
}, |
'wb_master' => { |
'wb_master' => {}, |
'value' => 2, |
'type' => 'num', |
'0' => { |
'name' => 'iwb' |
}, |
'1' => { |
'name' => 'dwb' |
} |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num', |
'value' => 1 |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
} |
} |
}, |
'sockets' => { |
'interrupt_cpu' => { |
'type' => 'num', |
'0' => { |
'name' => 'interrupt_cpu' |
}, |
'connection_num' => 'single connection', |
'value' => 1 |
} |
}, |
'gen_sw_files_ticked' => [], |
'system_h' => ' |
#include "aemb/core.hh" |
|
static inline void nop (void) { |
asm volatile ("nop"); |
} |
|
void general_int_main( void ) __attribute__ ((interrupt_handler)); // general_int_main() is defined by interrupt controller |
void aemb_enable_interrupt (void); |
void exit (int); |
|
#define general_cpu_int_en aemb_enable_interrupt |
|
', |
'parameters' => { |
'AEMB_DWB' => { |
'redefine_param' => 1, |
'info' => undef, |
'default' => ' 32', |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed' |
}, |
'AEMB_BSF' => { |
'default' => ' 1', |
'content' => '', |
'redefine_param' => 1, |
'info' => undef, |
'global_param' => 'Localparam', |
'type' => 'Fixed' |
}, |
'AEMB_IWB' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'content' => '', |
'default' => ' 32', |
'info' => undef, |
'redefine_param' => 1, |
'info' => undef |
'default' => ' 1' |
}, |
'AEMB_XWB' => { |
'type' => 'Fixed', |
'AEMB_ICH' => { |
'global_param' => 'Localparam', |
'content' => '', |
'default' => ' 7', |
'default' => ' 11', |
'redefine_param' => 1, |
'info' => undef, |
'redefine_param' => 1 |
'type' => 'Fixed' |
}, |
'HEAP_SIZE' => { |
'info' => undef, |
'redefine_param' => 0, |
'content' => '', |
'default' => '0x400', |
'type' => 'Entry', |
'global_param' => 'Don\'t include' |
}, |
'AEMB_MUL' => { |
'default' => ' 1', |
'content' => '', |
'AEMB_IDX' => { |
'type' => 'Fixed', |
'info' => undef, |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => ' 6', |
'content' => '', |
'global_param' => 'Localparam' |
}, |
'AEMB_IDX' => { |
'AEMB_IWB' => { |
'info' => undef, |
'type' => 'Fixed', |
'redefine_param' => 1, |
'default' => ' 6', |
'default' => ' 32', |
'content' => '', |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'AEMB_ICH' => { |
'AEMB_DWB' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'content' => '', |
'default' => ' 11', |
'default' => ' 32', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'info' => undef |
}, |
'AEMB_MUL' => { |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'info' => undef, |
'default' => ' 1', |
'redefine_param' => 1 |
}, |
'STACK_SIZE' => { |
'content' => '', |
'global_param' => 'Don\'t include', |
'type' => 'Entry', |
'global_param' => 'Don\'t include', |
'default' => '0x400', |
'content' => '', |
'info' => 'The stack size in hex', |
'redefine_param' => 0 |
} |
'redefine_param' => 0, |
'default' => '0x400' |
}, |
'AEMB_XWB' => { |
'global_param' => 'Localparam', |
'content' => '', |
'default' => ' 7', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'info' => undef |
}, |
'HEAP_SIZE' => { |
'global_param' => 'Don\'t include', |
'content' => '', |
'default' => '0x400', |
'redefine_param' => 0, |
'type' => 'Entry', |
'info' => undef |
} |
}, |
'description' => 'AEMB 32-bit Microprocessor Core |
For more information check http://opencores.org/project,aemb', |
'ip_name' => 'aeMB', |
'module_name' => 'aeMB_top', |
'ports_order' => [ |
'dwb_adr_o', |
'dwb_cyc_o', |
'dwb_dat_o', |
'dwb_sel_o', |
'dwb_stb_o', |
'dwb_tag_o', |
'dwb_wre_o', |
'dwb_cti_o', |
'dwb_bte_o', |
'dwb_ack_i', |
'dwb_dat_i', |
'dwb_err_i', |
'dwb_rty_i', |
'iwb_adr_o', |
'iwb_cyc_o', |
'iwb_sel_o', |
'iwb_stb_o', |
'iwb_tag_o', |
'iwb_wre_o', |
'iwb_dat_o', |
'iwb_cti_o', |
'iwb_bte_o', |
'iwb_ack_i', |
'iwb_dat_i', |
'iwb_err_i', |
'iwb_rty_i', |
'clk', |
'reset', |
'sys_int_i', |
'sys_ena_i' |
], |
'parameters_order' => [ |
'AEMB_IWB', |
'AEMB_DWB', |
'AEMB_XWB', |
'AEMB_ICH', |
'AEMB_IDX', |
'AEMB_BSF', |
'AEMB_MUL', |
'STACK_SIZE', |
'HEAP_SIZE' |
], |
'file_name' => 'mpsoc/src_processor/aeMB/verilog/aemb.v', |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'modules' => { |
'aeMB_top' => {} |
}, |
'hdl_files' => [ |
'/mpsoc/src_processor/aeMB/verilog/aemb.v', |
'/mpsoc/src_processor/aeMB/verilog/src/aeMB_core.v', |
117,308 → 233,237
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iche.v', |
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iwbif.v' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/aeMB/verilog/aemb.v', |
'module_name' => 'aeMB_top', |
'sockets' => { |
'interrupt_cpu' => { |
'connection_num' => 'single connection', |
'type' => 'num', |
'0' => { |
'name' => 'interrupt_cpu' |
}, |
'value' => 1 |
} |
}, |
'version' => 2, |
'description' => 'AEMB 32-bit Microprocessor Core |
For more information check http://opencores.org/project,aemb', |
'gen_sw_files' => [ |
'/mpsoc/src_processor/aeMB/sw/compile/gccromfrename_sep_tcompile/gccrom', |
'/mpsoc/src_processor/aeMB/sw/Makefilefrename_sep_tMakefile' |
'/mpsoc/src_processor/aeMB/sw/link.ldfrename_sep_tlink.ld' |
], |
'plugs' => { |
'enable' => { |
'type' => 'num', |
'0' => { |
'name' => 'enable' |
}, |
'value' => 1, |
'enable' => {} |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'wb_master' => { |
'wb_master' => {}, |
'1' => { |
'name' => 'dwb' |
}, |
'value' => 2, |
'type' => 'num', |
'0' => { |
'name' => 'iwb' |
} |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'value' => 1 |
} |
}, |
'sw_files' => [ |
'/mpsoc/src_processor/aeMB/sw/aemb', |
'/mpsoc/src_processor/aeMB/sw/aemb.specs', |
'/mpsoc/src_processor/aeMB/sw/Makefile' |
], |
'unused' => undef, |
'category' => 'Processor', |
'version' => 10, |
'ports' => { |
'iwb_tag_o' => { |
'dwb_wre_o' => { |
'type' => 'output', |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '' |
}, |
'dwb_ack_i' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input', |
'intfc_port' => 'ack_i' |
}, |
'iwb_bte_o' => { |
'range' => '1:0', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'tag_o', |
'range' => '2:0' |
'type' => 'output', |
'intfc_port' => 'bte_o' |
}, |
'iwb_adr_o' => { |
'iwb_wre_o' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'we_o' |
}, |
'iwb_ack_i' => { |
'type' => 'input', |
'intfc_port' => 'ack_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'dwb_adr_o' => { |
'range' => '31:0', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'adr_o', |
'range' => '31:0' |
'type' => 'output' |
}, |
'clk' => { |
'range' => '', |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]' |
'intfc_name' => 'plug:clk[0]', |
'range' => '' |
}, |
'dwb_rty_i' => { |
'iwb_tag_o' => { |
'intfc_port' => 'tag_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '2:0' |
}, |
'iwb_err_i' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input', |
'intfc_port' => 'err_i' |
}, |
'dwb_cti_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'rty_i', |
'range' => '' |
'range' => '2:0', |
'intfc_port' => 'cti_o', |
'type' => 'output' |
}, |
'dwb_stb_o' => { |
'dwb_cyc_o' => { |
'type' => 'output', |
'intfc_port' => 'cyc_o', |
'range' => '', |
'intfc_port' => 'stb_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'dwb_wre_o' => { |
'dwb_err_i' => { |
'range' => '', |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
'type' => 'input', |
'intfc_port' => 'err_i' |
}, |
'iwb_stb_o' => { |
'range' => '', |
'intfc_port' => 'stb_o', |
'dwb_bte_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '1:0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
'intfc_port' => 'bte_o' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'range' => '' |
}, |
'dwb_bte_o' => { |
'iwb_cti_o' => { |
'intfc_port' => 'cti_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'bte_o', |
'range' => '1:0' |
'range' => '2:0', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'dwb_dat_i' => { |
'range' => '31:0', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input' |
}, |
'dwb_dat_o' => { |
'range' => '31:0', |
'intfc_port' => 'dat_o', |
'iwb_adr_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]' |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '31:0' |
}, |
'iwb_rty_i' => { |
'sys_ena_i' => { |
'intfc_name' => 'plug:enable[0]', |
'range' => '', |
'intfc_port' => 'rty_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[0]' |
'intfc_port' => 'enable_i', |
'type' => 'input' |
}, |
'iwb_cyc_o' => { |
'intfc_port' => 'cyc_o', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cyc_o', |
'type' => 'output' |
}, |
'dwb_cyc_o' => { |
'dwb_dat_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '31:0', |
'type' => 'output', |
'intfc_port' => 'dat_o' |
}, |
'dwb_stb_o' => { |
'range' => '', |
'intfc_port' => 'cyc_o' |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'stb_o', |
'type' => 'output' |
}, |
'dwb_sel_o' => { |
'intfc_port' => 'sel_o', |
'range' => '3:0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'sys_int_i' => { |
'intfc_port' => 'int_i', |
'iwb_rty_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'socket:interrupt_cpu[0]' |
}, |
'iwb_dat_i' => { |
'intfc_port' => 'dat_i', |
'range' => '31:0', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'rty_i', |
'type' => 'input' |
}, |
'dwb_err_i' => { |
'intfc_port' => 'err_i', |
'iwb_stb_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'stb_o' |
}, |
'dwb_dat_i' => { |
'range' => '31:0', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[1]' |
'intfc_port' => 'dat_i' |
}, |
'iwb_sel_o' => { |
'intfc_port' => 'sel_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'sel_o', |
'range' => '3:0' |
}, |
'iwb_wre_o' => { |
'intfc_port' => 'we_o', |
'range' => '', |
'dwb_sel_o' => { |
'intfc_port' => 'sel_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'dwb_adr_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'intfc_port' => 'adr_o', |
'range' => '31:0' |
'range' => '3:0' |
}, |
'iwb_cti_o' => { |
'range' => '2:0', |
'intfc_port' => 'cti_o', |
'iwb_dat_o' => { |
'range' => '31:0', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
'intfc_port' => 'dat_o' |
}, |
'iwb_err_i' => { |
'intfc_port' => 'err_i', |
'sys_int_i' => { |
'type' => 'input', |
'intfc_port' => 'int_i', |
'range' => '', |
'intfc_name' => 'socket:interrupt_cpu[0]' |
}, |
'iwb_dat_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input' |
}, |
'dwb_tag_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'tag_o', |
'range' => '2:0' |
}, |
'sys_ena_i' => { |
'intfc_name' => 'plug:enable[0]', |
'range' => '31:0', |
'type' => 'input', |
'intfc_port' => 'enable_i', |
'range' => '' |
'intfc_port' => 'dat_i' |
}, |
'dwb_ack_i' => { |
'dwb_rty_i' => { |
'range' => '', |
'intfc_port' => 'ack_i', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input' |
'type' => 'input', |
'intfc_port' => 'rty_i' |
}, |
'iwb_bte_o' => { |
'range' => '1:0', |
'intfc_port' => 'bte_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output' |
}, |
'iwb_dat_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'range' => '31:0' |
}, |
'dwb_cti_o' => { |
'type' => 'output', |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'reset_i' |
}, |
'dwb_tag_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '2:0', |
'intfc_port' => 'cti_o' |
}, |
'iwb_ack_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input', |
'intfc_port' => 'ack_i', |
'range' => '' |
'type' => 'output', |
'intfc_port' => 'tag_o' |
} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'modules' => { |
'aeMB_top' => {} |
}, |
'ip_name' => 'aeMB', |
'system_h' => ' #include <stdio.h> |
#include <stdlib.h> |
#include "aemb/core.hh" |
|
inline void nop (void) { |
asm volatile ("nop"); |
}', |
'ports_order' => [ |
'dwb_adr_o', |
'dwb_cyc_o', |
'dwb_dat_o', |
'dwb_sel_o', |
'dwb_stb_o', |
'dwb_tag_o', |
'dwb_wre_o', |
'dwb_cti_o', |
'dwb_bte_o', |
'dwb_ack_i', |
'dwb_dat_i', |
'dwb_err_i', |
'dwb_rty_i', |
'iwb_adr_o', |
'iwb_cyc_o', |
'iwb_sel_o', |
'iwb_stb_o', |
'iwb_tag_o', |
'iwb_wre_o', |
'iwb_dat_o', |
'iwb_cti_o', |
'iwb_bte_o', |
'iwb_ack_i', |
'iwb_dat_i', |
'iwb_err_i', |
'iwb_rty_i', |
'clk', |
'reset', |
'sys_int_i', |
'sys_ena_i' |
], |
'category' => 'Processor', |
'sw_files' => [ |
'/mpsoc/src_processor/aeMB/sw/aemb', |
'/mpsoc/src_processor/aeMB/sw/compile', |
'/mpsoc/src_processor/aeMB/sw/program', |
'/mpsoc/src_processor/program.sh', |
'/mpsoc/src_processor/aeMB/sw/define_printf.h' |
], |
'parameters_order' => [ |
'AEMB_IWB', |
'AEMB_DWB', |
'AEMB_XWB', |
'AEMB_ICH', |
'AEMB_IDX', |
'AEMB_BSF', |
'AEMB_MUL', |
'STACK_SIZE', |
'HEAP_SIZE' |
] |
'system_c' => ' |
#include "aemb/core.cc" |
|
/*! |
* Assembly macro to enable MSR_IE |
*/ |
void aemb_enable_interrupt () |
{ |
int msr, tmp; |
asm volatile ("mfs %0, rmsr;" |
"ori %1, %0, 0x02;" |
"mts rmsr, %1;" |
: "=r"(msr) |
: "r" (tmp) |
); |
} |
|
void aemb_disable_interrupt () |
{ |
int msr, tmp; |
asm volatile ("mfs %0, rmsr;" |
"andi %1, %0, 0xFD;" |
"mts rmsr, %1;" |
: "=r"(msr) |
: "r" (tmp) |
); |
} |
|
|
/* Loops/exits simulation */ |
void exit (int i) |
{ |
aemb_disable_interrupt (); |
while (1); |
} |
|
|
|
|
' |
}, 'ip_gen' ); |
/Processor/lm32.IP
1,381 → 1,448
####################################################################### |
## File: lm32.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.7.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$lm32 = bless( { |
'hdl_files' => [ |
'/mpsoc/src_processor/lm32/verilog/src/er1.v', |
'/mpsoc/src_processor/lm32/verilog/src/JTAGB.v', |
'/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_include.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_top.v', |
'/mpsoc/src_processor/lm32/verilog/src/spiprog.v', |
'/mpsoc/src_processor/lm32/verilog/src/system_conf.v', |
'/mpsoc/src_processor/lm32/verilog/src/typea.v', |
'/mpsoc/src_processor/lm32/verilog/src/typeb.v' |
], |
'category' => 'Processor', |
'sockets' => { |
'interrupt_peripheral' => { |
'type' => 'param', |
'interrupt_peripheral' => {}, |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'value' => 'INTR_NUM', |
'connection_num' => 'single connection' |
} |
}, |
'sw_files' => [ |
'/mpsoc/src_processor/lm32/sw/crt0ram.S', |
'/mpsoc/src_processor/lm32/sw/linker.ld', |
'/mpsoc/src_processor/lm32/sw/lm32_system.h', |
'/mpsoc/src_processor/lm32/sw/Makefile', |
'/mpsoc/src_processor/lm32/sw/program', |
'/mpsoc/src_processor/program.sh', |
'/mpsoc/src_processor/lm32/sw/define_printf.h', |
'/mpsoc/src_processor/src_lib/simple-printf' |
], |
'unused' => { |
'plug:wb_master[0]' => [ |
'tag_o' |
], |
'plug:wb_master[1]' => [ |
'tag_o' |
] |
}, |
'module_name' => 'lm32', |
'parameters_order' => [ |
'INTR_NUM', |
'CFG_PL_MULTIPLY', |
'CFG_PL_BARREL_SHIFT', |
'CFG_SIGN_EXTEND', |
'CFG_MC_DIVIDE' |
], |
'system_h' => '#include "lm32_system.h" |
inline void nop (void) { |
asm volatile ("nop"); |
}', |
'modules' => { |
'lm32' => {} |
}, |
'ip_name' => 'lm32', |
'plugs' => { |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'reset' => {}, |
'1' => { |
'name' => 'reset_1' |
}, |
'value' => 1 |
}, |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num', |
'clk' => {}, |
'value' => 1 |
}, |
'enable' => { |
'enable' => {}, |
'type' => 'num', |
$ipgen = bless( { |
'version' => 5, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'ports_order' => [ |
'clk_i', |
'rst_i', |
'en_i', |
'interrupt', |
'I_DAT_I', |
'I_ACK_I', |
'I_ERR_I', |
'I_RTY_I', |
'I_DAT_O', |
'I_ADR_O', |
'I_CYC_O', |
'I_SEL_O', |
'I_STB_O', |
'I_WE_O', |
'I_CTI_O', |
'I_BTE_O', |
'D_DAT_I', |
'D_ACK_I', |
'D_ERR_I', |
'D_RTY_I', |
'D_DAT_O', |
'D_ADR_O', |
'D_CYC_O', |
'D_SEL_O', |
'D_STB_O', |
'D_WE_O', |
'D_CTI_O', |
'D_BTE_O' |
], |
'ip_name' => 'lm32', |
'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement. |
|
for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx', |
'plugs' => { |
'enable' => { |
'type' => 'num', |
'enable' => {}, |
'value' => 1, |
'0' => { |
'name' => 'enable' |
} |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'wb_master' => { |
'1' => { |
'name' => 'dwb' |
}, |
'0' => { |
'name' => 'iwb' |
}, |
'value' => 2, |
'type' => 'num', |
'wb_master' => {} |
}, |
'reset' => { |
'value' => 1, |
'1' => { |
'name' => 'reset_1' |
}, |
'0' => { |
'name' => 'enable' |
'name' => 'reset' |
}, |
'value' => 1 |
}, |
'wb_master' => { |
'1' => { |
'name' => 'dwb' |
}, |
'value' => 2, |
'0' => { |
'name' => 'iwb' |
}, |
'type' => 'num', |
'wb_master' => {} |
} |
}, |
'ports' => { |
'interrupt' => { |
'intfc_port' => 'int_i', |
'type' => 'input', |
'range' => '(32-1):0', |
'intfc_name' => 'socket:interrupt_peripheral[array]' |
}, |
'D_ACK_I' => { |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'D_RTY_I' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'rty_i', |
'range' => '', |
'type' => 'input' |
}, |
'I_CTI_O' => { |
'intfc_name' => 'plug:wb_master[0]', |
'reset' => {}, |
'type' => 'num' |
} |
}, |
'ports' => { |
'D_CYC_O' => { |
'type' => 'output', |
'intfc_port' => 'cyc_o', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'I_WE_O' => { |
'type' => 'output', |
'range' => '(3-1):0', |
'intfc_port' => 'cti_o' |
}, |
'I_DAT_O' => { |
'type' => 'output', |
'range' => '(32-1):0', |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'I_DAT_I' => { |
'type' => 'input', |
'range' => '(32-1):0', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'D_ADR_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'adr_o', |
'type' => 'output', |
'range' => '(32-1):0' |
}, |
'I_ACK_I' => { |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'I_BTE_O' => { |
'intfc_port' => 'bte_o', |
'type' => 'output', |
'range' => '(2-1):0', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'I_RTY_I' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'rty_i' |
'intfc_port' => 'we_o' |
}, |
'clk_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]' |
}, |
'D_CTI_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '(3-1):0', |
'type' => 'output', |
'intfc_port' => 'cti_o' |
}, |
'D_DAT_I' => { |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input', |
'range' => '(32-1):0', |
'intfc_port' => 'dat_i' |
}, |
'D_WE_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'we_o', |
'I_DAT_O' => { |
'intfc_port' => 'dat_o', |
'range' => '(32-1):0', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output' |
}, |
'rst_i' => { |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'output' |
'intfc_name' => 'plug:reset[0]' |
}, |
'rst_i' => { |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'D_ERR_I' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'err_i', |
'type' => 'input' |
}, |
'D_CTI_O' => { |
'intfc_port' => 'cti_o', |
'range' => '(3-1):0', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
}, |
'en_i' => { |
'range' => '', |
'intfc_port' => 'reset_i' |
'intfc_name' => 'plug:enable[0]', |
'intfc_port' => 'enable_i', |
'type' => 'input' |
}, |
'en_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'enable_i', |
'intfc_name' => 'plug:enable[0]' |
}, |
'D_BTE_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'bte_o', |
'type' => 'output', |
'range' => '(2-1):0' |
}, |
'I_SEL_O' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(4-1):0', |
'type' => 'output', |
'intfc_port' => 'sel_o' |
}, |
'D_DAT_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => '(32-1):0', |
'intfc_port' => 'dat_o' |
}, |
'D_ERR_I' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'err_i', |
'range' => '', |
'type' => 'input' |
}, |
'I_STB_O' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'stb_o', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'I_WE_O' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'we_o', |
'I_ERR_I' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'err_i', |
'type' => 'input' |
}, |
'clk_i' => { |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'output' |
'intfc_name' => 'plug:clk[0]' |
}, |
'I_ADR_O' => { |
'intfc_name' => 'plug:wb_master[0]', |
'I_ACK_I' => { |
'intfc_port' => 'ack_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input' |
}, |
'I_ADR_O' => { |
'type' => 'output', |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(32-1):0' |
}, |
'D_ADR_O' => { |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '(32-1):0', |
'type' => 'output' |
}, |
'D_STB_O' => { |
'intfc_port' => 'stb_o', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
}, |
'I_RTY_I' => { |
'intfc_port' => 'rty_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input' |
}, |
'interrupt' => { |
'type' => 'input', |
'intfc_port' => 'int_i', |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'range' => '(32-1):0' |
}, |
'D_BTE_O' => { |
'range' => '(2-1):0', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'bte_o', |
'type' => 'output' |
}, |
'D_RTY_I' => { |
'intfc_port' => 'rty_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input' |
}, |
'I_CTI_O' => { |
'type' => 'output', |
'intfc_port' => 'cti_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(3-1):0' |
}, |
'D_WE_O' => { |
'type' => 'output', |
'range' => '(32-1):0', |
'intfc_port' => 'adr_o' |
}, |
'I_ERR_I' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'err_i' |
}, |
'D_STB_O' => { |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'stb_o', |
'range' => '', |
'type' => 'output' |
'range' => '' |
}, |
'D_CYC_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'cyc_o', |
'range' => '', |
'type' => 'output' |
}, |
'D_SEL_O' => { |
'range' => '(4-1):0', |
'type' => 'output', |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'I_CYC_O' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cyc_o', |
'type' => 'output', |
'range' => '' |
} |
}, |
'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement. |
|
for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx', |
'ports_order' => [ |
'clk_i', |
'rst_i', |
'en_i', |
'interrupt', |
'I_DAT_I', |
'I_ACK_I', |
'I_ERR_I', |
'I_RTY_I', |
'I_DAT_O', |
'I_ADR_O', |
'I_CYC_O', |
'I_SEL_O', |
'I_STB_O', |
'I_WE_O', |
'I_CTI_O', |
'I_BTE_O', |
'D_DAT_I', |
'D_ACK_I', |
'D_ERR_I', |
'D_RTY_I', |
'D_DAT_O', |
'D_ADR_O', |
'D_CYC_O', |
'D_SEL_O', |
'D_STB_O', |
'D_WE_O', |
'D_CTI_O', |
'D_BTE_O' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v', |
'version' => 2, |
'I_CYC_O' => { |
'type' => 'output', |
'intfc_port' => 'cyc_o', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'D_DAT_I' => { |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'range' => '(32-1):0', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'I_SEL_O' => { |
'type' => 'output', |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(4-1):0' |
}, |
'I_BTE_O' => { |
'type' => 'output', |
'range' => '(2-1):0', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'bte_o' |
}, |
'I_STB_O' => { |
'intfc_port' => 'stb_o', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output' |
}, |
'D_ACK_I' => { |
'intfc_port' => 'ack_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input' |
}, |
'D_SEL_O' => { |
'type' => 'output', |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '(4-1):0' |
}, |
'D_DAT_O' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '(32-1):0', |
'intfc_port' => 'dat_o' |
}, |
'I_DAT_I' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(32-1):0', |
'intfc_port' => 'dat_i', |
'type' => 'input' |
} |
}, |
'hdl_files' => [ |
'/mpsoc/src_processor/lm32/verilog/src/er1.v', |
'/mpsoc/src_processor/lm32/verilog/src/JTAGB.v', |
'/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_include.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v', |
'/mpsoc/src_processor/lm32/verilog/src/lm32_top.v', |
'/mpsoc/src_processor/lm32/verilog/src/spiprog.v', |
'/mpsoc/src_processor/lm32/verilog/src/system_conf.v', |
'/mpsoc/src_processor/lm32/verilog/src/typea.v', |
'/mpsoc/src_processor/lm32/verilog/src/typeb.v' |
], |
'unused' => { |
'plug:wb_master[0]' => [ |
'tag_o' |
], |
'plug:wb_master[1]' => [ |
'tag_o' |
] |
}, |
'module_name' => 'lm32', |
'parameters_order' => [ |
'INTR_NUM', |
'BARREL_SHIFT', |
'SIGN_EXTEND', |
'BARREL_SHIFT', |
'MULTIPLIER_TYPE', |
'DIVIDOR_TYPE', |
'INSTRUCTION_CACHE', |
'ICACHE_ASSOCIATIVITY', |
'ICACHE_SETS', |
'DATA_CACHE', |
'DCACHE_ASSOCIATIVITY', |
'DCACHE_SETS' |
], |
'system_c' => '#include "lm32/lm32_system.c"', |
'category' => 'Processor', |
'modules' => { |
'lm32' => {} |
}, |
'gen_sw_files' => [ |
'/mpsoc/src_processor/new_lm32/sw/cpu_flags_genfrename_sep_tcpu_flags' |
], |
'gen_hw_files' => [ |
'/mpsoc/src_processor/new_lm32/config/lm32_config_gen.vfrename_sep_tlib/lm32_config.v' |
], |
'sw_files' => [ |
'/mpsoc/src_processor/lm32/sw/lm32', |
'/mpsoc/src_processor/lm32/sw/linker.ld', |
'/mpsoc/src_processor/lm32/sw/Makefile' |
], |
'parameters' => { |
'CFG_MC_DIVIDE' => { |
'global_param' => 0, |
'content' => '"ENABLED","DISABLED"', |
'info' => undef, |
'INTR_NUM' => { |
'redefine_param' => 1, |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'content' => '', |
'default' => '32', |
'info' => undef |
}, |
'SIGN_EXTEND' => { |
'content' => 'ENABLED,DISABLED', |
'global_param' => 'Don\'t include', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'info' => 'Enable sign-extension instructions', |
'default' => 'ENABLED' |
}, |
'INSTRUCTION_CACHE' => { |
'default' => 'ENABLED', |
'info' => 'Enable/Disable Instruction cache', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'content' => 'ENABLED,DISABLED', |
'global_param' => 'Don\'t include' |
}, |
'BARREL_SHIFT' => { |
'content' => 'MULTI_CYCLE,PIPE_LINE,NONE', |
'global_param' => 'Don\'t include', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'default' => '"DISABLED"', |
'type' => 'Fixed' |
'info' => 'Shifter |
You may either enable the piplined or the multi-cycle barrel |
shifter. The multi-cycle shifter will stall the pipeline until |
the result is available after 32 cycles. |
If both options are disabled, only "right shift by one bit" is |
available.', |
'default' => 'PIPE_LINE' |
}, |
'INTR_NUM' => { |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'content' => '', |
'global_param' => 0 |
}, |
'CFG_SIGN_EXTEND' => { |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'redefine_param' => 1, |
'info' => undef, |
'content' => '"ENABLED","DISABLED"', |
'global_param' => 0 |
}, |
'CFG_PL_MULTIPLY' => { |
'content' => '"ENABLED","DISABLED"', |
'global_param' => 0, |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '"ENABLED"' |
}, |
'CFG_PL_BARREL_SHIFT' => { |
'content' => '"ENABLED","DISABLED"', |
'global_param' => 0, |
'type' => 'Fixed', |
'default' => '"ENABLED"', |
'redefine_param' => 1, |
'info' => undef |
} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
} |
}, 'ip_gen' ); |
'DCACHE_ASSOCIATIVITY' => { |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'content' => '1,2,4,8', |
'global_param' => 'Don\'t include', |
'default' => '1', |
'info' => 'Data cache assocativity number ' |
}, |
'DIVIDOR_TYPE' => { |
'info' => ' Enable the multi-cycle divider. Stalls the pipe until the result |
is ready after 32 cycles. If disabled, the divide operation is not supported.', |
'default' => 'MULTI_CYCLE', |
'global_param' => 'Don\'t include', |
'content' => 'MULTI_CYCLE,NONE', |
'type' => 'Combo-box', |
'redefine_param' => 1 |
}, |
'MULTIPLIER_TYPE' => { |
'info' => '// Multiplier |
The multiplier is available either in a multi-cycle version or |
in a pipelined one. The multi-cycle multiplier stalls the pipe |
for 32 cycles. If both options are disabled, multiply operations |
are not supported.', |
'default' => 'PIPE_LINE', |
'global_param' => 'Don\'t include', |
'content' => 'MULTI_CYCLE,PIPE_LINE,NONE', |
'type' => 'Combo-box', |
'redefine_param' => 1 |
}, |
'DATA_CACHE' => { |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'global_param' => 'Don\'t include', |
'content' => 'ENABLED,DISABLED', |
'default' => 'ENABLED', |
'info' => 'Enable/Disable the data cache' |
}, |
'DCACHE_SETS' => { |
'info' => ' Number of sets', |
'default' => '256', |
'global_param' => 'Don\'t include', |
'content' => '128,256,512,1024,2048,4096,8119,16384', |
'redefine_param' => 1, |
'type' => 'Combo-box' |
}, |
'ICACHE_ASSOCIATIVITY' => { |
'info' => 'Istruction cache assocativity number ', |
'default' => '1', |
'global_param' => 'Don\'t include', |
'content' => '1,2,4,8', |
'redefine_param' => 1, |
'type' => 'Combo-box' |
}, |
'ICACHE_SETS' => { |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'global_param' => 'Don\'t include', |
'content' => '128,256,512,1024,2048,4096,8119,16384', |
'default' => '256', |
'info' => ' Number of sets' |
} |
}, |
'system_h' => '#include "lm32/lm32_system.h" |
static inline void nop (void) { |
asm volatile ("nop"); |
}', |
'sockets' => { |
'interrupt_peripheral' => { |
'connection_num' => 'single connection', |
'type' => 'param', |
'interrupt_peripheral' => {}, |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'value' => 'INTR_NUM' |
} |
}, |
'file_name' => 'mpsoc/src_processor/lm32/verilog/src/lm32.v' |
}, 'ip_gen' ); |
/Processor/lm32_new.IP
0,0 → 1,442
####################################################################### |
## File: lm32_new.IP |
## |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ipgen = bless( { |
'parameters_order' => [ |
'INTR_NUM', |
'BARREL_SHIFT', |
'SIGN_EXTEND', |
'BARREL_SHIFT', |
'MULTIPLIER_TYPE', |
'DIVIDOR_TYPE', |
'INSTRUCTION_CACHE', |
'ICACHE_ASSOCIATIVITY', |
'ICACHE_SETS', |
'DATA_CACHE', |
'DCACHE_ASSOCIATIVITY', |
'DCACHE_SETS' |
], |
'sw_files' => [ |
'/mpsoc/src_processor/lm32/sw/lm32', |
'/mpsoc/src_processor/lm32/sw/linker.ld', |
'/mpsoc/src_processor/lm32/sw/Makefile' |
], |
'version' => 17, |
'system_h' => '#include "lm32/lm32_system.h" |
static inline void nop (void) { |
asm volatile ("nop"); |
}', |
'sockets' => { |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'value' => 'INTR_NUM', |
'type' => 'param', |
'connection_num' => 'single connection', |
'0' => { |
'name' => 'interrupt_peripheral' |
} |
} |
}, |
'hdl_files' => [ |
'/mpsoc/src_processor/new_lm32/rtl/lm32_top.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_shifter.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_ram.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_multiplier.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_mc_arithmetic.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_logic_op.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_load_store_unit.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_jtag.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_itlb.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_interrupt.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_instruction_unit.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_include.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_icache.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_dtlb.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_dp_ram.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_decoder.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_debug.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_dcache.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_cpu.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_addsub.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32_adder.v', |
'/mpsoc/src_processor/new_lm32/rtl/lm32.v', |
'/mpsoc/src_processor/new_lm32/rtl/jtag_tap_spartan6.v', |
'/mpsoc/src_processor/new_lm32/rtl/jtag_cores.v' |
], |
'file_name' => 'mpsoc/src_processor/lm32/verilog/src/lm32.v', |
'module_name' => 'lm32', |
'ip_name' => 'lm32_new', |
'parameters' => { |
'INTR_NUM' => { |
'type' => 'Fixed', |
'redefine_param' => 1, |
'default' => '32', |
'content' => '', |
'info' => undef, |
'global_param' => 'Localparam' |
}, |
'DIVIDOR_TYPE' => { |
'global_param' => 'Don\'t include', |
'info' => ' Enable the multi-cycle divider. Stalls the pipe until the result |
is ready after 32 cycles. If disabled, the divide operation is not supported.', |
'content' => 'MULTI_CYCLE,NONE', |
'default' => 'MULTI_CYCLE', |
'redefine_param' => 1, |
'type' => 'Combo-box' |
}, |
'BARREL_SHIFT' => { |
'default' => 'PIPE_LINE', |
'global_param' => 'Don\'t include', |
'info' => 'Shifter |
You may either enable the piplined or the multi-cycle barrel |
shifter. The multi-cycle shifter will stall the pipeline until |
the result is available after 32 cycles. |
If both options are disabled, only "right shift by one bit" is |
available.', |
'content' => 'MULTI_CYCLE,PIPE_LINE,NONE', |
'type' => 'Combo-box', |
'redefine_param' => 1 |
}, |
'DCACHE_SETS' => { |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'content' => '128,256,512,1024,2048,4096,8119,16384', |
'info' => ' Number of sets', |
'global_param' => 'Don\'t include', |
'default' => '256' |
}, |
'DCACHE_ASSOCIATIVITY' => { |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'content' => '1,2,4,8', |
'global_param' => 'Don\'t include', |
'info' => 'Data cache assocativity number ', |
'default' => '1' |
}, |
'INSTRUCTION_CACHE' => { |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'default' => 'ENABLED', |
'global_param' => 'Don\'t include', |
'info' => 'Enable/Disable Instruction cache', |
'content' => 'ENABLED,DISABLED' |
}, |
'DATA_CACHE' => { |
'content' => 'ENABLED,DISABLED', |
'global_param' => 'Don\'t include', |
'info' => 'Enable/Disable the data cache', |
'default' => 'ENABLED', |
'redefine_param' => 1, |
'type' => 'Combo-box' |
}, |
'ICACHE_ASSOCIATIVITY' => { |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'global_param' => 'Don\'t include', |
'content' => '1,2,4,8', |
'info' => 'Istruction cache assocativity number ', |
'default' => '1' |
}, |
'ICACHE_SETS' => { |
'default' => '256', |
'info' => ' Number of sets', |
'global_param' => 'Don\'t include', |
'content' => '128,256,512,1024,2048,4096,8119,16384', |
'type' => 'Combo-box', |
'redefine_param' => 1 |
}, |
'MULTIPLIER_TYPE' => { |
'content' => 'MULTI_CYCLE,PIPE_LINE,NONE', |
'global_param' => 'Don\'t include', |
'info' => '// Multiplier |
The multiplier is available either in a multi-cycle version or |
in a pipelined one. The multi-cycle multiplier stalls the pipe |
for 32 cycles. If both options are disabled, multiply operations |
are not supported.', |
'default' => 'PIPE_LINE', |
'redefine_param' => 1, |
'type' => 'Combo-box' |
}, |
'SIGN_EXTEND' => { |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'default' => 'ENABLED', |
'global_param' => 'Don\'t include', |
'content' => 'ENABLED,DISABLED', |
'info' => 'Enable sign-extension instructions' |
} |
}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'modules' => { |
'lm32' => {} |
}, |
'ports' => { |
'I_ERR_I' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'err_i' |
}, |
'D_ERR_I' => { |
'intfc_port' => 'err_i', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '', |
'type' => 'input' |
}, |
'I_CTI_O' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '(3-1):0', |
'intfc_port' => 'cti_o' |
}, |
'D_SEL_O' => { |
'intfc_port' => 'sel_o', |
'range' => '(4-1):0', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
}, |
'I_SEL_O' => { |
'range' => '(4-1):0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'sel_o' |
}, |
'en_i' => { |
'range' => '', |
'intfc_name' => 'plug:enable[0]', |
'type' => 'input', |
'intfc_port' => 'enable_i' |
}, |
'interrupt' => { |
'type' => 'input', |
'range' => '(32-1):0', |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'intfc_port' => 'int_i' |
}, |
'I_DAT_O' => { |
'type' => 'output', |
'range' => '(32-1):0', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'dat_o' |
}, |
'D_ADR_O' => { |
'intfc_port' => 'adr_o', |
'range' => '(32-1):0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'I_BTE_O' => { |
'type' => 'output', |
'range' => '(2-1):0', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'bte_o' |
}, |
'D_STB_O' => { |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'stb_o' |
}, |
'I_ACK_I' => { |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'I_DAT_I' => { |
'intfc_port' => 'dat_i', |
'type' => 'input', |
'range' => '(32-1):0', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'D_CYC_O' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '', |
'intfc_port' => 'cyc_o' |
}, |
'clk_i' => { |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]' |
}, |
'I_ADR_O' => { |
'intfc_port' => 'adr_o', |
'type' => 'output', |
'range' => '(32-1):0', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'rst_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i' |
}, |
'D_DAT_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '(32-1):0', |
'type' => 'output', |
'intfc_port' => 'dat_o' |
}, |
'I_STB_O' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'stb_o' |
}, |
'D_RTY_I' => { |
'intfc_port' => 'rty_i', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '', |
'type' => 'input' |
}, |
'I_RTY_I' => { |
'intfc_port' => 'rty_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'input' |
}, |
'I_CYC_O' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'cyc_o' |
}, |
'D_CTI_O' => { |
'intfc_port' => 'cti_o', |
'range' => '(3-1):0', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output' |
}, |
'D_ACK_I' => { |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'I_WE_O' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'we_o' |
}, |
'D_DAT_I' => { |
'intfc_port' => 'dat_i', |
'type' => 'input', |
'range' => '(32-1):0', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'D_BTE_O' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '(2-1):0', |
'type' => 'output', |
'intfc_port' => 'bte_o' |
}, |
'D_WE_O' => { |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => '' |
} |
}, |
'unused' => { |
'plug:wb_master[1]' => [ |
'tag_o' |
], |
'plug:wb_master[0]' => [ |
'tag_o' |
] |
}, |
'category' => 'Processor', |
'gen_sw_files' => [ |
'/mpsoc/src_processor/new_lm32/sw/cpu_flags_genfrename_sep_tcpu_flags' |
], |
'description' => 'A fork of the original LatticeMico32 sources that includes new features. The source code is adopted from: |
https://github.com/m-labs/lm32', |
'plugs' => { |
'enable' => { |
'enable' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'enable' |
}, |
'value' => 1 |
}, |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num', |
'value' => 1, |
'clk' => {} |
}, |
'wb_master' => { |
'value' => 2, |
'type' => 'num', |
'0' => { |
'name' => 'iwb' |
}, |
'1' => { |
'name' => 'dwb' |
}, |
'wb_master' => {} |
}, |
'reset' => { |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'1' => { |
'name' => 'reset_1' |
}, |
'reset' => {} |
} |
}, |
'gen_hw_files' => [ |
'/mpsoc/src_processor/new_lm32/config/lm32_config_gen.vfrename_sep_tlib/lm32_config.v' |
], |
'system_c' => '#include "lm32/lm32_system.c"', |
'ports_order' => [ |
'clk_i', |
'rst_i', |
'en_i', |
'interrupt', |
'I_DAT_I', |
'I_ACK_I', |
'I_ERR_I', |
'I_RTY_I', |
'I_DAT_O', |
'I_ADR_O', |
'I_CYC_O', |
'I_SEL_O', |
'I_STB_O', |
'I_WE_O', |
'I_CTI_O', |
'I_BTE_O', |
'D_DAT_I', |
'D_ACK_I', |
'D_ERR_I', |
'D_RTY_I', |
'D_DAT_O', |
'D_ADR_O', |
'D_CYC_O', |
'D_SEL_O', |
'D_STB_O', |
'D_WE_O', |
'D_CTI_O', |
'D_BTE_O' |
] |
}, 'ip_gen' ); |
/Processor/mor1kx.IP
1,65 → 1,15
####################################################################### |
## File: mor1kx.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.1 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
## MAY CAUSE UNEXPECTED BEHAVIOR. |
################################################################################ |
|
$ipgen = bless( { |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'modules' => { |
'mor1k' => {} |
}, |
'hdl_files' => [ |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_branch_prediction.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_avalon.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_wb32.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cache_lru.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cfgrs.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dcache.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode_execute_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-defines.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dmmu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_alu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_icache.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_immu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_pic.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_simple_dpram_sclk.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-sprs.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_store_buffer.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ticktimer.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_true_dpram_sclk.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_utils.vh', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v' |
], |
'module_name' => 'mor1k', |
'parameters_order' => [ |
'OPTION_OPERAND_WIDTH', |
'IRQ_NUM', |
67,135 → 17,123
'FEATURE_INSTRUCTIONCACHE', |
'FEATURE_DATACACHE', |
'FEATURE_IMMU', |
'FEATURE_DMMU' |
'FEATURE_DMMU', |
'FEATURE_MULTIPLIER', |
'FEATURE_DIVIDER', |
'OPTION_SHIFTER' |
], |
'sw_files' => [ |
'/mpsoc/src_processor/mor1kx-3.1/sw/link.ld', |
'/mpsoc/src_processor/mor1kx-3.1/sw/Makefile', |
'/mpsoc/src_processor/mor1kx-3.1/sw/mor1kx', |
'/mpsoc/src_processor/src_lib/simple-printf', |
'/mpsoc/src_processor/mor1kx-3.1/sw/define_printf.h' |
], |
'version' => 17, |
'sockets' => { |
'interrupt_peripheral' => { |
'type' => 'param', |
'value' => 'IRQ_NUM', |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'connection_num' => 'single connection' |
} |
}, |
'ip_name' => 'mor1kx', |
'category' => 'Processor', |
'file_name' => '/home/alireza/mywork/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v', |
'unused' => { |
'plug:wb_master[1]' => [ |
'tag_o' |
], |
'plug:wb_master[0]' => [ |
'tag_o' |
] |
}, |
'parameters' => { |
'FEATURE_IMMU' => { |
'content' => '"NONE","ENABLED"', |
'type' => 'Combo-box', |
'default' => '"ENABLED"', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'info' => '' |
}, |
'OPTION_OPERAND_WIDTH' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'default' => '32', |
'type' => 'Fixed', |
'default' => '32', |
'content' => '', |
'info' => 'Parameter', |
'redefine_param' => 1, |
'global_param' => 'Parameter' |
'global_param' => 'Localparam' |
}, |
'FEATURE_DMMU' => { |
'info' => '', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'default' => '"ENABLED"', |
'content' => '"NONE","ENABLED"' |
}, |
'FEATURE_INSTRUCTIONCACHE' => { |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'info' => '', |
'global_param' => 'Localparam', |
'content' => '"NONE","ENABLED"', |
'type' => 'Combo-box', |
'default' => '"ENABLED"', |
'type' => 'Combo-box' |
'redefine_param' => 1, |
'info' => '' |
}, |
'OPTION_DCACHE_SNOOP' => { |
'info' => '', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'global_param' => 'Localparam', |
'content' => '"NONE","ENABLED"', |
'type' => 'Combo-box', |
'default' => '"NONE"', |
'type' => 'Combo-box', |
'content' => '"NONE","ENABLED"' |
'redefine_param' => 1 |
}, |
'FEATURE_DMMU' => { |
'type' => 'Combo-box', |
'content' => '"NONE","ENABLED"', |
'global_param' => 'Localparam', |
'default' => '"ENABLED"', |
'redefine_param' => 1, |
'info' => '' |
}, |
'FEATURE_DATACACHE' => { |
'info' => '', |
'type' => 'Combo-box', |
'content' => '"NONE","ENABLED"', |
'global_param' => 'Localparam', |
'default' => '"ENABLED"', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'info' => '' |
'redefine_param' => 1 |
}, |
'OPTION_SHIFTER' => { |
'info' => 'Specify the shifter implementation', |
'redefine_param' => 1, |
'default' => '"BARREL"', |
'content' => '"BARREL","SERIAL"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam' |
}, |
'IRQ_NUM' => { |
'info' => undef, |
'default' => '32', |
'content' => '', |
'type' => 'Fixed', |
'default' => '32', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'info' => undef |
} |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'FEATURE_DIVIDER' => { |
'info' => 'Specify the divider implementation', |
'redefine_param' => 1, |
'default' => '"SERIAL"', |
'content' => '"SERIAL","NONE"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam' |
}, |
'FEATURE_MULTIPLIER' => { |
'default' => '"THREESTAGE"', |
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Specify the multiplier implementation' |
}, |
'FEATURE_IMMU' => { |
'info' => '', |
'default' => '"ENABLED"', |
'content' => '"NONE","ENABLED"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
} |
}, |
'plugs' => { |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'enable' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'enable' |
} |
}, |
'wb_master' => { |
'1' => { |
'name' => 'dwb' |
}, |
'0' => { |
'name' => 'iwb' |
}, |
'value' => 2, |
'type' => 'num' |
}, |
'snoop' => { |
'type' => 'num', |
'0' => { |
'name' => 'snoop' |
}, |
'value' => 1 |
} |
}, |
'gen_sw_files' => [ |
'/mpsoc/src_processor/mor1kx-3.1/sw/march_flags.makfrename_sep_tmarch_flags.mak' |
], |
'module_name' => 'mor1k', |
'sw_files' => [ |
'/mpsoc/src_processor/mor1kx-3.1/sw/link.ld', |
'/mpsoc/src_processor/mor1kx-3.1/sw/Makefile', |
'/mpsoc/src_processor/mor1kx-3.1/sw/mor1kx' |
], |
'system_c' => '', |
'unused' => { |
'plug:wb_master[1]' => [ |
'tag_o' |
], |
'plug:wb_master[0]' => [ |
'tag_o' |
] |
}, |
'sockets' => { |
'interrupt_peripheral' => { |
'value' => 'IRQ_NUM', |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'type' => 'param', |
'connection_num' => 'single connection' |
} |
}, |
'file_name' => 'mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v', |
'ports_order' => [ |
'clk', |
'rst', |
228,9 → 166,50
'dwbm_rty_i', |
'irq_i' |
], |
'plugs' => { |
'snoop' => { |
'type' => 'num', |
'0' => { |
'name' => 'snoop' |
}, |
'value' => 1 |
}, |
'clk' => { |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1 |
}, |
'wb_master' => { |
'0' => { |
'name' => 'iwb' |
}, |
'value' => 2, |
'type' => 'num', |
'1' => { |
'name' => 'dwb' |
} |
}, |
'enable' => { |
'value' => 1, |
'0' => { |
'name' => 'enable' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
} |
}, |
'version' => 26, |
'system_h' => ' #include "mor1kx/system.h" |
|
inline void nop (){ |
static inline void nop (){ |
__asm__("l.nop 1"); |
} |
/********************* |
259,186 → 238,236
} |
} |
*******************************/', |
'category' => 'Processor', |
'hdl_files' => [ |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_branch_prediction.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_avalon.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_bus_if_wb32.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cache_lru.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cfgrs.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_cpu_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ctrl_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dcache.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_decode_execute_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-defines.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_dmmu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_alu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_icache.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_immu.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_lsu_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_pic.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_rf_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_simple_dpram_sclk.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx-sprs.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_store_buffer.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_ticktimer.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_true_dpram_sclk.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_utils.vh', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/verilog/mor1kx_wb_mux_espresso.v', |
'/mpsoc/src_processor/mor1kx-3.1/rtl/mor1k.v' |
], |
'ports' => { |
'iwbm_stb_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'stb_o', |
'dwbm_ack_i' => { |
'intfc_port' => 'ack_i', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input', |
'range' => '' |
}, |
'dwbm_sel_o' => { |
'intfc_port' => 'sel_o', |
'type' => 'output', |
'range' => '3:0', |
'dwbm_dat_i' => { |
'range' => '31:0', |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'iwbm_sel_o' => { |
'iwbm_rty_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'rty_i', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'iwbm_cyc_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'sel_o', |
'type' => 'output', |
'range' => '3:0' |
'intfc_port' => 'cyc_o' |
}, |
'dwbm_stb_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'stb_o' |
}, |
'rst' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]' |
}, |
'iwbm_stb_o' => { |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'stb_o', |
'type' => 'output' |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'stb_o' |
}, |
'iwbm_adr_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'dwbm_adr_o' => { |
'type' => 'output', |
'range' => '31:0', |
'intfc_port' => 'adr_o', |
'type' => 'output' |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'adr_o' |
}, |
'iwbm_err_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'err_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'dwbm_cyc_o' => { |
'dwbm_rty_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'cyc_o' |
'intfc_port' => 'rty_i' |
}, |
'clk' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]' |
}, |
'dwbm_err_i' => { |
'dwbm_dat_o' => { |
'range' => '31:0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'dat_o' |
}, |
'iwbm_sel_o' => { |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '3:0', |
'type' => 'output' |
}, |
'dwbm_cyc_o' => { |
'range' => '', |
'intfc_port' => 'err_i', |
'type' => 'input', |
'type' => 'output', |
'intfc_port' => 'cyc_o', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'iwbm_rty_i' => { |
'dwbm_cti_o' => { |
'intfc_port' => 'cti_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'range' => '2:0' |
}, |
'iwbm_dat_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'dat_i', |
'type' => 'input', |
'intfc_port' => 'rty_i', |
'range' => '31:0' |
}, |
'dwbm_err_i' => { |
'intfc_port' => 'err_i', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'input', |
'range' => '' |
}, |
'dwbm_dat_o' => { |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'range' => '31:0', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'cpu_en' => { |
'intfc_port' => 'enable_i', |
'intfc_name' => 'plug:enable[0]', |
'type' => 'input', |
'intfc_port' => 'enable_i', |
'range' => '' |
}, |
'iwbm_bte_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'bte_o', |
'range' => '1:0' |
}, |
'iwbm_ack_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'intfc_port' => 'ack_i', |
'type' => 'input' |
}, |
'dwbm_rty_i' => { |
'type' => 'input', |
'intfc_port' => 'rty_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'dwbm_ack_i' => { |
'type' => 'input', |
'intfc_port' => 'ack_i', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'snoop_en_i' => { |
'intfc_name' => 'plug:snoop[0]', |
'intfc_port' => 'snoop_en_i', |
'range' => '', |
'type' => 'input' |
}, |
'dwbm_adr_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '31:0', |
'intfc_port' => 'adr_o', |
'type' => 'output' |
}, |
'iwbm_cyc_o' => { |
'intfc_port' => 'cyc_o', |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'dwbm_bte_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '1:0', |
'iwbm_cti_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cti_o', |
'type' => 'output', |
'intfc_port' => 'bte_o' |
'range' => '2:0' |
}, |
'dwbm_dat_i' => { |
'range' => '31:0', |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'irq_i' => { |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'type' => 'input', |
'intfc_port' => 'int_i', |
'range' => '31:0' |
'range' => '31:0', |
'type' => 'input' |
}, |
'iwbm_we_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'we_o', |
'range' => '', |
'type' => 'output' |
}, |
'iwbm_adr_o' => { |
'type' => 'output', |
'range' => '31:0', |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'snoop_adr_i' => { |
'intfc_port' => 'snoop_adr_i', |
'intfc_name' => 'plug:snoop[0]', |
'intfc_port' => 'snoop_adr_i', |
'range' => '31:0', |
'type' => 'input' |
'type' => 'input', |
'range' => '31:0' |
}, |
'dwbm_cti_o' => { |
'intfc_port' => 'cti_o', |
'range' => '2:0', |
'snoop_en_i' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:snoop[0]', |
'intfc_port' => 'snoop_en_i' |
}, |
'dwbm_sel_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'sel_o', |
'range' => '3:0', |
'type' => 'output' |
}, |
'dwbm_bte_o' => { |
'intfc_port' => 'bte_o', |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]' |
'range' => '1:0' |
}, |
'dwbm_we_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'we_o', |
'type' => 'output', |
'range' => '' |
}, |
'iwbm_dat_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '31:0', |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'type' => 'output' |
}, |
'iwbm_dat_i' => { |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'range' => '31:0', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'iwbm_we_o' => { |
'intfc_port' => 'we_o', |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'iwbm_cti_o' => { |
'iwbm_bte_o' => { |
'intfc_port' => 'bte_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '2:0', |
'intfc_port' => 'cti_o', |
'range' => '1:0', |
'type' => 'output' |
}, |
'dwbm_we_o' => { |
'intfc_port' => 'we_o', |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'rst' => { |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'intfc_port' => 'reset_i', |
'type' => 'input' |
} |
} |
} |
}, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'modules' => { |
'mor1k' => {} |
} |
}, 'ip_gen' ); |
/Processor/mor1kx5.IP
0,0 → 1,493
####################################################################### |
## File: mor1kx5.IP |
## |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAVIOR. |
################################################################################ |
|
$ipgen = bless( { |
'version' => 29, |
'parameters_order' => [ |
'OPTION_OPERAND_WIDTH', |
'IRQ_NUM', |
'OPTION_DCACHE_SNOOP', |
'FEATURE_INSTRUCTIONCACHE', |
'FEATURE_DATACACHE', |
'FEATURE_IMMU', |
'FEATURE_DMMU', |
'FEATURE_MULTIPLIER', |
'FEATURE_DIVIDER', |
'OPTION_SHIFTER', |
'FEATURE_FPU' |
], |
'modules' => { |
'mor1k' => {} |
}, |
'module_name' => 'mor1k', |
'parameters' => { |
'FEATURE_IMMU' => { |
'default' => '"ENABLED"', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'info' => '', |
'global_param' => 'Localparam', |
'content' => '"NONE","ENABLED"' |
}, |
'FEATURE_FPU' => { |
'content' => '"ENABLED","NONE"', |
'global_param' => 'Localparam', |
'info' => 'Enable the FPU, for cappuccino pipeline only', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'default' => '"NONE"' |
}, |
'OPTION_SHIFTER' => { |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'default' => '"BARREL"', |
'global_param' => 'Localparam', |
'content' => '"BARREL","SERIAL"', |
'info' => 'Specify the shifter implementation' |
}, |
'FEATURE_DATACACHE' => { |
'content' => '"NONE","ENABLED"', |
'global_param' => 'Localparam', |
'info' => '', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'default' => '"ENABLED"' |
}, |
'OPTION_OPERAND_WIDTH' => { |
'info' => 'Parameter', |
'global_param' => 'Localparam', |
'content' => '', |
'default' => '32', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'FEATURE_INSTRUCTIONCACHE' => { |
'info' => '', |
'content' => '"NONE","ENABLED"', |
'global_param' => 'Localparam', |
'default' => '"ENABLED"', |
'type' => 'Combo-box', |
'redefine_param' => 1 |
}, |
'FEATURE_DIVIDER' => { |
'default' => '"SERIAL"', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'info' => 'Specify the divider implementation', |
'content' => '"SERIAL","NONE"', |
'global_param' => 'Localparam' |
}, |
'IRQ_NUM' => { |
'type' => 'Fixed', |
'redefine_param' => 1, |
'default' => '32', |
'global_param' => 'Localparam', |
'content' => '', |
'info' => undef |
}, |
'OPTION_DCACHE_SNOOP' => { |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'default' => '"ENABLED"', |
'content' => '"NONE","ENABLED"', |
'global_param' => 'Localparam', |
'info' => '' |
}, |
'FEATURE_MULTIPLIER' => { |
'global_param' => 'Localparam', |
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"', |
'info' => 'Specify the multiplier implementation', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'default' => '"THREESTAGE"' |
}, |
'FEATURE_DMMU' => { |
'global_param' => 'Localparam', |
'content' => '"NONE","ENABLED"', |
'info' => '', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'default' => '"ENABLED"' |
} |
}, |
'ip_name' => 'mor1kx5', |
'unused' => { |
'plug:wb_master[1]' => [ |
'tag_o' |
], |
'plug:wb_master[0]' => [ |
'tag_o' |
] |
}, |
'category' => 'Processor', |
'file_name' => 'mpsoc/src_processor/mor1kx-5.0/rtl/mor1k.v', |
'ports' => { |
'snoop_en_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'snoop_en_i', |
'intfc_name' => 'plug:snoop[0]' |
}, |
'iwbm_stb_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'stb_o', |
'range' => '' |
}, |
'dwbm_dat_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'dat_o', |
'range' => '31:0' |
}, |
'iwbm_ack_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'range' => '' |
}, |
'iwbm_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => '31:0' |
}, |
'dwbm_rty_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'rty_i' |
}, |
'cpu_en' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:enable[0]', |
'intfc_port' => 'enable_i' |
}, |
'snoop_adr_i' => { |
'intfc_name' => 'plug:snoop[0]', |
'type' => 'input', |
'intfc_port' => 'snoop_adr_i', |
'range' => '31:0' |
}, |
'irq_i' => { |
'range' => '31:0', |
'intfc_port' => 'int_i', |
'type' => 'input', |
'intfc_name' => 'socket:interrupt_peripheral[array]' |
}, |
'dwbm_sel_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'intfc_port' => 'sel_o', |
'range' => '3:0' |
}, |
'iwbm_dat_i' => { |
'intfc_port' => 'dat_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '31:0' |
}, |
'dwbm_dat_i' => { |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'dat_i', |
'type' => 'input', |
'range' => '31:0' |
}, |
'dwbm_bte_o' => { |
'range' => '1:0', |
'intfc_port' => 'bte_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'dwbm_err_i' => { |
'range' => '', |
'intfc_port' => 'err_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'iwbm_err_i' => { |
'type' => 'input', |
'intfc_port' => 'err_i', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '' |
}, |
'iwbm_sel_o' => { |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'range' => '3:0' |
}, |
'dwbm_we_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'intfc_port' => 'we_o', |
'range' => '' |
}, |
'dwbm_cyc_o' => { |
'type' => 'output', |
'intfc_port' => 'cyc_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '' |
}, |
'dwbm_ack_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[1]', |
'intfc_port' => 'ack_i' |
}, |
'iwbm_cyc_o' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'cyc_o' |
}, |
'dwbm_stb_o' => { |
'type' => 'output', |
'intfc_port' => 'stb_o', |
'intfc_name' => 'plug:wb_master[1]', |
'range' => '' |
}, |
'iwbm_adr_o' => { |
'intfc_port' => 'adr_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '31:0' |
}, |
'dwbm_cti_o' => { |
'intfc_name' => 'plug:wb_master[1]', |
'type' => 'output', |
'intfc_port' => 'cti_o', |
'range' => '2:0' |
}, |
'rst' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => '' |
}, |
'iwbm_cti_o' => { |
'range' => '2:0', |
'intfc_port' => 'cti_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output' |
}, |
'dwbm_adr_o' => { |
'range' => '31:0', |
'intfc_port' => 'adr_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[1]' |
}, |
'iwbm_bte_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'bte_o', |
'range' => '1:0' |
}, |
'iwbm_we_o' => { |
'range' => '', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output', |
'intfc_port' => 'we_o' |
}, |
'iwbm_rty_i' => { |
'range' => '', |
'intfc_port' => 'rty_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[0]' |
} |
}, |
'ports_order' => [ |
'clk', |
'rst', |
'cpu_en', |
'snoop_adr_i', |
'snoop_en_i', |
'iwbm_adr_o', |
'iwbm_stb_o', |
'iwbm_cyc_o', |
'iwbm_sel_o', |
'iwbm_we_o', |
'iwbm_cti_o', |
'iwbm_bte_o', |
'iwbm_dat_o', |
'iwbm_err_i', |
'iwbm_ack_i', |
'iwbm_dat_i', |
'iwbm_rty_i', |
'dwbm_adr_o', |
'dwbm_stb_o', |
'dwbm_cyc_o', |
'dwbm_sel_o', |
'dwbm_we_o', |
'dwbm_cti_o', |
'dwbm_bte_o', |
'dwbm_dat_o', |
'dwbm_err_i', |
'dwbm_ack_i', |
'dwbm_dat_i', |
'dwbm_rty_i', |
'irq_i' |
], |
'hdl_files' => [ |
'/mpsoc/src_processor/mor1kx-5.0/rtl/mor1k.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_wb_mux_espresso.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_wb_mux_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_utils.vh', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_true_dpram_sclk.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_ticktimer.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_store_buffer.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx-sprs.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_simple_dpram_sclk.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_rf_espresso.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_rf_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_pic.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_pcu.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_lsu_espresso.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_lsu_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_immu.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_icache.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_fetch_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_fetch_espresso.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_fetch_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_execute_alu.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_dmmu.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx-defines.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_decode_execute_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_decode.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_dcache.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_ctrl_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_ctrl_espresso.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_ctrl_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cpu_prontoespresso.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cpu_espresso.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cpu_cappuccino.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cpu.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cfgrs.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_cache_lru.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_bus_if_wb32.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_branch_predictor_simple.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_branch_predictor_gshare.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx_branch_prediction.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/mor1kx.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_top.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_rnd.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_muldiv.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_i2f.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_f2i.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_cmp.v', |
'/mpsoc/src_processor/mor1kx-5.0/rtl/verilog/pfpu32/pfpu32_addsub.v' |
], |
'sockets' => { |
'interrupt_peripheral' => { |
'connection_num' => 'single connection', |
'value' => 'IRQ_NUM', |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'type' => 'param' |
} |
}, |
'hdl_files_ticked' => [], |
'plugs' => { |
'wb_master' => { |
'value' => 2, |
'1' => { |
'name' => 'dwb' |
}, |
'0' => { |
'name' => 'iwb' |
}, |
'type' => 'num' |
}, |
'enable' => { |
'value' => 1, |
'0' => { |
'name' => 'enable' |
}, |
'type' => 'num' |
}, |
'snoop' => { |
'0' => { |
'name' => 'snoop' |
}, |
'type' => 'num', |
'value' => 1 |
}, |
'reset' => { |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1 |
}, |
'clk' => { |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1 |
} |
}, |
'system_c' => '', |
'system_h' => ' #include "mor1kx/system.h" |
|
static inline void nop (){ |
__asm__("l.nop 1"); |
} |
/********************* |
//Interrupt template: check mor1kx/int.c for more information |
// interrupt function |
void hw_isr(void){ |
//place your interrupt code here |
|
|
HW_ISR=HW_ISR; //ack the interrupt at the end of isr function |
return; |
} |
|
int main(){ |
|
int_init(); |
//assume hw interrupt pin is connected to 10th cpu intrrupt pin |
int_add(10, hw_isr, 0); |
// Enable this interrupt |
int_enable(10); |
cpu_enable_user_interrupts(); |
hw_init ( ); // hw interrupt enable function |
while(1){ |
//place rest of the code |
|
} |
} |
*******************************/', |
'sw_files' => [ |
'/mpsoc/src_processor/mor1kx-5.0/sw/link.ld', |
'/mpsoc/src_processor/mor1kx-5.0/sw/Makefile', |
'/mpsoc/src_processor/mor1kx-5.0/sw/mor1kx' |
], |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'gen_sw_files' => [ |
'/mpsoc/src_processor/mor1kx-5.0/sw/march_flags.makfrename_sep_tmarch_flags.mak' |
] |
}, 'ip_gen' ); |
/RAM/dual_port_ram.IP
1,417 → 1,436
####################################################################### |
## File: dual_port_ram.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
## MAY CAUSE UNEXPECTED BEHAVIOR. |
################################################################################ |
|
$ipgen = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ram/generic_ram.v', |
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv', |
'/mpsoc/src_peripheral/ram/wb_dual_port_ram.v', |
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v' |
], |
'ports_order' => [ |
'clk', |
'reset', |
'sa_dat_i', |
'sa_sel_i', |
'sa_addr_i', |
'sa_tag_i', |
'sa_cti_i', |
'sa_bte_i', |
'sa_stb_i', |
'sa_cyc_i', |
'sa_we_i', |
'sa_dat_o', |
'sa_ack_o', |
'sa_err_o', |
'sa_rty_o', |
'sb_dat_i', |
'sb_sel_i', |
'sb_addr_i', |
'sb_tag_i', |
'sb_cti_i', |
'sb_bte_i', |
'sb_stb_i', |
'sb_cyc_i', |
'sb_we_i', |
'sb_dat_o', |
'sb_ack_o', |
'sb_err_o', |
'sb_rty_o' |
], |
'parameters_order' => [ |
'Dw', |
'Aw', |
'BYTE_WR_EN', |
'FPGA_VENDOR', |
'TAGw', |
'SELw', |
'CTIw', |
'BTEw', |
'WB_Aw', |
'RAM_INDEX', |
'PORT_A_BURST_MODE', |
'PORT_B_BURST_MODE', |
'INITIAL_EN', |
'MEM_CONTENT_FILE_NAME', |
'INIT_FILE_PATH' |
], |
'category' => 'RAM', |
'plugs' => { |
'reset' => { |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'reset' => {} |
}, |
'clk' => { |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
}, |
'clk' => {}, |
'value' => 1 |
}, |
'wb_slave' => { |
'type' => 'num', |
'0' => { |
'addr' => '0x0000_0000 0x3fff_ffff RAM', |
'width' => 'WB_Aw', |
'name' => 'wb_a' |
}, |
'1' => { |
'name' => 'wb_b', |
'width' => 'WB_Aw', |
'addr' => '0x0000_0000 0x3fff_ffff RAM' |
}, |
'wb_slave' => {}, |
'value' => 2 |
} |
}, |
'modules' => { |
'wb_dual_port_ram' => {} |
}, |
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf', |
'version' => 10, |
'description' => 'Dual port ram.', |
'ip_name' => 'dual_port_ram', |
'module_name' => 'wb_dual_port_ram', |
'unused' => undef, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_dual_port_ram.v', |
'parameters' => { |
'RAM_INDEX' => { |
'global_param' => 'Localparam', |
'type' => 'Entry', |
'content' => '', |
'default' => 'CORE_ID', |
'redefine_param' => 1, |
'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only. |
|
' |
}, |
'SELw' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'default' => 'Dw/8', |
'global_param' => 'Localparam' |
}, |
'BYTE_WR_EN' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'type' => 'Combo-box', |
'content' => '"YES","NO"', |
'default' => '"YES"', |
'global_param' => 'Localparam' |
}, |
'INITIAL_EN' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'If selected as "YES", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', |
'default' => '"NO"', |
'content' => '"YES","NO"', |
'type' => 'Combo-box' |
}, |
'CTIw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'default' => '3', |
'type' => 'Fixed', |
'content' => '' |
}, |
'Dw' => { |
'redefine_param' => 1, |
'info' => 'Ram data width in Bits', |
'type' => 'Spin-button', |
'default' => '32', |
'content' => '4,1024,1', |
'global_param' => 'Localparam' |
}, |
'FPGA_VENDOR' => { |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'redefine_param' => 1, |
'default' => '"GENERIC"', |
'type' => 'Combo-box', |
'content' => '"ALTERA","GENERIC"' |
}, |
'INIT_FILE_PATH' => { |
'global_param' => 'Don\'t include', |
'content' => '', |
'default' => 'SW_LOC', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => undef |
}, |
'PORT_A_BURST_MODE' => { |
'info' => ' wisbone bus burst mode enable/disable on port A', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'default' => '"ENABLED"', |
'content' => '"DISABLED","ENABLED"', |
'global_param' => 'Localparam' |
}, |
'MEM_CONTENT_FILE_NAME' => { |
'global_param' => 'Localparam', |
'content' => '', |
'default' => '"ram0"', |
'type' => 'Entry', |
'redefine_param' => 1, |
'info' => 'MEM_FILE_NAME: |
The memory file name (without file type extension ) that is used for writting the memory content at initialization time. |
|
File Path: |
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}. |
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME} |
|
file_type: |
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command. |
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ' |
}, |
'TAGw' => { |
'content' => '', |
'type' => 'Fixed', |
'default' => '3', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'global_param' => 'Localparam' |
}, |
'BTEw' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'default' => '2', |
'content' => '', |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'Aw' => { |
'info' => 'Ram address width', |
'redefine_param' => 1, |
'default' => '12', |
'content' => '2,31,1', |
'type' => 'Spin-button', |
'global_param' => 'Localparam' |
}, |
'PORT_B_BURST_MODE' => { |
'redefine_param' => 1, |
'info' => 'wisbone bus burst mode ebable/disable on port B', |
'type' => 'Combo-box', |
'content' => '"DISABLED","ENABLED"', |
'default' => '"ENABLED"', |
'global_param' => 'Localparam' |
}, |
'WB_Aw' => { |
'info' => 'Wishbone bus address width in byte', |
'redefine_param' => 0, |
'content' => '', |
'default' => 'Aw+2', |
'type' => 'Fixed', |
'global_param' => 'Don\'t include' |
} |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'file_name' => 'mpsoc/rtl/src_peripheral/ram/wb_dual_port_ram.v', |
'ports' => { |
'reset' => { |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'range' => '', |
'intfc_name' => 'plug:reset[0]' |
}, |
'sb_we_i' => { |
'clk' => { |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => '' |
}, |
'sb_sel_i' => { |
'type' => 'input', |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => 'SELw-1 : 0' |
}, |
'sb_err_o' => { |
'type' => 'output', |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => '' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'type' => 'input', |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[1]' |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '' |
}, |
'sb_err_o' => { |
'sa_err_o' => { |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[1]' |
'type' => 'output' |
}, |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'rty_o', |
'sb_stb_i' => { |
'type' => 'input', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => '' |
}, |
'sa_dat_o' => { |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_cyc_i' => { |
'type' => 'input', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sb_dat_o' => { |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[1]' |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'intfc_port' => 'reset_i', |
'type' => 'input' |
}, |
'sb_we_i' => { |
'range' => '', |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input', |
'intfc_port' => 'we_i' |
}, |
'sb_cti_i' => { |
'range' => 'CTIw-1 : 0', |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input', |
'intfc_port' => 'cti_i' |
}, |
'sa_stb_i' => { |
'range' => '', |
'intfc_port' => 'stb_i', |
'sa_bte_i' => { |
'range' => 'BTEw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
'intfc_port' => 'bte_i' |
}, |
'sa_cti_i' => { |
'type' => 'input', |
'intfc_port' => 'cti_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'CTIw-1 : 0' |
}, |
'sa_tag_i' => { |
'type' => 'input', |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0', |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_dat_i' => { |
'sb_tag_i' => { |
'intfc_port' => 'tag_i', |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
'range' => 'TAGw-1 : 0', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sa_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'we_i' |
}, |
'sb_bte_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => 'BTEw-1 : 0', |
'intfc_port' => 'bte_i', |
'intfc_name' => 'plug:wb_slave[1]' |
'type' => 'input' |
}, |
'sb_addr_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input', |
'range' => 'Aw-1 : 0', |
'intfc_port' => 'adr_i' |
}, |
'sb_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => '', |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'cyc_i' |
}, |
'sa_sel_i' => { |
'sa_dat_i' => { |
'range' => 'Dw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]' |
'intfc_port' => 'dat_i' |
}, |
'sb_sel_i' => { |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
'sb_dat_o' => { |
'intfc_port' => 'dat_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[1]', |
'range' => 'Dw-1 : 0' |
}, |
'sb_dat_i' => { |
'type' => 'input', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sb_cti_i' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'input', |
'range' => 'CTIw-1 : 0', |
'intfc_port' => 'cti_i' |
'range' => 'Dw-1 : 0' |
}, |
'sb_ack_o' => { |
'sb_addr_i' => { |
'range' => 'Aw-1 : 0', |
'intfc_name' => 'plug:wb_slave[1]', |
'intfc_port' => 'adr_i', |
'type' => 'input' |
}, |
'sb_rty_o' => { |
'intfc_port' => 'rty_o', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'sa_cti_i' => { |
'type' => 'input', |
'range' => 'CTIw-1 : 0', |
'intfc_port' => 'cti_i', |
'sa_addr_i' => { |
'type' => 'input', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_rty_o' => { |
'type' => 'output', |
'intfc_port' => 'rty_o', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_err_o' => { |
'intfc_port' => 'err_o', |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sb_tag_i' => { |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[1]' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sb_stb_i' => { |
'type' => 'input', |
'intfc_port' => 'stb_i', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[1]' |
'type' => 'input' |
}, |
'sa_bte_i' => { |
'sa_sel_i' => { |
'range' => 'SELw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'intfc_port' => 'bte_i', |
'range' => 'BTEw-1 : 0' |
'intfc_port' => 'sel_i', |
'type' => 'input' |
}, |
'sa_cyc_i' => { |
'type' => 'input', |
'sb_ack_o' => { |
'range' => '', |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sb_rty_o' => { |
'intfc_name' => 'plug:wb_slave[1]', |
'type' => 'output', |
'intfc_port' => 'rty_o', |
'range' => '' |
'intfc_port' => 'ack_o' |
} |
}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
} |
'description' => 'Dual port ram.', |
'parameters' => { |
'FPGA_VENDOR' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'default' => '"GENERIC"', |
'content' => '"ALTERA","XILINX","GENERIC"', |
'global_param' => 'Localparam', |
'type' => 'Combo-box' |
}, |
'Dw' => { |
'content' => '4,1024,1', |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'info' => 'Ram data width in Bits', |
'default' => '32', |
'redefine_param' => 1 |
}, |
'INIT_FILE_PATH' => { |
'content' => '', |
'global_param' => 'Don\'t include', |
'type' => 'Fixed', |
'info' => undef, |
'default' => 'SW_LOC', |
'redefine_param' => 1 |
}, |
'BYTE_WR_EN' => { |
'redefine_param' => 1, |
'default' => '"YES"', |
'info' => 'Parameter', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'content' => '"YES","NO"' |
}, |
'PORT_A_BURST_MODE' => { |
'default' => '"ENABLED"', |
'redefine_param' => 1, |
'info' => ' wisbone bus burst mode enable/disable on port A', |
'content' => '"DISABLED","ENABLED"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam' |
}, |
'INITIAL_EN' => { |
'info' => 'If selected as "YES", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', |
'redefine_param' => 1, |
'default' => '"NO"', |
'content' => '"YES","NO"', |
'global_param' => 'Localparam', |
'type' => 'Combo-box' |
}, |
'BTEw' => { |
'default' => '2', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'content' => '' |
}, |
'CTIw' => { |
'info' => 'Parameter', |
'default' => '3', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'content' => '' |
}, |
'WB_Byte_Aw' => { |
'global_param' => 'Don\'t include', |
'type' => 'Fixed', |
'content' => '', |
'info' => 'Wishbone bus address width in byte', |
'redefine_param' => 0, |
'default' => 'WB_Aw+2' |
}, |
'WB_Aw' => { |
'content' => '4,31,1', |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw).', |
'default' => '20', |
'redefine_param' => 1 |
}, |
'MEM_CONTENT_FILE_NAME' => { |
'global_param' => 'Localparam', |
'type' => 'Entry', |
'content' => '', |
'info' => 'MEM_FILE_NAME: |
The memory file name (without file type extension ) that is used for writting the memory content at initialization time. |
|
File Path: |
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}. |
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME} |
|
file_type: |
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command. |
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ', |
'default' => '"ram0"', |
'redefine_param' => 1 |
}, |
'RAM_INDEX' => { |
'type' => 'Entry', |
'global_param' => 'Localparam', |
'content' => '', |
'default' => 'CORE_ID', |
'redefine_param' => 1, |
'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only. |
|
' |
}, |
'CORE_NUM' => { |
'content' => '', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => 'CORE_ID', |
'info' => 'Parameter' |
}, |
'Aw' => { |
'info' => 'Ram address width', |
'redefine_param' => 1, |
'default' => '12', |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'content' => '2,31,1' |
}, |
'TAGw' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'default' => '3', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'content' => '' |
}, |
'PORT_B_BURST_MODE' => { |
'info' => 'wisbone bus burst mode ebable/disable on port B', |
'redefine_param' => 1, |
'default' => '"ENABLED"', |
'content' => '"DISABLED","ENABLED"', |
'global_param' => 'Localparam', |
'type' => 'Combo-box' |
}, |
'SELw' => { |
'content' => '', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => 'Dw/8', |
'info' => 'Parameter' |
} |
}, |
'parameters_order' => [ |
'Dw', |
'Aw', |
'WB_Aw', |
'BYTE_WR_EN', |
'FPGA_VENDOR', |
'CORE_NUM', |
'TAGw', |
'SELw', |
'CTIw', |
'BTEw', |
'WB_Byte_Aw', |
'RAM_INDEX', |
'PORT_A_BURST_MODE', |
'PORT_B_BURST_MODE', |
'INITIAL_EN', |
'MEM_CONTENT_FILE_NAME', |
'INIT_FILE_PATH' |
|
], |
'version' => 11, |
'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf', |
'plugs' => { |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num', |
'value' => 1, |
'clk' => {} |
}, |
'wb_slave' => { |
'1' => { |
'name' => 'wb_b', |
'width' => 'WB_Byte_Aw', |
'addr' => '0x0000_0000 0x3fff_ffff RAM' |
}, |
'0' => { |
'name' => 'wb_a', |
'addr' => '0x0000_0000 0x3fff_ffff RAM', |
'width' => 'WB_Byte_Aw' |
}, |
'wb_slave' => {}, |
'value' => 2, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'reset' |
} |
} |
}, |
'category' => 'RAM', |
'unused' => undef, |
'module_name' => 'wb_dual_port_ram', |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/ram/generic_ram.v', |
'/mpsoc/rtl/src_peripheral/ram/byte_enabled_generic_ram.sv', |
'/mpsoc/rtl/src_peripheral/ram/wb_dual_port_ram.v', |
'/mpsoc/rtl/src_peripheral/ram/wb_bram_ctrl.v' |
], |
'ports_order' => [ |
'clk', |
'reset', |
'sa_dat_i', |
'sa_sel_i', |
'sa_addr_i', |
'sa_tag_i', |
'sa_cti_i', |
'sa_bte_i', |
'sa_stb_i', |
'sa_cyc_i', |
'sa_we_i', |
'sa_dat_o', |
'sa_ack_o', |
'sa_err_o', |
'sa_rty_o', |
'sb_dat_i', |
'sb_sel_i', |
'sb_addr_i', |
'sb_tag_i', |
'sb_cti_i', |
'sb_bte_i', |
'sb_stb_i', |
'sb_cyc_i', |
'sb_we_i', |
'sb_dat_o', |
'sb_ack_o', |
'sb_err_o', |
'sb_rty_o' |
] |
}, 'ip_gen' ); |
/RAM/single_port_ram.IP
1,77 → 1,244
####################################################################### |
## File: single_port_ram.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.8.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
## MAY CAUSE UNEXPECTED BEHAVIOR. |
################################################################################ |
|
$ipgen = bless( { |
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf', |
'unused' => undef, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'modules' => { |
'wb_single_port_ram' => {} |
'sockets' => { |
'jtag_to_wb' => { |
'value' => 1, |
'0' => { |
'name' => 'jtag_to_wb' |
}, |
'connection_num' => 'single connection', |
'type' => 'num' |
} |
}, |
'parameters_order' => [ |
'Dw', |
'Aw', |
'WB_Aw', |
'BYTE_WR_EN', |
'FPGA_VENDOR', |
'JTAG_CONNECT', |
'JTAG_INDEX', |
'CORE_NUM', |
'TAGw', |
'SELw', |
'CTIw', |
'BTEw', |
'WB_Byte_Aw', |
'BURST_MODE', |
'MEM_CONTENT_FILE_NAME', |
'INITIAL_EN', |
'INIT_FILE_PATH', |
'JDw', |
'JAw', |
'JSTATUSw', |
'JINDEXw', |
'J2WBw', |
'WB2Jw', |
'JTAG_CHAIN' |
|
], |
'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf', |
'version' => 39, |
'parameters' => { |
'JTAG_INDEX' => { |
'default' => 'CORE_ID', |
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory. |
|
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1). |
|
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units). |
|
', |
'type' => 'Entry', |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1 |
}, |
'JAw' => { |
'content' => '', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'default' => '32', |
'type' => 'Fixed', |
'info' => 'Parameter' |
}, |
'INIT_FILE_PATH' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => 'SW_LOC', |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Localparam' |
}, |
'FPGA_VENDOR' => { |
'global_param' => 'Localparam', |
'content' => '"ALTERA","XILINX","GENERIC"', |
'redefine_param' => 1, |
'default' => '"GENERIC"', |
'info' => '', |
'type' => 'Combo-box' |
}, |
'Aw' => { |
'global_param' => 'Parameter', |
'default' => '12', |
'type' => 'Spin-button', |
'info' => 'Memory address width', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'default' => '12', |
'content' => '4,31,1' |
'content' => '4,31,1', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'CTIw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'default' => '3' |
}, |
'JINDEXw' => { |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'default' => '8' |
}, |
'INITIAL_EN' => { |
'content' => '"YES","NO"', |
'redefine_param' => 1, |
'default' => '"NO"', |
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', |
'type' => 'Combo-box', |
'global_param' => 'Localparam' |
'global_param' => 'Localparam', |
'content' => '"YES","NO"', |
'redefine_param' => 1 |
}, |
'WB_Aw' => { |
'global_param' => 'Don\'t include', |
'J2WBw' => { |
'info' => undef, |
'type' => 'Fixed', |
'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1', |
'redefine_param' => 1, |
'default' => 'Aw+2', |
'content' => '' |
'content' => '', |
'global_param' => 'Parameter' |
}, |
'WB2Jw' => { |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'info' => undef, |
'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1' |
}, |
'JDw' => { |
'type' => 'Fixed', |
'info' => 'Parameter', |
'default' => 'Dw', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'content' => '' |
}, |
'BTEw' => { |
'default' => '2', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1 |
}, |
'BURST_MODE' => { |
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ', |
'type' => 'Combo-box', |
'default' => '"ENABLED"', |
'redefine_param' => 1, |
'content' => '"DISABLED","ENABLED"', |
'global_param' => 'Localparam' |
}, |
'WB_Aw' => { |
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ', |
'type' => 'Spin-button', |
'default' => '20', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '4,31,1' |
}, |
'Dw' => { |
'type' => 'Spin-button', |
'info' => 'Memory data width in Bits.', |
'default' => '32', |
'redefine_param' => 1, |
'content' => '8,1024,1', |
'global_param' => 'Parameter' |
}, |
'JTAG_CHAIN' => { |
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are: |
4: JTAG runtime memory programmers. |
3: UART |
1,2: reserved', |
'type' => 'Combo-box', |
'default' => '4', |
'redefine_param' => 0, |
'content' => '1,2,3,4', |
'global_param' => 'Parameter' |
}, |
'BYTE_WR_EN' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '"YES","NO"', |
'info' => 'Byte enable', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => '"YES","NO"', |
'default' => '"YES"' |
}, |
'TAGw' => { |
'SELw' => { |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'default' => 'Dw/8' |
}, |
'WB_Byte_Aw' => { |
'global_param' => 'Don\'t include', |
'content' => '', |
'redefine_param' => 1, |
'default' => 'WB_Aw+2', |
'info' => undef, |
'type' => 'Fixed' |
}, |
'CORE_NUM' => { |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'default' => 'CORE_ID', |
'info' => 'Parameter', |
'type' => 'Fixed' |
}, |
'TAGw' => { |
'type' => 'Fixed', |
'content' => '', |
'info' => 'Parameter', |
'default' => '3', |
'redefine_param' => 1 |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '' |
}, |
'FPGA_VENDOR' => { |
'content' => '"ALTERA","GENERIC"', |
'redefine_param' => 1, |
'default' => '"GENERIC"', |
'info' => '', |
'type' => 'Combo-box', |
'global_param' => 'Localparam' |
}, |
'JSTATUSw' => { |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'default' => '8', |
'type' => 'Fixed', |
'info' => 'Parameter' |
}, |
'MEM_CONTENT_FILE_NAME' => { |
'default' => '"ram0"', |
'redefine_param' => 1, |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Entry', |
'info' => 'MEM_FILE_NAME: |
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time. |
81,231 → 248,164
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME} |
|
file_type: |
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime. |
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime. |
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command. |
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ', |
'global_param' => 'Localparam' |
'default' => '"ram0"' |
}, |
'Dw' => { |
'content' => '8,1024,1', |
'redefine_param' => 1, |
'default' => '32', |
'global_param' => 'Parameter', |
'info' => 'Memory data width in Bits.', |
'type' => 'Spin-button' |
}, |
'JTAG_INDEX' => { |
'content' => '', |
'default' => 'CORE_ID', |
'redefine_param' => 1, |
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory. |
|
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1). |
|
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units). |
|
', |
'type' => 'Entry', |
'global_param' => 'Localparam' |
}, |
'CTIw' => { |
'content' => '', |
'redefine_param' => 1, |
'default' => '3', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'info' => 'Parameter' |
}, |
'SELw' => { |
'content' => '', |
'redefine_param' => 1, |
'default' => 'Dw/8', |
'info' => 'Parameter', |
'type' => 'Fixed', |
'global_param' => 'Localparam' |
}, |
'BURST_MODE' => { |
'default' => '"ENABLED"', |
'content' => '"DISABLED","ENABLED"', |
'redefine_param' => 1, |
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ', |
'type' => 'Combo-box', |
'global_param' => 'Localparam' |
}, |
'BTEw' => { |
'redefine_param' => 1, |
'default' => '2', |
'content' => '', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'global_param' => 'Localparam' |
}, |
'INIT_FILE_PATH' => { |
'type' => 'Fixed', |
'info' => undef, |
'global_param' => 'Localparam', |
'content' => '', |
'default' => 'SW_LOC', |
'redefine_param' => 1 |
}, |
'JTAG_CONNECT' => { |
'default' => '"DISABLED"', |
'type' => 'Combo-box', |
'info' => 'JTAG_CONNECT: |
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ', |
'global_param' => 'Localparam', |
'default' => '"DISABLED"', |
'redefine_param' => 1, |
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"' |
'global_param' => 'Parameter', |
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"', |
'redefine_param' => 1 |
} |
}, |
'version' => 22, |
'ports' => { |
'module_name' => 'wb_single_port_ram', |
'file_name' => 'mpsoc/rtl/src_peripheral/ram/wb_single_port_ram.v', |
'plugs' => { |
'reset' => { |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]' |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'reset' => {}, |
'type' => 'num' |
}, |
'sa_bte_i' => { |
'wb_slave' => { |
'type' => 'num', |
'wb_slave' => {}, |
'0' => { |
'addr' => '0x0000_0000 0x3fff_ffff RAM', |
'name' => 'wb', |
'width' => 'WB_Byte_Aw' |
}, |
'value' => 1 |
}, |
'clk' => { |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num', |
'clk' => {} |
} |
}, |
'category' => 'RAM', |
'ports' => { |
'sa_rty_o' => { |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'rty_o', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'bte_i', |
'type' => 'output', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0' |
}, |
'sa_dat_i' => { |
'range' => 'Dw-1 : 0', |
'type' => 'input', |
'range' => 'BTEw-1 : 0' |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'range' => '' |
}, |
'jtag_to_wb' => { |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'range' => 'J2WBw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'jwb_i' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_sel_i' => { |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
'reset' => { |
'range' => '', |
'intfc_port' => 'reset_i', |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]' |
}, |
'sa_err_o' => { |
'range' => '', |
'intfc_port' => 'err_o', |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_stb_i' => { |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o' |
'intfc_port' => 'stb_i', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_tag_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'TAGw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'tag_i', |
'type' => 'input', |
'range' => 'TAGw-1 : 0' |
}, |
'sa_dat_i' => { |
'type' => 'input', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'cyc_i', |
'type' => 'input', |
'range' => '' |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_rty_o' => { |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'intfc_port' => 'adr_i', |
'type' => 'input' |
}, |
'sa_cti_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_cti_i' => { |
'range' => 'CTIw-1 : 0', |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cti_i' |
}, |
'sa_sel_i' => { |
'range' => 'SELw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_we_i' => { |
'type' => 'input', |
'intfc_port' => 'we_i', |
'range' => '', |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'sa_bte_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => 'Dw-1 : 0' |
'type' => 'input', |
'intfc_port' => 'bte_i', |
'range' => 'BTEw-1 : 0' |
}, |
'clk' => { |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i' |
}, |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
} |
'wb_to_jtag' => { |
'type' => 'output', |
'intfc_port' => 'jwb_o', |
'range' => 'WB2Jw-1 : 0', |
'intfc_name' => 'socket:jtag_to_wb[0]' |
} |
}, |
'parameters_order' => [ |
'Dw', |
'Aw', |
'BYTE_WR_EN', |
'FPGA_VENDOR', |
'JTAG_CONNECT', |
'JTAG_INDEX', |
'TAGw', |
'SELw', |
'CTIw', |
'BTEw', |
'WB_Aw', |
'BURST_MODE', |
'MEM_CONTENT_FILE_NAME', |
'INITIAL_EN', |
'INIT_FILE_PATH' |
], |
'plugs' => { |
'reset' => { |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num', |
'value' => 1, |
'reset' => {} |
}, |
'wb_slave' => { |
'type' => 'num', |
'0' => { |
'name' => 'wb', |
'addr' => '0x0000_0000 0x3fff_ffff RAM', |
'width' => 'WB_Aw' |
}, |
'wb_slave' => {}, |
'value' => 1 |
}, |
'clk' => { |
'value' => 1, |
'clk' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'clk' |
} |
} |
}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ram/wb_single_port_ram.v', |
'/mpsoc/src_peripheral/ram/generic_ram.v', |
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv', |
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v' |
], |
'ip_name' => 'single_port_ram', |
'modules' => { |
'wb_single_port_ram' => {} |
}, |
'ports_order' => [ |
'clk', |
'reset', |
'jtag_to_wb', |
'wb_to_jtag', |
'sa_dat_i', |
'sa_sel_i', |
'sa_addr_i', |
320,8 → 420,17
'sa_err_o', |
'sa_rty_o' |
], |
'module_name' => 'wb_single_port_ram', |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/ram/wb_single_port_ram.v', |
'/mpsoc/rtl/src_peripheral/ram/generic_ram.v', |
'/mpsoc/rtl/src_peripheral/ram/byte_enabled_generic_ram.sv', |
'/mpsoc/rtl/src_peripheral/ram/wb_bram_ctrl.v' |
], |
'description' => 'Single port ram with wishbone bus interface.', |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v', |
'category' => 'RAM' |
'unused' => undef, |
'ip_name' => 'single_port_ram', |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
} |
}, 'ip_gen' ); |
/Source/clk_source.IP
1,94 → 1,109
####################################################################### |
## File: clk_source.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$clk_source = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/reset_sync/altera_reset_synchronizer.v', |
'/mpsoc/src_peripheral/reset_sync/clk_source.v' |
], |
'ip_name' => 'clk_source', |
'description' => 'clk source. This module provides the clk and reset (socket) interfaces for all other IPs. It also synchronizes the reset signal.', |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'modules' => { |
'clk_source' => {} |
}, |
'plugs' => { |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
} |
$ipgen = bless( { |
'version' => 1, |
'unused' => undef, |
'parameters' => { |
'FPGA_VENDOR' => { |
'content' => '"ALTERA","XILINX"', |
'info' => '', |
'default' => '"ALTERA"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
} |
}, |
'ports' => { |
'clk_out' => { |
'intfc_port' => 'clk_o', |
'intfc_name' => 'socket:clk[0]', |
'range' => '', |
'type' => 'output' |
'category' => 'Source', |
'ip_name' => 'clk_source', |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/clk_source/altera_reset_synchronizer.v', |
'/mpsoc/rtl/src_peripheral/clk_source/clk_source.v', |
'/mpsoc/rtl/src_peripheral/clk_source/xilinx_reset_synchroniser.v' |
], |
'file_name' => 'mpsoc/rtl/src_peripheral/clk_source/clk_source.v', |
'parameters_order' => [ |
'FPGA_VENDOR' |
], |
'ports' => { |
'reset_in' => { |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]' |
}, |
'clk_in' => { |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'clk_i' |
}, |
'reset_out' => { |
'range' => '', |
'intfc_port' => 'reset_o', |
'type' => 'output', |
'intfc_name' => 'socket:reset[0]' |
}, |
'clk_out' => { |
'intfc_port' => 'clk_o', |
'range' => '', |
'type' => 'output', |
'intfc_name' => 'socket:clk[0]' |
} |
}, |
'description' => 'clk source. This module provides the clk and reset (socket) interfaces for all other IPs. It also synchronizes the reset signal.', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'sockets' => { |
'clk' => { |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'connection_num' => 'multi connection', |
'clk' => {}, |
'type' => 'num' |
}, |
'reset' => { |
'connection_num' => 'multi connection', |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'reset' => {}, |
'type' => 'num' |
} |
}, |
'modules' => { |
'clk_source' => {} |
}, |
'plugs' => { |
'reset' => { |
'reset' => {}, |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'reset' |
} |
}, |
'clk' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'reset_out' => { |
'intfc_port' => 'reset_o', |
'intfc_name' => 'socket:reset[0]', |
'range' => '', |
'type' => 'output' |
}, |
'clk_in' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
}, |
'reset_in' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'type' => 'input' |
} |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/reset_sync/clk_source.v', |
'sockets' => { |
'clk' => { |
'clk' => {}, |
'connection_num' => 'multi connection', |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'connection_num' => 'multi connection', |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
} |
}, |
'module_name' => 'clk_source', |
'unused' => undef, |
'category' => 'Source' |
}, 'ip_gen' ); |
'clk' => {} |
} |
}, |
'module_name' => 'clk_source' |
}, 'ip_gen' ); |
/Source/xilinx_IBUFGDS.IP
0,0 → 1,127
####################################################################### |
## File: xilinx_IBUFGDS.IP |
## |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ipgen = bless( { |
'version' => 3, |
'modules' => { |
'IBUFGDS' => {} |
}, |
'description' => 'Xilinx Differential Signaling Input Clock Buffer', |
'file_name' => 'mpsoc/perl_gui/lib/verilog/IBUFGDS.v', |
'sockets' => { |
'clk' => { |
'type' => 'num', |
'connection_num' => 'multi connection', |
'1' => { |
'name' => 'clk_1' |
}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
} |
} |
}, |
'ip_name' => 'xilinx_IBUFGDS', |
'hdl_files' => [], |
'ports_order' => [ |
'O', |
'I', |
'IB' |
], |
'module_name' => 'IBUFGDS', |
'category' => 'Source', |
'parameters' => { |
'IBUF_LOW_PWR' => { |
'redefine_param' => 1, |
'default' => '"TRUE"', |
'info' => 'Low power="TRUE",Highest performance="FALSE"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'content' => '"FALSE", "TRUE"' |
}, |
'CAPACITANCE' => { |
'content' => '"LOW", "NORMAL", "DONT_CARE"', |
'global_param' => 'Localparam', |
'type' => 'Combo-box', |
'info' => '', |
'default' => '"DONT_CARE"', |
'redefine_param' => 1 |
}, |
'IBUF_DELAY_VALUE' => { |
'info' => 'Parameter', |
'type' => 'Combo-box', |
'default' => '"0"', |
'redefine_param' => 1, |
'content' => '"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16"', |
'global_param' => 'Localparam' |
}, |
'IOSTANDARD' => { |
'global_param' => 'Localparam', |
'content' => '', |
'default' => '"DEFAULT"', |
'redefine_param' => 1, |
'info' => 'Specify the input I/O standard', |
'type' => 'Fixed' |
}, |
'DIFF_TERM' => { |
'info' => 'Differential Termination', |
'type' => 'Combo-box', |
'default' => '"FALSE"', |
'redefine_param' => 1, |
'content' => ' "TRUE", "FALSE"', |
'global_param' => 'Localparam' |
} |
}, |
'ports' => { |
'O' => { |
'range' => '', |
'intfc_name' => 'socket:clk[0]', |
'intfc_port' => 'clk_o', |
'type' => 'output' |
}, |
'I' => { |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:clk[0]' |
}, |
'IB' => { |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:clk[1]' |
} |
}, |
'unused' => undef, |
'gui_status' => { |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'parameters_order' => [ |
'CAPACITANCE', |
'DIFF_TERM', |
'IBUF_DELAY_VALUE', |
'IBUF_LOW_PWR', |
'IOSTANDARD' |
], |
'plugs' => { |
'clk' => { |
'type' => 'num', |
'0' => { |
'name' => 'clk_p' |
}, |
'value' => 2, |
'1' => { |
'name' => 'clk_n' |
} |
} |
} |
}, 'ip_gen' ); |
/Source/xilinx_pll.IP
0,0 → 1,356
####################################################################### |
## File: xilinx_pll.IP |
## |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$ipgen = bless( { |
'plugs' => { |
'clk' => { |
'0' => { |
'name' => 'clk_in' |
}, |
'type' => 'num', |
'value' => 1 |
}, |
'reset' => { |
'value' => 1, |
'0' => { |
'name' => 'reset_in' |
}, |
'type' => 'num' |
} |
}, |
'sockets' => { |
'reset' => { |
'connection_num' => 'multi connection', |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
}, |
'1' => { |
'name' => 'reset_1' |
}, |
'value' => 1 |
}, |
'clk' => { |
'1' => { |
'name' => 'clk_1' |
}, |
'3' => { |
'name' => 'clk_3' |
}, |
'value' => 'CLKOUT_NUM', |
'5' => { |
'name' => 'clk_5' |
}, |
'type' => 'param', |
'connection_num' => 'multi connection', |
'0' => { |
'name' => 'clk' |
}, |
'2' => { |
'name' => 'clk_2' |
}, |
'4' => { |
'name' => 'clk_4' |
} |
} |
}, |
'category' => 'Source', |
'parameters_order' => [ |
'CLKOUT_NUM', |
'BANDWIDTH', |
'CLKFBOUT_MULT', |
'CLKFBOUT_PHASE', |
'CLKIN1_PERIOD', |
'CLKOUT0_DIVIDE', |
'CLKOUT1_DIVIDE', |
'CLKOUT2_DIVIDE', |
'CLKOUT3_DIVIDE', |
'CLKOUT4_DIVIDE', |
'CLKOUT5_DIVIDE', |
'CLKOUT0_DUTY_CYCLE', |
'CLKOUT1_DUTY_CYCLE', |
'CLKOUT2_DUTY_CYCLE', |
'CLKOUT3_DUTY_CYCLE', |
'CLKOUT4_DUTY_CYCLE', |
'CLKOUT5_DUTY_CYCLE', |
'CLKOUT0_PHASE', |
'CLKOUT1_PHASE', |
'CLKOUT2_PHASE', |
'CLKOUT3_PHASE', |
'CLKOUT4_PHASE', |
'CLKOUT5_PHASE', |
'DIVCLK_DIVIDE', |
'REF_JITTER1', |
'STARTUP_WAIT' |
], |
'modules' => { |
'xilinx_pll2_base' => {} |
}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'ports_order' => [ |
'clk_out', |
'reset_out', |
'clk_in', |
'reset_in' |
], |
'parameters' => { |
'CLKOUT1_DIVIDE' => { |
'info' => 'Divide amount for CLKOUT1 (1-128)', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '1,128,1', |
'default' => '1' |
}, |
'CLKOUT4_DIVIDE' => { |
'type' => 'Spin-button', |
'content' => '1,128,1', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'info' => 'Divide amount for CLKOUT4 (1-128)', |
'default' => '1' |
}, |
'CLKOUT2_DUTY_CYCLE' => { |
'global_param' => 'Localparam', |
'info' => ' Duty cycle for CLKOUT2 (0.001-0.999).', |
'content' => '0.001,0.999,0.001', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'default' => '0.5' |
}, |
'CLKIN1_PERIOD' => { |
'default' => '0.0', |
'global_param' => 'Localparam', |
'info' => 'Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).', |
'content' => '0,1000,0.001', |
'type' => 'Spin-button', |
'redefine_param' => 1 |
}, |
'CLKOUT4_PHASE' => { |
'type' => 'Spin-button', |
'content' => '-360.000,360.000,0.001', |
'redefine_param' => 1, |
'info' => 'Phase offset for each CLKOUT4 (-360.000-360.000).', |
'global_param' => 'Localparam', |
'default' => '0.0' |
}, |
'CLKOUT2_PHASE' => { |
'global_param' => 'Localparam', |
'info' => 'Phase offset for each CLKOUT2 (-360.000-360.000).', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '-360.000,360.000,0.001', |
'default' => '0.0' |
}, |
'CLKOUT_NUM' => { |
'global_param' => 'Localparam', |
'info' => 'Number of out put clk sources', |
'redefine_param' => 1, |
'content' => '1,2,3,4,5,6', |
'type' => 'Combo-box', |
'default' => '1' |
}, |
'CLKOUT3_DUTY_CYCLE' => { |
'info' => ' Duty cycle for CLKOUT3 (0.001-0.999).', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '0.001,0.999,0.001', |
'default' => '0.5' |
}, |
'CLKOUT4_DUTY_CYCLE' => { |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '0.001,0.999,0.001', |
'global_param' => 'Localparam', |
'info' => ' Duty cycle for CLKOUT4 (0.001-0.999).', |
'default' => '0.5' |
}, |
'CLKOUT2_DIVIDE' => { |
'default' => '1', |
'redefine_param' => 1, |
'content' => '1,128,1', |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'info' => 'Divide amount for CLKOUT2 (1-128)' |
}, |
'CLKOUT0_PHASE' => { |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '-360.000,360.000,0.001', |
'global_param' => 'Localparam', |
'info' => 'Phase offset for each CLKOUT0 (-360.000-360.000).', |
'default' => '0.0' |
}, |
'CLKFBOUT_MULT' => { |
'default' => '5', |
'type' => 'Spin-button', |
'content' => '2,64,1', |
'redefine_param' => 1, |
'info' => 'Multiply value for all CLKOUT', |
'global_param' => 'Localparam' |
}, |
'CLKOUT0_DIVIDE' => { |
'default' => '1', |
'global_param' => 'Localparam', |
'info' => 'Divide amount for CLKOUT0 (1-128)', |
'redefine_param' => 1, |
'content' => '1,128,1', |
'type' => 'Spin-button' |
}, |
'CLKOUT0_DUTY_CYCLE' => { |
'default' => '0.5', |
'type' => 'Spin-button', |
'content' => '0.001,0.999,0.001', |
'redefine_param' => 1, |
'info' => ' Duty cycle for CLKOUT0 (0.001-0.999).', |
'global_param' => 'Localparam' |
}, |
'CLKOUT3_PHASE' => { |
'default' => '0.0', |
'content' => '-360.000,360.000,0.001', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'info' => 'Phase offset for each CLKOUT3 (-360.000-360.000).', |
'global_param' => 'Localparam' |
}, |
'CLKOUT5_DIVIDE' => { |
'default' => '1', |
'info' => 'Divide amount for CLKOUT5 (1-128)', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '1,128,1' |
}, |
'CLKOUT1_PHASE' => { |
'global_param' => 'Localparam', |
'info' => 'Phase offset for each CLKOUT1 (-360.000-360.000).', |
'content' => '-360.000,360.000,0.001', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'default' => '0.0' |
}, |
'BANDWIDTH' => { |
'default' => '"OPTIMIZED"', |
'redefine_param' => 1, |
'type' => 'Combo-box', |
'content' => '"OPTIMIZED","HIGH","LOW"', |
'info' => '', |
'global_param' => 'Localparam' |
}, |
'CLKFBOUT_PHASE' => { |
'info' => 'Phase offset in degrees of CLKFB, (-360.000-360.000).', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '-360.000,360.000,0.001', |
'default' => '0.0' |
}, |
'DIVCLK_DIVIDE' => { |
'redefine_param' => 1, |
'content' => '1,56,1', |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'info' => 'Master division value, (1-56)', |
'default' => '1' |
}, |
'STARTUP_WAIT' => { |
'default' => '"FALSE"', |
'global_param' => 'Localparam', |
'info' => 'Delay DONE until PLL Locks, ("TRUE"/"FALSE")', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'content' => '"TRUE","FALSE"' |
}, |
'CLKOUT5_PHASE' => { |
'redefine_param' => 1, |
'content' => '-360.000,360.000,0.001', |
'type' => 'Spin-button', |
'info' => 'Phase offset for each CLKOUT5 (-360.000-360.000).', |
'global_param' => 'Localparam', |
'default' => '0.0' |
}, |
'CLKOUT5_DUTY_CYCLE' => { |
'redefine_param' => 1, |
'content' => '0.001,0.999,0.001', |
'type' => 'Spin-button', |
'info' => ' Duty cycle for CLKOUT5 (0.001-0.999).', |
'global_param' => 'Localparam', |
'default' => '0.5' |
}, |
'CLKOUT1_DUTY_CYCLE' => { |
'default' => '0.5', |
'global_param' => 'Localparam', |
'info' => ' Duty cycle for CLKOUT1 (0.001-0.999).', |
'type' => 'Spin-button', |
'content' => '0.001,0.999,0.001', |
'redefine_param' => 1 |
}, |
'REF_JITTER1' => { |
'default' => '0.0', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'content' => '0.000,0.999,0.001', |
'global_param' => 'Localparam', |
'info' => 'Reference input jitter in UI, (0.000-0.999).' |
}, |
'CLKOUT3_DIVIDE' => { |
'info' => 'Divide amount for CLKOUT3 (1-128)', |
'global_param' => 'Localparam', |
'content' => '1,128,1', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'default' => '1' |
} |
}, |
'unused' => undef, |
'description' => 'PLLE2_BASE', |
'module_name' => 'xilinx_pll2_base', |
'version' => 17, |
'file_name' => 'mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll2_base.v', |
'hdl_files_ticked' => [ |
'/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll_sim' |
], |
'ip_name' => 'xilinx_pll', |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll2_base.v', |
'/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll_sim' |
], |
'ports' => { |
'reset_in' => { |
'range' => '', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
}, |
'clk_in' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
}, |
'reset_out' => { |
'type' => 'output', |
'range' => '', |
'intfc_name' => 'socket:reset[0]', |
'intfc_port' => 'reset_o' |
}, |
'clk_out' => { |
'range' => 'CLKOUT_NUM-1: 0', |
'intfc_port' => 'clk_o', |
'intfc_name' => 'socket:clk[array]', |
'type' => 'output' |
} |
} |
}, 'ip_gen' ); |
/Timer/timer.IP
1,238 → 1,144
####################################################################### |
## File: timer.IP |
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## Copyright (C) 2014-2019 Alireza Monemi |
## |
## This file is part of ProNoC 1.7.0 |
## This file is part of ProNoC 1.9.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
################################################################################ |
|
$timer = bless( { |
'system_h' => '#define ${IP}_TCSR (*((volatile unsigned int *) ($BASE ))) |
|
/* |
//timer control register |
TCSR |
bit |
PRESCALER WIDTH+3:4 : clk_dev_ctrl |
3 : timer_isr |
2 : rst_on_cmp_value |
1 : int_enble_on_cmp_value |
0 : timer enable |
*/ |
#define ${IP}_TLR (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_TCMR (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_EN (1 << 0) |
#define ${IP}_INT_EN (1 << 1) |
#define ${IP}_RST_ON_CMP (1 << 2) |
//Initialize the timer. Enable the timer, reset on compare value, and interrupt |
void ${IP}_int_init ( unsigned int compare ){ |
${IP}_TCMR = compare; |
${IP}_TCSR = ( ${IP}_EN | ${IP}_INT_EN | ${IP}_RST_ON_CMP); |
} |
|
#define ${IP}_start() ${IP}_TCSR|=${IP}_EN |
#define ${IP}_stop() ${IP}_TCSR&=~${IP}_EN |
#define ${IP}_reset() ${IP}_TLR=0 |
#define ${IP}_read() ${IP}_TLR', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'parameters' => { |
'CNTw' => { |
'default' => '32 ', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'content' => '', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'Dw' => { |
'default' => '32', |
'type' => 'Fixed', |
'content' => '', |
'global_param' => 'Localparam', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'SELw' => { |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '4' |
}, |
'TAGw' => { |
'redefine_param' => 1, |
'info' => undef, |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'default' => '3' |
}, |
'PRESCALER_WIDTH' => { |
'type' => 'Spin-button', |
'default' => '8', |
'redefine_param' => 1, |
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured. |
|
|
', |
'global_param' => 'Parameter', |
'content' => '1,32,1' |
}, |
'Aw' => { |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '3' |
} |
}, |
'module_name' => 'timer', |
'description' => 'A simple, general purpose, Wishbone bus-based, 32-bit timer.', |
'sockets' => {}, |
'hdl_files' => [ |
'/mpsoc/src_peripheral/timer/timer.v' |
], |
'category' => 'Timer', |
'parameters_order' => [ |
'CNTw', |
'Dw', |
'Aw', |
'TAGw', |
'SELw', |
'PRESCALER_WIDTH' |
], |
$ipgen = bless( { |
'plugs' => { |
'wb_slave' => { |
'wb_slave' => {}, |
'type' => 'num', |
'value' => 1, |
'0' => { |
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl', |
'name' => 'wb', |
'width' => 5 |
} |
}, |
'interrupt_peripheral' => { |
'type' => 'num', |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'intrp' |
} |
}, |
'type' => 'num', |
'interrupt_peripheral' => {} |
}, |
'wb_slave' => { |
'type' => 'num', |
'wb_slave' => {}, |
'0' => { |
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl', |
'width' => 5, |
'name' => 'wb' |
}, |
'value' => 1 |
}, |
'reset' => { |
'reset' => {}, |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
'reset' => {} |
}, |
'clk' => { |
'clk' => {}, |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1 |
'clk' => {} |
} |
}, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'bte_i' |
] |
}, |
'description' => 'A simple, general purpose, Wishbone bus-based, 32-bit timer.', |
'file_name' => 'mpsoc/rtl/src_peripheral/timer/timer.v', |
'module_name' => 'timer', |
'parameters_order' => [ |
'CNTw', |
'Dw', |
'Aw', |
'TAGw', |
'SELw', |
'PRESCALER_WIDTH' |
], |
'ports' => { |
'sa_err_o' => { |
'intfc_port' => 'err_o', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output' |
}, |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output' |
}, |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
'sa_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_i', |
'type' => 'input' |
}, |
'sa_we_i' => { |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'type' => 'input', |
'range' => '' |
'type' => 'input' |
}, |
'sa_tag_i' => { |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0', |
'sa_cyc_i' => { |
'type' => 'input', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_stb_i' => { |
'range' => '', |
'type' => 'input', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]' |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i' |
}, |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'type' => 'input', |
'range' => 'Aw-1 : 0' |
}, |
'irq' => { |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'int_o' |
'intfc_port' => 'int_o', |
'type' => 'output' |
}, |
'sa_tag_i' => { |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'TAGw-1 : 0', |
'type' => 'input' |
}, |
'reset' => { |
'type' => 'input', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input', |
'range' => '', |
'intfc_port' => 'reset_i' |
'range' => '' |
}, |
'sa_err_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output', |
'intfc_port' => 'err_o' |
}, |
'sa_sel_i' => { |
'range' => 'SELw-1 : 0', |
'type' => 'input', |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]' |
}, |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'rty_o' |
}, |
'sa_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'input', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'dat_i' |
}, |
'sa_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'type' => 'input', |
'range' => '' |
}, |
'sa_addr_i' => { |
'range' => 'Aw-1 : 0', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'type' => 'input' |
}, |
'clk' => { |
'type' => 'input', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]' |
}, |
'sa_dat_o' => { |
'sa_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'dat_o' |
'intfc_port' => 'dat_i', |
'type' => 'input' |
}, |
'sa_stb_i' => { |
'range' => '', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'type' => 'input' |
}, |
'sa_ack_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_slave[0]', |
'type' => 'output', |
'range' => '', |
'intfc_port' => 'ack_o' |
} |
240,8 → 146,102
'modules' => { |
'timer' => {} |
}, |
'version' => 9, |
'ip_name' => 'timer', |
'description_pdf' => '/mpsoc/src_peripheral/timer/timer.pdf', |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/timer/timer.v' |
'description_pdf' => '/mpsoc/rtl/src_peripheral/timer/timer.pdf', |
'version' => 12, |
'system_h' => '#define ${IP}_TCSR (*((volatile unsigned int *) ($BASE ))) |
|
/* |
//timer control register |
TCSR |
bit |
PRESCALER WIDTH+3:4 : clk_dev_ctrl |
3 : timer_isr |
2 : rst_on_cmp_value |
1 : int_enble_on_cmp_value |
0 : timer enable |
*/ |
#define ${IP}_TLR (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_TCMR (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_EN (1 << 0) |
#define ${IP}_INT_EN (1 << 1) |
#define ${IP}_RST_ON_CMP (1 << 2) |
//Initialize the timer. Enable the timer, reset on compare value, and interrupt |
static inline void ${IP}_int_init ( unsigned int compare ){ |
${IP}_TCMR = compare; |
${IP}_TCSR = ( ${IP}_EN | ${IP}_INT_EN | ${IP}_RST_ON_CMP); |
} |
|
#define ${IP}_start() ${IP}_TCSR|=${IP}_EN |
#define ${IP}_stop() ${IP}_TCSR&=~${IP}_EN |
#define ${IP}_reset() ${IP}_TLR=0 |
#define ${IP}_read() ${IP}_TLR', |
'hdl_files' => [ |
'/mpsoc/rtl/src_peripheral/timer/timer.v' |
], |
'parameters' => { |
'CNTw' => { |
'info' => undef, |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Localparam', |
'default' => '32 ', |
'type' => 'Fixed' |
}, |
'TAGw' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '3', |
'info' => undef, |
'redefine_param' => 1, |
'content' => '' |
}, |
'SELw' => { |
'global_param' => 'Localparam', |
'default' => '4', |
'type' => 'Fixed', |
'content' => '', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'PRESCALER_WIDTH' => { |
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured. |
|
|
', |
'redefine_param' => 1, |
'content' => '1,32,1', |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'default' => '8' |
}, |
'Aw' => { |
'info' => undef, |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '3' |
}, |
'Dw' => { |
'content' => '', |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => '32', |
'type' => 'Fixed' |
} |
}, |
'category' => 'Timer', |
'sockets' => {}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'unused' => { |
'plug:wb_slave[0]' => [ |
'bte_i', |
'cti_i' |
] |
} |
}, 'ip_gen' ); |