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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/mpsoc
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  •

Rev 48 → Rev 54

/mor1k_mpsoc.MPSOC
9,6952 → 9,781
## MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
 
$mpsoc = bless( {
'SOURCE_SET' => {
'REDEFINE_TOP' => 0,
'clk_0_name' => 'clk',
'SOC' => bless( {
'TOP' => {
'version' => 0
},
'SOURCE_SET' => {
'IP' => bless( {
'parameters_order' => [],
'ports_order' => [],
'plugs' => {
'clk' => {
'type' => 'num',
'1' => {},
'0' => {
'name' => 'clk'
},
'value' => 1
},
'reset' => {
'1' => {},
'0' => {
'name' => 'reset'
},
'value' => 1,
'type' => 'num'
}
},
'module_name' => 'TOP',
'file_name' => undef,
'hdl_files' => [],
'hdl_files_ticked' => [],
'ip_name' => 'TOP',
'ports' => {
'clk' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => undef,
'intfc_name' => 'plug:clk[0]'
},
'reset' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => undef
}
},
'category' => 'TOP',
'GUI_REMOVE_SET' => 'DISABLE'
}, 'ip_gen' )
},
'instance_order' => [
'TOP'
],
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'hdl_files' => undef,
'instances' => {
'TOP' => {
'sockets' => {},
'parameters_order' => [],
'module' => 'TOP',
'module_name' => 'TOP',
'plugs' => {
'clk' => {
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'IO',
'connect_socket' => undef,
'connect_socket_num' => undef
$mor1k_mpsoc = bless( {
'RAM3' => {
'end' => 65536,
'start' => 49152
},
'mpsoc_name' => 'mor1k_mpsoc',
'compile_pin_range_lsb' => {
'processors_en' => 0
},
'ROM3' => {
'end' => 49152,
'start' => 0
},
'compile' => {
'cpu_num' => '4',
'modelsim_bin' => 'export LM_LICENSE_FILE=1717@epi03.bsc.es; /home/alireza/intelFPGA_lite/questa/questasim/bin',
'type' => 'QuartusII',
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim',
'board' => 'DE10_Nano_VB2',
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin'
},
'MEM2' => {
'percent' => '75',
'width' => '14'
},
'socs' => {
'mor1k_tile' => {
'tile_nums' => [
0,
1,
2,
3
],
'top' => bless( {
'interface' => {
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input'
},
'uart_RxD_ready_sim' => {
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'range' => ''
},
'uart_RxD_wr_sim' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'instance_name' => 'ProNoC_jtag_uart0'
}
}
},
'type' => 'num',
'connection_num' => undef
},
'reset' => {
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_socket' => undef,
'connect_id' => 'IO',
'name' => 'reset'
}
},
'value' => 1,
'type' => 'num',
'connection_num' => undef
}
},
'instance_name' => 'TOP',
'description_pdf' => undef,
'category' => 'TOP'
}
},
'modules' => {},
'soc_name' => {
'TOP' => undef
},
'device_win_adj' => {
'ha' => '0',
'va' => '0'
}
}, 'soc' ),
'clk_number' => 1,
'reset_number' => 1,
'reset_0_name' => 'reset'
},
'tile' => {
'2' => {},
'1' => {},
'0' => {},
'3' => {}
},
'soc_param' => {
'default' => {
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JSTATUSw' => '8',
'uart_JTAG_CHAIN' => '3',
'ram_Aw' => '14',
'ram_JTAG_CHAIN' => '4',
'ram_Dw' => '32',
'uart_JINDEXw' => '8',
'ram_JAw' => '32',
'ram_JDw' => 'ram_Dw',
'ram_JINDEXw' => '8',
'uart_JDw' => '32'
}
},
'ROM1' => {
'end' => 49152,
'start' => 0
},
'noc_param' => {
'SSA_EN' => '"NO"',
'SWA_ARBITER_TYPE' => '"RRA"',
'B' => '4',
'MUX_TYPE' => '"BINARY"',
'DEBUG_EN' => '0',
'Fpay' => '32',
'ROUTE_NAME' => '"XY"',
'AVC_ATOMIC_EN' => 0,
'ESCAP_VC_MASK' => '2\'b01',
'TOPOLOGY' => '"MESH"',
'T3' => '1',
'T2' => '2',
'BYTE_EN' => '1',
'T1' => '2',
'WEIGHTw' => '4',
'CONGESTION_INDEX' => 3,
'V' => '2',
'MIN_PCK_SIZE' => '2',
'FIRST_ARBITER_EXT_P_EN' => 1,
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'C' => 0
},
'MEM3' => {
'width' => '14',
'percent' => '75'
},
'RAM2' => {
'start' => 49152,
'end' => 65536
},
'liststore' => {
'ha' => '0',
'va' => '0'
},
'RAM3' => {
'end' => 65536,
'start' => 49152
},
'ROM0' => {
'end' => 22937,
'start' => 0
},
'MEM2' => {
'percent' => '75',
'width' => '14'
},
'MEM0' => {
'percent' => '70',
'width' => '13'
},
'mpsoc_name' => 'mor1k_mpsoc',
'compile' => {
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin',
'type' => 'Modelsim',
'modelsim_bin' => 'export LM_LICENSE_FILE=1717@epi03.bsc.es; /home/alireza/intelFPGA_lite/questa/questasim/bin',
'board' => 'DE5',
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim'
},
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'SOURCE_SET_CONNECT' => {
'NoC_clk' => 'clk',
'T0_cs_reset_in' => 'reset',
'T1_ss_clk_in' => 'clk0',
'T2_cs_reset_in' => 'reset',
'T3_cs_clk_in' => 'clk',
'NoC_reset' => 'reset',
'T3_cs_reset_in' => 'reset',
'T1_cs_clk_in' => 'clk',
'T3_ss_clk_in' => 'clk0',
'T0_cs_clk_in' => 'clk',
'T0_ss_clk_in' => 'clk0',
'T1_ss_reset_in' => 'reset0',
'T1_cs_reset_in' => 'reset',
'T2_ss_clk_in' => 'clk0',
'T2_ss_reset_in' => 'reset0',
'T2_cs_clk_in' => 'clk',
'T3_ss_reset_in' => 'reset0',
'T0_ss_reset_in' => 'reset0'
},
'socs' => {
'mor1k_xilinx_tile' => {
'top' => bless( {
'parameters' => {
'ram1_JAw' => '32',
'ram2_JDw' => 'ram2_Dw',
'ram2_JTAG_INDEX' => 'CORE_ID',
'ram1_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram2_JINDEXw' => '8',
'ram2_WB2Jw' => '(ram2_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram2_JSTATUSw+ram2_JINDEXw+1+ram2_JDw : 1',
'ram1_JSTATUSw' => '8',
'ram1_JDw' => 'ram1_Dw',
'ram2_JAw' => '32',
'ram1_Dw' => '32',
'ram2_J2WBw' => '(ram2_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram2_JDw+ram2_JAw : 1',
'ram1_JINDEXw' => '8',
'ram2_Dw' => '32',
'ram2_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram2_JTAG_CHAIN' => '4',
'ram1_J2WBw' => '(ram1_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram1_JDw+ram1_JAw : 1',
'ram1_JTAG_INDEX' => 'CORE_ID',
'ram2_JSTATUSw' => '8',
'ram1_WB2Jw' => '(ram1_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram1_JSTATUSw+ram1_JINDEXw+1+ram1_JDw : 1',
'ram1_JTAG_CHAIN' => '4'
},
'interface' => {
'plug:reset[0]' => {
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'range' => '',
'type' => 'input',
'instance_name' => 'clk_source0',
'intfc_port' => 'clk_i'
}
}
},
'plug:enable[0]' => {
'ports' => {
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
}
'cpu_cpu_en' => {
'range' => '',
'instance_name' => 'mor1kx0',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'socket:ni[0]' => {
'plug:reset[0]' => {
'ports' => {
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'range' => '',
'instance_name' => 'ni_master0'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out',
'type' => 'output'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'range' => '',
'instance_name' => 'ni_master0'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0'
}
'source_reset_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'intfc_port' => 'IO',
'type' => 'output'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'instance_name' => 'mor1kx0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram1_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'single_port_ram0',
'range' => 'ram1_WB2Jw-1 : 0'
},
'ram2_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'ram2_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram1'
},
'ram2_jtag_to_wb' => {
'range' => 'ram2_J2WBw-1 : 0',
'instance_name' => 'single_port_ram1',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'ram1_jtag_to_wb' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram1_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
}
}
},
'ports' => {
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ram2_jtag_to_wb' => {
'instance_name' => 'single_port_ram1',
'range' => 'ram2_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => ''
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ram2_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram2_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram1',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'led_port_o' => {
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'type' => 'output',
'intfc_port' => 'IO'
},
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'ram1_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram1_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'ram1_jtag_to_wb' => {
'range' => 'ram1_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'type' => 'input'
}
},
'instance_ids' => {
'mor1kx0' => {
'instance' => 'cpu',
'module_name' => 'mor1k',
'localparam' => {
'cpu_FEATURE_DMMU' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1
},
'cpu_OPTION_OPERAND_WIDTH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'cpu_IRQ_NUM' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '32',
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'cpu_FEATURE_IMMU' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => ''
},
'cpu_OPTION_DCACHE_SNOOP' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'cpu_FEATURE_DATACACHE' => {
'default' => '"ENABLED"',
'info' => '',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"'
}
},
'category' => 'Processor',
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
}
},
'module' => 'mor1kx'
},
'single_port_ram1' => {
'category' => 'RAM',
'localparam' => {
'ram2_CORE_NUM' => {
'default' => 'CORE_ID',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ram2_INITIAL_EN' => {
'content' => '"YES","NO"',
'redefine_param' => 1,
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram2_BURST_MODE' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'default' => '"ENABLED"',
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1
},
'ram2_INIT_FILE_PATH' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => 'SW_LOC'
},
'ram2_BTEw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '2',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram2_CTIw' => {
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'ram2_MEM_CONTENT_FILE_NAME' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Entry',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"'
},
'ram2_BYTE_WR_EN' => {
'content' => '"YES","NO"',
'redefine_param' => 1,
'default' => '"YES"',
'info' => 'Byte enable',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ram2_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => 'ram2_Dw/8',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram2_TAGw' => {
'default' => '3',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ram2_Aw' => {
'redefine_param' => 1,
'content' => '4,31,1',
'default' => '14',
'info' => 'Memory address width',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'ram2_WB_Aw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'default' => 'ram2_Aw+2',
'content' => '4,31,1',
'redefine_param' => 1
},
'ram2_FPGA_VENDOR' => {
'content' => '"ALTERA","XILINX","GENERIC"',
'redefine_param' => 1,
'info' => '',
'default' => '"XILINX"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
}
},
'module_name' => 'wb_single_port_ram',
'instance' => 'ram2',
'parameters' => {
'ram2_WB2Jw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => undef,
'default' => '(ram2_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram2_JSTATUSw+ram2_JINDEXw+1+ram2_JDw : 1'
},
'ram2_JSTATUSw' => {
'info' => 'Parameter',
'default' => '8',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram2_JTAG_INDEX' => {
'type' => 'Entry',
'global_param' => 'Parameter',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'content' => '',
'redefine_param' => 1
},
'ram2_JINDEXw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram2_JTAG_CHAIN' => {
'global_param' => 'Parameter',
'type' => 'Combo-box',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'redefine_param' => 0,
'content' => '1,2,3,4'
},
'ram2_Dw' => {
'content' => '8,1024,1',
'redefine_param' => 1,
'info' => 'Memory data width in Bits.',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Spin-button'
},
'ram2_JTAG_CONNECT' => {
'redefine_param' => 1,
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"XILINX_JTAG_WB"'
},
'ram2_JDw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => 'ram2_Dw',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ram2_JAw' => {
'info' => 'Parameter',
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram2_J2WBw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(ram2_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram2_JDw+ram2_JAw : 1',
'info' => undef,
'content' => '',
'redefine_param' => 1
}
},
'module' => 'single_port_ram',
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram2_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram2_J2WBw-1 : 0',
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ram2_wb_to_jtag' => {
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'single_port_ram0',
'type' => 'input'
},
'uart_wb_to_jtag' => {
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram2_WB2Jw-1 : 0'
}
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'output',
'intfc_port' => 'jwb_o'
}
}
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'localparam' => {
'bus_Aw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'The wishbone Bus address width',
'redefine_param' => 1,
'content' => '4,128,1'
},
'bus_SELw' => {
'default' => 'bus_Dw/8',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'bus_BTEw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '2 ',
'info' => undef
},
'bus_TAGw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef
},
'bus_S' => {
'info' => 'Number of wishbone slave interface',
'default' => '5',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_Dw' => {
'content' => '8,512,8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '32',
'info' => 'The wishbone Bus data width in bits.'
},
'bus_CTIw' => {
'content' => '',
'redefine_param' => 1,
'default' => '3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_M' => {
'info' => 'Number of wishbone master interface',
'default' => ' 4',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '1,256,1'
}
},
'category' => 'Bus'
},
'timer0' => {
'localparam' => {
'timer_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => '4',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'timer_Dw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '32',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'timer_PRESCALER_WIDTH' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'default' => '8',
'redefine_param' => 1,
'content' => '1,32,1'
},
'timer_TAGw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => undef
},
'timer_Aw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '3',
'redefine_param' => 1,
'content' => ''
},
'timer_CNTw' => {
'info' => undef,
'default' => '32 ',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
}
},
'category' => 'Timer',
'module_name' => 'timer',
'instance' => 'timer',
'module' => 'timer'
},
'ni_master0' => {
'parameters' => {
'ni_T3' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '1',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_RAw' => {
'info' => undef,
'default' => '16',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 0,
'content' => ''
},
'ni_Fpay' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter'
},
'ni_BYTE_EN' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => 0
'socket:ni[0]' => {
'ports' => {
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr',
'instance_name' => 'ni_master0'
},
'ni_TOPOLOGY' => {
'default' => '"MESH"',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_B' => {
'content' => '',
'redefine_param' => 1,
'default' => '4',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
'ni_chan_in' => {
'range' => 'smartflit_chanel_t',
'intfc_port' => 'chan_in',
'instance_name' => 'ni_master0',
'type' => 'input'
},
'ni_chan_out' => {
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'chan_out'
},
'ni_DEBUG_EN' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '0',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_T1' => {
'redefine_param' => 1,
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'intfc_port' => 'current_r_addr',
'type' => 'input',
'instance_name' => 'ni_master0'
}
}
}
},
'parameters' => {
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_JAw' => '32',
'ram_Dw' => '32',
'uart_JAw' => '32',
'uart_JTAG_CHAIN' => '3',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JSTATUSw' => '8',
'uart_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'ram_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1'
},
'instance_ids' => {
'timer0' => {
'module' => 'timer',
'localparam' => {
'timer_CNTw' => {
'content' => '',
'default' => '2',
'info' => 'Parameter',
'info' => undef,
'default' => '32 ',
'type' => 'Fixed',
'global_param' => 'Parameter'
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_C' => {
'default' => 0,
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_EAw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '16',
'info' => undef,
'redefine_param' => 0,
'content' => ''
},
'ni_T2' => {
'timer_SELw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '2',
'global_param' => 'Parameter',
'global_param' => 'Localparam',
'default' => '4',
'type' => 'Fixed'
},
'ni_V' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2'
},
'ni_ROUTE_NAME' => {
'default' => '"XY"',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
}
},
'ports' => {
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'ni_flit_out_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
}
},
'module' => 'ni_master',
'module_name' => 'ni_master',
'localparam' => {
'ni_Fw' => {
'default' => '2+ni_V+ni_Fpay',
'info' => undef,
'timer_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'content' => ''
},
'timer_PRESCALER_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8',
'type' => 'Spin-button',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'content' => '1,32,1'
},
'timer_Dw' => {
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => undef
},
'timer_TAGw' => {
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'redefine_param' => 0
},
'ni_MAX_TRANSACTION_WIDTH' => {
'redefine_param' => 1,
'content' => '4,32,1',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'default' => '13'
},
'ni_MAX_BURST_SIZE' => {
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1,
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ni_S_Aw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_M_Aw' => {
'content' => 'Dw',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter'
},
'ni_HDATA_PRECAPw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'default' => 4,
'content' => '0,8,1',
'redefine_param' => 1
},
'ni_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '4',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'wishbone_bus data width in bits.',
'default' => '32',
'content' => '32,256,8',
'redefine_param' => 1
},
'ni_CRC_EN' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'default' => '"NO"',
'redefine_param' => 1,
'content' => '"YES","NO"'
}
},
'category' => 'NoC',
'instance' => 'ni'
},
'single_port_ram0' => {
'module_name' => 'wb_single_port_ram',
'localparam' => {
'ram1_CORE_NUM' => {
'info' => undef
}
},
'category' => 'Timer',
'instance' => 'timer',
'module_name' => 'timer'
},
'ProNoC_jtag_uart0' => {
'category' => 'Communication',
'parameters' => {
'uart_JTAG_CONNECT' => {
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box'
},
'uart_JSTATUSw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'default' => '8',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => 'CORE_ID',
'type' => 'Fixed',
'global_param' => 'Localparam'
'content' => ''
},
'ram1_MEM_CONTENT_FILE_NAME' => {
'type' => 'Entry',
'global_param' => 'Localparam',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"',
'redefine_param' => 1,
'content' => ''
},
'ram1_FPGA_VENDOR' => {
'content' => '"ALTERA","XILINX","GENERIC"',
'redefine_param' => 1,
'default' => '"XILINX"',
'info' => '',
'global_param' => 'Localparam',
'type' => 'Combo-box'
},
'ram1_INITIAL_EN' => {
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'default' => '"YES"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'redefine_param' => 1
},
'ram1_Aw' => {
'redefine_param' => 1,
'content' => '4,31,1',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '14',
'info' => 'Memory address width'
},
'ram1_BYTE_WR_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'default' => '"YES"',
'info' => 'Byte enable',
'global_param' => 'Localparam',
'type' => 'Combo-box'
},
'ram1_BTEw' => {
'info' => 'Parameter',
'default' => '2',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'ram1_TAGw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram1_WB_Aw' => {
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'default' => 'ram1_Aw+2',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'uart_J2WBw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'content' => '4,31,1'
'global_param' => 'Parameter',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'type' => 'Fixed'
},
'ram1_BURST_MODE' => {
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1
},
'ram1_SELw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'ram1_Dw/8',
'info' => 'Parameter'
},
'ram1_INIT_FILE_PATH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'SW_LOC',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'ram1_CTIw' => {
'default' => '3',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
}
},
'category' => 'RAM',
'instance' => 'ram1',
'parameters' => {
'ram1_Dw' => {
'redefine_param' => 1,
'content' => '8,1024,1',
'default' => '32',
'info' => 'Memory data width in Bits.',
'type' => 'Spin-button',
'global_param' => 'Parameter'
},
'ram1_JINDEXw' => {
'redefine_param' => 1,
'uart_JDw' => {
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JINDEXw' => {
'content' => '',
'info' => 'Parameter',
'default' => '8',
'global_param' => 'Parameter',
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram1_JAw' => {
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Entry',
'default' => '126-CORE_ID'
},
'uart_JAw' => {
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
'info' => 'Parameter'
},
'ram1_JTAG_CONNECT' => {
'redefine_param' => 1,
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'default' => '"XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'type' => 'Combo-box',
'global_param' => 'Parameter'
},
'ram1_J2WBw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(ram1_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram1_JDw+ram1_JAw : 1',
'info' => undef
},
'ram1_JTAG_INDEX' => {
'type' => 'Entry',
'global_param' => 'Parameter',
'default' => 'CORE_ID',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'redefine_param' => 1,
'content' => ''
},
'ram1_WB2Jw' => {
'default' => '(ram1_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram1_JSTATUSw+ram1_JINDEXw+1+ram1_JDw : 1',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram1_JSTATUSw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram1_JTAG_CHAIN' => {
'global_param' => 'Parameter',
'type' => 'Combo-box',
'default' => '4',
'uart_JTAG_CHAIN' => {
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'content' => '1,2,3,4',
'redefine_param' => 0
'global_param' => 'Parameter',
'redefine_param' => 0,
'default' => '3',
'type' => 'Combo-box'
},
'ram1_JDw' => {
'redefine_param' => 1,
'content' => '',
'default' => 'ram1_Dw',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
}
'uart_WB2Jw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'info' => '',
'content' => ''
}
},
'ports' => {
'ram1_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'ram1_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram1_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram1_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
}
},
'module' => 'single_port_ram'
},
'gpo0' => {
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
}
},
'module' => 'gpo',
'instance' => 'led',
'module_name' => 'gpo',
'localparam' => {
'led_PORT_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'output port width',
'default' => ' 1',
'content' => '1,32,1',
'redefine_param' => 1
},
'led_TAGw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => ' 3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'led_Dw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => 'led_PORT_WIDTH',
'content' => '',
'redefine_param' => 1
},
'led_SELw' => {
'default' => ' 4',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'led_Aw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => ' 2'
}
},
'category' => 'GPIO'
},
'clk_source0' => {
'module' => 'clk_source',
'ports' => {
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ss_clk_in' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input'
}
},
'instance' => 'ss',
'category' => 'Source',
'module_name' => 'clk_source'
}
}
}, 'ip_gen' ),
'tile_nums' => undef
},
'lm32_new_tile' => {
'top' => bless( {
'instance_ids' => {
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'localparam' => {
'bus_CTIw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'bus_M' => {
'content' => '1,256,1',
'redefine_param' => 1,
'default' => ' 4',
'info' => 'Number of wishbone master interface',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'bus_S' => {
'content' => '1,256,1',
'redefine_param' => 1,
'default' => 5,
'info' => 'Number of wishbone slave interface',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'bus_Dw' => {
'default' => '32',
'info' => 'The wishbone Bus data width in bits.',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'content' => '8,512,8',
'redefine_param' => 1
},
'bus_Aw' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '32',
'info' => 'The wishbone Bus address width',
'content' => '4,128,1',
'redefine_param' => 1
},
'bus_BTEw' => {
'info' => undef,
'default' => '2 ',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'bus_TAGw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => undef
},
'bus_SELw' => {
'default' => 'bus_Dw/8',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
}
},
'instance' => 'bus'
},
'ProNoC_jtag_uart0' => {
'module' => 'ProNoC_jtag_uart',
'ports' => {
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
},
'parameters' => {
'uart_JDw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '32'
},
'uart_WB2Jw' => {
'info' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'global_param' => 'Parameter',
'module' => 'ProNoC_jtag_uart',
'localparam' => {
'uart_BUFF_Aw' => {
'default' => '4',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '2,16,1',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.'
},
'uart_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter',
'content' => ''
},
'uart_JINDEXw' => {
'uart_TAGw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '3',
'info' => 'Parameter',
'default' => '8',
'content' => ''
},
'uart_SELw' => {
'content' => '',
'redefine_param' => 1
},
'uart_JSTATUSw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '8',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'default' => '126-CORE_ID',
'type' => 'Entry',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_BUFF_Aw' => {
'content' => '2,16,1',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '4',
'redefine_param' => 1,
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => '6',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.'
'global_param' => 'Localparam'
},
'uart_J2WBw' => {
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter',
'uart_Aw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'uart_JAw' => {
'info' => 'Parameter',
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'uart_JTAG_CONNECT' => {
'default' => '"XILINX_JTAG_WB"',
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"'
},
'uart_JTAG_CHAIN' => {
'global_param' => 'Parameter',
'type' => 'Combo-box',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '3',
'redefine_param' => 0,
'content' => '1,2,3,4'
}
},
'instance' => 'uart',
'category' => 'Communication',
'localparam' => {
'uart_SELw' => {
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'uart_TAGw' => {
'default' => '3',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'uart_Dw' => {
'content' => '',
'redefine_param' => 1,
'default' => '1',
'type' => 'Fixed'
}
},
'instance' => 'uart',
'module_name' => 'pronoc_jtag_uart',
'ports' => {
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0'
},
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
}
}
},
'wishbone_bus0' => {
'localparam' => {
'bus_SELw' => {
'type' => 'Fixed',
'default' => 'bus_Dw/8',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '32'
},
'uart_Aw' => {
'redefine_param' => 1,
'content' => '',
'default' => '1',
'info' => 'Parameter',
'info' => undef
},
'bus_CTIw' => {
'type' => 'Fixed',
'global_param' => 'Localparam'
}
},
'module_name' => 'pronoc_jtag_uart'
},
'lm32_new0' => {
'module_name' => 'lm32',
'category' => 'Processor',
'localparam' => {
'lm32_new_INTR_NUM' => {
'info' => undef,
'default' => '32',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
}
},
'instance' => 'lm32_new',
'ports' => {
'lm32_new_en_i' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'module' => 'lm32_new'
},
'clk_source0' => {
'module' => 'clk_source',
'ports' => {
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ss_clk_in' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input'
}
},
'instance' => 'ss',
'category' => 'Source',
'module_name' => 'clk_source'
},
'single_port_ram0' => {
'category' => 'RAM',
'localparam' => {
'ram_CTIw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '3'
},
'ram_INITIAL_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram_SELw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => 'ram_Dw/8',
'info' => 'Parameter'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Entry',
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . '
},
'ram_BTEw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '2',
'info' => 'Parameter'
'info' => undef
},
'ram_CORE_NUM' => {
'content' => '',
'redefine_param' => 1,
'default' => 'CORE_ID',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram_BURST_MODE' => {
'redefine_param' => 1,
'content' => '"DISABLED","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'default' => '"ENABLED"'
},
'ram_TAGw' => {
'bus_S' => {
'content' => '1,256,1',
'info' => 'Number of wishbone slave interface',
'default' => '4',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'bus_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '3'
'redefine_param' => 1
},
'ram_INIT_FILE_PATH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => 'SW_LOC',
'redefine_param' => 1,
'content' => ''
},
'ram_BYTE_WR_EN' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'Byte enable',
'default' => '"YES"',
'content' => '"YES","NO"',
'redefine_param' => 1
}
},
'module_name' => 'wb_single_port_ram',
'instance' => 'ram',
'parameters' => {
'ram_JTAG_CONNECT' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'redefine_param' => 1
},
'ram_JINDEXw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram_WB2Jw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'redefine_param' => 1,
'content' => ''
},
'ram_JAw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '32',
'redefine_param' => 1,
'content' => ''
},
'ram_JDw' => {
'info' => 'Parameter',
'default' => 'ram_Dw',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_FPGA_VENDOR' => {
'info' => '',
'default' => '"XILINX"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"'
},
'ram_JTAG_INDEX' => {
'type' => 'Entry',
'global_param' => 'Parameter',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'content' => '',
'redefine_param' => 1
},
'ram_JSTATUSw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'redefine_param' => 0,
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'ram_J2WBw' => {
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ram_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1',
'redefine_param' => 1
},
'ram_Aw' => {
'global_param' => 'Parameter',
'type' => 'Spin-button',
'info' => 'Memory address width',
'default' => '14',
'content' => '4,31,1',
'redefine_param' => 1
}
},
'module' => 'single_port_ram',
'ports' => {
'ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
}
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'redefine_param' => 1,
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => ' 1',
'info' => 'output port width'
}
},
'module' => 'gpo',
'ports' => {
'led_port_o' => {
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
},
'localparam' => {
'led_TAGw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => ' 3',
'redefine_param' => 1,
'content' => ''
},
'led_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => ' 4',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'led_Aw' => {
'info' => undef,
'default' => ' 2',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'led_Dw' => {
'info' => undef,
'default' => 'led_PORT_WIDTH',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
}
},
'category' => 'GPIO',
'module_name' => 'gpo',
'instance' => 'led'
},
'ni_master0' => {
'instance' => 'ni',
'module_name' => 'ni_master',
'category' => 'NoC',
'localparam' => {
'ni_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'wishbone_bus data width in bits.',
'default' => '32',
'content' => '32,256,8',
'redefine_param' => 1
},
'ni_SELw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '4'
},
'ni_TAGw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => 'Parameter'
},
'ni_CRC_EN' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'default' => '"NO"',
'redefine_param' => 1,
'content' => '"YES","NO"'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'content' => '4,32,1',
'redefine_param' => 1,
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'default' => '13'
},
'ni_Fw' => {
'redefine_param' => 0,
'content' => '',
'default' => '2+ni_V+ni_Fpay',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_HDATA_PRECAPw' => {
'default' => '4',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '0,8,1',
'redefine_param' => 1
},
'ni_M_Aw' => {
'default' => '32',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => 'Dw'
},
'ni_S_Aw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'ni_MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1
}
},
'ports' => {
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'type' => 'output'
}
},
'module' => 'ni_master',
'parameters' => {
'ni_TOPOLOGY' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '"MESH"',
'redefine_param' => 1,
'content' => ''
},
'ni_B' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '4',
'content' => '',
'redefine_param' => 1
},
'ni_DEBUG_EN' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '0'
},
'ni_T3' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '1'
},
'ni_BYTE_EN' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => 0,
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'ni_RAw' => {
'content' => '',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '16'
},
'ni_Fpay' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter'
},
'ni_T2' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '2',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_EAw' => {
'redefine_param' => 0,
'content' => '',
'info' => undef,
'default' => '16',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '"XY"'
},
'ni_V' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '2'
},
'ni_C' => {
'info' => 'Parameter',
'default' => 0,
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_T1' => {
'info' => 'Parameter',
'default' => '2',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
}
}
},
'timer0' => {
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'default' => '8'
}
},
'ports' => {
'timer_irq' => {
'type' => 'output',
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'range' => ''
}
},
'module' => 'timer',
'module_name' => 'timer',
'localparam' => {
'timer_TAGw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'timer_Aw' => {
'default' => '3',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'timer_CNTw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '32 '
},
'timer_SELw' => {
'default' => '4',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'timer_Dw' => {
'default' => '32',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
}
},
'category' => 'Timer',
'instance' => 'timer'
}
},
'ports' => {
'timer_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'instance_name' => 'timer0',
'intfc_name' => 'plug:interrupt_peripheral[0]'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:clk[0]'
},
'ram_wb_to_jtag' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'lm32_new_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'lm32_new0',
'range' => '',
'intfc_name' => 'plug:enable[0]'
},
'ni_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_r_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'intfc_port' => 'jwb_o'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'lm32_new_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'instance_name' => 'lm32_new0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_WB2Jw-1 : 0'
},
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0'
},
'uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0'
},
'ram_jtag_to_wb' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'type' => 'output',
'intfc_port' => 'IO'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'ni_current_r_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_flit_in_wr' => {
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'timer_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'instance_name' => 'timer0'
}
}
}
},
'parameters' => {
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'uart_BUFF_Aw' => '6',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JSTATUSw' => '8',
'ram_FPGA_VENDOR' => '"XILINX"',
'uart_JTAG_CHAIN' => '3',
'ram_Aw' => '14',
'timer_PRESCALER_WIDTH' => '8',
'led_PORT_WIDTH' => ' 1',
'ram_JTAG_CHAIN' => '4',
'ram_Dw' => '32',
'uart_JINDEXw' => '8',
'ram_JAw' => '32',
'ram_JDw' => 'ram_Dw',
'ram_JINDEXw' => '8',
'uart_JDw' => '32'
}
}, 'ip_gen' ),
'tile_nums' => undef
},
'Tile' => {
'tile_nums' => undef,
'top' => bless( {
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'range' => '',
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_out_wr' => {
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'ni_credit_out' => {
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out',
'type' => 'output'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram_wb_to_jtag' => {
'instance_name' => 'single_port_ram0',
'range' => 'WB2Jw-1 : 0',
'intfc_port' => 'wb_to_jtag',
'type' => 'output'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jtag_to_wb',
'instance_name' => 'single_port_ram0',
'range' => 'J2WBw-1 : 0'
}
}
},
'IO' => {
'ports' => {
'key_port_i' => {
'instance_name' => 'gpi0',
'range' => 'key_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'type' => 'input'
}
}
}
},
'parameters' => {
'cpu_FEATURE_DMMU' => '"ENABLED"',
'cpu_OPTION_OPERAND_WIDTH' => '32',
'cpu_OPTION_DCACHE_SNOOP' => '"ENABLED"',
'cpu_FEATURE_IMMU' => '"ENABLED"',
'ram_Aw' => 14,
'timer_PRESCALER_WIDTH' => '8',
'cpu_IRQ_NUM' => '32',
'key_PORT_WIDTH' => ' 1',
'ram_Dw' => '32',
'cpu_FEATURE_DATACACHE' => '"ENABLED"',
'cpu_FEATURE_INSTRUCTIONCACHE' => '"ENABLED"'
},
'instance_ids' => {
'gpi0' => {
'category' => 'GPIO',
'localparam' => {
'key_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => ' 4',
'redefine_param' => 1,
'content' => ''
},
'key_Dw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => 'key_PORT_WIDTH',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'key_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => ' 2',
'content' => '',
'redefine_param' => 1
},
'key_TAGw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => ' 3',
'type' => 'Fixed',
'global_param' => 'Localparam'
}
},
'module_name' => 'gpi',
'instance' => 'key',
'parameters' => {
'key_PORT_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'info' => 'Input port width ',
'default' => ' 1',
'redefine_param' => 1,
'content' => '1,32,1'
}
},
'module' => 'gpi',
'ports' => {
'key_port_i' => {
'type' => 'input',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'key_PORT_WIDTH-1 : 0'
}
}
},
'timer0' => {
'instance' => 'timer',
'localparam' => {
'timer_TAGw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'timer_CNTw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '32 ',
'redefine_param' => 1,
'content' => ''
},
'timer_Aw' => {
'redefine_param' => 1,
'content' => '',
'default' => '3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'timer_Dw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'timer_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '4',
'redefine_param' => 1,
'content' => ''
}
},
'category' => 'Timer',
'module_name' => 'timer',
'module' => 'timer',
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'global_param' => 'Parameter',
'type' => 'Spin-button',
'content' => '1,32,1',
'redefine_param' => 1
}
}
},
'ni_master0' => {
'instance' => 'ni',
'localparam' => {
'ni_CRC_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'default' => '"NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box'
},
'ni_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_SELw' => {
'info' => 'Parameter',
'default' => '4',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_Dw' => {
'content' => '32,256,8',
'redefine_param' => 1,
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'wishbone_bus data width in bits.',
'default' => '32'
},
'ni_MAX_BURST_SIZE' => {
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1
},
'ni_M_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw',
'redefine_param' => 1
},
'ni_S_Aw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '8',
'info' => 'Parameter'
},
'ni_Fw' => {
'content' => '',
'redefine_param' => 0,
'default' => '2+ni_V+ni_Fpay',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '4,32,1',
'redefine_param' => 1
}
},
'category' => 'NoC',
'module_name' => 'ni_master',
'module' => 'ni_master',
'ports' => {
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_in_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0'
}
},
'parameters' => {
'ni_TOPOLOGY' => {
'redefine_param' => 1,
'content' => '',
'default' => '"MESH"',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_B' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '4',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '0',
'redefine_param' => 1,
'content' => ''
},
'ni_T3' => {
'default' => '1',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_RAw' => {
'redefine_param' => 0,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '16'
},
'ni_Fpay' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32'
},
'ni_EAw' => {
'default' => '16',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 0
},
'ni_T2' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2'
},
'ni_V' => {
'redefine_param' => 1,
'content' => '',
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_ROUTE_NAME' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '"XY"',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_C' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => 0,
'content' => '',
'redefine_param' => 1
},
'ni_T1' => {
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
}
}
},
'clk_source0' => {
'module' => 'clk_source',
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]'
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
},
'instance' => 'ss',
'category' => 'Source',
'module_name' => 'clk_source'
},
'single_port_ram0' => {
'module' => 'single_port_ram',
'ports' => {
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'wb_to_jtag'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jtag_to_wb',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'J2WBw-1 : 0'
}
},
'parameters' => {
'ram_Dw' => {
'default' => '32',
'info' => 'Memory data width in Bits.',
'global_param' => 'Parameter',
'type' => 'Spin-button',
'content' => '8,1024,1',
'redefine_param' => 1
},
'ram_Aw' => {
'content' => '4,31,1',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button',
'default' => 14,
'info' => 'Memory address width'
}
},
'instance' => 'ram',
'category' => 'RAM',
'localparam' => {
'ram_MEM_CONTENT_FILE_NAME' => {
'type' => 'Entry',
'global_param' => 'Localparam',
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'content' => '',
'redefine_param' => 1
},
'ram_BTEw' => {
'redefine_param' => 1,
'content' => '',
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ram_JTAG_CONNECT' => {
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'redefine_param' => 1,
'default' => ' "ALTERA_JTAG_WB" ',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ram_CTIw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram_INITIAL_EN' => {
'content' => '"YES","NO"',
'redefine_param' => 1,
'type' => 'Combo-box',
'bus_M' => {
'content' => '1,256,1',
'info' => 'Number of wishbone master interface',
'type' => 'Spin-button',
'default' => ' 4',
'global_param' => 'Localparam',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'default' => '"YES"'
'redefine_param' => 1
},
'ram_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => 'ram_Dw/8',
'content' => '',
'redefine_param' => 1
},
'ram_JTAG_INDEX' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Entry',
'global_param' => 'Localparam',
'default' => 'CORE_ID',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
'
},
'ram_TAGw' => {
'info' => 'Parameter',
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ram_FPGA_VENDOR' => {
'info' => '',
'default' => '"ALTERA"',
'bus_Dw' => {
'info' => 'The wishbone Bus data width in bits.',
'content' => '8,512,8',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"'
'type' => 'Spin-button',
'default' => '32'
},
'ram_INIT_FILE_PATH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'SW_LOC',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'ram_BYTE_WR_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'Byte enable',
'default' => '"YES"'
},
'ram_BURST_MODE' => {
'redefine_param' => 1,
'content' => '"DISABLED","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. '
}
},
'module_name' => 'wb_single_port_ram'
},
'mor1kx0' => {
'instance' => 'cpu',
'category' => 'Processor',
'module_name' => 'mor1k',
'module' => 'mor1kx',
'ports' => {
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:enable[0]'
}
},
'parameters' => {
'cpu_FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'info' => '',
'default' => '"ENABLED"',
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'default' => '"ENABLED"',
'info' => '',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"'
},
'cpu_FEATURE_IMMU' => {
'info' => '',
'default' => '"ENABLED"',
'global_param' => 'Parameter',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"ENABLED"',
'info' => ''
},
'cpu_IRQ_NUM' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'cpu_FEATURE_DMMU' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'default' => '"ENABLED"',
'info' => '',
'type' => 'Combo-box',
'global_param' => 'Parameter'
},
'cpu_OPTION_OPERAND_WIDTH' => {
'bus_Aw' => {
'info' => 'The wishbone Bus address width',
'content' => '4,128,1',
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
}
}
},
'wishbone_bus0' => {
'category' => 'Bus',
'localparam' => {
'bus_M' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => 4,
'info' => 'Number of wishbone master interface',
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_CTIw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef
},
'bus_Dw' => {
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '8,512,8'
},
'bus_S' => {
'content' => '1,256,1',
'redefine_param' => 1,
'info' => 'Number of wishbone slave interface',
'default' => 5,
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'bus_TAGw' => {
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'bus_BTEw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '2 ',
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'bus_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => 'bus_Dw/8',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_Aw' => {
'content' => '4,128,1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '32',
'info' => 'The wishbone Bus address width'
}
},
'module_name' => 'wishbone_bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'jtag_uart0' => {
'instance' => 'uart',
'category' => 'Communication',
'localparam' => {
'uart_SIM_WAIT_COUNT' => {
'info' => 'This parameter is valid only in simulation.
If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.',
'default' => '1000',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '2,100000,1'
},
'uart_SIM_BUFFER_SIZE' => {
'info' => 'Internal buffer size.
This parameter is valid only in simulation.
If internal buffer overflows, the buffer content are displayed on simulator terminal.',
'default' => 1000,
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '10,10000,1'
},
'uart_FPGA_VENDOR' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => ' "ALTERA"',
'info' => 'FPGA VENDOR name. Only Altera FPGA is supported. Currently the Generic serial port is not supported. ',
'redefine_param' => 1,
'content' => ' "ALTERA"'
}
},
'module_name' => 'jtag_uart_wb',
'module' => 'jtag_uart'
}
},
'ports' => {
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => ''
},
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'single_port_ram0',
'range' => 'WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'wb_to_jtag'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => ''
},
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_name' => 'plug:enable[0]'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'ss_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0'
},
'ni_flit_out' => {
'type' => 'output',
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0'
},
'key_port_i' => {
'intfc_name' => 'IO',
'instance_name' => 'gpi0',
'range' => 'key_PORT_WIDTH-1 : 0',
'type' => 'input',
'intfc_port' => 'IO'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jtag_to_wb',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'J2WBw-1 : 0',
'instance_name' => 'single_port_ram0'
}
}
}, 'ip_gen' )
},
'mor1k_tile_kc' => {
'top' => bless( {
'instance_ids' => {
'clk_source0' => {
'module' => 'clk_source',
'ports' => {
'ss_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => ''
},
'ss_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => ''
}
},
'instance' => 'ss',
'category' => 'Source',
'module_name' => 'clk_source'
},
'single_port_ram0' => {
'instance' => 'ram',
'module_name' => 'wb_single_port_ram',
'category' => 'RAM',
'localparam' => {
'ram_TAGw' => {
'type' => 'Spin-button'
},
'bus_BTEw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'default' => '3',
'info' => 'Parameter',
'global_param' => 'Localparam',
'default' => '2 ',
'type' => 'Fixed'
},
'ram_JTAG_INDEX' => {
'content' => '',
'redefine_param' => 1,
'default' => 'CORE_ID',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'global_param' => 'Localparam',
'type' => 'Entry'
},
'ram_BYTE_WR_EN' => {
'content' => '"YES","NO"',
'redefine_param' => 1,
'info' => 'Byte enable',
'default' => '"YES"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ram_INIT_FILE_PATH' => {
'content' => '',
'redefine_param' => 1,
'default' => 'SW_LOC',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ram_CORE_NUM' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => 'CORE_ID',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_BURST_MODE' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'redefine_param' => 1,
'content' => '"DISABLED","ENABLED"'
},
'ram_BTEw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '2',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Entry',
'global_param' => 'Localparam',
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . '
},
'ram_CTIw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => 'Parameter'
},
'ram_SELw' => {
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ram_INITIAL_EN' => {
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"YES","NO"'
}
}
},
'ports' => {
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
}
},
'module' => 'single_port_ram',
'parameters' => {
'ram_JTAG_CONNECT' => {
'module' => 'wishbone_bus',
'category' => 'Bus',
'module_name' => 'wishbone_bus',
'instance' => 'bus'
},
'clk_source0' => {
'category' => 'Source',
'module' => 'clk_source',
'localparam' => {
'source_FPGA_VENDOR' => {
'default' => '"ALTERA"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'redefine_param' => 1
},
'ram_JDw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => 'ram_Dw',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ram_JAw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32'
},
'ram_WB2Jw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'redefine_param' => 1,
'content' => ''
},
'ram_JINDEXw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram_JSTATUSw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '8',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_FPGA_VENDOR' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'info' => '',
'default' => '"XILINX"',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"'
},
'ram_Aw' => {
'content' => '4,31,1',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button',
'default' => '14',
'info' => 'Memory address width'
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX"',
'info' => ''
}
},
'ports' => {
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ram_Dw' => {
'redefine_param' => 1,
'content' => '8,1024,1',
'info' => 'Memory data width in Bits.',
'default' => '32',
'type' => 'Spin-button',
'global_param' => 'Parameter'
},
'ram_J2WBw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'type' => 'Fixed',
'global_param' => 'Parameter'
'source_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => ''
}
},
'instance' => 'source',
'module_name' => 'clk_source'
},
'ni_master0' => {
'ports' => {
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0'
},
'ram_JTAG_CHAIN' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'redefine_param' => 0,
'content' => '1,2,3,4'
}
}
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'content' => '1,32,1',
'redefine_param' => 1,
'default' => ' 1',
'info' => 'output port width',
'global_param' => 'Parameter',
'type' => 'Spin-button'
}
},
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
}
},
'module' => 'gpo',
'module_name' => 'gpo',
'localparam' => {
'led_TAGw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => ' 3',
'info' => undef
},
'led_Dw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => 'led_PORT_WIDTH'
},
'led_SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => ' 4',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'led_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => ' 2',
'redefine_param' => 1,
'content' => ''
}
},
'category' => 'GPIO',
'instance' => 'led'
},
'ni_master0' => {
'module_name' => 'ni_master',
'localparam' => {
'ni_S_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_M_Aw' => {
'redefine_param' => 1,
'content' => 'Dw',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '32'
},
'ni_HDATA_PRECAPw' => {
'content' => '0,8,1',
'redefine_param' => 1,
'default' => '4',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'ni_MAX_BURST_SIZE' => {
'redefine_param' => 1,
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. '
},
'ni_MAX_TRANSACTION_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'default' => '13',
'content' => '4,32,1',
'redefine_param' => 1
},
'ni_Fw' => {
'info' => undef,
'default' => '2+ni_V+ni_Fpay',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 0
},
'ni_CRC_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '
},
'ni_Dw' => {
'default' => '32',
'info' => 'wishbone_bus data width in bits.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '32,256,8',
'redefine_param' => 1
},
'ni_TAGw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_SELw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '4',
'info' => 'Parameter'
}
},
'category' => 'NoC',
'instance' => 'ni',
'parameters' => {
'ni_T1' => {
'info' => 'Parameter',
'default' => ' 4',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_C' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => ' 4',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_T2' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => ' 4',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_EAw' => {
'redefine_param' => 0,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => undef,
'default' => '16'
},
'ni_V' => {
'info' => 'Parameter',
'default' => '4',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_ROUTE_NAME' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '"XY" ',
'info' => 'Parameter'
},
'ni_T3' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '1',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_RAw' => {
'content' => '',
'redefine_param' => 0,
'info' => undef,
'default' => '16',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_Fpay' => {
'redefine_param' => 1,
'content' => '',
'default' => ' 32',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_BYTE_EN' => {
'info' => undef,
'default' => '0',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_TOPOLOGY' => {
'default' => '"MESH"',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_B' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => ' 4',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_DEBUG_EN' => {
'default' => ' 1',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
}
},
'ports' => {
'ni_flit_in' => {
'type' => 'input',
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0'
},
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_in_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_credit_out' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'ni_chan_out' => {
'type' => 'output',
'range' => '',
'intfc_port' => 'chan_out',
'range' => 'smartflit_chanel_t',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
}
},
'module' => 'ni_master'
},
'timer0' => {
'module_name' => 'timer',
'category' => 'Timer',
'localparam' => {
'timer_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => '4',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'timer_Dw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '32',
'content' => '',
'redefine_param' => 1
},
'timer_CNTw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '32 '
},
'timer_Aw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef
},
'timer_TAGw' => {
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
}
},
'instance' => 'timer',
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
'
}
},
'module' => 'timer'
},
'wishbone_bus0' => {
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'localparam' => {
'bus_S' => {
'default' => 5,
'info' => 'Number of wishbone slave interface',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '1,256,1'
'ni_chan_in' => {
'intfc_port' => 'chan_in',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'bus_Dw' => {
'default' => '32',
'info' => 'The wishbone Bus data width in bits.',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'content' => '8,512,8',
'redefine_param' => 1
},
'bus_CTIw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '3'
},
'bus_M' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'Number of wishbone master interface',
'default' => ' 4',
'content' => '1,256,1',
'redefine_param' => 1
},
'bus_Aw' => {
'redefine_param' => 1,
'content' => '4,128,1',
'info' => 'The wishbone Bus address width',
'default' => '32',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'bus_SELw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => 'bus_Dw/8',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_BTEw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '2 ',
'info' => undef,
'redefine_param' => 1,
'content' => ''
}
},
'category' => 'Bus',
'module' => 'wishbone_bus'
},
'ProNoC_jtag_uart0' => {
'parameters' => {
'uart_JINDEXw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_JSTATUSw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '8',
'redefine_param' => 1,
'content' => ''
},
'uart_WB2Jw' => {
'redefine_param' => 1,
'content' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'uart_JDw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_JTAG_CONNECT' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"XILINX_JTAG_WB"',
'info' => undef,
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'redefine_param' => 1
},
'uart_JAw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32'
},
'uart_JTAG_CHAIN' => {
'default' => '3',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'content' => '1,2,3,4',
'redefine_param' => 0
},
'uart_BUFF_Aw' => {
'redefine_param' => 1,
'content' => '2,16,1',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'default' => '6',
'type' => 'Spin-button',
'global_param' => 'Parameter'
},
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'default' => '126-CORE_ID',
'type' => 'Entry',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'uart_J2WBw' => {
'content' => '',
'redefine_param' => 1,
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter'
}
},
'ports' => {
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
}
},
'module' => 'ProNoC_jtag_uart',
'module_name' => 'pronoc_jtag_uart',
'category' => 'Communication',
'localparam' => {
'uart_TAGw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '3'
},
'uart_Aw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '1',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'uart_Dw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter'
},
'uart_SELw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '4',
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'instance' => 'uart'
},
'mor1kx0' => {
'category' => 'Processor',
'module_name' => 'mor1k',
'instance' => 'cpu',
'parameters' => {
'cpu_IRQ_NUM' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'cpu_FEATURE_DMMU' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'default' => '"ENABLED"',
'info' => '',
'type' => 'Combo-box',
'global_param' => 'Parameter'
},
'cpu_OPTION_OPERAND_WIDTH' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Combo-box',
'info' => '',
'default' => '"ENABLED"'
},
'cpu_FEATURE_DATACACHE' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"ENABLED"',
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"ENABLED"',
'info' => ''
},
'cpu_FEATURE_IMMU' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'global_param' => 'Parameter',
'type' => 'Combo-box'
}
},
'module' => 'mor1kx',
'ports' => {
'cpu_cpu_en' => {
'type' => 'input',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => ''
}
}
}
},
'ports' => {
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'type' => 'output'
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
},
'ni_current_r_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_in_wr' => {
'range' => '',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
},
'interface' => {
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'instance_name' => 'mor1kx0',
'intfc_port' => 'enable_i',
'type' => 'input'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'uart_jtag_to_wb' => {
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0'
},
'uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_WB2Jw-1 : 0'
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => ''
},
'ni_credit_in' => {
'type' => 'input',
'intfc_port' => 'credit_in',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_current_r_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => ''
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_out',
'type' => 'output'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
}
}
}
},
'parameters' => {
'cpu_FEATURE_DMMU' => '"ENABLED"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'cpu_FEATURE_IMMU' => '"ENABLED"',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'cpu_OPTION_DCACHE_SNOOP' => '"ENABLED"',
'uart_BUFF_Aw' => '6',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'cpu_FEATURE_DATACACHE' => '"ENABLED"',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JAw' => '32',
'ram_JINDEXw' => '8',
'cpu_OPTION_OPERAND_WIDTH' => '32',
'uart_JDw' => '32',
'ram_JAw' => '32',
'ram_JDw' => 'ram_Dw',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_Dw' => '32',
'ram_Aw' => '14',
'timer_PRESCALER_WIDTH' => '8',
'led_PORT_WIDTH' => ' 1',
'cpu_IRQ_NUM' => '32',
'ram_FPGA_VENDOR' => '"XILINX"',
'cpu_FEATURE_INSTRUCTIONCACHE' => '"ENABLED"',
'uart_JTAG_CHAIN' => '3',
'ram_JSTATUSw' => '8'
}
}, 'ip_gen' ),
'tile_nums' => undef
},
'ooo' => {
'tile_nums' => undef,
'top' => bless( {
'ports' => {
'ni_master0_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_master0_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_master0_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_master0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_master0_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]'
},
'ni_master0_flit_out' => {
'type' => 'output',
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_Fw-1 : 0'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'ni_master0_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'bus_snoop_adr_o' => {
'intfc_port' => 'snoop_adr_o',
'type' => 'output',
'instance_name' => 'wishbone_bus0',
'range' => 'bus_Aw-1 : 0',
'intfc_name' => 'socket:snoop[0]'
},
'ni_master0_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'bus_snoop_en_o' => {
'intfc_name' => 'socket:snoop[0]',
'range' => '',
'instance_name' => 'wishbone_bus0',
'type' => 'output',
'intfc_port' => 'snoop_en_o'
},
'ni_master0_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ss_clk_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input'
}
},
'instance_ids' => {
'clk_source0' => {
'instance' => 'ss',
'module_name' => 'clk_source',
'category' => 'Source',
'ports' => {
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
}
},
'module' => 'clk_source',
'parameters' => {
'ss_FPGA_VENDOR' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"ALTERA"',
'info' => '',
'content' => '"ALTERA","XILINX"',
'redefine_param' => 1
}
}
},
'wishbone_bus0' => {
'category' => 'Bus',
'localparam' => {
'bus_Aw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'The wishbone Bus address width',
'default' => '32',
'redefine_param' => 1,
'content' => '4,128,1'
},
'bus_CTIw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '3',
'content' => '',
'redefine_param' => 1
},
'bus_BTEw' => {
'content' => '',
'redefine_param' => 1,
'default' => '2 ',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_TAGw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef
},
'bus_S' => {
'info' => 'Number of wishbone slave interface',
'default' => '4',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'content' => '1,256,1',
'redefine_param' => 1
},
'bus_SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => 'bus_Dw/8',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'The wishbone Bus data width in bits.',
'content' => '8,512,8',
'redefine_param' => 1
}
},
'module_name' => 'wishbone_bus',
'instance' => 'bus',
'parameters' => {
'bus_M' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => ' 4',
'info' => 'Number of wishbone master interface',
'redefine_param' => 1,
'content' => '1,256,1'
}
},
'module' => 'wishbone_bus',
'ports' => {
'bus_snoop_en_o' => {
'range' => '',
'intfc_name' => 'socket:snoop[0]',
'intfc_port' => 'snoop_en_o',
'type' => 'output'
},
'bus_snoop_adr_o' => {
'intfc_name' => 'socket:snoop[0]',
'range' => 'bus_Aw-1 : 0',
'type' => 'output',
'intfc_port' => 'snoop_adr_o'
}
}
},
'ni_master0' => {
'ports' => {
'ni_master0_credit_out' => {
'range' => 'ni_master0_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'ni_master0_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_master0_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_master0_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_master0_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_master0_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_master0_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_master0_flit_out' => {
'type' => 'output',
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_master0_Fw-1 : 0'
},
'ni_master0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_master0_irq' => {
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'intfc_port' => 'int_o',
'type' => 'output'
},
'ni_master0_flit_out_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ni_master0_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_master0_EAw-1 : 0'
}
},
'module' => 'ni_master',
'parameters' => {
'ni_master0_Fpay' => {
'default' => '32',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ni_master0_T1' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '2',
'info' => 'Parameter'
},
'ni_master0_TOPOLOGY' => {
'info' => 'Parameter',
'default' => '"MESH"',
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_e_addr',
'type' => 'input'
}
},
'instance' => 'ni',
'module_name' => 'ni_master',
'category' => 'NoC',
'parameters' => {
'ni_RAw' => {
'content' => '',
'info' => undef,
'default' => '16',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
'redefine_param' => 0,
'global_param' => 'Parameter'
},
'ni_master0_BYTE_EN' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => 0,
'redefine_param' => 1,
'content' => ''
},
'ni_master0_DEBUG_EN' => {
'info' => 'Parameter',
'default' => '0',
'ni_EAw' => {
'global_param' => 'Parameter',
'redefine_param' => 0,
'default' => '16',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_master0_ROUTE_NAME' => {
'info' => 'Parameter',
'default' => '"XY"',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_master0_C' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => 0,
'info' => 'Parameter'
},
'ni_master0_B' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '4'
},
'ni_master0_EAw' => {
'content' => '',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '16'
},
'ni_master0_RAw' => {
'content' => '',
'redefine_param' => 0,
'info' => undef,
'default' => '16',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_master0_T2' => {
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_master0_V' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '2',
'info' => 'Parameter'
},
'ni_master0_T3' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '1',
'redefine_param' => 1,
'content' => ''
}
},
'instance' => 'ni_master0',
'module_name' => 'ni_master',
'category' => 'NoC',
'localparam' => {
'ni_master0_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ni_master0_S_Aw' => {
'info' => 'Parameter',
'default' => '8',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ni_master0_M_Aw' => {
'content' => 'Dw',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_master0_HDATA_PRECAPw' => {
'default' => '0',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '0,8,1'
},
'ni_master0_CRC_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ni_master0_Fw' => {
'info' => undef,
'default' => '2+ni_master0_V+ni_master0_Fpay',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 0,
'content' => ''
},
'ni_master0_Dw' => {
'default' => '32',
'info' => 'wishbone_bus data width in bits.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '32,256,8'
},
'ni_master0_MAX_BURST_SIZE' => {
'redefine_param' => 1,
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'info' => 'Maximum burst size in words.
'info' => undef,
'content' => ''
}
},
'module' => 'ni_master',
'localparam' => {
'ni_MAX_BURST_SIZE' => {
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ni_master0_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '4',
'redefine_param' => 1,
'content' => ''
},
'ni_master0_MAX_TRANSACTION_WIDTH' => {
'redefine_param' => 1,
'content' => '4,32,1',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '13',
'info' => 'maximum packet size width in words.
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '16',
'type' => 'Combo-box'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'default' => '13',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '4,32,1',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.'
}
}
}
},
'parameters' => {
'ss_FPGA_VENDOR' => '"ALTERA"',
'bus_M' => ' 4'
},
'interface' => {
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'ni_master0_irq' => {
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'int_o'
}
}
},
'socket:snoop[0]' => {
'ports' => {
'bus_snoop_en_o' => {
'intfc_port' => 'snoop_en_o',
'type' => 'output',
'range' => '',
'instance_name' => 'wishbone_bus0'
},
'bus_snoop_adr_o' => {
'range' => 'bus_Aw-1 : 0',
'instance_name' => 'wishbone_bus0',
'type' => 'output',
'intfc_port' => 'snoop_adr_o'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_master0_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_master0_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_master0_credit_in' => {
'range' => 'ni_master0_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_master0_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_master0_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_V-1 : 0'
},
'ni_master0_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'range' => 'ni_master0_RAw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_master0_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_master0_Fw-1 : 0',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_master0_current_e_addr' => {
'range' => 'ni_master0_EAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_master0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => ''
}
}
}
}
}, 'ip_gen' )
},
'mor1k_tile' => {
'tile_nums' => [
0,
1,
2,
3
],
'top' => bless( {
'parameters' => {
'uart_JSTATUSw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'uart_JINDEXw' => '8',
'ram_JDw' => 'ram_Dw',
'ram_JAw' => '32',
'uart_JDw' => '32',
'ram_JINDEXw' => '8',
'ram_JSTATUSw' => '8',
'uart_JTAG_CHAIN' => '3',
'ram_Aw' => '14',
'ram_Dw' => '32',
'ram_JTAG_CHAIN' => '4'
},
'tiles' => {
'2' => {},
'1' => {},
'0' => {},
'3' => {}
},
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_flit_in' => {
'type' => 'input',
'intfc_port' => 'flit_in',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni_master0',
'range' => ''
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'instance_name' => 'ni_master0'
},
'ni_current_r_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0'
}
}
},
'plug:reset[0]' => {
'ports' => {
'cs_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:clk[0]' => {
'ports' => {
'cs_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_ready_sim' => {
'instance_name' => 'ProNoC_jtag_uart1',
'range' => '',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output'
},
'uart_RxD_wr_sim' => {
'range' => '',
'instance_name' => 'ProNoC_jtag_uart1',
'intfc_port' => 'RxD_wr_sim',
'type' => 'input'
},
'uart_RxD_din_sim' => {
'instance_name' => 'ProNoC_jtag_uart1',
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'type' => 'input',
'intfc_port' => 'enable_i',
'instance_name' => 'mor1kx0',
'range' => ''
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram_jtag_to_wb' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart1'
},
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart1'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0'
}
}
}
},
'ports' => {
'ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'cs_clk_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input'
},
'ni_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart1',
'type' => 'input',
'intfc_port' => 'RxD_din_sim'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'cs_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'uart_RxD_wr_sim' => {
'instance_name' => 'ProNoC_jtag_uart1',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_wr_sim',
'type' => 'input'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_name' => 'plug:enable[0]'
},
'ni_current_e_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart1',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'uart_RxD_ready_sim' => {
'range' => '',
'instance_name' => 'ProNoC_jtag_uart1',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output'
}
},
'instance_ids' => {
'mor1kx0' => {
'module' => 'mor1kx',
'ports' => {
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'instance' => 'cpu',
'category' => 'Processor',
'localparam' => {
'cpu_IRQ_NUM' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => undef
},
'cpu_OPTION_OPERAND_WIDTH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32',
'content' => '',
'redefine_param' => 1
},
'cpu_FEATURE_DMMU' => {
},
'ni_M_Aw' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => ''
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw'
},
'cpu_FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => ''
},
'cpu_OPTION_DCACHE_SNOOP' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => '',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"'
},
'cpu_FEATURE_IMMU' => {
'content' => '"NONE","ENABLED"',
'ni_S_Aw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => '',
'default' => '"ENABLED"'
'default' => '8',
'type' => 'Fixed'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => '',
'default' => '"ENABLED"'
}
},
'module_name' => 'mor1k'
},
'ProNoC_jtag_uart1' => {
'instance' => 'uart',
'module_name' => 'pronoc_jtag_uart',
'localparam' => {
'uart_Aw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '1',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_Dw' => {
'redefine_param' => 1,
'content' => '',
'default' => '32',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'uart_TAGw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '3'
},
'uart_SELw' => {
'info' => 'Parameter',
'default' => '4',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'uart_BUFF_Aw' => {
'default' => '4',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '2,16,1'
}
},
'category' => 'Communication',
'ports' => {
'uart_RxD_ready_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'RxD_ready_sim'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0'
},
'uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]'
},
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
}
},
'module' => 'ProNoC_jtag_uart',
'parameters' => {
'uart_JTAG_CHAIN' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '3',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'redefine_param' => 0,
'content' => '1,2,3,4'
},
'uart_JTAG_CONNECT' => {
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'default' => '"XILINX_JTAG_WB"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"'
},
'uart_JAw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'uart_J2WBw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'uart_JTAG_INDEX' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Entry',
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'default' => '126-CORE_ID'
},
'uart_JSTATUSw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '8'
},
'uart_JINDEXw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '8',
'content' => '',
'redefine_param' => 1
},
'uart_JDw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_WB2Jw' => {
'redefine_param' => 1,
'content' => '',
'info' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'global_param' => 'Parameter',
'type' => 'Fixed'
}
}
},
'wishbone_bus0' => {
'category' => 'Bus',
'localparam' => {
'bus_M' => {
'default' => ' 4',
'info' => 'Number of wishbone master interface',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_CTIw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'bus_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'redefine_param' => 1,
'content' => '8,512,8'
},
'bus_S' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'Number of wishbone slave interface',
'default' => 5,
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_TAGw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => undef
},
'bus_BTEw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '2 '
},
'bus_SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => 'bus_Dw/8',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_Aw' => {
'content' => '4,128,1',
'redefine_param' => 1,
'default' => '32',
'info' => 'The wishbone Bus address width',
'type' => 'Spin-button',
'global_param' => 'Localparam'
}
},
'module_name' => 'wishbone_bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'timer0' => {
'module' => 'timer',
'localparam' => {
'timer_TAGw' => {
'default' => '3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'timer_PRESCALER_WIDTH' => {
'content' => '1,32,1',
'redefine_param' => 1,
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'timer_Aw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'timer_CNTw' => {
'info' => undef,
'default' => '32 ',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'timer_Dw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '32',
'redefine_param' => 1,
'content' => ''
},
'timer_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => '4',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam'
}
},
'category' => 'Timer',
'module_name' => 'timer',
'instance' => 'timer'
},
'ni_master0' => {
'parameters' => {
'ni_C' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => 0,
'info' => 'Parameter'
},
'ni_T1' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2',
'content' => '',
'redefine_param' => 1
},
'ni_T2' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '2',
'info' => 'Parameter'
},
'ni_EAw' => {
'info' => undef,
'default' => '16',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 0
},
'ni_ROUTE_NAME' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '"XY"',
'ni_SELw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'content' => ''
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '4'
},
'ni_V' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2'
},
'ni_T3' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '1'
},
'ni_BYTE_EN' => {
'info' => undef,
'default' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ni_Fpay' => {
'default' => '32',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ni_RAw' => {
'redefine_param' => 0,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '16',
'info' => undef
},
'ni_TOPOLOGY' => {
'info' => 'Parameter',
'default' => '"MESH"',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_DEBUG_EN' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '0',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_B' => {
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
}
},
'module' => 'ni_master',
'ports' => {
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'type' => 'input'
}
},
'localparam' => {
'ni_CRC_EN' => {
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'default' => '"NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'redefine_param' => 1
},
'ni_Dw' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'wishbone_bus data width in bits.',
'default' => '32',
'redefine_param' => 1,
'content' => '32,256,8'
},
'ni_TAGw' => {
'content' => '',
'redefine_param' => 1,
'default' => '3',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '4',
'redefine_param' => 1,
'content' => ''
},
'ni_S_Aw' => {
'redefine_param' => 1,
'content' => '',
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ni_M_Aw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32',
'redefine_param' => 1,
'content' => 'Dw'
},
'ni_HDATA_PRECAPw' => {
'redefine_param' => 1,
'content' => '0,8,1',
'default' => '4',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'ni_MAX_BURST_SIZE' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1
},
'ni_MAX_TRANSACTION_WIDTH' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1',
'redefine_param' => 1
},
'ni_Fw' => {
'redefine_param' => 0,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '2+ni_V+ni_Fpay',
'info' => undef
}
},
'category' => 'NoC',
'module_name' => 'ni_master',
'instance' => 'ni'
},
'single_port_ram0' => {
'parameters' => {
'ram_JDw' => {
'global_param' => 'Parameter',
'ni_TAGw' => {
'default' => '3',
'type' => 'Fixed',
'default' => 'ram_Dw',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_JAw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
'info' => 'Parameter'
},
'ram_WB2Jw' => {
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'ni_CRC_EN' => {
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
'type' => 'Combo-box',
'default' => '"NO"'
},
'ram_JINDEXw' => {
'redefine_param' => 1,
'content' => '',
'default' => '8',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ram_JTAG_CONNECT' => {
'ni_Dw' => {
'default' => '32',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '32,256,8',
'info' => 'wishbone_bus data width in bits.'
},
'ni_HDATA_PRECAPw' => {
'type' => 'Spin-button',
'default' => '0',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'global_param' => 'Parameter',
'content' => '0,8,1',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.'
}
}
},
'mor1kx0' => {
'category' => 'Processor',
'localparam' => {
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"'
},
'cpu_OPTION_SHIFTER' => {
'info' => 'Specify the shifter implementation',
'content' => '"BARREL","SERIAL"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"BARREL"'
},
'cpu_FEATURE_DMMU' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'type' => 'Combo-box'
},
'cpu_FEATURE_MULTIPLIER' => {
'type' => 'Combo-box',
'default' => '"THREESTAGE"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'info' => 'Specify the multiplier implementation'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'default' => '"ENABLED"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'info' => ''
},
'cpu_OPTION_OPERAND_WIDTH' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32'
},
'cpu_FEATURE_IMMU' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"'
},
'cpu_FEATURE_DIVIDER' => {
'default' => '"SERIAL"',
'type' => 'Combo-box',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"XILINX_JTAG_WB"'
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"SERIAL","NONE"',
'info' => 'Specify the divider implementation'
},
'ram_Aw' => {
'default' => '14',
'info' => 'Memory address width',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'content' => '4,31,1',
'redefine_param' => 1
},
'ram_Dw' => {
'content' => '8,1024,1',
'redefine_param' => 1,
'default' => '32',
'info' => 'Memory data width in Bits.',
'type' => 'Spin-button',
'global_param' => 'Parameter'
},
'ram_JTAG_CHAIN' => {
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'global_param' => 'Parameter',
'type' => 'Combo-box',
'content' => '1,2,3,4',
'redefine_param' => 0
},
'ram_J2WBw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'info' => undef
},
'ram_JSTATUSw' => {
'content' => '',
'redefine_param' => 1,
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ram_JTAG_INDEX' => {
'content' => '',
'redefine_param' => 1,
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'type' => 'Entry',
'global_param' => 'Parameter'
}
},
'module' => 'single_port_ram',
'ports' => {
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
},
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
},
'localparam' => {
'ram_CTIw' => {
'type' => 'Fixed',
'cpu_IRQ_NUM' => {
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'default' => '3',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram_SELw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => 'ram_Dw/8',
'type' => 'Fixed',
'global_param' => 'Localparam'
'default' => '32'
},
'ram_INITIAL_EN' => {
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'redefine_param' => 1
},
'ram_BTEw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '2',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_WB_Aw' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '20',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'redefine_param' => 1,
'content' => '4,31,1'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"',
'type' => 'Entry',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'ram_CORE_NUM' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => 'CORE_ID',
'content' => '',
'redefine_param' => 1
},
'ram_BURST_MODE' => {
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1
},
'ram_TAGw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram_BYTE_WR_EN' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => 'Byte enable',
'default' => '"YES"',
'redefine_param' => 1,
'content' => '"YES","NO"'
},
'ram_FPGA_VENDOR' => {
'default' => '"XILINX"',
'info' => '',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"'
},
'ram_INIT_FILE_PATH' => {
'cpu_FEATURE_DATACACHE' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => 'SW_LOC'
'default' => '"ENABLED"',
'type' => 'Combo-box'
}
},
'category' => 'RAM',
'module_name' => 'wb_single_port_ram',
'instance' => 'ram'
},
'gpo0' => {
'ports' => {
'led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0'
}
},
'module' => 'gpo',
'instance' => 'led',
'module_name' => 'gpo',
'category' => 'GPIO',
'localparam' => {
'led_Aw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => ' 2',
'info' => undef
},
'led_SELw' => {
'info' => undef,
'default' => ' 4',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'led_Dw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'led_PORT_WIDTH',
'info' => undef
},
'led_TAGw' => {
'default' => ' 3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'led_PORT_WIDTH' => {
'default' => ' 1',
'info' => 'output port width',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '1,32,1',
'redefine_param' => 1
},
'module' => 'mor1kx',
'module_name' => 'mor1k',
'ports' => {
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'clk_source0' => {
'instance' => 'cs',
'category' => 'Source',
'localparam' => {
'cs_FPGA_VENDOR' => {
'info' => '',
'default' => '"XILINX"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX"'
}
},
'module_name' => 'clk_source',
'module' => 'clk_source',
'ports' => {
'cs_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'cs_reset_in' => {
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'type' => 'input'
}
}
}
}
}, 'ip_gen' )
},
'lm32_tile' => {
'top' => bless( {
'ports' => {
'ss_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => ''
},
'lm32_en_i' => {
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'lm320',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
},
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'range' => '',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ss_reset_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'type' => 'input'
},
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ni_current_e_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'intfc_name' => 'IO'
}
},
'instance_ids' => {
'ProNoC_jtag_uart0' => {
'instance' => 'uart',
'module_name' => 'pronoc_jtag_uart',
'category' => 'Communication',
'localparam' => {
'uart_Dw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '32',
'content' => '',
'redefine_param' => 1
},
'uart_Aw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '1'
},
'uart_TAGw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '3'
},
'uart_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '4',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
}
},
'ports' => {
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0'
},
'uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_WB2Jw-1 : 0'
}
},
'module' => 'ProNoC_jtag_uart',
'parameters' => {
'uart_JTAG_CHAIN' => {
'default' => '3',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 0,
'content' => '1,2,3,4'
},
'instance' => 'cpu'
},
'single_port_ram0' => {
'instance' => 'ram',
'module_name' => 'wb_single_port_ram',
'ports' => {
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
},
'uart_JTAG_CONNECT' => {
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
},
'category' => 'RAM',
'module' => 'single_port_ram',
'parameters' => {
'ram_JSTATUSw' => {
'content' => '',
'info' => 'Parameter',
'default' => '8',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ram_JINDEXw' => {
'default' => '8',
'type' => 'Fixed',
'redefine_param' => 1,
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"XILINX_JTAG_WB"',
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.'
'content' => '',
'info' => 'Parameter'
},
'uart_JAw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'uart_J2WBw' => {
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'default' => '126-CORE_ID',
'ram_J2WBw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Entry',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'info' => undef,
'content' => ''
},
'uart_BUFF_Aw' => {
'content' => '2,16,1',
'ram_WB2Jw' => {
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => undef
},
'ram_Dw' => {
'redefine_param' => 1,
'default' => '6',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'global_param' => 'Parameter',
'type' => 'Spin-button'
'type' => 'Spin-button',
'default' => '32',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1'
},
'uart_JSTATUSw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '8'
},
'uart_JINDEXw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '8'
},
'uart_JDw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_WB2Jw' => {
'redefine_param' => 1,
'content' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'info' => '',
'type' => 'Fixed',
'global_param' => 'Parameter'
}
}
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'localparam' => {
'bus_M' => {
'redefine_param' => 1,
'content' => '1,256,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'Number of wishbone master interface',
'default' => ' 4'
},
'bus_CTIw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'bus_Dw' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'content' => '8,512,8',
'redefine_param' => 1
},
'bus_S' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => 5,
'info' => 'Number of wishbone slave interface',
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_BTEw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '2 '
},
'bus_TAGw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '3'
},
'bus_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => 'bus_Dw/8',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'bus_Aw' => {
'default' => '32',
'info' => 'The wishbone Bus address width',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '4,128,1',
'redefine_param' => 1
}
}
},
'lm320' => {
'instance' => 'lm32',
'module_name' => 'lm32',
'category' => 'Processor',
'localparam' => {
'lm32_CFG_PL_BARREL_SHIFT' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '"ENABLED"',
'redefine_param' => 1,
'content' => '"ENABLED","DISABLED"'
},
'lm32_INTR_NUM' => {
'content' => '',
'redefine_param' => 1,
'default' => '32',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'lm32_CFG_MC_DIVIDE' => {
'info' => undef,
'default' => '"DISABLED"',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '"ENABLED","DISABLED"',
'redefine_param' => 1
},
'lm32_CFG_SIGN_EXTEND' => {
'redefine_param' => 1,
'content' => '"ENABLED","DISABLED"',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '"ENABLED"'
},
'lm32_CFG_PL_MULTIPLY' => {
'content' => '"ENABLED","DISABLED"',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '"ENABLED"'
}
},
'ports' => {
'lm32_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:enable[0]'
}
},
'module' => 'lm32'
},
'single_port_ram0' => {
'module' => 'single_port_ram',
'ports' => {
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
}
},
'parameters' => {
'ram_FPGA_VENDOR' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'info' => '',
'default' => '"XILINX"',
'content' => '"ALTERA","XILINX","GENERIC"',
'redefine_param' => 1
},
'ram_JTAG_INDEX' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Entry',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
'ram_JTAG_INDEX' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => 'CORE_ID',
'type' => 'Entry',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
6961,949 → 790,129
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID'
},
'ram_JSTATUSw' => {
'default' => '8',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ram_J2WBw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1'
},
'ram_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'redefine_param' => 0,
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'content' => ''
},
'ram_JAw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'ram_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'info' => 'Memory data width in Bits.',
'default' => '32',
'redefine_param' => 1,
'content' => '8,1024,1'
},
'ram_Aw' => {
'default' => '14',
'info' => 'Memory address width',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '4,31,1'
},
'ram_JTAG_CONNECT' => {
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"XILINX_JTAG_WB"',
'global_param' => 'Parameter',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"'
},
'ram_JINDEXw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram_JAw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '32'
},
'ram_WB2Jw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ram_JDw' => {
'default' => 'ram_Dw',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
}
},
'instance' => 'ram',
'category' => 'RAM',
'localparam' => {
'ram_BURST_MODE' => {
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"DISABLED","ENABLED"'
'default' => '32',
'type' => 'Fixed'
},
'ram_CORE_NUM' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => 'CORE_ID',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_INIT_FILE_PATH' => {
'default' => 'SW_LOC',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'ram_BYTE_WR_EN' => {
'ram_JTAG_CONNECT' => {
'type' => 'Combo-box',
'default' => '"ALTERA_JTAG_WB"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
},
'ram_JDw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"YES","NO"',
'info' => 'Byte enable',
'default' => '"YES"',
'global_param' => 'Localparam',
'type' => 'Combo-box'
'default' => 'ram_Dw',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
},
'ram_TAGw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '3',
'redefine_param' => 1,
'content' => ''
},
'ram_INITIAL_EN' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'redefine_param' => 1,
'content' => '"YES","NO"'
},
'ram_SELw' => {
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'ram_CTIw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'type' => 'Entry',
'global_param' => 'Localparam',
'ram_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 0
}
},
'localparam' => {
'ram_CTIw' => {
'content' => '',
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_TAGw' => {
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ram_SELw' => {
'default' => 'ram_Dw/8',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ram_FPGA_VENDOR' => {
'type' => 'Combo-box',
'default' => '"ALTERA"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"',
'info' => ''
},
'ram_BYTE_WR_EN' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"YES"',
'type' => 'Combo-box',
'info' => 'Byte enable',
'content' => '"YES","NO"'
},
'ram_CORE_NUM' => {
'default' => 'CORE_ID',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ram_INIT_FILE_PATH' => {
'content' => '',
'info' => undef,
'default' => 'SW_LOC',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
'global_param' => 'Localparam'
},
'ram_BTEw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '2',
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'module_name' => 'wb_single_port_ram'
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'redefine_param' => 1,
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => ' 1',
'info' => 'output port width'
}
},
'module' => 'gpo',
'ports' => {
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
}
},
'localparam' => {
'led_Dw' => {
'default' => 'led_PORT_WIDTH',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'led_SELw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => ' 4',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'led_Aw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => ' 2',
'info' => undef
},
'led_TAGw' => {
'info' => undef,
'default' => ' 3',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
}
},
'category' => 'GPIO',
'module_name' => 'gpo',
'instance' => 'led'
},
'clk_source0' => {
'instance' => 'ss',
'module_name' => 'clk_source',
'category' => 'Source',
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
}
},
'module' => 'clk_source'
},
'ni_master0' => {
'ports' => {
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_in' => {
'type' => 'input',
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0'
},
'ni_flit_out_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0'
}
},
'module' => 'ni_master',
'parameters' => {
'ni_DEBUG_EN' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '0',
'info' => 'Parameter'
},
'ni_B' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '4'
},
'ni_TOPOLOGY' => {
'redefine_param' => 1,
'content' => '',
'default' => '"MESH"',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_RAw' => {
'redefine_param' => 0,
'content' => '',
'default' => '16',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_Fpay' => {
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_BYTE_EN' => {
'default' => 0,
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_T3' => {
'default' => '1',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_ROUTE_NAME' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '"XY"',
'content' => '',
'redefine_param' => 1
},
'ni_V' => {
'content' => '',
'redefine_param' => 1,
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_EAw' => {
'content' => '',
'redefine_param' => 0,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '16',
'info' => undef
},
'ni_T2' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '2',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_C' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => 0,
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_T1' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2'
}
},
'instance' => 'ni',
'module_name' => 'ni_master',
'category' => 'NoC',
'localparam' => {
'ni_MAX_BURST_SIZE' => {
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1
},
'ni_S_Aw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '8'
},
'ni_M_Aw' => {
'redefine_param' => 1,
'content' => 'Dw',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter'
},
'ni_HDATA_PRECAPw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '4',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'content' => '0,8,1',
'redefine_param' => 1
},
'ni_Fw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '2+ni_V+ni_Fpay',
'info' => undef,
'content' => '',
'redefine_param' => 0
},
'ni_MAX_TRANSACTION_WIDTH' => {
'content' => '4,32,1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.'
},
'ni_CRC_EN' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'redefine_param' => 1,
'content' => '"YES","NO"'
},
'ni_SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => '4',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_TAGw' => {
'redefine_param' => 1,
'content' => '',
'default' => '3',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_Dw' => {
'info' => 'wishbone_bus data width in bits.',
'default' => '32',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '32,256,8',
'redefine_param' => 1
}
}
},
'timer0' => {
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'content' => '1,32,1',
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'global_param' => 'Parameter',
'type' => 'Spin-button'
}
},
'module' => 'timer',
'localparam' => {
'timer_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '4',
'content' => '',
'redefine_param' => 1
},
'timer_Dw' => {
'default' => '32',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'timer_Aw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'timer_CNTw' => {
'default' => '32 ',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'timer_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'category' => 'Timer',
'module_name' => 'timer',
'instance' => 'timer'
}
},
'parameters' => {
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JTAG_INDEX' => '126-CORE_ID',
'uart_BUFF_Aw' => '6',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'uart_JINDEXw' => '8',
'ram_JINDEXw' => '8',
'uart_JDw' => '32',
'ram_JAw' => '32',
'ram_JDw' => 'ram_Dw',
'ram_FPGA_VENDOR' => '"XILINX"',
'uart_JTAG_CHAIN' => '3',
'ram_JSTATUSw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_Dw' => '32',
'ram_Aw' => '14',
'timer_PRESCALER_WIDTH' => '8',
'led_PORT_WIDTH' => ' 1'
},
'interface' => {
'IO' => {
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_wb_to_jtag' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0'
}
}
},
'plug:enable[0]' => {
'ports' => {
'lm32_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'instance_name' => 'lm320'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out',
'type' => 'output'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_current_e_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
}
}
}
}
}, 'ip_gen' ),
'tile_nums' => undef
},
'mor1k_atera' => {
'top' => bless( {
'interface' => {
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => 'uart_J2WBw-1 : 0'
'ram_INITIAL_EN' => {
'default' => '"YES"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"YES","NO"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram_WB_Aw' => {
'content' => '4,31,1',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'default' => '20',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_Aw' => {
'content' => '4,31,1',
'info' => 'Memory address width',
'type' => 'Spin-button',
'default' => '14',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'uart_wb_to_jtag' => {
'instance_name' => 'ProNoC_jtag_uart1',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'ram_jtag_to_wb' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'instance_name' => 'mor1kx0',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'type' => 'output',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => ''
},
'uart_RxD_din_sim' => {
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart1'
},
'uart_RxD_wr_sim' => {
'instance_name' => 'ProNoC_jtag_uart1',
'range' => '',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim'
}
}
},
'plug:clk[0]' => {
'ports' => {
'cs_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => ''
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
}
}
},
'plug:reset[0]' => {
'ports' => {
'cs_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => ''
}
}
}
},
'parameters' => {
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'uart_JAw' => '32',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_Aw' => '14',
'ram_JTAG_CHAIN' => '4',
'ram_Dw' => '32',
'ram_JSTATUSw' => '8',
'uart_JTAG_CHAIN' => '3',
'ram_JAw' => '32',
'ram_JDw' => 'ram_Dw',
'ram_JINDEXw' => '8',
'uart_JDw' => '32',
'uart_JINDEXw' => '8'
},
'instance_ids' => {
'clk_source0' => {
'ports' => {
'cs_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'cs_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
},
'module' => 'clk_source',
'module_name' => 'clk_source',
'localparam' => {
'cs_FPGA_VENDOR' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => '',
'default' => '"ALTERA"',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX"'
}
},
'category' => 'Source',
'instance' => 'cs'
},
'single_port_ram0' => {
'localparam' => {
'ram_BTEw' => {
'content' => '',
'redefine_param' => 1,
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ram_WB_Aw' => {
'redefine_param' => 1,
'content' => '4,31,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '20',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). '
},
'ram_MEM_CONTENT_FILE_NAME' => {
'redefine_param' => 1,
'content' => '',
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
'ram_MEM_CONTENT_FILE_NAME' => {
'content' => '',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
7914,1590 → 923,998
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'global_param' => 'Localparam',
'type' => 'Entry'
},
'ram_SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ram_INITIAL_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'default' => '"YES"'
},
'ram_CTIw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '3',
'redefine_param' => 1,
'content' => ''
},
'ram_BYTE_WR_EN' => {
'default' => '"YES"',
'info' => 'Byte enable',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"YES","NO"'
},
'ram_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => '',
'default' => '"ALTERA"',
'content' => '"ALTERA","XILINX","GENERIC"',
'redefine_param' => 1
},
'ram_INIT_FILE_PATH' => {
'default' => 'SW_LOC',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'ram_TAGw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '3',
'content' => '',
'redefine_param' => 1
},
'ram_BURST_MODE' => {
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1,
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ram_CORE_NUM' => {
'redefine_param' => 1,
'content' => '',
'default' => 'CORE_ID',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
}
},
'category' => 'RAM',
'module_name' => 'wb_single_port_ram',
'instance' => 'ram',
'parameters' => {
'ram_JINDEXw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter'
},
'ram_JDw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => 'ram_Dw',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ram_JAw' => {
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ram_WB2Jw' => {
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ram_JTAG_CONNECT' => {
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'redefine_param' => 1,
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"ALTERA_JTAG_WB"',
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'ram_Dw' => {
'global_param' => 'Parameter',
'type' => 'Spin-button',
'default' => '32',
'info' => 'Memory data width in Bits.',
'redefine_param' => 1,
'content' => '8,1024,1'
},
'ram_J2WBw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1'
},
'ram_JTAG_CHAIN' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'redefine_param' => 0,
'content' => '1,2,3,4'
},
'ram_Aw' => {
'default' => '14',
'info' => 'Memory address width',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'content' => '4,31,1',
'redefine_param' => 1
},
'ram_JSTATUSw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '8',
'content' => '',
'redefine_param' => 1
},
'ram_JTAG_INDEX' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Entry',
'global_param' => 'Parameter',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID'
}
},
'module' => 'single_port_ram',
'ports' => {
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
}
}
},
'gpo0' => {
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
}
},
'module' => 'gpo',
'instance' => 'led',
'module_name' => 'gpo',
'category' => 'GPIO',
'localparam' => {
'led_Dw' => {
'info' => undef,
'default' => 'led_PORT_WIDTH',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'led_Aw' => {
'redefine_param' => 1,
'content' => '',
'default' => ' 2',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'led_SELw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => ' 4'
},
'led_PORT_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'output port width',
'default' => ' 1',
'redefine_param' => 1,
'content' => '1,32,1'
},
'led_TAGw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => ' 3'
}
}
},
'ni_master0' => {
'ports' => {
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_credit_in' => {
'type' => 'input',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out' => {
'type' => 'output',
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
}
},
'module' => 'ni_master',
'parameters' => {
'ni_TOPOLOGY' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '"MESH"',
'content' => '',
'redefine_param' => 1
},
'ni_DEBUG_EN' => {
'default' => '0',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_B' => {
'info' => 'Parameter',
'default' => '4',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_T3' => {
'info' => 'Parameter',
'default' => '1',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_Fpay' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_RAw' => {
'content' => '',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '16',
'info' => undef
},
'ni_BYTE_EN' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '1',
'info' => undef
},
'ni_EAw' => {
'content' => '',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '16'
},
'ni_T2' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '3',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_ROUTE_NAME' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '"XY"',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_V' => {
'info' => 'Parameter',
'default' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_C' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => 0,
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_T1' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '2',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
}
},
'instance' => 'ni',
'module_name' => 'ni_master',
'category' => 'NoC',
'localparam' => {
'ni_Dw' => {
'content' => '32,256,8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'wishbone_bus data width in bits.',
'default' => '32'
},
'ni_TAGw' => {
'redefine_param' => 1,
'content' => '',
'default' => '3',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ni_CRC_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '
},
'ni_MAX_TRANSACTION_WIDTH' => {
'redefine_param' => 1,
'content' => '4,32,1',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'default' => '13',
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'ni_Fw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '2+ni_V+ni_Fpay',
'content' => '',
'redefine_param' => 0
},
'ni_HDATA_PRECAPw' => {
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'default' => '4',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '0,8,1'
},
'ni_M_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '32',
'content' => 'Dw',
'redefine_param' => 1
},
'ni_S_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_MAX_BURST_SIZE' => {
'redefine_param' => 1,
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'global_param' => 'Localparam',
'type' => 'Combo-box'
}
}
},
'timer0' => {
'instance' => 'timer',
'category' => 'Timer',
'localparam' => {
'timer_SELw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => '4',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'timer_Dw' => {
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'timer_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '3',
'redefine_param' => 1,
'content' => ''
},
'timer_CNTw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32 ',
'info' => undef
},
'timer_PRESCALER_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'redefine_param' => 1,
'content' => '1,32,1'
},
'timer_TAGw' => {
'content' => '',
'redefine_param' => 1,
'default' => '3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'module_name' => 'timer',
'module' => 'timer'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'localparam' => {
'bus_Aw' => {
'redefine_param' => 1,
'content' => '4,128,1',
'default' => '32',
'info' => 'The wishbone Bus address width',
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'bus_BTEw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '2 ',
'redefine_param' => 1,
'content' => ''
},
'bus_TAGw' => {
'default' => '3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'bus_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => 'bus_Dw/8',
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'bus_M' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => ' 4',
'info' => 'Number of wishbone master interface',
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_CTIw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '3'
},
'bus_Dw' => {
'redefine_param' => 1,
'content' => '8,512,8',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'bus_S' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => 5,
'info' => 'Number of wishbone slave interface',
'content' => '1,256,1',
'redefine_param' => 1
}
},
'category' => 'Bus',
'module_name' => 'wishbone_bus',
'instance' => 'bus'
},
'ProNoC_jtag_uart1' => {
'instance' => 'uart',
'category' => 'Communication',
'localparam' => {
'uart_BUFF_Aw' => {
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'default' => '4',
'type' => 'Spin-button',
'type' => 'Entry',
'default' => '"ram0"',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_BTEw' => {
'default' => '2',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '2,16,1',
'redefine_param' => 1
},
'uart_SELw' => {
'info' => 'Parameter',
'default' => '4',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'uart_Dw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32',
'content' => '',
'redefine_param' => 1
},
'uart_TAGw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '3',
'content' => '',
'redefine_param' => 1
},
'uart_Aw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '1',
'type' => 'Fixed',
'global_param' => 'Localparam'
}
},
'module_name' => 'pronoc_jtag_uart',
'module' => 'ProNoC_jtag_uart',
'ports' => {
'uart_RxD_wr_sim' => {
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'type' => 'input',
'intfc_port' => 'RxD_din_sim'
},
'uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
},
'uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
}
},
'parameters' => {
'uart_JINDEXw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'redefine_param' => 1
'info' => 'Parameter'
},
'uart_JSTATUSw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '8',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'uart_WB2Jw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'info' => ''
},
'uart_JDw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32',
'content' => '',
'redefine_param' => 1
},
'uart_JTAG_CONNECT' => {
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'redefine_param' => 1,
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box',
'global_param' => 'Parameter'
},
'uart_JAw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'uart_JTAG_CHAIN' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '3',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'redefine_param' => 0,
'content' => '1,2,3,4'
},
'uart_J2WBw' => {
'redefine_param' => 1,
'content' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'uart_JTAG_INDEX' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Entry',
'global_param' => 'Parameter',
'default' => '126-CORE_ID',
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.'
}
}
},
'mor1kx0' => {
'module' => 'mor1kx',
'ports' => {
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'instance' => 'cpu',
'localparam' => {
'cpu_FEATURE_DMMU' => {
'default' => '"ENABLED"',
'info' => '',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1
},
'cpu_OPTION_OPERAND_WIDTH' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'Parameter'
},
'cpu_IRQ_NUM' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '32',
'redefine_param' => 1,
'content' => ''
},
'cpu_FEATURE_IMMU' => {
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'content' => '"NONE","ENABLED"',
'ram_BURST_MODE' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'info' => ''
},
'cpu_FEATURE_DATACACHE' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'default' => '"ENABLED"',
'info' => '',
'global_param' => 'Localparam',
'type' => 'Combo-box'
}
},
'category' => 'Processor',
'module_name' => 'mor1k'
}
},
'ports' => {
'ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => ''
},
'cs_clk_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input'
},
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0'
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]'
},
'ni_flit_out' => {
'type' => 'output',
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'cs_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0'
},
'uart_RxD_din_sim' => {
'type' => 'input',
'intfc_port' => 'RxD_din_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart1'
},
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0'
},
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'instance_name' => 'mor1kx0',
'type' => 'input',
'intfc_port' => 'enable_i'
},
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => 'uart_J2WBw-1 : 0'
},
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'instance_name' => 'ProNoC_jtag_uart1'
},
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0'
}
}
}, 'ip_gen' )
}
},
'setting' => {
'show_tile_setting' => 1,
'soc_path' => 'lib/soc',
'show_noc_setting' => 1,
'show_adv_setting' => 0
},
'current_tile_param' => undef,
'noc_indept_param' => {},
'file_name' => undef,
'verilator' => {
'libs' => {
'Vtile0' => 'tile_0.v',
'Vtile1' => 'tile_1.v',
'Vnoc' => 'noc_connection.sv',
'Vtile3' => 'tile_3.v',
'Vrouter1' => 'router_verilator_p5.v',
'Vtile2' => 'tile_2.v'
}
},
'RAM0' => {
'end' => 32768,
'start' => 22937
},
'JTAG' => {
'M_CHAIN' => 4
},
'RAM1' => {
'start' => 49152,
'end' => 65536
},
'top_ip' => bless( {
'instance_ids' => {
'IO' => {
'ports' => {
'reset' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'clk' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]'
},
'processors_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'T1' => {
'ports' => {
'T1_ram_wb_to_jtag' => {
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'content' => '"DISABLED","ENABLED"'
}
}
}
},
'tiles' => {
'0' => {
'parameters' => {
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_JINDEXw' => '8',
'ram_JSTATUSw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_JTAG_CHAIN' => '3',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_JAw' => '32',
'uart_JAw' => '32',
'ram_Dw' => '32'
}
},
'1' => {
'parameters' => {
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Aw' => '14',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'ram_JINDEXw' => '8',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JAw' => '32',
'ram_Dw' => '32',
'uart_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_CHAIN' => '3',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1'
}
},
'2' => {
'parameters' => {
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_Dw' => '32',
'uart_JAw' => '32',
'uart_JTAG_CHAIN' => '3',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JINDEXw' => '8',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'ram_Aw' => '14',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JSTATUSw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"'
}
},
'3' => {
'parameters' => {
'ram_Dw' => '32',
'ram_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JDw' => 'ram_Dw',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'uart_JTAG_CHAIN' => '3',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Aw' => '14',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JINDEXw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'uart_JSTATUSw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1'
}
}
},
'ports' => {
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_WB2Jw-1 : 0',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T1_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_uart_WB2Jw-1 : 0'
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'source_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'T1_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T1_led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => ' 1-1 : 0',
'intfc_name' => 'IO'
},
'T1_uart_jtag_to_wb' => {
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'type' => 'output',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_uart_J2WBw-1 : 0'
}
}
},
'T2' => {
'ports' => {
'T2_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T2_uart_jtag_to_wb' => {
'range' => 'T2_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'uart_RxD_wr_sim' => {
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim'
},
'T2_led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => ' 1-1 : 0'
}
}
},
'T3' => {
'ports' => {
'T3_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_ram_J2WBw-1 : 0'
},
'T3_led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => ' 1-1 : 0',
'intfc_name' => 'IO'
'ni_chan_out' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'chan_out',
'range' => 'smartflit_chanel_t',
'intfc_name' => 'socket:ni[0]'
},
'ni_chan_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t',
'type' => 'input',
'intfc_port' => 'chan_in',
'instance_name' => 'ni_master0'
},
'T3_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T3_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T3_uart_wb_to_jtag' => {
'range' => 'T3_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output'
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T3_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_J2WBw-1 : 0'
}
}
},
'T0' => {
'ports' => {
'T0_ram_wb_to_jtag' => {
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T0_led_port_o' => {
'range' => ' 1-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'T0_ram_jtag_to_wb' => {
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_J2WBw-1 : 0'
'range' => 'ram_J2WBw-1 : 0'
},
'T0_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T0_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
}
}
},
'ports' => {
'T3_ram_jtag_to_wb' => {
'range' => 'T3_ram_J2WBw-1 : 0',
'instance_name' => 'T3',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T0_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T0',
'range' => 'T0_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T0_led_port_o' => {
'range' => ' 1-1 : 0',
'instance_name' => 'T0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'T1_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T1',
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T2',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T3_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_WB2Jw-1 : 0',
'instance_name' => 'T3'
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'intfc_port' => 'enable_i',
'instance_name' => 'mor1kx0',
'type' => 'input'
}
}
}, 'ip_gen' )
}
},
'MEM1' => {
'percent' => '75',
'width' => '14'
},
'SOURCE_SET' => {
'clk_number' => 1,
'reset_number' => 1,
'reset_0_name' => 'reset',
'REDEFINE_TOP' => 0,
'clk_0_name' => 'clk',
'SOC' => bless( {
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'T2_led_port_o' => {
'instance_name' => 'T2',
'range' => ' 1-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'T2_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'range' => 'T2_uart_WB2Jw-1 : 0'
},
'T0_uart_wb_to_jtag' => {
'instance_name' => 'T0',
'range' => 'T0_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T1_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T1',
'range' => 'T1_uart_J2WBw-1 : 0'
},
'T3_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T3_ram_WB2Jw-1 : 0',
'instance_name' => 'T3',
'intfc_name' => 'socket:jtag_to_wb[0]'
'hdl_files' => undef,
'instances' => {
'TOP' => {
'parameters_order' => [],
'sockets' => {},
'category' => 'TOP',
'description_pdf' => undef,
'module' => 'TOP',
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'reset',
'connect_socket' => undef,
'connect_socket_num' => undef
}
}
},
'clk' => {
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'IO',
'connect_socket' => undef,
'connect_socket_num' => undef
}
},
'value' => 1
}
},
'module_name' => 'TOP',
'instance_name' => 'TOP'
}
},
'T0_ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'instance_name' => 'T0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T2_uart_jtag_to_wb' => {
'instance_name' => 'T2',
'range' => 'T2_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
'instance_order' => [
'TOP'
],
'SOURCE_SET' => {
'IP' => bless( {
'file_name' => undef,
'hdl_files_ticked' => [],
'parameters_order' => [],
'GUI_REMOVE_SET' => 'DISABLE',
'hdl_files' => [],
'plugs' => {
'reset' => {
'type' => 'num',
'1' => {},
'value' => 1,
'0' => {
'name' => 'reset'
}
},
'clk' => {
'type' => 'num',
'value' => 1,
'1' => {},
'0' => {
'name' => 'clk'
}
}
},
'module_name' => 'TOP',
'ports' => {
'clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => undef,
'type' => 'input',
'intfc_port' => 'clk_i'
},
'reset' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => undef
}
},
'ip_name' => 'TOP',
'ports_order' => [],
'category' => 'TOP'
}, 'ip_gen' )
},
'T1_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_J2WBw-1 : 0',
'instance_name' => 'T1',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'processors_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'IO',
'range' => '',
'intfc_name' => 'plug:enable[0]'
},
'T2_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'range' => 'T2_ram_J2WBw-1 : 0'
},
'T0_uart_jtag_to_wb' => {
'instance_name' => 'T0',
'range' => 'T0_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'clk' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'IO'
},
'T3_led_port_o' => {
'range' => ' 1-1 : 0',
'instance_name' => 'T3',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'T1_uart_wb_to_jtag' => {
'range' => 'T1_uart_WB2Jw-1 : 0',
'instance_name' => 'T1',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'reset' => {
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'IO',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'T3_uart_jtag_to_wb' => {
'range' => 'T3_uart_J2WBw-1 : 0',
'instance_name' => 'T3',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T1_led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => ' 1-1 : 0',
'instance_name' => 'T1'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'processors_en' => {
'type' => 'input',
'intfc_port' => 'enable_i',
'range' => '',
'instance_name' => 'IO'
}
}
},
'plug:clk[0]' => {
'TOP' => {
'version' => 0
},
'soc_name' => {
'TOP' => undef
},
'device_win_adj' => {
'va' => '0',
'ha' => '0'
},
'modules' => {}
}, 'soc' )
},
'tile' => {
'2' => {},
'0' => {},
'1' => {},
'3' => {}
},
'compile_pin_pos' => {
'TOP_reset' => [
0,
0
],
'jtag_debug_reset_in' => [
0,
0
],
'TOP_clk' => [
4,
0
],
'processors_en' => [
6,
0
]
},
'current_tile_param' => undef,
'gen_tiles_adj' => {
'ha' => '0',
'va' => '0'
},
'parameters_order' => {
'noc_param' => [
'TOPOLOGY',
'T1',
'T2',
'T3',
'V',
'B',
'Fpay',
'ROUTE_NAME',
'MIN_PCK_SIZE',
'BYTE_EN',
'SSA_EN',
'CONGESTION_INDEX',
'ESCAP_VC_MASK',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'SWA_ARBITER_TYPE',
'WEIGHTw',
'AVC_ATOMIC_EN',
'LB',
'PCK_TYPE',
'CAST_TYPE',
'SMART_MAX',
'SELF_LOOP_EN'
],
'SOURCE_SET' => [
'clk_number',
'clk_0_name',
'reset_number',
'reset_0_name'
],
'noc_type' => [
'ROUTER_TYPE'
],
'compile' => [
'cpu_num'
],
'SOURCE_SET_CONNECT' => [
'NoC_clk',
'T0_ss_clk_in',
'T1_ss_clk_in',
'T2_ss_clk_in',
'T3_ss_clk_in',
'NoC_reset',
'T0_ss_reset_in',
'T1_ss_reset_in',
'T2_ss_reset_in',
'T3_ss_reset_in',
'T0_cs_clk_in',
'T1_cs_clk_in',
'T2_cs_clk_in',
'T3_cs_clk_in',
'T0_cs_reset_in',
'T1_cs_reset_in',
'T2_cs_reset_in',
'T3_cs_reset_in'
]
},
'noc_indept_param' => {},
'file_name' => undef,
'noc_param' => {
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'T3' => '1',
'ROUTE_NAME' => '"XY"',
'C' => 0,
'V' => '2',
'SSA_EN' => '"NO"',
'CONGESTION_INDEX' => 3,
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'WEIGHTw' => '4',
'DEBUG_EN' => '0',
'SMART_MAX' => '0',
'SWA_ARBITER_TYPE' => '"RRA"',
'FIRST_ARBITER_EXT_P_EN' => 1,
'SELF_LOOP_EN' => '"NO"',
'Fpay' => '32',
'T1' => '2',
'MUX_TYPE' => '"BINARY"',
'PCK_TYPE' => '"MULTI_FLIT"',
'BYTE_EN' => '1',
'AVC_ATOMIC_EN' => 0,
'MIN_PCK_SIZE' => '2',
'ESCAP_VC_MASK' => '2\'b01',
'T2' => '2',
'B' => '4',
'CAST_TYPE' => '"UNICAST"',
'TOPOLOGY' => '"MESH"',
'LB' => '4'
},
'compile_pin' => {
'TOP_reset' => '*GND',
'jtag_debug_reset_in' => '*GND',
'TOP_clk' => 'FPGA_CLK1_50',
'processors_en' => 'KEY'
},
'ROM2' => {
'start' => 0,
'end' => 49152
},
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
},
'SOURCE_SET_CONNECT' => {
'T2_cs_clk_in' => 'clk',
'T1_cs_clk_in' => 'clk',
'T0_cs_clk_in' => 'clk',
'T0_ss_clk_in' => 'clk0',
'T3_ss_clk_in' => 'clk0',
'T2_ss_reset_in' => 'reset0',
'T2_cs_reset_in' => 'reset',
'T0_ss_reset_in' => 'reset0',
'T1_ss_clk_in' => 'clk0',
'T3_cs_clk_in' => 'clk',
'T3_cs_reset_in' => 'reset',
'T1_ss_reset_in' => 'reset0',
'T2_ss_clk_in' => 'clk0',
'T0_cs_reset_in' => 'reset',
'NoC_clk' => 'clk',
'T1_cs_reset_in' => 'reset',
'T3_ss_reset_in' => 'reset0',
'NoC_reset' => 'reset'
},
'compile_pin_range_hsb' => {},
'setting' => {
'show_adv_setting' => 0,
'show_noc_setting' => 1,
'show_tile_setting' => 1,
'soc_path' => 'lib/soc'
},
'RAM2' => {
'start' => 49152,
'end' => 65536
},
'top_ip' => bless( {
'ports' => {
'T2_uart_wb_to_jtag' => {
'range' => 'T2_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T1_uart_jtag_to_wb' => {
'range' => 'T1_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'instance_name' => 'T1',
'intfc_port' => 'jwb_i'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i',
'instance_name' => 'IO',
'type' => 'input'
},
'T3_ram_wb_to_jtag' => {
'instance_name' => 'T3',
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_ram_WB2Jw-1 : 0'
},
'T3_ram_jtag_to_wb' => {
'range' => 'T3_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T3',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T1_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_uart_WB2Jw-1 : 0',
'type' => 'output',
'instance_name' => 'T1',
'intfc_port' => 'jwb_o'
},
'T3_uart_wb_to_jtag' => {
'instance_name' => 'T3',
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_WB2Jw-1 : 0'
},
'processors_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'instance_name' => 'IO',
'intfc_port' => 'enable_i',
'type' => 'input'
},
'reset' => {
'type' => 'input',
'instance_name' => 'IO',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => ''
},
'T0_ram_jtag_to_wb' => {
'range' => 'T0_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'instance_name' => 'T0',
'type' => 'input'
},
'T0_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_J2WBw-1 : 0',
'instance_name' => 'T0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T1_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_J2WBw-1 : 0',
'type' => 'input',
'instance_name' => 'T1',
'intfc_port' => 'jwb_i'
},
'T3_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'T3',
'type' => 'input'
},
'T2_uart_jtag_to_wb' => {
'instance_name' => 'T2',
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_J2WBw-1 : 0'
},
'T2_ram_jtag_to_wb' => {
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T1_ram_wb_to_jtag' => {
'instance_name' => 'T1',
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T0_ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'instance_name' => 'T0',
'type' => 'output'
},
'T0_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_WB2Jw-1 : 0',
'type' => 'output',
'instance_name' => 'T0',
'intfc_port' => 'jwb_o'
},
'T2_ram_wb_to_jtag' => {
'type' => 'output',
'instance_name' => 'T2',
'intfc_port' => 'jwb_o',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
},
'interface' => {
'plug:clk[0]' => {
'ports' => {
'clk' => {
'intfc_port' => 'clk_i',
'instance_name' => 'IO',
'type' => 'input',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'reset' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'IO'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'T0_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'instance_name' => 'T0',
'type' => 'input',
'range' => 'T0_uart_J2WBw-1 : 0'
},
'T0_ram_jtag_to_wb' => {
'range' => 'T0_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'T0'
},
'T3_uart_jtag_to_wb' => {
'range' => 'T3_uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'T3'
},
'T2_uart_jtag_to_wb' => {
'range' => 'T2_uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T2'
},
'T1_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T1',
'range' => 'T1_ram_J2WBw-1 : 0'
},
'T2_ram_jtag_to_wb' => {
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'T2',
'type' => 'input'
},
'T1_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'instance_name' => 'T1',
'type' => 'output',
'range' => 'T1_ram_WB2Jw-1 : 0'
},
'T0_ram_wb_to_jtag' => {
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T0'
},
'T0_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T0',
'range' => 'T0_uart_WB2Jw-1 : 0'
},
'T2_ram_wb_to_jtag' => {
'range' => 'T2_ram_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T2'
},
'T2_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T2',
'range' => 'T2_uart_WB2Jw-1 : 0'
},
'T1_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T1',
'range' => 'T1_uart_J2WBw-1 : 0'
},
'T3_ram_wb_to_jtag' => {
'range' => 'T3_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'instance_name' => 'T3',
'type' => 'output'
},
'T3_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T3',
'range' => 'T3_uart_WB2Jw-1 : 0'
},
'T1_uart_wb_to_jtag' => {
'instance_name' => 'T1',
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T1_uart_WB2Jw-1 : 0'
},
'T3_ram_jtag_to_wb' => {
'range' => 'T3_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T3'
}
}
},
'plug:enable[0]' => {
'ports' => {
'processors_en' => {
'type' => 'input',
'intfc_port' => 'enable_i',
'instance_name' => 'IO',
'range' => ''
}
}
}
},
'instance_ids' => {
'IO' => {
'ports' => {
'reset' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
},
'processors_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => ''
},
'clk' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i',
'instance_name' => 'IO',
'range' => ''
'intfc_port' => 'clk_i'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'T2_ram_jtag_to_wb' => {
'range' => 'T2_ram_J2WBw-1 : 0',
'instance_name' => 'T2',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T0_uart_jtag_to_wb' => {
'range' => 'T0_uart_J2WBw-1 : 0',
'instance_name' => 'T0',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T3_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T3',
'range' => 'T3_uart_J2WBw-1 : 0'
},
'T1_uart_wb_to_jtag' => {
'instance_name' => 'T1',
'range' => 'T1_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T0_ram_jtag_to_wb' => {
'instance_name' => 'T0',
'range' => 'T0_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T3_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T3_ram_J2WBw-1 : 0',
'instance_name' => 'T3'
},
'T3_uart_wb_to_jtag' => {
'range' => 'T3_uart_WB2Jw-1 : 0',
'instance_name' => 'T3',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T2_ram_wb_to_jtag' => {
'instance_name' => 'T2',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T1_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T1',
'range' => 'T1_ram_WB2Jw-1 : 0'
},
'T1_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T1_uart_J2WBw-1 : 0',
'instance_name' => 'T1'
},
'T0_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T0_uart_WB2Jw-1 : 0',
'instance_name' => 'T0'
},
'T2_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T2_uart_WB2Jw-1 : 0',
'instance_name' => 'T2'
},
'T2_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T2',
'range' => 'T2_uart_J2WBw-1 : 0'
},
'T1_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T1',
'range' => 'T1_ram_J2WBw-1 : 0'
},
'T0_ram_wb_to_jtag' => {
'instance_name' => 'T0',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T3_ram_wb_to_jtag' => {
'range' => 'T3_ram_WB2Jw-1 : 0',
'instance_name' => 'T3',
'intfc_port' => 'jwb_o',
'type' => 'output'
}
}
},
'IO' => {
'ports' => {
'T0_led_port_o' => {
'instance_name' => 'T0',
'range' => ' 1-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
},
'T3_led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'range' => ' 1-1 : 0',
'instance_name' => 'T3'
},
'T2_led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'instance_name' => 'T2',
'range' => ' 1-1 : 0'
},
'T1_led_port_o' => {
'instance_name' => 'T1',
'range' => ' 1-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
}
},
'plug:reset[0]' => {
'ports' => {
'reset' => {
'instance_name' => 'IO',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
}
'T0' => {
'ports' => {
'T0_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T0_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T0_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T0_ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T0_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T0_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
}
},
'T3' => {
'ports' => {
'T3_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_ram_WB2Jw-1 : 0'
},
'T3_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_J2WBw-1 : 0'
},
'T3_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_WB2Jw-1 : 0'
},
'T3_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_ram_J2WBw-1 : 0'
}
}
},
'T1' => {
'ports' => {
'T1_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T1_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_uart_J2WBw-1 : 0'
},
'T1_uart_wb_to_jtag' => {
'range' => 'T1_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T1_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_J2WBw-1 : 0'
}
}
},
'T2' => {
'ports' => {
'T2_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_uart_jtag_to_wb' => {
'range' => 'T2_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T2_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_ram_J2WBw-1 : 0'
},
'T2_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_WB2Jw-1 : 0'
}
}
}
}
}, 'ip_gen' ),
'ROM0' => {
'start' => 0,
'end' => 22937
},
'soc_param' => {
'default' => {
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Aw' => '14',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'uart_JDw' => '32',
'ram_JSTATUSw' => '8',
'ram_JINDEXw' => '8',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_Dw' => '32',
'uart_JAw' => '32',
'ram_JTAG_CHAIN' => '4',
'uart_JINDEXw' => '8',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_CHAIN' => '3'
}
}, 'ip_gen' ),
'MEM1' => {
'width' => '14',
'percent' => '75'
},
'ROM2' => {
'start' => 0,
'end' => 49152
},
'parameters_order' => {
'SOURCE_SET' => [
'clk_number',
'clk_0_name',
'reset_number',
'reset_0_name'
],
'noc_type' => [
'ROUTER_TYPE'
],
'noc_param' => [
'TOPOLOGY',
'T1',
'T2',
'T3',
'V',
'B',
'Fpay',
'ROUTE_NAME',
'MIN_PCK_SIZE',
'BYTE_EN',
'SSA_EN',
'CONGESTION_INDEX',
'ESCAP_VC_MASK',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'SWA_ARBITER_TYPE',
'WEIGHTw',
'AVC_ATOMIC_EN'
],
'SOURCE_SET_CONNECT' => [
'NoC_clk',
'T0_ss_clk_in',
'T1_ss_clk_in',
'T2_ss_clk_in',
'T3_ss_clk_in',
'NoC_reset',
'T0_ss_reset_in',
'T1_ss_reset_in',
'T2_ss_reset_in',
'T3_ss_reset_in',
'T0_cs_clk_in',
'T1_cs_clk_in',
'T2_cs_clk_in',
'T3_cs_clk_in',
'T0_cs_reset_in',
'T1_cs_reset_in',
'T2_cs_reset_in',
'T3_cs_reset_in'
]
},
'ROM3' => {
'start' => 0,
'end' => 49152
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'verilator' => {
'libs' => {
'Vtile3' => '--top-module tile_3',
'Vtile0' => '--top-module tile_0',
'Vrouter1' => '--top-module router_top_v -GP=5 ',
'Vtile1' => '--top-module tile_1',
'Vtile2' => '--top-module tile_2'
}
},
'JTAG' => {
'M_CHAIN' => 4
},
'get_config_adj' => {
'va' => '0',
'ha' => '0'
},
'MEM0' => {
'percent' => '70',
'width' => '13'
},
'RAM1' => {
'end' => 65536,
'start' => 49152
},
'MEM3' => {
'width' => '14',
'percent' => '75'
},
'ROM1' => {
'end' => 49152,
'start' => 0
},
'compile_assign_type' => {
'TOP_reset' => 'Direct',
'jtag_debug_reset_in' => 'Direct',
'processors_en' => 'Direct',
'TOP_clk' => 'Direct'
},
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'liststore' => {
'ha' => '0',
'va' => '0'
},
'fpga_param' => {},
'RAM0' => {
'end' => 32768,
'start' => 22937
}
}, 'mpsoc' );
}, 'mpsoc' );

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