OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

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  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl
    from Rev 41 to Rev 42
    ↔ Reverse comparison
  •

Rev 41 → Rev 42

/compile.pl
764,9 → 764,25
 
my $board_name=$self->object_get_attribute('compile','board');
#copy board jtag_intfc.sh file
my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
copy("../boards/$board_name/jtag_intfc.sh","${fpath}../sw/jtag_intfc.sh");
copy("../boards/$board_name/jtag_intfc.sh","${fpath}../sw/jtag_intfc.sh");
my $n= $self->object_get_attribute('soc_name',undef);
if(!defined $n){ # we are compiling a complete NoC-based mpsoc
my $nx= $self->object_get_attribute('noc_param',"NX");
my $ny= $self->object_get_attribute('noc_param',"NY");
for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){
my $tile_num= $y*$nx+$x;
#print "$tile_num\n";
my ($soc_name,$num)= $self->mpsoc_get_tile_soc_name($tile_num);
next if(!defined $soc_name);
copy("../boards/$board_name/jtag_intfc.sh","${fpath}../sw/tile$tile_num/jtag_intfc.sh");
}}
}
 
#copy board program_device.sh file
copy("../boards/$board_name/program_device.sh","${fpath}../program_device.sh");
818,11 → 834,13
if (length($portrange)!=0){
#replace parameter with their values
my @a= split (/\b/,$portrange);
foreach my $l (@a){
my $value=$param{$l};
if(defined $value){
chomp $value;
($portrange=$portrange)=~ s/\b$l\b/$value/g if(defined $param{$l});
# print"($portrange=$portrange)=~ s/\b$l\b/$value/g if(defined $param{$l})\n";
}
}
$portrange = "[ $portrange ]" ;
1149,6 → 1167,7
add_info(\$tview,"creat Modelsim dir in $target_dir\n");
my $model="$target_dir/Modelsim";
rmtree("$model");
rmtree("$target_dir/rtl_work");
mkpath("$model/rtl_work",1,01777);
#create modelsim.tcl file
1193,6 → 1212,7
$app->do_save();
my $modelsim_bin= $self->object_get_attribute('compile','modelsim_bin');
my $cmd="cd $target_dir; $modelsim_bin/vsim -do $model/run.tcl";
add_info(\$tview,"$cmd\n");
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
1228,7 → 1248,7
add_info(\$outtext,"Copy all verilog files in rtl_work folder\n");
my @files = File::Find::Rule->file()
->name( '*.v','*.V','*.sv','*.vh')
->in( "$target_dir/src_verilog" );
->in( "$target_dir/src_verilog","$target_dir/src_verilator" );
foreach my $file (@files) {
copy($file,"$verilator/rtl_work/");
}
1235,7 → 1255,7
@files = File::Find::Rule->file()
->name( '*.sv','*.vh' )
->in( "$target_dir/src_verilog" );
->in( "$target_dir/src_verilog","$target_dir/src_verilator" );
foreach my $file (@files) {
copy($file,"$verilator/processed_rtl");
}
1253,12 → 1273,13
$split->write_files();
$split->read_and_split(glob("$verilator/rtl_work/*.sv"));
$split->write_files();
#run verilator
#my $cmd= "cd \"$verilator/processed_rtl\" \n xterm -e sh -c ' verilator --cc $name.v --profile-cfuncs --prefix \"Vtop\" -O3 -CFLAGS -O3'";
foreach my $top (sort keys %tops) {
my $cmd= "cd \"$verilator/processed_rtl\" \n verilator --cc $tops{$top} --profile-cfuncs --prefix \"$top\" -O3 -CFLAGS -O3";
add_colored_info(\$outtext,"Generate $top Verilator model from $tops{$top} file\n",'green');
my $cmd= "cd \"$verilator/processed_rtl\" \n verilator --cc $tops{$top} --prefix \"$top\" -O3 -CFLAGS -O3";
add_info(\$outtext,"$cmd\n");
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
1272,13 → 1293,14
#check if verilator model has been generated
foreach my $top (sort keys %tops) {
if (-f "$verilator/processed_rtl/obj_dir/$top.cpp"){#succsess
#generate makefile
gen_verilator_makefile($top_ref,"$verilator/processed_rtl/obj_dir/Makefile");
}else {
return 0;
}
}
#generate makefile
gen_verilator_makefile($top_ref,"$verilator/processed_rtl/obj_dir/Makefile");
return 1;
}
 
1290,11 → 1312,15
my $q='';
my $h='';
my $l;
my $lib_num=0;
my $all_lib="";
foreach my $top (sort keys %tops) {
$p = "$p ${top}__ALL.a ";
$q = "$q\t\$(MAKE) -f ${top}.mk\n";
$q = $q."lib$lib_num:\n\t\$(MAKE) -f ${top}.mk\n";
$h = "$h ${top}.h ";
$l = $top;
$all_lib=$all_lib." lib$lib_num";
$lib_num++;
}
1306,7 → 1332,8
 
include $l.mk
 
lib:
lib: $all_lib
 
$q
 
 
1329,7 → 1356,7
testbench.o: testbench.cpp $h
 
clean:
rm *.o *.a main
rm *.o *.a testbench
";
 
 
1371,9 → 1398,27
verilator_testbench($self,$name,$top,$target_dir);
});
my %tops;
$tops{"Vtop"}= "$name.v";
my $result = verilator_compilation (\%tops,$target_dir,$outtext);
 
$window->add ($mtable);
$window->show_all();
 
my $result;
my $n= $self->object_get_attribute('soc_name',undef);
if(defined $n){ #we are compiling a single tile as SoC
my %tops;
$tops{"Vtop"}= "$name.v";
$result = verilator_compilation (\%tops,$target_dir,$outtext);
$self->object_add_attribute('verilator','libs',\%tops);
}
else { # we are compiling a complete NoC-based mpsoc
$result = gen_mpsoc_verilator_model ($self,$name,$top,$target_dir,$outtext);
}
 
#check if verilator model has been generated
if ($result){
add_colored_info(\$outtext,"Veriator model has been generated successfully!",'blue');
1385,8 → 1430,7
 
 
$window->add ($mtable);
$window->show_all();
 
 
 
1394,11 → 1438,126
 
 
 
 
 
sub gen_mpsoc_verilator_model{
my ($self,$name,$top,$target_dir,$outtext)=@_;
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/..");
my $src_verilator_dir="$project_dir/src_verilator";
my $sw_dir = "$target_dir/sw";
#copy src_verilator files
add_info(\$outtext,"Copy verilator files\n");
my @files=(
"$src_verilator_dir/noc_connection.sv",
"$src_verilator_dir/router_verilator.v"
);
if (-d "$target_dir/src_verilator/"==0){
mkpath("$target_dir/src_verilator/",1,01777);
}
copy_file_and_folders (\@files,$project_dir,"$target_dir/src_verilator");
#create each tile top module
my $nx= $self->object_get_attribute('noc_param',"NX");
my $ny= $self->object_get_attribute('noc_param',"NY");
my $processors_en=0;
my $mpsoc=$self;
my $lisence= get_license_header("verilator_tiles");
my $warning=autogen_warning();
my $verilator=$lisence.$warning;
# generate NoC parameter file
my ($noc_param,$pass_param)=gen_noc_param_v($self);
my $noc_param_v= " \`ifdef INCLUDE_PARAM \n \n
$noc_param
/* verilator lint_off WIDTH */
localparam P=(TOPOLOGY==\"RING\" || TOPOLOGY==\"LINE\")? 3 : 5;
localparam ROUTE_TYPE = (ROUTE_NAME == \"XY\" || ROUTE_NAME == \"TRANC_XY\" )? \"DETERMINISTIC\" :
(ROUTE_NAME == \"DUATO\" || ROUTE_NAME == \"TRANC_DUATO\" )? \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\";
/* verilator lint_on WIDTH */
//simulation parameter
\n \n \`endif" ;
save_file("$target_dir/src_verilator/parameter.v",$noc_param_v);
my %tops = (
"Vrouter" => "router_verilator.v",
"Vnoc" => "noc_connection.sv"
);
for (my $y=0;$y<$ny;$y++){
for (my $x=0; $x<$nx;$x++){
my $tile_num= $y*$nx+$x;
#print "$tile_num\n";
my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num);
if(!defined $soc_name){
#this tile is not connected to any ip. the noc input ports will be connected to ground
my $soc_v="\n\n // Tile:$tile_num (x=$x,y=$y) is not assigned to any ip\n";
$soc_v="$soc_v
assign ni_credit_out[$tile_num]={V{1'b0}};
assign ni_flit_out[$tile_num]={Fw{1'b0}};
assign ni_flit_out_wr[$tile_num]=1'b0;
";
next;
}
my $soc=eval_soc($mpsoc,$soc_name,$outtext);
my $top=$mpsoc->mpsoc_get_soc($soc_name);
my $soc_num= $y*$nx+$x;
#update core id
$soc->object_add_attribute('global_param','CORE_ID',$tile_num);
#update NoC param
#my %nocparam = %{$mpsoc->object_get_attribute('noc_param',undef)};
my $nocparam =$mpsoc->object_get_attribute('noc_param',undef);
my @nis=get_NI_instance_list($top);
$soc->soc_add_instance_param($nis[0] ,$nocparam );
my $tile=($nx*$y)+ $x;
my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile);
my %params;
if ($setting eq 'Custom'){
%params= $top->top_get_custom_soc_param($tile);
}else{
%params=$top->top_get_default_soc_param();
}
my $sw_path = "$sw_dir/tile$tile_num";
$verilator = $verilator.soc_generate_verilatore ($soc,$sw_path,"tile_$tile",\%params);
$tops{"Vtile$tile_num"}= "tile_$tile.v";
}}
save_file ("$target_dir/src_verilator/verilator_tiles.v",$verilator);
my $result = verilator_compilation (\%tops,$target_dir,$outtext);
$self->object_add_attribute('verilator','libs',\%tops);
return $result;
 
}
 
 
sub gen_verilator_soc_testbench {
my ($self,$name,$top,$target_dir)=@_;
my $verilator="$target_dir/verilator";
my $dir="$verilator/";
my $soc_top= $self->soc_get_top ();
my @intfcs=$soc_top->top_get_intfc_list();
my %PP;
my $top_port_info="IO type\t port_size\t port_name\n";
1487,7 → 1646,383
 
}
 
sub eval_soc{
my ($mpsoc,$soc_name,$outtext)=@_;
my $path=$mpsoc->object_get_attribute('setting','soc_path');
$path=~ s/ /\\ /g;
my $p = "$path/$soc_name.SOC";
my $soc = eval { do $p };
if ($@ || !defined $soc){
show_info(\$outtext,"**Error reading $p file: $@\n");
next;
}
return $soc;
}
 
 
sub gen_verilator_mpsoc_testbench {
my ($mpsoc,$name,$top,$target_dir,$tview)=@_;
my $verilator="$target_dir/verilator";
my $dir="$verilator/";
#my $soc_top= $self->soc_get_top ();
my $nx= $mpsoc->object_get_attribute('noc_param',"NX");
my $ny= $mpsoc->object_get_attribute('noc_param',"NY");
my $libh="";
my $inst= "";
my $newinst="";
my $tile_x="";
my $tile_y="";
my $tile_flit_in="";
my $tile_flit_in_l="";
my $tile_credit="";
my $noc_credit="";
my $noc_flit_in="";
my $noc_flit_in_l="";
my $noc_flit_in_wr="";
my $noc_flit_in_wr_l="";
my $tile_flit_in_wr="";
my $tile_flit_in_wr_l="";
my $tile_eval="";
my $tile_final="";
my $tile_reset="";
my $tile_clk="";
my $tile_en="";
my $top_port_info="IO type\t port_size\t port_name\n";
my $no_connected='';
for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){
my $t= $y*$nx+$x;
my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($t);
if(defined $soc_name) {#we have a conncted tile
#get ni instance name
my $ni_name;
my $soc=eval_soc($mpsoc,$soc_name,$tview);
my $soc_top=$soc->object_get_attribute('top_ip',undef);
my @intfcs=$soc_top->top_get_intfc_list();
my @instances=$soc->soc_get_all_instances();
foreach my $id (@instances){
my $category = $soc->soc_get_category($id);
if ($category eq 'NoC') {
$ni_name= $soc->soc_get_instance_name($id);
}
}
$libh=$libh."#include \"Vtile${t}.h\"\n";
$inst=$inst."Vtile${t}\t*tile${t};\t // Instantiation of tile${t}\n";
$newinst = $newinst."\ttile${t}\t=\tnew Vtile${t};\n";
$tile_flit_in = $tile_flit_in . "\ttile${t}->${ni_name}_flit_in = noc->ni_flit_out [${t}];\n";
$tile_flit_in_l = $tile_flit_in_l . "\t\ttile${t}->${ni_name}_flit_in[j] = noc->ni_flit_out [${t}][j];\n";
$tile_credit= $tile_credit."\ttile${t}->${ni_name}_credit_in= noc->ni_credit_out[${t}];\n";
$noc_credit= $noc_credit."\tnoc->ni_credit_in[${t}] = tile${t}->${ni_name}_credit_out;\n";
$noc_flit_in=$noc_flit_in."\tnoc->ni_flit_in [${t}] = tile${t}->${ni_name}_flit_out;\n";
$noc_flit_in_l=$noc_flit_in_l."\t\t\tnoc->ni_flit_in [${t}][j] = tile${t}->${ni_name}_flit_out[j];\n";
$noc_flit_in_wr= $noc_flit_in_wr."\tif(tile${t}->${ni_name}_flit_out_wr) noc->ni_flit_in_wr = noc->ni_flit_in_wr | ((vluint64_t)1<<${t});\n";
$tile_flit_in_wr=$tile_flit_in_wr."\ttile${t}->${ni_name}_flit_in_wr= ((noc->ni_flit_out_wr >> ${t}) & 0x01);\n";
$noc_flit_in_wr_l= $noc_flit_in_wr_l."\tif(tile${t}->${ni_name}_flit_out_wr) MY_VL_SETBIT_W(noc->ni_flit_in_wr ,${t});\n";
$tile_flit_in_wr_l=$tile_flit_in_wr_l."\ttile${t}->${ni_name}_flit_in_wr= (VL_BITISSET_W(noc->ni_flit_out_wr,${t})>0);\n";
$tile_eval=$tile_eval."\ttile${t}->eval();\n";
$tile_final=$tile_final."\ttile${t}->final();\n";
foreach my $intfc (@intfcs){
my $key=($intfc eq 'plug:clk[0]')? 'clk' :
($intfc eq 'plug:reset[0]')? 'reset':
($intfc eq 'plug:enable[0]')? 'en' :
'other';
my @ports=$soc_top->top_get_intfc_ports_list($intfc);
foreach my $p (@ports){
my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
$tile_reset=$tile_reset."\t\ttile${t}->$p=reset;\n" if $key eq 'reset';
$tile_clk=$tile_clk."\t\ttile${t}->$p=clk;\n" if $key eq 'clk';
$tile_en=$tile_en."\t\ttile${t}->$p=enable;\n" if $key eq 'en'; ;
$top_port_info="$top_port_info $type $range tile${t}->$p \n";
}#ports
}#interface
$tile_x= $tile_x."\ttile${t}->${ni_name}_current_x=$x;\n";
$tile_y= $tile_y."\ttile${t}->${ni_name}_current_y=$y;\n";
}else{
#this tile is not connected to any ip. the noc input ports will be connected to ground
$no_connected=$no_connected."\n // Tile:$t (x=$x,y=$y) is not assigned to any ip\n";
$no_connected=$no_connected."\t\tnoc->ni_credit_in[${t}]=0; \n";
}
}}
my $main_c=get_license_header("testbench.cpp");
$main_c="$main_c
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#include <verilated.h> // Defines common routines
 
#include \"Vnoc.h\"
#include \"Vrouter.h\"
$libh
 
 
/*
$top_port_info
*/
 
 
#ifndef NX
#define NX $nx
#endif
 
#ifndef NY
#define NY $ny
#endif
 
#ifndef NC
#define NC ($nx*$ny)
#endif
 
 
Vrouter *router[NC]; // Instantiation of router
Vnoc *noc;
$inst
 
 
int reset,clk,enable;
unsigned int main_time = 0; // Current simulation time
 
void update_all_instances_inputs(void);
 
 
int main(int argc, char** argv) {
int i,j,x,y;
Verilated::commandArgs(argc, argv); // Remember args
for(i=0;i<NC;i++) router[i] = new Vrouter; // Create instance
noc = new Vnoc;
$newinst
/********************
* initialize input
*********************/
 
reset=1;
enable=1;
$no_connected
for(x=0;x<NX;x++)for(y=0;y<NY;y++){
i=(y*NX)+x;
router[i]->current_x = x;
router[i]->current_y = y;
}
$tile_x
$tile_y
 
main_time=0;
printf(\"Start Simulation\\n\");
while (!Verilated::gotFinish()) {
if (main_time >= 10 ) {
reset=0;
}
 
 
if ((main_time % 5) == 0) {
clk = 1; // Toggle clock
// you can change the inputs and read the outputs here in case they are captured at posedge of clock
}
else{
clk = 0; // Toggle clock
update_all_instances_inputs();
}
 
 
//clk,reset,enable
noc-> clk = clk;
noc-> reset = reset;
$tile_reset
$tile_clk
$tile_en
for(i=0;i<NC;i++){
router[i]->reset= reset;
router[i]->clk= clk;
}
 
//eval instances
noc->eval();
for(i=0;i<NC;i++) {
router[i]->eval();
}
$tile_eval
 
main_time++;
 
}//while
// Simulation is dne
for(i=0;i<NC;i++) {
router[i]->final();
}
noc->final();
$tile_final
}
 
double sc_time_stamp () { // Called by \$time in Verilog
return main_time;
}
 
 
void update_all_instances_inputs(void){
int x,y,i,j;
int flit_out_all_size = sizeof(router[0]->flit_out_all)/sizeof(router[0]->flit_out_all[0]);
 
#if (NC<=64)
noc->ni_flit_in_wr =0;
#else
for(j=0;j<(sizeof(noc->ni_flit_in_wr)/sizeof(noc->ni_flit_in_wr[0])); j++) noc->ni_flit_in_wr[j]=0;
#endif
for(x=0;x<NX;x++)for(y=0;y<NY;y++){
i=(y*NX)+x;
router[i]->flit_in_we_all = noc->router_flit_out_we_all[i];
router[i]->credit_in_all = noc->router_credit_out_all[i];
router[i]->congestion_in_all = noc->router_congestion_out_all[i];
for(j=0;j<flit_out_all_size;j++) router[i]->flit_in_all[j] = noc->router_flit_out_all[i][j];
noc->router_flit_in_we_all[i] = router[i]->flit_out_we_all ;
noc->router_credit_in_all[i] = router[i]->credit_out_all;
noc->router_congestion_in_all[i]= router[i]->congestion_out_all;
for(j=0;j<flit_out_all_size;j++) noc->router_flit_in_all[i][j] = router[i]->flit_out_all[j] ;
} //for
 
#if (Fpay<=32)
//tile[i]->flit_in = noc->ni_flit_out [i];
$tile_flit_in
#else
for(j=0;j<(sizeof(traffic[i]->flit_out)/sizeof(traffic[i]->flit_out[0])); j++){
//traffic[i]->flit_in[j] = noc->ni_flit_out [i][j];
$tile_flit_in_l
}
#endif
//traffic[i]->credit_in= noc->ni_credit_out[i];
$tile_credit
//noc->ni_credit_in[i] = traffic[i]->credit_out;
$noc_credit
#if (Fpay<=32)
//noc->ni_flit_in [i] = traffic[i]->flit_out;
$noc_flit_in
#else
for(j=0;j<(sizeof(traffic[i]->flit_out)/sizeof(traffic[i]->flit_out[0])); j++){
//noc->ni_flit_in [i][j] = traffic[i]->flit_out[j];
$noc_flit_in_l
}
#endif
 
 
#if (NC<=64)
//if(traffic[i]->flit_out_wr) noc->ni_flit_in_wr = noc->ni_flit_in_wr | ((vluint64_t)1<<i);
$noc_flit_in_wr
//traffic[i]->flit_in_wr= ((noc->ni_flit_out_wr >> i) & 0x01);
$tile_flit_in_wr
#else
//if(traffic[i]->flit_out_wr) MY_VL_SETBIT_W(noc->ni_flit_in_wr ,i);
$noc_flit_in_wr_l
//traffic[i]->flit_in_wr= (VL_BITISSET_W(noc->ni_flit_out_wr,i)>0);
$tile_flit_in_wr_l
#endif
}
";
 
save_file("$dir/testbench.cpp",$main_c);
 
}
 
 
 
sub soc_get_all_parameters {
my $soc=shift;
my @instances=$soc->soc_get_all_instances();
my %all_param;
foreach my $id (@instances){
my $module =$soc->soc_get_module($id);
my $category =$soc->soc_get_category($id);
my $inst = $soc->soc_get_instance_name($id);
my %params = $soc->soc_get_module_param($id);
my $ip = ip->lib_new ();
my @param_order=$soc->soc_get_instance_param_order($id);
foreach my $p (sort keys %params){
my $inst_param= "$inst\_$p";
#add instance name to parameter value
$params{$p}=add_instantc_name_to_parameters(\%params,$inst,$params{$p});
my ($default,$type,$content,$info,$vfile_param_type,$redefine_param)= $ip->ip_get_parameter($category,$module,$p);
$vfile_param_type= "Don't include" if (!defined $vfile_param_type );
$vfile_param_type= "Parameter" if ($vfile_param_type eq 1);
$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);
$all_param{ $inst_param} = $params{ $p} if($vfile_param_type eq "Parameter" || $vfile_param_type eq "Localparam" );
print"$all_param{ $inst_param} = $params{ $p} if($vfile_param_type eq \"Parameter\" || $vfile_param_type eq \"Localparam\" ); \n";
}
}
return %all_param;
}
 
sub soc_get_all_parameters_order {
my $soc=shift;
my @instances=$soc->soc_get_all_instances();
my $ip = ip->lib_new ();
my @all_order;
foreach my $id (@instances){
my $module =$soc->soc_get_module($id);
my $category =$soc->soc_get_category($id);
my $inst = $soc->soc_get_instance_name($id);
my @order = $soc->soc_get_instance_param_order($id);
foreach my $p ( @order){
my $inst_param= "$inst\_$p";
my ($default,$type,$content,$info,$vfile_param_type,$redefine_param)= $ip->ip_get_parameter($category,$module,$p);
$vfile_param_type= "Don't include" if (!defined $vfile_param_type );
$vfile_param_type= "Parameter" if ($vfile_param_type eq 1);
$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);
push(@all_order, $inst_param) if($vfile_param_type eq "Parameter" || $vfile_param_type eq "Localparam" );
}
}
return @all_order;
}
 
 
 
sub gen_modelsim_soc_testbench {
my ($self,$name,$top,$target_dir)=@_;
my $dir="$target_dir/src_verilog";
1498,15 → 2033,39
my $pin_assign;
my $rst_inputs='';
 
#read port list
my $vdb=read_verilog_file($top);
my %param = $vdb->get_modules_parameters("${name}_top");
#add functions
my $d = Cwd::getcwd();
open my $file1, "<", "$d/lib/verilog/functions.v" or die;
my $functions_all='';
while (my $f1 = readline ($file1)) {
$functions_all="$functions_all $f1 ";
}
close($file1);
#get parameters
my $params_v="";
my $n= $self->object_get_attribute('soc_name',undef);
if(defined $n){ #we are compiling a single tile as SoC
my $core_id= $self->object_get_attribute('global_param','CORE_ID');
my $sw_loc = $self->object_get_attribute('global_param','SW_LOC');
$params_v="\tlocalparam\tCORE_ID=$core_id;
\tlocalparam\tSW_LOC=\"$sw_loc\";\n";
my %params=soc_get_all_parameters($self);
my @order= soc_get_all_parameters_order($self);
foreach my $p (@order){
add_text_to_string(\$params_v,"\tlocalparam $p = $params{$p};\n") if(defined $params{$p} );
}
}else{ # we are simulating a mpsoc
$params_v= gen_socs_param($self);
}
 
 
 
 
foreach my $intfc (@intfcs){
my $key= ( $intfc eq 'plug:clk[0]')? 'clk' :
( $intfc eq 'plug:reset[0]')? 'reset':
1524,20 → 2083,24
 
 
if (length($range)!=0){
#replace parameter with their values
my @a= split (/\b/,$range);
foreach my $l (@a){
my $value=$param{$l};
if(defined $value){
chomp $value;
($range=$range)=~ s/\b$l\b/$value/g if(defined $param{$l});
}
}
# #replace parameter with their values #
# my @a= split (/\b/,$range);
# print "a=@a\n";
# foreach my $l (@a){
# my $value=$params{$l};
# if(defined $value){
# chomp $value;
# ($range=$range)=~ s/\b$l\b/$value/g if(defined $params{$l});
# print "($range=$range)=~ s/\b$l\b/$value/g if(defined $params{$l}); \n";
# }
# }
$range = "[ $range ]" ;
}
 
 
 
 
 
if($type eq 'input'){
$top_port_def="$top_port_def reg $range $p;\n"
}else{
1558,6 → 2121,10
 
module testbench;
 
$functions_all
 
$params_v
 
$top_port_def
 
 
1603,12 → 2170,23
my ($self,$name,$top,$target_dir)=@_;
my $verilator="$target_dir/verilator";
my $dir="$verilator";
gen_verilator_soc_testbench (@_) if((-f "$dir/testbench.cpp")==0);
my ($app,$table,$tview,$window) = software_main($dir,'testbench.cpp');
my $n= $self->object_get_attribute('soc_name',undef);
if(defined $n){ #we are compiling a single tile as SoC
gen_verilator_soc_testbench (@_) if((-f "$dir/testbench.cpp")==0);
}
else { # we are compiling a complete NoC-based mpsoc
gen_verilator_mpsoc_testbench (@_,$tview) if((-f "$dir/testbench.cpp")==0);
}
#copy makefile
#copy("../script/verilator_soc_make", "$verilator/processed_rtl/obj_dir/Makefile");
 
my ($app,$table,$tview,$window) = software_main($dir,'testbench.cpp');
 
 
my $make = def_image_button('icons/gen.png','Compile');
1636,7 → 2214,15
"Are you sure you want to regenaret the testbench.cpp file? Note that any changes you have made will be lost");
my $response = $dialog->run;
if ($response eq 'yes') {
gen_verilator_soc_testbench ($self,$name,$top,$target_dir);
my $n= $self->object_get_attribute('soc_name',undef);
if(defined $n){ #we are compiling a single tile as SoC
gen_verilator_soc_testbench ($self,$name,$top,$target_dir);
}
else { # we are compiling a complete NoC-based mpsoc
gen_verilator_mpsoc_testbench ($self,$name,$top,$target_dir,$tview);
}
$app->load_source("$dir/testbench.cpp");
}
$dialog->destroy;
1647,7 → 2233,16
$make -> signal_connect("clicked" => sub{
$app->do_save();
copy("$dir/testbench.cpp", "$verilator/processed_rtl/obj_dir/testbench.cpp");
run_make_file("$verilator/processed_rtl/obj_dir/",$tview);
my $tops_ref=$self->object_get_attribute('verilator','libs');
my %tops=%{$tops_ref};
my $lib_num=0;
foreach my $top (sort keys %tops) {
run_make_file("$verilator/processed_rtl/obj_dir/",$tview,"lib$lib_num");
$lib_num++;
}
run_make_file("$verilator/processed_rtl/obj_dir/",$tview,"sim");
 
});
 
/emulator.pl
1168,7 → 1168,7
);
 
my @charts = (
{ type=>"2D_line", page_num=>0, graph_name=> "Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency (clock)', Z_Title=>undef, Y_Max=>100},
{ type=>"2D_line", page_num=>0, graph_name=> "Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Latency (clock)', Z_Title=>undef, Y_Max=>100},
{ type=>"2D_line", page_num=>0, graph_name=> "Throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Received", result_name => "packet_rsvd_result", X_Title=>'Core ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Sent", result_name => "packet_sent_result", X_Title=>'Core ID' , Y_Title=>'Sent Packets Per Router', Z_Title=>undef},
/graph.pl
331,12 → 331,12
my $scale= $self->object_get_attribute("${graph_id}_graph_scale",undef);
$scale = 5 if(!defined $scale);
$minues -> signal_connect("clicked" => sub{
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale+0.5);
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*1.05);
set_gui_status($self,"ref",1);
});
 
$plus -> signal_connect("clicked" => sub{
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale-0.5) if( $scale>0.5);
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*0.95) if( $scale>0.5);
set_gui_status($self,"ref",5);
});
 
595,13 → 595,13
 
$minues -> signal_connect("clicked" => sub{
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale+0.5);
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*1.05);
set_gui_status($self,"ref",1);
});
set_tip($minues, "Zoom out");
 
$plus -> signal_connect("clicked" => sub{
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale-0.5) if( $scale>0.5);
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*0.95) if( $scale>0.5);
set_gui_status($self,"ref",5);
});
set_tip($plus, "Zoom in");
/ip_gen.pm
529,6 → 529,17
$self->{instance_ids}{$inst}{parameters}{$parameter}{redefine_param}=$redefine;
}
 
sub top_add_localparam{
my ($self,$inst,$parameter,$default,$type,$content,$info,$global_param,$redefine)=@_;
$self->{instance_ids}{$inst}{localparam}{$parameter}{"default"}=$default;
$self->{instance_ids}{$inst}{localparam}{$parameter}{type}=$type;
$self->{instance_ids}{$inst}{localparam}{$parameter}{content}=$content;
$self->{instance_ids}{$inst}{localparam}{$parameter}{info}=$info;
$self->{instance_ids}{$inst}{localparam}{$parameter}{global_param}=$global_param;
$self->{instance_ids}{$inst}{localparam}{$parameter}{redefine_param}=$redefine;
}
 
 
sub top_get_parameter{
my ($self,$inst,$parameter)=@_;
my ($default,$type,$content,$info,$global_param,$redefine);
550,6 → 561,9
return @l;
}
 
 
 
 
sub top_add_default_soc_param{
my ($self,$param_ref)=@_;
my %l=%{$param_ref};
588,6 → 602,8
}
 
 
 
 
sub top_get_intfc_ports_list{
my($self,$intfc_name)=@_;
my @ports;
/mpsoc_gen.pl
482,24 → 482,6
my $ok = def_image_button('icons/select.png','OK');
my $okbox=def_hbox(TRUE,0);
$okbox->pack_start($ok, FALSE, FALSE,0);
825,7 → 807,7
$row= noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$show_noc,'noc_param',undef);
#packet payload width
$label='payload width';
$label='Payload width';
$param='Fpay';
$default='32';
$content='32,256,32';
1003,10 → 985,21
$default="1\'b0";
$info="If enabeled it adds a pipline register at the output port of the router.";
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
#MAX_SBP_NUM = 4 //
$label="Number of multiple router bypassing ";
$param="MAX_SBP_NUM ";
$type='Spin-button';
$content='0,1,1';
$default=0;
$info="maximum number of routers which a packet can by pass during one clock cycle. Define it as zero will disable bypassing.";
#$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param');
#FIRST_ARBITER_EXT_P_EN
$label='Swich allocator first level
arbiters extenal priority enable';
arbiters external priority enable';
$param='FIRST_ARBITER_EXT_P_EN';
$default= 1;
$info='If set as 1 then the switch allocator\'s input (first) arbiters\' priority registers are enabled only when a request get both input and output arbiters\' grants';
1016,7 → 1009,7
#Arbiter type
$label='SW allocator arbiteration type';
$label='SW allocator arbitration type';
$param='SWA_ARBITER_TYPE';
$default='"RRA"';
$content='"RRA","WRRA"'; #,"WRRA_CLASSIC"';
1202,9 → 1195,13
#remove old rtl files that were copied by ProNoC
my $old_file_ref= eval { do "$hw_dir/file_list" };
if (defined $old_file_ref){
remove_file_and_folders($old_file_ref,$target_dir);
}
my @generated_tiles;
unlink "$hw_dir/file_list";
#print "nx=$nx,ny=$ny\n";
for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){
1212,6 → 1209,9
my $tile_num= $y*$nx+$x;
#print "$tile_num\n";
my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num);
next if(!defined $soc_name);
my $path=$mpsoc->object_get_attribute('setting','soc_path');
$path=~ s/ /\\ /g;
my $p = "$path/$soc_name.SOC";
1240,7 → 1240,9
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,0);
}else{
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,1);
move ("$hw_dir/$soc_name.v","$hw_dir/tiles/");
move ("$hw_dir/$soc_name.v","$hw_dir/tiles/");
my @tmp= ("$hw_dir/tiles/$soc_name.v");
add_to_project_file_list(\@tmp,"$hw_dir/tiles",$hw_dir);
}
1302,9 → 1304,18
}
show_info(\$info,$warnings) if(defined $warnings);
show_info(\$info,$warnings) if(defined $warnings);
#save project hdl file/folder list
my @new_file_ref;
foreach my $f(@{$hdl_ref}){
my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
push(@new_file_ref,"$target_dir/src_verilog/lib/$name$suffix");
}
open(FILE, ">$target_dir/src_verilog/file_list") || die "Can not open: $!";
print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
close(FILE) || die "Error closing file: $!";
#my @pathes=("$dir/../src_peripheral","$dir/../src_noc","$dir/../src_processor");
#foreach my $p(@pathes){
# find(
1359,7 → 1370,7
#################
 
sub generate_mpsoc{
my ($mpsoc,$info)=@_;
my ($mpsoc,$info,$show_sucess_msg)=@_;
my $name=$mpsoc->object_get_attribute('mpsoc_name');
my $error = check_verilog_identifier_syntax($name);
if ( defined $error ){
1430,7 → 1441,7
message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
message_dialog("MPSoC \"$name\" has been created successfully at $target_dir/ " ) if($show_sucess_msg);
1482,6 → 1493,7
 
#programe the memory
for i in $(ls -d */); do
echo "Enter ${i%%/}"
cd ${i%%/}
sh write_memory.sh
cd ..
1635,7 → 1647,7
my @list=(' ',@socs);
my $pos=(defined $soc_name)? get_scolar_pos($soc_name,@list): 0;
my $combo=gen_combo(\@list, $pos);
my $lable=gen_label_in_left(" SoC name:");
my $lable=gen_label_in_left(" Processing tile name:");
$table->attach_defaults($lable,0,3,$row,$row+1);
$table->attach_defaults($combo,3,7,$row,$row+1);$row++;
my $separator1 = Gtk2::HSeparator->new;
1767,18 → 1779,21
message_dialog("Please define the MPSoC name!");
return ;
}
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name/sw";
my $sw = "$target_dir";
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
my $sw = "$target_dir/sw";
my ($app,$table,$tview) = software_main($sw);
 
 
 
my $make = def_image_button('icons/gen.png','Compile');
my $prog= def_image_button('icons/write.png','Program the memories');
$table->attach ($make,9, 10, 1,2,'shrink','shrink',0,0);
$table->attach ($make,5, 6, 1,2,'shrink','shrink',0,0);
$table->attach ($prog,9, 10, 1,2,'shrink','shrink',0,0);
 
$make -> signal_connect("clicked" => sub{
$app->do_save();
1786,7 → 1801,46
run_make_file($sw,$tview);
 
});
#Programe the board
$prog-> signal_connect("clicked" => sub{
my $error = 0;
my $bash_file="$sw/program.sh";
my $jtag_intfc="$sw/jtag_intfc.sh";
add_info(\$tview,"Programe the board using quartus_pgm and $bash_file file\n");
#check if the programming file exists
unless (-f $bash_file) {
add_colored_info(\$tview,"\tThe $bash_file does not exists! \n", 'red');
$error=1;
}
#check if the jtag_intfc.sh file exists
unless (-f $jtag_intfc) {
add_colored_info(\$tview,"\tThe $jtag_intfc does not exists!. Press the compile button and select your FPGA board first to generate $jtag_intfc file\n", 'red');
$error=1;
}
return if($error);
my $command = "cd $sw; sh program.sh";
add_info(\$tview,"$command\n");
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
if(length $stderr>1){
add_colored_info(\$tview,"$stderr\n",'red');
add_colored_info(\$tview,"Memory was not programed successfully!\n",'red');
}else {
 
if($exit){
add_colored_info(\$tview,"$stdout\n",'red');
add_colored_info(\$tview,"Memory was not programed successfully!\n",'red');
}else{
add_info(\$tview,"$stdout\n");
add_colored_info(\$tview,"Memory is programed successfully!\n",'blue');
 
}
}
});
 
}
 
 
1946,7 → 2000,7
$generate-> signal_connect("clicked" => sub{
generate_mpsoc($mpsoc,$info);
generate_mpsoc($mpsoc,$info,1);
set_gui_status($mpsoc,"refresh_soc",1);
 
});
1969,6 → 2023,7
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
my $top_file = "$target_dir/src_verilog/${name}_top.v";
if (-f $top_file){
generate_mpsoc($mpsoc,$info,0);
select_compiler($mpsoc,$name,$top_file,$target_dir);
} else {
message_dialog("Cannot find $top_file file. Please run RTL Generator first!");
/mpsoc_verilog_gen.pl
46,7 → 46,7
#functions
my $functions=get_functions();
my $mpsoc_v = (defined $param_as_in_v )? "module $mpsoc_name #(\n $param_as_in_v\n)(\n$io_v\n);\n": "module $mpsoc_name (\n$io_v\n);\n";
my $mpsoc_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule $mpsoc_name #(\n $param_as_in_v\n)(\n$io_v\n);\n": "`timescale 1ns/1ps\nmodule $mpsoc_name (\n$io_v\n);\n";
add_text_to_string (\$mpsoc_v,$noc_param);
add_text_to_string (\$mpsoc_v,$functions);
add_text_to_string (\$mpsoc_v,$socs_param);
56,7 → 56,8
add_text_to_string (\$mpsoc_v,$socs_v);
add_text_to_string (\$mpsoc_v,"\nendmodule\n");
my $top_v = (defined $param_as_in_v )? "module ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$io_v\n);\n": "module ${mpsoc_name}_top (\n $io_v\n);\n";
my $top_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$io_v\n);\n": "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top (\n $io_v\n);\n";
add_text_to_string (\$top_v,$socs_param);
add_text_to_string (\$top_v,$io_def_v);
add_text_to_string(\$top_v,"
579,6 → 580,7
}
#enable
elsif( $intfc eq 'plug:enable[0]'){
my @ports=$top->top_get_intfc_ports_list($intfc);
foreach my $p (@ports){
592,6 → 594,18
}
#RxD_sim
elsif( $intfc eq 'socket:RxD_sim[0]'){
#This interface is for simulation only donot include it in top module
my @ports=$top->top_get_intfc_ports_list($intfc);
foreach my $p (@ports){
add_text_to_string(\$soc_v,',') if ($i);
add_text_to_string(\$soc_v,"\n\t\t.$p( )");
$i=1;
}
}
else {
#other interface
my @ports=$top->top_get_intfc_ports_list($intfc);
/simulator.pl
757,6 → 757,7
#@q =split (/\n/,$d);
#my $avg=$q[0];
my $avg_latency =capture_number_after("average latency =",$stdout);
my $sd_latency =capture_number_after("standard_dev =",$stdout);
my $avg_thput =capture_number_after("Avg throughput is:",$stdout);
my $total_time =capture_number_after("simulation clock cycles:",$stdout);
769,6 → 770,7
next if (!defined $avg_latency);
update_result($simulate,$sample,"latency_result",$ratio_in,$avg_latency);
update_result($simulate,$sample,"sd_latency_result",$ratio_in,$sd_latency);
update_result($simulate,$sample,"throughput_result",$ratio_in,$avg_thput);
update_result($simulate,$sample,"exe_time_result",$ratio_in,$total_time);
foreach my $p (sort keys %packet_rsvd_per_core){
825,6 → 827,7
#@q =split (/\n/,$d);
#my $avg=$q[0];
my $avg_latency =capture_number_after("average latency =",$stdout);
my $sd_latency =capture_number_after("standard_dev =",$stdout);
my $avg_thput =capture_number_after("Avg throughput is:",$stdout);
my %packet_rsvd_per_core = capture_cores_data("total number of received packets:",$stdout);
my %worst_rsvd_delay_per_core = capture_cores_data('worst-case-delay of received pckets \(clks\):',$stdout);
836,6 → 839,7
next if (!defined $avg_latency);
update_result($simulate,$sample,"latency_result",$i,$avg_latency);
update_result($simulate,$sample,"sd_latency_result",$i,$sd_latency);
update_result($simulate,$sample,"throughput_result",$i,$avg_thput);
update_result($simulate,$sample,"exe_time_result",$i,$total_time);
foreach my $p (sort keys %packet_rsvd_per_core){
926,8 → 930,9
 
 
my @charts = (
{ type=>"2D_line", page_num=>0, graph_name=> "Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency (clock)', Z_Title=>undef, Y_Max=>100},
{ type=>"2D_line", page_num=>0, graph_name=> "Throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef},
{ type=>"2D_line", page_num=>0, graph_name=> "Throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef},
{ type=>"2D_line", page_num=>0, graph_name=> "Avg. Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Latency (clock)', Z_Title=>undef, Y_Max=>100},
{ type=>"2D_line", page_num=>0, graph_name=> "SD latency", result_name => "sd_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency Standard Deviation (clock)', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Received", result_name => "packet_rsvd_result", X_Title=>'Core ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Sent", result_name => "packet_sent_result", X_Title=>'Core ID' , Y_Title=>'Sent Packets Per Router', Z_Title=>undef},
{ type=>"3D_bar", page_num=>2, graph_name=> "Received", result_name => "worst_delay_rsvd_result",X_Title=>'Core ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
/soc.pm
786,4 → 786,7
}
 
 
 
 
 
1
/soc_gen.pl
941,6 → 941,30
return \@files,$warnings;
}
 
 
sub add_to_project_file_list{
my ($files_ref,$files_path,$list_path )=@_;
my @new_file_ref;
foreach my $f(@{$files_ref}){
my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
push(@new_file_ref,"$files_path/$name$suffix");
}
my $old_file_ref= eval { do "$list_path/file_list" };
if (defined $old_file_ref){
foreach my $f(@{$old_file_ref}){
unless ( grep( /^$f$/, @new_file_ref ) ){
push(@new_file_ref,$f);
}
 
}
}
open(FILE, ">$list_path/file_list") || die "Can not open: $!";
print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
close(FILE) || die "Error closing file: $!";
}
 
 
 
################
# generate_soc
#################
984,7 → 1008,7
close(FILE) || die "Error closing file: $!";
 
#generate prog_mem
open(FILE, ">lib/verilog/program.sh") || die "Can not open: $!";
open(FILE, ">lib/verilog/program.sh") || die "Can not open: $!";
print FILE soc_mem_prog();
close(FILE) || die "Error closing file: $!";
 
998,18 → 1022,26
my $hw_lib="$hw_path/lib";
mkpath("$hw_lib/",1,01777);
mkpath("$sw_path/",1,01777);
#remove old rtl files that were copied by ProNoC
my $old_file_ref= eval { do "$hw_path/file_list" };
if (defined $old_file_ref){
remove_file_and_folders($old_file_ref,$target_dir);
}
#copy hdl codes in src_verilog
my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");
#copy hdl codes in src_verilog
my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");
copy_file_and_folders($file_ref,$project_dir,$hw_lib);
show_info(\$info,$warnings) if(defined $warnings);
show_info(\$info,$warnings) if(defined $warnings);
add_to_project_file_list($file_ref,$hw_lib,$hw_path);
#copy jtag control files
my @jtags=(("/mpsoc/src_peripheral/jtag/jtag_wb"),("jtag"));
copy_file_and_folders(\@jtags,$project_dir,$hw_lib);
copy_file_and_folders(\@jtags,$project_dir,$hw_lib);
add_to_project_file_list(\@jtags,$hw_lib,$hw_path);
move ("$dir/lib/verilog/$name.v","$hw_path/");
move ("$dir/lib/verilog/${name}_top.v","$hw_path/");
move ("$dir/lib/verilog/README" ,"$sw_path/");
1017,10 → 1049,29
move ("$dir/lib/verilog/program.sh" ,"$sw_path/");
}
#remove old software files that were copied by ProNoC
my $old_file_ref= eval { do "$sw_path/file_list" };
if (defined $old_file_ref){
remove_file_and_folders($old_file_ref,$project_dir);
}
# Copy Software files
my ($file_ref,$warnings)= get_all_files_list($soc,"sw_files");
copy_file_and_folders($file_ref,$project_dir,$sw_path);
my @new_file_ref;
foreach my $f(@{$file_ref}){
my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
push(@new_file_ref,"$sw_path/$name$suffix");
}
push(@new_file_ref,"$sw_path/$name.h");
open(FILE, ">$sw_path/file_list") || die "Can not open: $!";
print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
close(FILE) || die "Error closing file: $!";
# Write system.h and Software gen files
generate_header_file($soc,$project_dir,$sw_path,$hw_path,$dir);
1121,7 → 1172,75
 
 
 
#############
# set_unset_infc
#############
 
sub set_unset_infc{
my $soc =shift;
my $window = def_popwin_size(40,60,"Unconnected Socket Interfaces",'percent');
my $table = def_table(10,4, FALSE);
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$scrolled_win->add_with_viewport($table);
my $row=0;
my $column=0;
my $ip = ip->lib_new ();
my @instances=$soc->soc_get_all_instances();
foreach my $id (@instances){
my $module =$soc->soc_get_module($id);
my $module_name =$soc->soc_get_module_name($id);
my $category =$soc->soc_get_category($id);
my $inst = $soc->soc_get_instance_name($id);
my @ports=$ip->ip_list_ports($category,$module);
foreach my $port (@ports){
my ($type,$range,$intfc_name,$i_port)=$ip->ip_get_port($category,$module,$port);
my($i_type,$i_name,$i_num) =split("[:\[ \\]]", $intfc_name);
if($i_type eq 'socket' && $i_name ne'wb_addr_map' ){
my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($id,$i_name,$i_num);
my %connected_plugs=%$ref1;
my %connected_plug_nums=%$ref2;
if(!%connected_plugs ){
my ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($id,$i_name);
my $v=$soc->soc_get_module_param_value($id,$s_value);
if ( length( $v || '' ) || $category eq 'NoC' ){ }
else {
($row,$column)=add_param_widget ($soc,"$inst->$port","$inst-$port", 'IO','Combo-box',"IO,NC",undef, $table,$row,$column,1,"Unset-intfc",undef,undef,"vertical");
if($column == 0){
$column = 4;
$row= $row-1;
}else{
$column = 0;
}
}
}
}
}
}
my $box1=def_hbox(FALSE, 1);
$box1->pack_start( Gtk2::VSeparator->new, FALSE, FALSE, 3);
$table->attach($box1,3,4,0,$row+1,'expand','fill',2,2);
my $ok = def_image_button('icons/select.png','OK');
$ok->signal_connect ( 'clicked'=> sub {
$window->destroy;
});
my $mtable = def_table(10, 1, FALSE);
$mtable->attach_defaults($scrolled_win,0,1,0,9);
$mtable->attach($ok,0,1,9,10,'expand','fill',2,2);
$window->add ($mtable);
$window->show_all;
}
 
 
 
1291,7 → 1410,7
$window->destroy;
}else{
message_dialog("Invalid address !");
message_dialog("Invalid address!");
}
1298,14 → 1417,14
});
$table->attach ($refbox,2,3,$row,$row+1,'expand','shrink',2,2);
$table->attach ($ok,3,4,$row,$row+1,'expand','shrink',2,2);
$window->add($scrolled_win);
my $mtable = def_table(10, 2, FALSE);
$mtable->attach_defaults($scrolled_win,0,2,0,9);
$mtable->attach ($refbox,0,1,9,10,'expand','shrink',2,2);
$mtable->attach($ok,1,2,9,10,'expand','fill',2,2);
$window->add ($mtable);
$window->show_all;
1605,6 → 1724,7
$prog-> signal_connect("clicked" => sub{
my $error = 0;
my $bash_file="$target_dir/sw/program.sh";
my $jtag_intfc="$sw/jtag_intfc.sh";
 
add_info(\$tview,"Programe the board using quartus_pgm and $bash_file file\n");
#check if the programming file exists
1612,6 → 1732,11
add_colored_info(\$tview,"\tThe $bash_file does not exists! \n", 'red');
$error=1;
}
#check if the jtag_intfc.sh file exists
unless (-f $jtag_intfc) {
add_colored_info(\$tview,"\tThe $jtag_intfc does not exists!. Press the compile button and select your FPGA board first to generate $jtag_intfc file\n", 'red');
$error=1;
}
return if($error);
my $command = "cd $target_dir/sw; sh program.sh";
1719,6 → 1844,8
my $compile = def_image_button('icons/gate.png','Compile RTL');
my $software = def_image_button('icons/binary.png','Software');
my $diagram = def_image_button('icons/diagram.png','Diagram');
my $unset = def_image_button('icons/intfc.png','Unset Intfc.');
my $ram = def_image_button('icons/RAM.png','Memory');
 
1726,7 → 1853,7
 
 
my $wb = def_image_button('icons/setting.png','Wishbone-bus addr');
my $wb = def_image_button('icons/setting.png','WB addr');
1755,8 → 1882,10
 
 
$main_table->attach ($open,0, 2, 19,20,'expand','shrink',2,2);
$main_table->attach_defaults ($entrybox,2, 4, 19,20);
$main_table->attach ($open,0, 1, 19,20,'expand','shrink',2,2);
$main_table->attach_defaults ($entrybox,1, 3, 19,20);
$main_table->attach ($unset, 3,4, 19,20,'expand','shrink',2,2);
$main_table->attach ($wb, 4,6, 19,20,'expand','shrink',2,2);
$main_table->attach ($diagram, 6, 7, 19,20,'expand','shrink',2,2);
$main_table->attach ($generate, 7, 8, 19,20,'expand','shrink',2,2);
1795,6 → 1924,9
my $sw_path = "$target_dir/sw";
$soc->object_add_attribute('global_param','CORE_ID',0);
$soc->object_add_attribute('global_param','SW_LOC',$sw_path);
unlink "$hw_dir/file_list";
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);
#message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
my $has_ni= check_for_ni($soc);
1823,6 → 1955,10
software_edit_soc($soc);
 
});
$unset-> signal_connect("clicked" => sub{
set_unset_infc($soc);
});
 
$ram-> signal_connect("clicked" => sub{
get_ram_init($soc);
1842,6 → 1978,7
my $sw_path = "$target_dir/sw";
my $top = "$target_dir/src_verilog/${name}_top.v";
if (-f $top){
unlink "$hw_dir/file_list";
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);
select_compiler($soc,$name,$top,$target_dir);
} else {
/software_editor.pl
88,51 → 88,16
$vpaned-> pack2 ($scwin_info, TRUE, TRUE);
 
 
my ($tree_view,$tree_store) =$self->build_tree_view($sw);
 
 
# Directory name, full path
my $tree_store = Gtk2::TreeStore->new('Glib::String', 'Glib::String');
my $tree_view = Gtk2::TreeView->new($tree_store);
my $column = Gtk2::TreeViewColumn->new_with_attributes('', Gtk2::CellRendererText->new(), text => "0");
$tree_view->append_column($column);
$tree_view->set_headers_visible(FALSE);
$tree_view->signal_connect (button_release_event => sub{
my $tree_model = $tree_view->get_model();
my $selection = $tree_view->get_selection();
my $iter = $selection->get_selected();
if(defined $iter){
my $path = $tree_model->get($iter, 1) ;
$path= substr $path, 0, -1;
$self->load_source($path) if(-f $path);
}
return;
});
 
 
$tree_view->signal_connect ('row-expanded' => sub {
my ($tree_view, $iter, $tree_path) = @_;
my $tree_model = $tree_view->get_model();
my ($dir, $path) = $tree_model->get($iter);
$scwin_dirs -> add($tree_view);
 
# for each of $iter's children add any subdirectories
my $child = $tree_model->iter_children ($iter);
while ($child) {
my ($dir, $path) = $tree_model->get($child, 0, 1);
add_to_tree($tree_view,$tree_store, $child, $dir, $path);
$child = $tree_model->iter_next ($child);
}
return;
});
 
 
$scwin_dirs -> add($tree_view);
 
 
 
my $child = $tree_store->append(undef);
$tree_store->set($child, 0, $sw, 1, '/');
add_to_tree($tree_view,$tree_store, $child, '/', "$sw/");
#print "$sw/\n";
 
#my $window = Gtk2::Window->new();
143,7 → 108,7
my $vbox = Gtk2::VBox->new(FALSE, 0);
$scwin_text->add_with_viewport($vbox);
 
$vbox->pack_start($self->build_menu, FALSE, FALSE, 0);
$vbox->pack_start($self->build_menu("$sw/",$window,$tree_view,$tree_store,$scwin_dirs), FALSE, FALSE, 0);
$vbox->pack_start($self->build_search_box, FALSE, FALSE, 0);
 
my $scroll = Gtk2::ScrolledWindow->new();
213,6 → 178,56
}
 
 
 
 
sub build_tree_view{
my ($self,$sw)=@_;
 
# Directory name, full path
my $tree_store = Gtk2::TreeStore->new('Glib::String', 'Glib::String');
my $tree_view = Gtk2::TreeView->new($tree_store);
my $column = Gtk2::TreeViewColumn->new_with_attributes('', Gtk2::CellRendererText->new(), text => "0");
$tree_view->append_column($column);
$tree_view->set_headers_visible(FALSE);
$tree_view->signal_connect (button_release_event => sub{
my $tree_model = $tree_view->get_model();
my $selection = $tree_view->get_selection();
my $iter = $selection->get_selected();
if(defined $iter){
my $path = $tree_model->get($iter, 1) ;
$path= substr $path, 0, -1;
$self->do_save();
#print "open $path\n";
$self->load_source($path) if(-f $path);
}
return;
});
 
 
$tree_view->signal_connect ('row-expanded' => sub {
my ($tree_view, $iter, $tree_path) = @_;
my $tree_model = $tree_view->get_model();
my ($dir, $path) = $tree_model->get($iter);
 
# for each of $iter's children add any subdirectories
my $child = $tree_model->iter_children ($iter);
while ($child) {
my ($dir, $path) = $tree_model->get($child, 0, 1);
add_to_tree($tree_view,$tree_store, $child, $dir, $path);
$child = $tree_model->iter_next ($child);
}
return;
});
 
my $child = $tree_store->append(undef);
$tree_store->set($child, 0, $sw, 1, '/');
add_to_tree($tree_view,$tree_store, $child, '/', "$sw/");
return ($tree_view,$tree_store);
 
}
 
 
 
sub build_search_box {
my $self = shift;
 
434,8 → 449,9
 
 
sub do_file_new {
my $self = shift;
my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs) = @_;
my $buffer = $self->buffer;
 
# Set no language
$buffer->set_language(undef);
450,6 → 466,7
 
$self->filename('');
$self->window->set_title("Untitled - $NAME");
$self->do_save_as($sw,$window,$tree_view,$tree_store,$scwin_dirs);
}
 
 
534,13 → 551,13
 
 
sub do_quit {
my $self = shift;
Gtk2->main_quit();
my ($self,$window) = @_;
$window->destroy;
}
 
 
sub do_save_as {
my $self = shift;
my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs) = @_;
 
# If no file is associated with the editor then ask the user for a file where
# to save the contents of the buffer.
549,13 → 566,28
'gtk-cancel' => 'cancel',
'gtk-save' => 'ok',
);
if(defined $sw){
$dialog->set_current_folder ($sw);
#print "open_in:$sw\n";
}
 
my $response = $dialog->run();
if ($response eq 'ok') {
$self->filename($dialog->get_filename);
my $file=$dialog->get_filename;
$self->filename($file);
$self->do_save();
$tree_view->destroy;
($tree_view,$tree_store) =$self->build_tree_view($sw);
$scwin_dirs->add($tree_view);
$scwin_dirs->show_all;
$self->load_source($file);
}
$dialog->destroy();
 
}
 
 
566,7 → 598,7
 
# If there's no file then do a save as...
if (! $filename) {
$self->do_save_as();
#$self->do_save_as();
return;
}
 
581,8 → 613,11
}
 
 
 
 
 
sub build_menu {
my $self = shift;
my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs) = @_;
 
my $entries = [
# name, stock id, label
597,7 → 632,7
"_New",
"<control>N",
"Create a new file",
sub { $self->do_file_new(@_) }
sub { $self->do_file_new($sw,$window,$tree_view,$tree_store,$scwin_dirs) }
],
[
"Open",
621,7 → 656,7
"Save _As...",
"<control><shift>S",
"Save to a file",
sub { $self->do_save_as(@_) }
sub { $self->do_save_as($sw,$window,$tree_view,$tree_store,$scwin_dirs) }
],
[
"Quit",
629,7 → 664,7
"_Quit",
"<control>Q",
"Quit",
sub { $self->do_quit() }
sub { $self->do_quit($window) }
],
[
"About",
/verilog_gen.pl
171,7 → 171,13
if(!%connected_plugs ){
my ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($id,$i_name);
my $v=$soc->soc_get_module_param_value($id,$s_value);
if ( length( $v || '' )){ $IO='no';} else {$IO='yes';}
if ( length( $v || '' )){ $IO='no';} else {
my $con= $soc->object_get_attribute("Unset-intfc" ,"$inst-$port");
if(!defined $con){ $IO='yes';}
else{
$IO='yes' if $con eq 'IO';
}
}
}
}
363,6 → 369,7
if($vfile_param_type eq "Localparam"){
$local_param_v="$local_param_v\tlocalparam\t$inst_param=$params{$param};\n";
$top_ip->top_add_localparam($id,$inst_param,$params{$param},$type,$content,$info,$vfile_param_type,$redefine_param);
}
elsif($vfile_param_type eq "Parameter"){
$param_v="$param_v\tparameter\t$inst_param=$params{$param};\n";
657,13 → 664,62
 
 
 
sub gen_soc_instance_v_no_modfy{
my ($soc,$soc_name,$param_pass_v)=@_;
my $soc_v;
my $processor_en=0;
 
my $mm="$soc_name #(\n $param_pass_v \n\t)the_${soc_name}(\n";
 
my $top=$soc->soc_get_top();
my @intfcs=$top->top_get_intfc_list();
my $i=0;
 
my $ss="";
my $ww="";
foreach my $intfc (@intfcs){
my @ports=$top->top_get_intfc_ports_list($intfc);
foreach my $p (@ports){
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
$mm="$mm," if ($i);
$mm="$mm\n\t\t.$p($p)";
$i=1;
}
}
$mm="$mm\n\t);";
add_text_to_string(\$soc_v,"$ww\n");
add_text_to_string(\$soc_v,"$mm\n");
add_text_to_string(\$soc_v,"$ss\n");
add_text_to_string(\$soc_v,"\n endmodule\n");
return $soc_v;
 
}
 
 
 
 
 
 
 
 
sub gen_system_info {
my ($soc,$param)=@_;
my ($wb_slaves,$wb_masters,$other,$jtag);
759,8 → 815,8
}elsif ($jtag_connect eq 'ALTERA_IMCE'){
#TODO add later
$prog= "$prog echo \"ALTERA_IMCE runtime programming is not supported yet for programming $instance_id\"\n";
} else{
#disabled check if its connected to jtag_wb via the bus
my $connect_id = $ram{$instance_id}{'connect'};
775,9 → 831,15
$prog= "$prog \$JTAG_INTFC -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i \"$BINFILE\" -c";
#print "prog= $prog\n";
}
}else{
$prog= "$prog echo \"JTAG runtime programming is not enabled in $instance_id\"\n";
}
}else{
$prog= "$prog echo \"JTAG runtime programming is not enabled in $instance_id\"\n";
}
}
845,14 → 907,112
 
 
 
######################
# soc_generate_verilog
#####################
 
sub soc_generate_verilatore{
my ($soc,$sw_path,$name,$params_ref)= @_;
my $soc_name=$soc->object_get_attribute('soc_name');
my $top_ip=ip_gen->top_gen_new();
if(!defined $soc_name){$soc_name='soc'};
my @instances=$soc->soc_get_all_instances();
my $io_sim_v;
my $io_top_sim_v;
my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
$core_id= 0 if(!defined $core_id);
my $param_as_in_v="\tparameter\tCORE_ID=$core_id,
\tparameter\tSW_LOC=\"$sw_path\"\n,";
 
my $param_pass_v="\t.CORE_ID(CORE_ID),\n\t.SW_LOC(SW_LOC)";
my $body_v;
my ($param_v_all, $local_param_v_all, $wire_def_v_all, $inst_v_all, $plugs_assign_v_all, $sockets_assign_v_all,$io_full_v_all,$io_top_full_v_all);
my $wires=soc->new_wires();
my $intfc=interface->interface_new();
foreach my $id (@instances){
my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v)=gen_module_inst($id,$soc,\$io_sim_v,\$io_top_sim_v,\$param_as_in_v,$top_ip,$intfc,$wires,\$param_pass_v);
my $inst = $soc->soc_get_instance_name($id);
add_text_to_string(\$body_v,"/*******************\n*\n*\t$inst\n*\n*\n*********************/\n");
add_text_to_string(\$local_param_v_all,"$local_param_v\n") if(defined($local_param_v));
add_text_to_string(\$wire_def_v_all,"$wire_def_v\n") if(defined($wire_def_v));
add_text_to_string(\$inst_v_all,$inst_v) if(defined($inst_v));
add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n") if(defined($plugs_assign_v));
add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
add_text_to_string(\$io_full_v_all,"$io_full_v\n") if(defined($io_full_v));
add_text_to_string(\$io_top_full_v_all,"$io_top_full_v\n") if(defined($io_top_full_v));
#print "$param_v $local_param_v $wire_def_v $inst_v $plugs_assign_v $sockets_assign_v $io_full_v";
}
my ($addr_map,$addr_localparam,$module_addr_localparam)= generate_address_cmp($soc,$wires);
 
#add functions
my $dir = Cwd::getcwd();
open my $file1, "<", "$dir/lib/verilog/functions.v" or die;
my $functions_all='';
while (my $f1 = readline ($file1)) {
$functions_all="$functions_all $f1 ";
}
close($file1);
my $unused_wiers_v=assign_unconnected_wires($wires,$intfc);
 
$soc->object_add_attribute('top_ip',undef,$top_ip);
#print @assigned_wires;
 
#generate topmodule
my $params_v="
\tparameter\tCORE_ID=$core_id;
\tparameter\tSW_LOC=\"$sw_path\";\n";
my %all_param=soc_get_all_parameters($soc);
my @order= soc_get_all_parameters_order($soc);
#replace global parameters
my @list=sort keys%{$params_ref};
foreach my $p (@list){
my %hash=%{$params_ref};
$all_param{$p}= $hash{$p};
}
foreach my $p (@order){
add_text_to_string(\$params_v,"\tlocalparam $p = $all_param{$p};\n") if(defined $all_param{$p} );
}
my $verilator_v = "
/*********************
${name}
*********************/
module ${name} (\n $io_top_sim_v\n);\n";
my $ins= gen_soc_instance_v_no_modfy($soc,$soc_name,$param_pass_v);
add_text_to_string(\$verilator_v,$functions_all);
add_text_to_string(\$verilator_v,$params_v."\n".$io_top_full_v_all);
add_text_to_string(\$verilator_v,$ins);
my ($readme,$prog)=gen_system_info($soc,$param_as_in_v);
return ($verilator_v);
 
 
}
 
 
 
 
 
 
 
1;
 
 
/widget.pl
1018,6 → 1018,26
 
}
 
 
sub remove_file_and_folders{
my ($file_ref,$project_dir)=@_;
 
foreach my $f(@{$file_ref}){
my $name= basename($f);
my $n="$project_dir$f";
if (-f "$n") { #copy file
unlink ("$n");
}elsif(-f "$f" ){
unlink ("$f");
}elsif (-d "$n") {#copy folder
rmtree ("$n");
}elsif(-d "$f" ){
rmtree ("$f");
}
}
 
}
 
sub read_file_cntent {
my ($f,$project_dir)=@_;
my $n="$project_dir$f";

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