Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

/ColorButton.pm

ColorButton.pm Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: common.pl =================================================================== --- common.pl (nonexistent) +++ common.pl (revision 43) @@ -0,0 +1,624 @@ +use strict; +use warnings; + +use String::Similarity; + + +sub find_the_most_similar_position{ + my ($item ,@list)=@_; + my $most_similar_pos=0; + my $lastsim=0; + my $i=0; + # convert item to lowercase + $item = lc $item; + foreach my $p(@list){ + my $similarity= similarity $item, $p; + if ($similarity > $lastsim){ + $lastsim=$similarity; + $most_similar_pos=$i; + } + $i++; + } + return $most_similar_pos; +} + + + +#################### +# file +################## + + +sub read_verilog_file{ + my @files = @_; + my %cmd_line_defines = (); + my $quiet = 1; + my @inc_dirs = (); + my @lib_dirs = (); + my @lib_exts = (); + my $vdb = rvp->read_verilog(\@files,[],\%cmd_line_defines, + $quiet,\@inc_dirs,\@lib_dirs,\@lib_exts); + + my @problems = $vdb->get_problems(); + if (@problems) { + foreach my $problem ($vdb->get_problems()) { + print STDERR "$problem.\n"; + } + # die "Warnings parsing files!"; + } + + return $vdb; +} + + + + +sub append_text_to_file { + my ($file_path,$text)=@_; + open(my $fd, ">>$file_path") or die "could not open $file_path: $!"; + print $fd $text; + close $fd; +} + + + + +sub save_file { + my ($file_path,$text)=@_; + open my $fd, ">$file_path" or die "could not open $file_path: $!"; + print $fd $text; + close $fd; +} + +sub load_file { + my $file_path=shift; + my $str; + if (-f "$file_path") { + + $str = do { + local $/ = undef; + open my $fh, "<", $file_path + or die "could not open $file_path: $!"; + <$fh>; + }; + + } + return $str; +} + +sub merg_files { + my ($source_file_path,$dest_file_path)=@_; + local $/=undef; + open FILE, $source_file_path or die "Couldn't open file: $!"; + my $string = ; + close FILE; + append_text_to_file ($dest_file_path,$string); +} + + + +sub copy_file_and_folders{ + my ($file_ref,$project_dir,$target_dir)=@_; + + foreach my $f(@{$file_ref}){ + my $name= basename($f); + + my $n="$project_dir$f"; + if (-f "$n") { #copy file + copy ("$n","$target_dir/$name"); + }elsif(-f "$f" ){ + copy ("$f","$target_dir/$name"); + }elsif (-d "$n") {#copy folder + dircopy ("$n","$target_dir/$name"); + }elsif(-d "$f" ){ + dircopy ("$f","$target_dir/$name"); + + } + } + +} + + +sub remove_file_and_folders{ + my ($file_ref,$project_dir)=@_; + + foreach my $f(@{$file_ref}){ + my $name= basename($f); + my $n="$project_dir$f"; + if (-f "$n") { #copy file + unlink ("$n"); + }elsif(-f "$f" ){ + unlink ("$f"); + }elsif (-d "$n") {#copy folder + rmtree ("$n"); + }elsif(-d "$f" ){ + rmtree ("$f"); + } + } + +} + +sub read_file_cntent { + my ($f,$project_dir)=@_; + my $n="$project_dir$f"; + my $str; + if (-f "$n") { + + $str = do { + local $/ = undef; + open my $fh, "<", $n + or die "could not open $n: $!"; + <$fh>; + }; + + }elsif(-f "$f" ){ + $str = do { + local $/ = undef; + open my $fh, "<", $f + or die "could not open $f: $!"; + <$fh>; + }; + + + } + return $str; + +} + + +sub check_file_has_string { + my ($file,$string)=@_; + my $r; + open(FILE,$file); + if (grep{/$string/} ){ + $r= 1; #print "word found\n"; + }else{ + $r= 0; #print "word not found\n"; + } + close FILE; + return $r; +} + +############## +# clone_obj +############# + +sub clone_obj{ + my ($self,$clone)=@_; + + foreach my $p (keys %$self){ + delete ($self->{$p}); + } + foreach my $p (keys %$clone){ + $self->{$p}= $clone->{$p}; + my $ref= ref ($clone->{$p}); + if( $ref eq 'HASH' ){ + + foreach my $q (keys %{$clone->{$p}}){ + $self->{$p}{$q}= $clone->{$p}{$q}; + my $ref= ref ($self->{$p}{$q}); + if( $ref eq 'HASH' ){ + + foreach my $z (keys %{$clone->{$p}{$q}}){ + $self->{$p}{$q}{$z}= $clone->{$p}{$q}{$z}; + my $ref= ref ($self->{$p}{$q}{$z}); + if( $ref eq 'HASH' ){ + + foreach my $w (keys %{$clone->{$p}{$q}{$z}}){ + $self->{$p}{$q}{$z}{$w}= $clone->{$p}{$q}{$z}{$w}; + my $ref= ref ($self->{$p}{$q}{$z}{$w}); + if( $ref eq 'HASH' ){ + + + foreach my $m (keys %{$clone->{$p}{$q}{$z}{$w}}){ + $self->{$p}{$q}{$z}{$w}{$m}= $clone->{$p}{$q}{$z}{$w}{$m}; + my $ref= ref ($self->{$p}{$q}{$z}{$w}{$m}); + if( $ref eq 'HASH' ){ + + foreach my $n (keys %{$clone->{$p}{$q}{$z}{$w}{$m}}){ + $self->{$p}{$q}{$z}{$w}{$m}{$n}= $clone->{$p}{$q}{$z}{$w}{$m}{$n}; + my $ref= ref ($self->{$p}{$q}{$z}{$w}{$m}{$n}); + if( $ref eq 'HASH' ){ + + foreach my $l (keys %{$clone->{$p}{$q}{$z}{$w}{$m}{$n}}){ + $self->{$p}{$q}{$z}{$w}{$m}{$n}{$l}= $clone->{$p}{$q}{$z}{$w}{$m}{$n}{$l}; + my $ref= ref ($self->{$p}{$q}{$z}{$w}{$m}{$n}{$l}); + if( $ref eq 'HASH' ){ + } + } + + }#if + }#n + }#if + }#m + }#if + }#w + }#if + }#z + }#if + }#q + }#if + }#p +}#sub + + +sub get_project_dir{ #mpsoc directory address + my $dir = Cwd::getcwd(); + my $project_dir = abs_path("$dir/../../"); + return $project_dir; +} + + +sub remove_project_dir_from_addr{ + my $file=shift; + my $project_dir = get_project_dir(); + $file =~ s/$project_dir//; + return $file; +} + +sub add_project_dir_to_addr{ + my $file=shift; + my $project_dir = get_project_dir(); + return $file if(-f $file ); + return "$project_dir/$file"; + +} + +sub get_full_path_addr{ + my $file=shift; + my $dir = Cwd::getcwd(); + my $full_path = "$dir/$file"; + return $full_path if -f ($full_path ); + return $file; +} + +sub regen_object { + my $path=shift; + $path = get_full_path_addr($path); + my $pp= eval { do $path }; + my $r= ($@ || !defined $pp); + return ($pp,$r,$@); +} + + +################ +# general +################# + + + + +sub trim { my $s = shift; $s=~s/[\n]//gs; return $s }; + +sub remove_all_white_spaces($) +{ + my $string = shift; + $string =~ s/\s+//g; + return $string; +} + + + + +sub get_scolar_pos{ + my ($item,@list)=@_; + my $pos; + my $i=0; + foreach my $c (@list) + { + if( $c eq $item) {$pos=$i} + $i++; + } + return $pos; +} + +sub remove_scolar_from_array{ + my ($array_ref,$item)=@_; + my @array=@{$array_ref}; + my @new; + foreach my $p (@array){ + if($p ne $item ){ + push(@new,$p); + } + } + return @new; +} + +sub replace_in_array{ + my ($array_ref,$item1,$item2)=@_; + my @array=@{$array_ref}; + my @new; + foreach my $p (@array){ + if($p eq $item1 ){ + push(@new,$item2); + }else{ + push(@new,$p); + } + } + return @new; +} + + + +# return an array of common elemnts between two input arays +sub get_common_array{ + my ($a_ref,$b_ref)=@_; + my @A=@{$a_ref}; + my @B=@{$b_ref}; + my @C; + foreach my $p (@A){ + if( grep (/^\Q$p\E$/,@B)){push(@C,$p)}; + } + return @C; +} + +#a-b +sub get_diff_array{ + my ($a_ref,$b_ref)=@_; + my @A=@{$a_ref}; + my @B=@{$b_ref}; + my @C; + foreach my $p (@A){ + if( !grep (/^\Q$p\E$/,@B)){push(@C,$p)}; + } + return @C; + +} + + + +sub compress_nums{ + my @nums=@_; + my @f=sort { $a <=> $b } @nums; + my $s; + my $ls; + my $range=0; + my $x; + + + foreach my $p (@f){ + if(!defined $x) { + $s="$p"; + $ls=$p; + + } + else{ + if($p-$x>1){ #gap exist + if( $range){ + $s=($x-$ls>1 )? "$s:$x,$p": "$s,$x,$p"; + $ls=$p; + $range=0; + }else{ + $s= "$s,$p"; + $ls=$p; + + } + + }else {$range=1;} + + + + } + + $x=$p + } + if($range==1){ $s= ($x-$ls>1 )? "$s:$x": "$s,$x";} + #update $s($ls,$hs); + + return $s; + +} + + + +sub metric_conversion{ + my $size=shift; + my $size_text= $size==0 ? 'Error': + $size<(1 << 10)? $size: + $size<(1 << 20)? join (' ', ($size>>10,"K")) : + $size<(1 << 30)? join (' ', ($size>>20,"M")) : + join (' ', ($size>>30,"G")) ; +return $size_text; +} + + + + + +###### +# state +##### +sub set_gui_status{ + my ($object,$status,$timeout)=@_; + $object->object_add_attribute('gui_status','status',$status); + $object->object_add_attribute('gui_status','timeout',$timeout); +} + + +sub get_gui_status{ + my ($object)=@_; + my $status= $object->object_get_attribute('gui_status','status'); + my $timeout=$object->object_get_attribute('gui_status','timeout'); + return ($status,$timeout); +} + + + + +########### +# color +######### + + + +sub get_color { + my $num=shift; + + my @colors=( + 0x6495ED,#Cornflower Blue + 0xFAEBD7,#Antiquewhite + 0xC71585,#Violet Red + 0xC0C0C0,#silver + 0xADD8E6,#Lightblue + 0x6A5ACD,#Slate Blue + 0x00CED1,#Dark Turquoise + 0x008080,#Teal + 0x2E8B57,#SeaGreen + 0xFFB6C1,#Light Pink + 0x008000,#Green + 0xFF0000,#red + 0x808080,#Gray + 0x808000,#Olive + 0xFF69B4,#Hot Pink + 0xFFD700,#Gold + 0xDAA520,#Goldenrod + 0xFFA500,#Orange + 0x32CD32,#LimeGreen + 0x0000FF,#Blue + 0xFF8C00,#DarkOrange + 0xA0522D,#Sienna + 0xFF6347,#Tomato + 0x0000CD,#Medium Blue + 0xFF4500,#OrangeRed + 0xDC143C,#Crimson + 0x9932CC,#Dark Orchid + 0x800000,#marron + 0x800080,#Purple + 0x4B0082,#Indigo + 0xFFFFFF,#white + 0x000000 #Black + ); + + my $color= ($num< scalar (@colors))? $colors[$num]: 0xFFFFFF; + my $red= ($color & 0xFF0000) >> 8; + my $green= ($color & 0x00FF00); + my $blue= ($color & 0x0000FF) << 8; + + return ($red,$green,$blue); + +} + + +sub get_color_hex_string { + my $num=shift; + + my @colors=( + "6495ED",#Cornflower Blue + "FAEBD7",#Antiquewhite + "C71585",#Violet Red + "C0C0C0",#silver + "ADD8E6",#Lightblue + "6A5ACD",#Slate Blue + "00CED1",#Dark Turquoise + "008080",#Teal + "2E8B57",#SeaGreen + "FFB6C1",#Light Pink + "008000",#Green + "FF0000",#red + "808080",#Gray + "808000",#Olive + "FF69B4",#Hot Pink + "FFD700",#Gold + "DAA520",#Goldenrod + "FFA500",#Orange + "32CD32",#LimeGreen + "0000FF",#Blue + "FF8C00",#DarkOrange + "A0522D",#Sienna + "FF6347",#Tomato + "0000CD",#Medium Blue + "FF4500",#OrangeRed + "DC143C",#Crimson + "9932CC",#Dark Orchid + "800000",#marron + "800080",#Purple + "4B0082",#Indigo + "FFFFFF",#white + "000000" #Black + ); + + my $color= ($num< scalar (@colors))? $colors[$num]: "FFFFFF"; + return $color; + +} + + + + + +sub check_verilog_identifier_syntax { + my $in=shift; + my $error=0; + my $message=''; +# an Identifiers must begin with an alphabetic character or the underscore character + if ($in =~ /^[0-9\$]/){ + return 'an Identifier must begin with an alphabetic character or the underscore character'; + } + + +# Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $ ) + if ($in =~ /[^a-zA-Z0-9_\$]+/){ + print "use of illegal character after\n" ; + my @w= split /([^a-zA-Z0-9_\$]+)/, $in; + return "Contain illegal character of \"$w[1]\". Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ \$ )\n"; + + } + + +# check Verilog reserved words + my @keys = ("always","and","assign","automatic","begin","buf","bufif0","bufif1","case","casex","casez","cell","cmos","config","deassign","default","defparam","design","disable","edge","else","end","endcase","endconfig","endfunction","endgenerate","endmodule","endprimitive","endspecify","endtable","endtask","event","for","force","forever","fork","function","generate","genvar","highz0","highz1","if","ifnone","incdir","include","initial","inout","input","instance","integer","join","large","liblist","library","localparam","macromodule","medium","module","nand","negedge","nmos","nor","noshowcancelled","not","notif0","notif1","or","output","parameter","pmos","posedge","primitive","pull0","pull1","pulldown","pullup","pulsestyle_onevent","pulsestyle_ondetect","remos","real","realtime","reg","release","repeat","rnmos","rpmos","rtran","rtranif0","rtranif1","scalared","showcancelled","signed","small","specify","specparam","strong0","strong1","supply0","supply1","table","task","time","tran","tranif0","tranif1","tri","tri0","tri1","triand","trior","trireg","unsigned","use","vectored","wait","wand","weak0","weak1","while","wire","wor","xnor","xor"); + if( grep (/^$in$/,@keys)){ + return "$in is a Verlig reserved word."; + } + return undef; + +} + + +sub capture_number_after { + my ($after,$text)=@_; + my @q =split (/$after/,$text); + #my $d=$q[1]; + my @d = split (/[^0-9. ]/,$q[1]); + return $d[0]; + +} + +sub capture_string_between { + my ($start,$text,$end)=@_; + my @q =split (/$start/,$text); + my @d = split (/$end/,$q[1]); + return $d[0]; +} + + +sub make_undef_as_string { + foreach my $p (@_){ + $$p= 'undef' if (! defined $$p); + + } +} + +sub powi{ # x^y + my ($x,$y)=@_; # compute x to the y + my $r=1; + for (my $i = 0; $i < $y; ++$i ) { + $r *= $x; + } + return $r; +} + +sub sum_powi{ # x^(y-1) + x^(y-2) + ...+ 1; + my ($x,$y)=@_; # compute x to the y + my $r = 0; + for (my $i = 0; $i < $y; $i++){ + $r += powi( $x, $i ); + } + return $r; +} + + + + +1 +

common.pl Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: compile.pl =================================================================== --- compile.pl (revision 42) +++ compile.pl (revision 43) @@ -2,11 +2,13 @@ use Glib qw/TRUE FALSE/; use strict; use warnings; + +use FindBin; +use lib $FindBin::Bin; + use soc; -#use ip; -#use interface; -#use POSIX 'strtol'; + use File::Path; use File::Find::Rule; use File::Copy; @@ -15,7 +17,6 @@ use Verilog::EditFiles; use Gtk2; -#use Gtk2::Pango; use List::MoreUtils qw( minmax ); @@ -201,12 +202,6 @@ - - - - - - sub select_compiler { my ($self,$name,$top,$target_dir,$end_func)=@_; my $window = def_popwin_size(40,40,"Step 1: Select Compiler",'percent'); @@ -401,7 +396,7 @@ my $widgets= add_new_fpga_board_widgets($self,$name,$top,$target_dir,$end_func); my ($Twin,$tview)=create_text(); - add_colors_to_textview($tview); + my $v1=gen_vpaned($widgets,0.3,$Twin); @@ -541,8 +536,6 @@ }); - - $window->add ($mtable); $window->show_all(); @@ -551,12 +544,6 @@ - - - - - - sub add_new_fpga_board_widgets{ my ($self,$name,$top,$target_dir,$end_func)=@_; my $table = def_table(2, 2, FALSE); @@ -758,27 +745,21 @@ $mtable->attach_defaults($scrolled_win,0,10,0,9); $mtable->attach($back,2,3,9,10,'shrink','shrink',2,2); $mtable->attach($next,8,9,9,10,'shrink','shrink',2,2); - - - - my $board_name=$self->object_get_attribute('compile','board'); #copy board jtag_intfc.sh file my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$"); copy("../boards/$board_name/jtag_intfc.sh","${fpath}../sw/jtag_intfc.sh"); - my $n= $self->object_get_attribute('soc_name',undef); - if(!defined $n){ # we are compiling a complete NoC-based mpsoc - my $nx= $self->object_get_attribute('noc_param',"NX"); - my $ny= $self->object_get_attribute('noc_param',"NY"); - for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){ - my $tile_num= $y*$nx+$x; - #print "$tile_num\n"; + my $m= $self->object_get_attribute('mpsoc_name',undef); + if(defined $m){ # we are compiling a complete NoC-based mpsoc + my ($nr,$ne,$router_p,$ref_tops)= get_noc_verilator_top_modules_info($self); + for (my $tile_num=0;$tile_num<$ne;$tile_num++){ + #print "$tile_num\n"; my ($soc_name,$num)= $self->mpsoc_get_tile_soc_name($tile_num); next if(!defined $soc_name); copy("../boards/$board_name/jtag_intfc.sh","${fpath}../sw/tile$tile_num/jtag_intfc.sh"); - }} + } } @@ -878,10 +859,8 @@ $box=get_range ($board,$self,$type,$text,$portrange,$p); $table->attach($box, 5,6, $loc, $loc+1,'fill','shrink',2,2); } + - - - $combo->signal_connect("changed" => sub{ #get and saved new value @@ -902,12 +881,6 @@ $table->attach($combo, 4,5, $row, $row+1,'fill','shrink',2,2); - - - - - - $row++; } @@ -951,7 +924,7 @@ my ($app,$table,$tview,$window) = software_main($fpath,'Top.v'); $table->attach($back,1,2,1,2,'shrink','shrink',2,2); $table->attach($regen,4,5,1,2,'shrink','shrink',2,2); - $table->attach ($run,7, 8, 1,2,'shrink','shrink',2,2); + $table->attach ($run,6, 7, 1,2,'shrink','shrink',2,2); $table->attach($prog,9,10,1,2,'shrink','shrink',2,2); @@ -982,7 +955,11 @@ #compile - $run-> signal_connect("clicked" => sub{ + $run-> signal_connect("clicked" => sub{ + my $load= show_gif("icons/load.gif"); + $table->attach ($load,8, 9, 1,2,'shrink','shrink',2,2); + $load->show_all; + set_gui_status($self,'save_project',1); $app->do_save(); my $error = 0; @@ -1065,6 +1042,7 @@ message_dialog("Error in Quartus compilation!",'error'); } } + $load->destroy; }); @@ -1105,8 +1083,7 @@ } } - }); - + }); } @@ -1124,7 +1101,7 @@ my $back=def_image_button('icons/left.png','Previous'); my $regen=def_image_button('icons/refresh.png','Regenerate testbench.v'); #create testbench.v - gen_modelsim_soc_testbench ($self,$name,$top,$target_dir) if ((-f "$target_dir/src_verilog/testbench.v")==0); + gen_modelsim_soc_testbench ($self,$name,$top,$target_dir) unless (-f "$target_dir/src_verilog/testbench.v"); @@ -1150,11 +1127,6 @@ }); - - - - - $back-> signal_connect("clicked" => sub{ $window->destroy; @@ -1242,13 +1214,17 @@ rmtree("$verilator/processed_rtl"); mkpath("$verilator/rtl_work/",1,01777); mkpath("$verilator/processed_rtl/",1,01777); - + my @ff = ("$target_dir/src_verilog"); + push (@ff,"$target_dir/src_verilator") if (-d "$target_dir/src_verilator"); + + + #copy all verilog files in rtl_work folder add_info(\$outtext,"Copy all verilog files in rtl_work folder\n"); my @files = File::Find::Rule->file() ->name( '*.v','*.V','*.sv','*.vh') - ->in( "$target_dir/src_verilog","$target_dir/src_verilator" ); + ->in( @ff ); foreach my $file (@files) { copy($file,"$verilator/rtl_work/"); } @@ -1255,7 +1231,7 @@ @files = File::Find::Rule->file() ->name( '*.sv','*.vh' ) - ->in( "$target_dir/src_verilog","$target_dir/src_verilator" ); + ->in( @ff ); foreach my $file (@files) { copy($file,"$verilator/processed_rtl"); } @@ -1359,13 +1335,8 @@ rm *.o *.a testbench "; - - save_file ($target_dir,$make); - - - } @@ -1375,14 +1346,16 @@ my $window = def_popwin_size(80,80,"Step 2: Compile",'percent'); my $mtable = def_table(10, 10, FALSE); my ($outbox,$outtext)= create_text(); - add_colors_to_textview($outtext); + + my $next=def_image_button('icons/run.png','Next'); my $back=def_image_button('icons/left.png','Previous'); + my $load= show_gif("icons/load.gif"); + $mtable->attach($load,8,9,9,10,'shrink','shrink',2,2); - $mtable->attach_defaults ($outbox ,0, 10, 4,9); $mtable->attach($back,2,3,9,10,'shrink','shrink',2,2); - $mtable->attach($next,8,9,9,10,'shrink','shrink',2,2); + @@ -1422,18 +1395,13 @@ #check if verilator model has been generated if ($result){ add_colored_info(\$outtext,"Veriator model has been generated successfully!",'blue'); + $load->destroy(); + $mtable->attach($next,8,9,9,10,'shrink','shrink',2,2); }else { add_colored_info(\$outtext,"Verilator compilation failed!\n","red"); + $load->destroy(); $next->destroy(); } - - - - - - - - } @@ -1445,26 +1413,36 @@ my $dir = Cwd::getcwd(); my $project_dir = abs_path("$dir/.."); my $src_verilator_dir="$project_dir/src_verilator"; + my $target_verilog_dr ="$target_dir/src_verilog"; + my $target_verilator_dr ="$target_dir/src_verilator"; + my $sw_dir = "$target_dir/sw"; - - + my $src_noc_dir="$project_dir/src_noc"; + mkpath("$target_verilator_dr",1,01777); + #copy src_verilator files - add_info(\$outtext,"Copy verilator files\n"); - my @files=( - "$src_verilator_dir/noc_connection.sv", - "$src_verilator_dir/router_verilator.v" - ); - if (-d "$target_dir/src_verilator/"==0){ - mkpath("$target_dir/src_verilator/",1,01777); + my @files_list = File::Find::Rule->file() + ->name( '*.v','*.V','*.sv' ) + ->in( "$src_verilator_dir" ); + + #make sure source files have key word 'module' + my @files; + foreach my $p (@files_list){ + push (@files,$p) if(check_file_has_string($p,'module')); } - copy_file_and_folders (\@files,$project_dir,"$target_dir/src_verilator"); + copy_file_and_folders (\@files,$project_dir,$target_verilator_dr); - #create each tile top module - my $nx= $self->object_get_attribute('noc_param',"NX"); - my $ny= $self->object_get_attribute('noc_param',"NY"); + + + #copy src_noc files + #my @files2; + #push (@files2,$src_noc_dir); + #copy_file_and_folders (\@files2,$project_dir,$target_verilog_dr); + + + #create each tile top module my $processors_en=0; - my $mpsoc=$self; - + my $mpsoc=$self; my $lisence= get_license_header("verilator_tiles"); my $warning=autogen_warning(); my $verilator=$lisence.$warning; @@ -1475,59 +1453,44 @@ my $noc_param_v= " \`ifdef INCLUDE_PARAM \n \n $noc_param - /* verilator lint_off WIDTH */ - localparam P=(TOPOLOGY==\"RING\" || TOPOLOGY==\"LINE\")? 3 : 5; - localparam ROUTE_TYPE = (ROUTE_NAME == \"XY\" || ROUTE_NAME == \"TRANC_XY\" )? \"DETERMINISTIC\" : - (ROUTE_NAME == \"DUATO\" || ROUTE_NAME == \"TRANC_DUATO\" )? \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\"; - /* verilator lint_on WIDTH */ + //simulation parameter \n \n \`endif" ; - save_file("$target_dir/src_verilator/parameter.v",$noc_param_v); + save_file("$target_verilator_dr/parameter.v",$noc_param_v); - - - my %tops = ( - "Vrouter" => "router_verilator.v", - "Vnoc" => "noc_connection.sv" - ); - for (my $y=0;$y<$ny;$y++){ - for (my $x=0; $x<$nx;$x++){ - - my $tile_num= $y*$nx+$x; + + + my ($nr,$ne,$router_p,$ref_tops)= get_noc_verilator_top_modules_info($self); + my %tops = %{$ref_tops}; + + for (my $tile_num=0;$tile_num<$ne;$tile_num++){ + #print "$tile_num\n"; my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num); - if(!defined $soc_name){ - #this tile is not connected to any ip. the noc input ports will be connected to ground - my $soc_v="\n\n // Tile:$tile_num (x=$x,y=$y) is not assigned to any ip\n"; - $soc_v="$soc_v - - assign ni_credit_out[$tile_num]={V{1'b0}}; - assign ni_flit_out[$tile_num]={Fw{1'b0}}; - assign ni_flit_out_wr[$tile_num]=1'b0; - "; - next; - - } + my $soc=eval_soc($mpsoc,$soc_name,$outtext); my $top=$mpsoc->mpsoc_get_soc($soc_name); - my $soc_num= $y*$nx+$x; + my $soc_num= $tile_num; - - #update core id $soc->object_add_attribute('global_param','CORE_ID',$tile_num); + #update NoC param - #my %nocparam = %{$mpsoc->object_get_attribute('noc_param',undef)}; my $nocparam =$mpsoc->object_get_attribute('noc_param',undef); + my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc); + my %y=%{$nocparam}; + $y{'EAw'} = $EAw; + $y{'RAw'} = $RAw; + $y{'Fw'} = $Fw; my @nis=get_NI_instance_list($top); - $soc->soc_add_instance_param($nis[0] ,$nocparam ); - my $tile=($nx*$y)+ $x; + $soc->soc_add_instance_param($nis[0] ,\%y ); + my $tile=$tile_num; my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile); my %params; if ($setting eq 'Custom'){ @@ -1542,9 +1505,9 @@ $tops{"Vtile$tile_num"}= "tile_$tile.v"; - }} + } - save_file ("$target_dir/src_verilator/verilator_tiles.v",$verilator); + save_file ("$target_verilator_dr/verilator_tiles.v",$verilator); my $result = verilator_compilation (\%tops,$target_dir,$outtext); $self->object_add_attribute('verilator','libs',\%tops); return $result; @@ -1651,9 +1614,9 @@ my $path=$mpsoc->object_get_attribute('setting','soc_path'); $path=~ s/ /\\ /g; my $p = "$path/$soc_name.SOC"; - my $soc = eval { do $p }; - if ($@ || !defined $soc){ - show_info(\$outtext,"**Error reading $p file: $@\n"); + my ($soc,$r,$err) = regen_object($p); + if ($r){ + show_info(\$outtext,"**Error reading $p file: $err\n"); next; } return $soc; @@ -1664,17 +1627,18 @@ my ($mpsoc,$name,$top,$target_dir,$tview)=@_; my $verilator="$target_dir/verilator"; my $dir="$verilator/"; - #my $soc_top= $self->soc_get_top (); + my $parameter_h=gen_noc_param_h($mpsoc); - my $nx= $mpsoc->object_get_attribute('noc_param',"NX"); - my $ny= $mpsoc->object_get_attribute('noc_param',"NY"); + my ($nr,$ne,$router_p,$ref_tops,$includ_h)= get_noc_verilator_top_modules_info($mpsoc); + $parameter_h=$parameter_h.$includ_h; + + my $libh=""; my $inst= ""; my $newinst=""; - my $tile_x=""; - my $tile_y=""; + my $tile_addr=""; my $tile_flit_in=""; my $tile_flit_in_l=""; my $tile_credit=""; @@ -1693,9 +1657,14 @@ my $top_port_info="IO type\t port_size\t port_name\n"; my $no_connected=''; - for (my $y=0;$y<$ny;$y++){for (my $x=0; $x<$nx;$x++){ - my $t= $y*$nx+$x; - my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($t); + for (my $endp=0; $endp<$ne;$endp++){ + + my $e_addr=endp_addr_encoder($mpsoc,$endp); + my $router_num = get_connected_router_id_to_endp($mpsoc,$endp); + my $r_addr=router_addr_encoder($mpsoc,$router_num); + + + my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($endp); if(defined $soc_name) {#we have a conncted tile #get ni instance name @@ -1712,27 +1681,23 @@ } - $libh=$libh."#include \"Vtile${t}.h\"\n"; - $inst=$inst."Vtile${t}\t*tile${t};\t // Instantiation of tile${t}\n"; - $newinst = $newinst."\ttile${t}\t=\tnew Vtile${t};\n"; - $tile_flit_in = $tile_flit_in . "\ttile${t}->${ni_name}_flit_in = noc->ni_flit_out [${t}];\n"; - $tile_flit_in_l = $tile_flit_in_l . "\t\ttile${t}->${ni_name}_flit_in[j] = noc->ni_flit_out [${t}][j];\n"; - $tile_credit= $tile_credit."\ttile${t}->${ni_name}_credit_in= noc->ni_credit_out[${t}];\n"; - $noc_credit= $noc_credit."\tnoc->ni_credit_in[${t}] = tile${t}->${ni_name}_credit_out;\n"; - $noc_flit_in=$noc_flit_in."\tnoc->ni_flit_in [${t}] = tile${t}->${ni_name}_flit_out;\n"; - $noc_flit_in_l=$noc_flit_in_l."\t\t\tnoc->ni_flit_in [${t}][j] = tile${t}->${ni_name}_flit_out[j];\n"; - $noc_flit_in_wr= $noc_flit_in_wr."\tif(tile${t}->${ni_name}_flit_out_wr) noc->ni_flit_in_wr = noc->ni_flit_in_wr | ((vluint64_t)1<<${t});\n"; - $tile_flit_in_wr=$tile_flit_in_wr."\ttile${t}->${ni_name}_flit_in_wr= ((noc->ni_flit_out_wr >> ${t}) & 0x01);\n"; - $noc_flit_in_wr_l= $noc_flit_in_wr_l."\tif(tile${t}->${ni_name}_flit_out_wr) MY_VL_SETBIT_W(noc->ni_flit_in_wr ,${t});\n"; - $tile_flit_in_wr_l=$tile_flit_in_wr_l."\ttile${t}->${ni_name}_flit_in_wr= (VL_BITISSET_W(noc->ni_flit_out_wr,${t})>0);\n"; - $tile_eval=$tile_eval."\ttile${t}->eval();\n"; - $tile_final=$tile_final."\ttile${t}->final();\n"; + $libh=$libh."#include \"Vtile${endp}.h\"\n"; + $inst=$inst."Vtile${endp}\t*tile${endp};\t // Instantiation of tile${endp}\n"; + $newinst = $newinst."\ttile${endp}\t=\tnew Vtile${endp};\n"; + $tile_flit_in = $tile_flit_in . "\ttile${endp}->${ni_name}_flit_in = noc->ni_flit_out [${endp}];\n"; + $tile_flit_in_l = $tile_flit_in_l . "\t\ttile${endp}->${ni_name}_flit_in[j] = noc->ni_flit_out [${endp}][j];\n"; + $tile_credit= $tile_credit."\ttile${endp}->${ni_name}_credit_in= noc->ni_credit_out[${endp}];\n"; + $noc_credit= $noc_credit."\tnoc->ni_credit_in[${endp}] = tile${endp}->${ni_name}_credit_out;\n"; + $noc_flit_in=$noc_flit_in."\tnoc->ni_flit_in [${endp}] = tile${endp}->${ni_name}_flit_out;\n"; + $noc_flit_in_l=$noc_flit_in_l."\t\t\tnoc->ni_flit_in [${endp}][j] = tile${endp}->${ni_name}_flit_out[j];\n"; + $noc_flit_in_wr= $noc_flit_in_wr."\tif(tile${endp}->${ni_name}_flit_out_wr) noc->ni_flit_in_wr = noc->ni_flit_in_wr | ((vluint64_t)1<<${endp});\n"; + $tile_flit_in_wr=$tile_flit_in_wr."\ttile${endp}->${ni_name}_flit_in_wr= ((noc->ni_flit_out_wr >> ${endp}) & 0x01);\n"; + $noc_flit_in_wr_l= $noc_flit_in_wr_l."\tif(tile${endp}->${ni_name}_flit_out_wr) MY_VL_SETBIT_W(noc->ni_flit_in_wr ,${endp});\n"; + $tile_flit_in_wr_l=$tile_flit_in_wr_l."\ttile${endp}->${ni_name}_flit_in_wr= (VL_BITISSET_W(noc->ni_flit_out_wr,${endp})>0);\n"; + $tile_eval=$tile_eval."\ttile${endp}->eval();\n"; + $tile_final=$tile_final."\ttile${endp}->final();\n"; - - - - foreach my $intfc (@intfcs){ my $key=($intfc eq 'plug:clk[0]')? 'clk' : ($intfc eq 'plug:reset[0]')? 'reset': @@ -1742,26 +1707,28 @@ my @ports=$soc_top->top_get_intfc_ports_list($intfc); foreach my $p (@ports){ my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p); - $tile_reset=$tile_reset."\t\ttile${t}->$p=reset;\n" if $key eq 'reset'; - $tile_clk=$tile_clk."\t\ttile${t}->$p=clk;\n" if $key eq 'clk'; - $tile_en=$tile_en."\t\ttile${t}->$p=enable;\n" if $key eq 'en'; ; - $top_port_info="$top_port_info $type $range tile${t}->$p \n"; + $tile_reset=$tile_reset."\t\ttile${endp}->$p=reset;\n" if $key eq 'reset'; + $tile_clk=$tile_clk."\t\ttile${endp}->$p=clk;\n" if $key eq 'clk'; + $tile_en=$tile_en."\t\ttile${endp}->$p=enable;\n" if $key eq 'en'; ; + $top_port_info="$top_port_info $type $range tile${endp}->$p \n"; }#ports }#interface - $tile_x= $tile_x."\ttile${t}->${ni_name}_current_x=$x;\n"; - $tile_y= $tile_y."\ttile${t}->${ni_name}_current_y=$y;\n"; + $tile_addr= $tile_addr."\ttile${endp}->${ni_name}_current_r_addr=$r_addr; // noc->er_addr[${endp}];\n"; + $tile_addr= $tile_addr."\ttile${endp}->${ni_name}_current_e_addr=$e_addr;\n"; + }else{ #this tile is not connected to any ip. the noc input ports will be connected to ground - $no_connected=$no_connected."\n // Tile:$t (x=$x,y=$y) is not assigned to any ip\n"; - $no_connected=$no_connected."\t\tnoc->ni_credit_in[${t}]=0; \n"; + $no_connected=$no_connected."\n // Tile:$endp ($e_addr) is not assigned to any ip\n"; + $no_connected=$no_connected."\t\tnoc->ni_credit_in[${endp}]=0; \n"; } - }} + } my $main_c=get_license_header("testbench.cpp"); + $main_c="$main_c #include #include @@ -1770,35 +1737,21 @@ #include // Defines common routines #include \"Vnoc.h\" -#include \"Vrouter.h\" $libh +Vnoc *noc; +$inst +int reset,clk,enable; + +#include \"parameter.h\" + + /* $top_port_info */ -#ifndef NX - #define NX $nx -#endif - -#ifndef NY - #define NY $ny -#endif - -#ifndef NC - #define NC ($nx*$ny) -#endif - - -Vrouter *router[NC]; // Instantiation of router -Vnoc *noc; -$inst - - - -int reset,clk,enable; unsigned int main_time = 0; // Current simulation time void update_all_instances_inputs(void); @@ -1808,8 +1761,7 @@ int i,j,x,y; Verilated::commandArgs(argc, argv); // Remember args - - for(i=0;icurrent_x = x; - router[i]->current_y = y; - } -$tile_x -$tile_y + +$tile_addr + main_time=0; printf(\"Start Simulation\\n\"); while (!Verilated::gotFinish()) { @@ -1858,16 +1806,13 @@ $tile_reset $tile_clk $tile_en - for(i=0;ireset= reset; - router[i]->clk= clk; - } + + connect_routers_reset_clk(); //eval instances noc->eval(); - for(i=0;ieval(); - } + routers_eval(); + $tile_eval @@ -1877,10 +1822,8 @@ }//while - // Simulation is dne - for(i=0;ifinal(); - } + // Simulation is done + routers_final(); noc->final(); $tile_final } @@ -1893,7 +1836,7 @@ void update_all_instances_inputs(void){ int x,y,i,j; - int flit_out_all_size = sizeof(router[0]->flit_out_all)/sizeof(router[0]->flit_out_all[0]); + #if (NC<=64) noc->ni_flit_in_wr =0; @@ -1900,20 +1843,9 @@ #else for(j=0;j<(sizeof(noc->ni_flit_in_wr)/sizeof(noc->ni_flit_in_wr[0])); j++) noc->ni_flit_in_wr[j]=0; #endif - for(x=0;xflit_in_we_all = noc->router_flit_out_we_all[i]; - router[i]->credit_in_all = noc->router_credit_out_all[i]; - router[i]->congestion_in_all = noc->router_congestion_out_all[i]; - for(j=0;jflit_in_all[j] = noc->router_flit_out_all[i][j]; - noc->router_flit_in_we_all[i] = router[i]->flit_out_we_all ; - noc->router_credit_in_all[i] = router[i]->credit_out_all; - noc->router_congestion_in_all[i]= router[i]->congestion_out_all; - for(j=0;jrouter_flit_in_all[i][j] = router[i]->flit_out_all[j] ; - } //for - - + connect_all_routers_to_noc (); + #if (Fpay<=32) //tile[i]->flit_in = noc->ni_flit_out [i]; @@ -1963,6 +1895,7 @@ } "; + save_file("$dir/parameter.h",$parameter_h); save_file("$dir/testbench.cpp",$main_c); } @@ -1992,7 +1925,7 @@ $vfile_param_type= "Parameter" if ($vfile_param_type eq 1); $vfile_param_type= "Localparam" if ($vfile_param_type eq 0); $all_param{ $inst_param} = $params{ $p} if($vfile_param_type eq "Parameter" || $vfile_param_type eq "Localparam" ); - print"$all_param{ $inst_param} = $params{ $p} if($vfile_param_type eq \"Parameter\" || $vfile_param_type eq \"Localparam\" ); \n"; + #print"$all_param{ $inst_param} = $params{ $p} if($vfile_param_type eq \"Parameter\" || $vfile_param_type eq \"Localparam\" ); \n"; } } return %all_param; @@ -2194,9 +2127,11 @@ my $run = def_image_button('icons/run.png','Run'); my $back=def_image_button('icons/left.png','Previous'); + + $table->attach ($back,1,2,1,2,'shrink','shrink',0,0); $table->attach ($regen,3,4,1,2,'shrink','shrink',0,0); - $table->attach ($make,7, 8, 1,2,'shrink','shrink',0,0); + $table->attach ($make,6, 7, 1,2,'shrink','shrink',0,0); $table->attach ($run,9, 10, 1,2,'shrink','shrink',0,0); $back-> signal_connect("clicked" => sub{ @@ -2231,8 +2166,13 @@ $make -> signal_connect("clicked" => sub{ + $make->hide_all; + my $load= show_gif("icons/load.gif"); + $table->attach ($load,8, 9, 1,2,'shrink','shrink',0,0); + $table->show_all; $app->do_save(); copy("$dir/testbench.cpp", "$verilator/processed_rtl/obj_dir/testbench.cpp"); + copy("$dir/parameter.h", "$verilator/processed_rtl/obj_dir/parameter.h") if(-f "$dir/parameter.h"); my $tops_ref=$self->object_get_attribute('verilator','libs'); my %tops=%{$tops_ref}; @@ -2243,7 +2183,9 @@ $lib_num++; } run_make_file("$verilator/processed_rtl/obj_dir/",$tview,"sim"); - + $load->destroy; + $make->show_all; + }); $run -> signal_connect("clicked" => sub{

/diagram.pl

/emulate_ram_gen.pl

/emulator.pl

/graph.pl

/interface_gen.pl

/ip_gen.pl

/mpsoc_gen.pl