OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/soc
    from Rev 41 to Rev 42
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  •

Rev 41 → Rev 42

/tutorial.SOC File deleted
/Tutorial_lm32.SOC
0,0 → 1,1133
#######################################################################
## File: Tutorial_lm32.SOC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$soc = bless( {
'global_param' => {
'CORE_ID' => 0
},
'clk_source0' => {},
'compile_pin_range_lsb' => {
'hex1_port_o' => '0',
'source_reset_in' => '0',
'ext_int_ext_int_i' => '1',
'hex0_port_o' => '0'
},
'compile' => {
'type' => 'Modelsim',
'quartus_bin' => '/home/alireza/altera/13.0sp1/quartus/bin',
'board' => 'DE2_115',
'modelsim_bin' => '/home/alireza/altera/modeltech/bin'
},
'hdl_files' => undef,
'dual_port_ram0' => {
'version' => 6
},
'wishbone_bus0' => {},
'gpo0' => {},
'gpo1' => {},
'ext_int0' => {},
'compile_pin' => {
'hex0_port_o' => 'HEX0',
'ext_int_ext_int_i' => 'KEY',
'source_clk_in' => 'CLOCK_50',
'hex1_port_o' => 'HEX1',
'source_reset_in' => 'KEY',
'lm32_en_i' => '*VCC'
},
'top_ip' => bless( {
'interface' => {
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'intfc_port' => 'reset_i',
'range' => '',
'type' => 'input',
'instance_name' => 'clk_source0'
}
}
},
'plug:enable[0]' => {
'ports' => {
'lm32_en_i' => {
'type' => 'input',
'instance_name' => 'lm320',
'intfc_port' => 'enable_i',
'range' => ''
}
}
},
'IO' => {
'ports' => {
'hex0_port_o' => {
'instance_name' => 'gpo0',
'type' => 'output',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
},
'hex1_port_o' => {
'type' => 'output',
'instance_name' => 'gpo1',
'range' => 'hex1_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
},
'ext_int_ext_int_i' => {
'type' => 'input',
'instance_name' => 'ext_int0',
'intfc_port' => 'IO',
'range' => 'ext_int_EXT_INT_NUM-1 : 0'
}
}
}
},
'ports' => {
'lm32_en_i' => {
'intfc_port' => 'enable_i',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'instance_name' => 'lm320'
},
'hex1_port_o' => {
'range' => 'hex1_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'instance_name' => 'gpo1',
'type' => 'output'
},
'source_reset_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i'
},
'ext_int_ext_int_i' => {
'type' => 'input',
'instance_name' => 'ext_int0',
'range' => 'ext_int_EXT_INT_NUM-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO'
},
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'type' => 'input'
},
'hex0_port_o' => {
'type' => 'output',
'instance_name' => 'gpo0',
'intfc_name' => 'IO',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
}
},
'instance_ids' => {
'clk_source0' => {
'category' => 'Source',
'ports' => {
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input'
},
'source_reset_in' => {
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i'
}
},
'module_name' => 'clk_source',
'module' => 'clk_source',
'instance' => 'source'
},
'ext_int0' => {
'instance' => 'ext_int',
'module' => 'ext_int',
'category' => 'Interrupt',
'module_name' => 'ext_int',
'ports' => {
'ext_int_ext_int_i' => {
'range' => 'ext_int_EXT_INT_NUM-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'input'
}
}
},
'timer0' => {
'instance' => 'timer',
'module' => 'timer',
'module_name' => 'timer',
'category' => 'Timer'
},
'dual_port_ram0' => {
'category' => 'RAM',
'module_name' => 'wb_dual_port_ram',
'module' => 'dual_port_ram',
'instance' => 'ram'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'instance' => 'bus',
'category' => 'Bus',
'module_name' => 'wishbone_bus'
},
'gpo0' => {
'ports' => {
'hex0_port_o' => {
'intfc_port' => 'IO',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output'
}
},
'parameters' => {
'hex0_PORT_WIDTH' => {
'info' => 'output port width',
'default' => 7,
'type' => 'Spin-button',
'global_param' => 'Parameter',
'content' => '1,32,1',
'redefine_param' => 1
}
},
'module_name' => 'gpo',
'category' => 'GPIO',
'module' => 'gpo',
'instance' => 'hex0'
},
'lm320' => {
'module_name' => 'lm32',
'ports' => {
'lm32_en_i' => {
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
}
},
'category' => 'Processor',
'instance' => 'lm32',
'module' => 'lm32'
},
'jtag_wb0' => {
'instance' => 'jtag_wb',
'module' => 'jtag_wb',
'module_name' => 'vjtag_wb',
'category' => 'JTAG'
},
'gpo1' => {
'category' => 'GPIO',
'module_name' => 'gpo',
'parameters' => {
'hex1_PORT_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '1,32,1',
'default' => 7,
'type' => 'Spin-button',
'info' => 'output port width'
}
},
'ports' => {
'hex1_port_o' => {
'intfc_name' => 'IO',
'range' => 'hex1_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'type' => 'output'
}
},
'instance' => 'hex1',
'module' => 'gpo'
}
}
}, 'ip_gen' ),
'timer0' => {},
'gui_status' => {
'status' => 'save_project',
'timeout' => 0
},
'instance_order' => [
'clk_source0',
'wishbone_bus0',
'gpo0',
'gpo1',
'ext_int0',
'timer0',
'jtag_wb0',
'lm320',
'dual_port_ram0'
],
'modules' => {},
'compile_pin_range_hsb' => {
'hex0_port_o' => '6',
'ext_int_ext_int_i' => '2',
'hex1_port_o' => '6'
},
'lm320' => {},
'compile_pin_pos' => {
'hex0_port_o' => [
7,
0
],
'hex1_port_o' => [
8,
0
],
'source_reset_in' => [
13,
0
],
'ext_int_ext_int_i' => [
13,
0
],
'source_clk_in' => [
4,
0
],
'lm32_en_i' => [
2,
0
]
},
'jtag_wb0' => {},
'soc_name' => 'Tutorial_lm32',
'compile_assign_type' => {
'source_reset_in' => 'Negate(~)',
'ext_int_ext_int_i' => 'Direct',
'source_clk_in' => 'Direct',
'lm32_en_i' => 'Direct'
},
'instances' => {
'gpo1' => {
'module_name' => 'gpo',
'instance_name' => 'hex1',
'plugs' => {
'wb_slave' => {
'nums' => {
'0' => {
'end' => 2432696383,
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O',
'base' => 2432696352,
'connect_socket' => 'wb_slave',
'connect_socket_num' => '1',
'name' => 'wb',
'connect_id' => 'wishbone_bus0',
'width' => 5
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'clk' => {
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
},
'reset' => {
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
}
},
'sockets' => {},
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'category' => 'GPIO',
'gpo1' => {},
'parameters' => {
'TAGw' => {
'value' => ' 3'
},
'SELw' => {
'value' => ' 4'
},
'Dw' => {
'value' => 'PORT_WIDTH'
},
'PORT_WIDTH' => {
'value' => 7
},
'Aw' => {
'value' => ' 2'
}
},
'module' => 'gpo'
},
'jtag_wb0' => {
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0'
}
},
'value' => 1,
'connection_num' => undef,
'type' => 'num'
},
'wb_master' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master',
'connect_socket_num' => '0',
'name' => 'wbm'
}
}
},
'clk' => {
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'instance_name' => 'jtag_wb',
'module_name' => 'vjtag_wb',
'parameters_order' => [
'DW',
'AW',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'VJTAG_INDEX'
],
'sockets' => {},
'module' => 'jtag_wb',
'category' => 'JTAG',
'parameters' => {
'SELw' => {
'value' => ' 4'
},
'S_Aw' => {
'value' => ' 7'
},
'AW' => {
'value' => '32'
},
'TAGw' => {
'value' => ' 3'
},
'DW' => {
'value' => '32'
},
'VJTAG_INDEX' => {
'value' => 'CORE_ID'
},
'M_Aw' => {
'value' => ' 32'
}
},
'jtag_wb0' => {}
},
'lm320' => {
'parameters_order' => [
'INTR_NUM',
'CFG_PL_MULTIPLY',
'CFG_PL_BARREL_SHIFT',
'CFG_SIGN_EXTEND',
'CFG_MC_DIVIDE'
],
'sockets' => {
'interrupt_peripheral' => {
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
},
'value' => 'INTR_NUM',
'connection_num' => 'single connection',
'type' => 'param'
}
},
'plugs' => {
'reset' => {
'type' => 'num',
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'name' => 'reset'
}
}
},
'enable' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'enable',
'connect_socket_num' => undef,
'connect_socket' => undef
}
}
},
'wb_master' => {
'type' => 'num',
'connection_num' => undef,
'value' => 2,
'nums' => {
'1' => {
'connect_id' => 'wishbone_bus0',
'name' => 'dwb',
'connect_socket_num' => '2',
'connect_socket' => 'wb_master'
},
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1',
'connect_socket' => 'wb_master',
'name' => 'iwb'
}
}
},
'clk' => {
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
}
},
'instance_name' => 'lm32',
'module_name' => 'lm32',
'lm320' => {},
'parameters' => {
'CFG_PL_MULTIPLY' => {
'value' => '"ENABLED"'
},
'CFG_PL_BARREL_SHIFT' => {
'value' => '"ENABLED"'
},
'CFG_MC_DIVIDE' => {
'value' => '"DISABLED"'
},
'INTR_NUM' => {
'value' => '32'
},
'CFG_SIGN_EXTEND' => {
'value' => '"ENABLED"'
}
},
'category' => 'Processor',
'module' => 'lm32'
},
'gpo0' => {
'category' => 'GPIO',
'parameters' => {
'TAGw' => {
'value' => ' 3'
},
'SELw' => {
'value' => ' 4'
},
'Dw' => {
'value' => 'PORT_WIDTH'
},
'PORT_WIDTH' => {
'value' => 7
},
'Aw' => {
'value' => ' 2'
}
},
'module' => 'gpo',
'gpo0' => {},
'sockets' => {},
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'instance_name' => 'hex0',
'module_name' => 'gpo',
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0'
}
},
'value' => 1,
'connection_num' => undef,
'type' => 'num'
},
'clk' => {
'type' => 'num',
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
}
},
'wb_slave' => {
'nums' => {
'0' => {
'name' => 'wb',
'connect_socket' => 'wb_slave',
'connect_socket_num' => '0',
'base' => 2432696320,
'end' => 2432696351,
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O',
'width' => 5,
'connect_id' => 'wishbone_bus0'
}
},
'value' => 1,
'connection_num' => undef,
'type' => 'num'
}
}
},
'wishbone_bus0' => {
'sockets' => {
'wb_master' => {
'nums' => {
'0' => {
'name' => 'wb_master'
}
},
'value' => 'M',
'connection_num' => 'single connection',
'type' => 'param'
},
'wb_addr_map' => {
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'value' => 1,
'connection_num' => 'single connection',
'type' => 'num'
},
'wb_slave' => {
'connection_num' => 'single connection',
'value' => 'S',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
}
}
},
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'instance_name' => 'bus',
'module_name' => 'wishbone_bus',
'plugs' => {
'clk' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
}
},
'reset' => {
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'name' => 'reset'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'category' => 'Bus',
'parameters' => {
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
},
'Aw' => {
'value' => '32'
},
'M' => {
'value' => 3
},
'Dw' => {
'value' => '32'
},
'BTEw' => {
'value' => '2 '
},
'CTIw' => {
'value' => '3'
},
'S' => {
'value' => 6
}
},
'wishbone_bus0' => {},
'module' => 'wishbone_bus'
},
'dual_port_ram0' => {
'instance_name' => 'ram',
'module_name' => 'wb_dual_port_ram',
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
}
},
'clk' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0'
}
}
},
'wb_slave' => {
'type' => 'num',
'value' => 2,
'connection_num' => undef,
'nums' => {
'0' => {
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'end' => 16383,
'base' => 0,
'name' => 'wb_a',
'connect_socket_num' => '4',
'connect_socket' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'width' => 'WB_Aw'
},
'1' => {
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'end' => 32767,
'base' => 16384,
'connect_socket' => 'wb_slave',
'connect_socket_num' => '5',
'name' => 'wb_b',
'connect_id' => 'wishbone_bus0',
'width' => 'WB_Aw'
}
}
}
},
'sockets' => {},
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'RAM_INDEX',
'PORT_A_BURST_MODE',
'PORT_B_BURST_MODE',
'INITIAL_EN',
'MEM_CONTENT_FILE_NAME',
'INIT_FILE_PATH'
],
'module' => 'dual_port_ram',
'dual_port_ram0' => {},
'parameters' => {
'PORT_B_BURST_MODE' => {
'value' => '"ENABLED"'
},
'Dw' => {
'value' => '32'
},
'INITIAL_EN' => {
'value' => '"YES"'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'CTIw' => {
'value' => '3'
},
'FPGA_VENDOR' => {
'value' => '"GENERIC"'
},
'RAM_INDEX' => {
'value' => 'CORE_ID'
},
'BTEw' => {
'value' => '2'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'SELw' => {
'value' => 'Dw/8'
},
'Aw' => {
'value' => '12'
},
'PORT_A_BURST_MODE' => {
'value' => '"ENABLED"'
},
'TAGw' => {
'value' => '3'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
}
},
'category' => 'RAM'
},
'timer0' => {
'instance_name' => 'timer',
'module_name' => 'timer',
'plugs' => {
'interrupt_peripheral' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'lm320',
'name' => 'interrupt_peripheral',
'connect_socket' => 'interrupt_peripheral',
'connect_socket_num' => '1'
}
}
},
'clk' => {
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
},
'reset' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'name' => 'reset',
'connect_id' => 'clk_source0'
}
}
},
'wb_slave' => {
'nums' => {
'0' => {
'end' => 2516582431,
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl',
'base' => 2516582400,
'name' => 'wb',
'connect_socket' => 'wb_slave',
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0',
'width' => 5
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
}
},
'sockets' => {},
'timer0' => {},
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw'
],
'module' => 'timer',
'parameters' => {
'CNTw' => {
'value' => '32 '
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => ' 32'
},
'Aw' => {
'value' => ' 3'
},
'SELw' => {
'value' => ' 4'
}
},
'category' => 'Timer'
},
'ext_int0' => {
'module' => 'ext_int',
'category' => 'Interrupt',
'parameters' => {
'EXT_INT_NUM' => {
'value' => 2
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'Aw' => {
'value' => '3'
},
'SELw' => {
'value' => '4'
}
},
'ext_int0' => {},
'instance_name' => 'ext_int',
'module_name' => 'ext_int',
'plugs' => {
'wb_slave' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'wb_slave',
'connect_socket_num' => '2',
'name' => 'wb',
'base' => 2650800128,
'end' => 2650800159,
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller',
'width' => 5,
'connect_id' => 'wishbone_bus0'
}
}
},
'clk' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0'
}
}
},
'interrupt_peripheral' => {
'nums' => {
'0' => {
'connect_id' => 'lm320',
'connect_socket' => 'interrupt_peripheral',
'connect_socket_num' => '0',
'name' => 'interrupt'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
},
'reset' => {
'type' => 'num',
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0'
}
}
}
},
'sockets' => {},
'parameters_order' => [
'Dw',
'Aw',
'TAGw',
'SELw',
'EXT_INT_NUM'
]
},
'clk_source0' => {
'parameters' => {},
'category' => 'Source',
'module' => 'clk_source',
'module_name' => 'clk_source',
'instance_name' => 'source',
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_socket' => undef,
'connect_socket_num' => undef,
'name' => 'reset',
'connect_id' => 'IO'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'clk' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'connect_socket' => undef,
'name' => 'clk'
}
}
}
},
'sockets' => {
'clk' => {
'nums' => {
'0' => {
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => 'multi connection'
},
'reset' => {
'nums' => {
'0' => {
'name' => 'reset'
}
},
'type' => 'num',
'connection_num' => 'multi connection',
'value' => 1
}
},
'parameters_order' => [],
'clk_source0' => {}
}
}
}, 'soc' );
/aemb_tile.SOC
0,0 → 1,1692
#######################################################################
## File: aemb_tile.SOC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$soc = bless( {
'dma0' => {
'version' => 4
},
'modules' => {},
'mor1kx0' => {
'version' => 13
},
'ni_master0' => {
'version' => 38
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'single_port_ram0' => {
'version' => 22
},
'hdl_files' => undef,
'clk_source0' => {
'version' => 0
},
'top_ip' => bless( {
'instance_ids' => {
'aeMB0' => {
'module' => 'aeMB',
'localparam' => {
'cpu_AEMB_ICH' => {
'default' => ' 11',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'cpu_AEMB_XWB' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'default' => ' 7',
'info' => undef
},
'cpu_AEMB_DWB' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => '',
'info' => undef,
'default' => ' 32'
},
'cpu_AEMB_IDX' => {
'info' => undef,
'default' => ' 6',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'cpu_AEMB_IWB' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => ' 32',
'info' => undef
},
'cpu_AEMB_BSF' => {
'info' => undef,
'default' => ' 1',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => ''
},
'cpu_AEMB_MUL' => {
'info' => undef,
'default' => ' 1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed'
}
},
'category' => 'Processor',
'ports' => {
'cpu_sys_ena_i' => {
'type' => 'input',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => ''
},
'cpu_sys_int_i' => {
'intfc_port' => 'int_i',
'intfc_name' => 'socket:interrupt_cpu[0]',
'type' => 'input',
'range' => ''
}
},
'instance' => 'cpu',
'module_name' => 'aeMB_top'
},
'single_port_ram0' => {
'category' => 'RAM',
'parameters' => {
'ram_Aw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '4,31,1',
'info' => 'Memory address width',
'default' => 14
},
'ram_Dw' => {
'info' => 'Memory data width in Bits.',
'default' => '32',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '8,1024,1',
'type' => 'Spin-button'
}
},
'localparam' => {
'ram_JTAG_CONNECT' => {
'type' => 'Combo-box',
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"DISABLED"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
},
'ram_BURST_MODE' => {
'content' => '"DISABLED","ENABLED"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'default' => '"ENABLED"'
},
'ram_JTAG_INDEX' => {
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'content' => '',
'type' => 'Entry',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_INIT_FILE_PATH' => {
'default' => 'SW_LOC',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => ''
},
'ram_INITIAL_EN' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '"YES","NO"',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram_BTEw' => {
'default' => '2',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => ''
},
'ram_CTIw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'default' => '3'
},
'ram_BYTE_WR_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"YES","NO"',
'type' => 'Combo-box',
'info' => 'Byte enable',
'default' => '"YES"'
},
'ram_FPGA_VENDOR' => {
'default' => '"ALTERA"',
'info' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '"ALTERA","GENERIC"'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"',
'type' => 'Entry',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_TAGw' => {
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_SELw' => {
'type' => 'Fixed',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => 'ram_Dw/8',
'info' => 'Parameter'
}
},
'module' => 'single_port_ram',
'module_name' => 'wb_single_port_ram',
'instance' => 'ram'
},
'clk_source0' => {
'instance' => 'ss',
'module_name' => 'clk_source',
'ports' => {
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => ''
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => ''
}
},
'category' => 'Source',
'module' => 'clk_source'
},
'ni_master0' => {
'localparam' => {
'ni_SELw' => {
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '4'
},
'ni_CLASS_HDR_WIDTH' => {
'info' => 'Parameter',
'default' => '8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed'
},
'ni_S_Aw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_CRC_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"YES","NO"',
'type' => 'Combo-box',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '
},
'ni_ROUTING_HDR_WIDTH' => {
'default' => '8',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '4,32,1',
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.'
},
'ni_DST_ADR_HDR_WIDTH' => {
'info' => 'Parameter',
'default' => '8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed'
},
'ni_Xw' => {
'info' => undef,
'default' => 'log2(ni_NX)',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 0,
'global_param' => 'Localparam'
},
'ni_SRC_ADR_HDR_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter'
},
'ni_TAGw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'default' => '3',
'info' => 'Parameter'
},
'ni_Fw' => {
'redefine_param' => 0,
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'info' => undef,
'default' => '2+ni_V+ni_Fpay'
},
'ni_Yw' => {
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 0,
'default' => 'log2(ni_NY)',
'info' => undef
},
'ni_M_Aw' => {
'info' => 'Parameter',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => 'Dw'
},
'ni_Dw' => {
'content' => '32,256,8',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '32',
'info' => 'wishbone_bus data width in bits.'
},
'ni_MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. '
}
},
'parameters' => {
'ni_DEBUG_EN' => {
'info' => 'Parameter',
'default' => '1',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_NX' => {
'default' => 2,
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_C' => {
'default' => 2,
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_V' => {
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2'
},
'ni_ROUTE_NAME' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'default' => '"XY"'
},
'ni_Fpay' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter'
},
'ni_NY' => {
'default' => ' 2',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_B' => {
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ni_TOPOLOGY' => {
'default' => '"MESH"',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1
}
},
'category' => 'NoC',
'module' => 'ni_master',
'ports' => {
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0'
},
'ni_credit_out' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'range' => 'ni_V-1 : 0'
},
'ni_current_x' => {
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_x'
},
'ni_current_y' => {
'range' => 'ni_Yw-1 : 0',
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_irq' => {
'intfc_name' => 'plug:interrupt_peripheral[0]',
'intfc_port' => 'int_o',
'type' => 'output',
'range' => ''
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_flit_in_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
}
},
'instance' => 'ni',
'module_name' => 'ni_master'
},
'jtag_uart0' => {
'instance' => 'uart',
'module_name' => 'jtag_uart_wb',
'ports' => {
'uart_RxD_ready_sim' => {
'range' => '',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'output'
},
'uart_irq' => {
'type' => 'output',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'intfc_port' => 'int_o',
'range' => ''
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'range' => ''
},
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
}
},
'module' => 'jtag_uart',
'category' => 'Communication',
'localparam' => {
'uart_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ' "ALTERA"',
'type' => 'Combo-box',
'info' => 'FPGA VENDOR name. Only Altera FPGA is supported. Currently the Generic serial port is not supported. ',
'default' => ' "ALTERA"'
},
'uart_SIM_WAIT_COUNT' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '2,100000,1',
'default' => '1000',
'info' => 'This parameter is valid only in simulation.
If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.'
},
'uart_SIM_BUFFER_SIZE' => {
'info' => 'Internal buffer size.
This parameter is valid only in simulation.
If internal buffer overflows, the buffer content are displayed on simulator terminal.',
'default' => '100',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '10,10000,1'
}
}
},
'wishbone_bus0' => {
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'localparam' => {
'bus_Dw' => {
'content' => '8,512,8',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '32',
'info' => 'The wishbone Bus data width in bits.'
},
'bus_Aw' => {
'info' => 'The wishbone Bus address width',
'default' => '32',
'type' => 'Spin-button',
'content' => '4,128,1',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'bus_CTIw' => {
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'info' => undef
},
'bus_TAGw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'info' => undef,
'default' => '3'
},
'bus_M' => {
'info' => 'Number of wishbone master interface',
'default' => ' 4',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '1,256,1'
},
'bus_BTEw' => {
'info' => undef,
'default' => '2 ',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => ''
},
'bus_S' => {
'default' => 3,
'info' => 'Number of wishbone slave interface',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '1,256,1'
},
'bus_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'info' => undef,
'default' => 'bus_Dw/8'
}
},
'category' => 'Bus',
'module' => 'wishbone_bus'
}
},
'interface' => {
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'range' => '',
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ni_current_y' => {
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_y',
'range' => 'ni_Yw-1 : 0'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ni_current_x' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'ni_Xw-1 : 0'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'credit_out',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out',
'range' => 'ni_Fw-1 : 0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => ''
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'range' => '',
'instance_name' => 'jtag_uart0'
},
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'instance_name' => 'jtag_uart0'
},
'uart_RxD_wr_sim' => {
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'range' => '',
'instance_name' => 'jtag_uart0'
}
}
},
'socket:interrupt_cpu[0]' => {
'ports' => {
'cpu_sys_int_i' => {
'type' => 'input',
'intfc_port' => 'int_i',
'range' => '',
'instance_name' => 'aeMB0'
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'uart_irq' => {
'instance_name' => 'jtag_uart0',
'range' => '',
'type' => 'output',
'intfc_port' => 'int_o'
},
'ni_irq' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'int_o',
'type' => 'output'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_sys_ena_i' => {
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'aeMB0'
}
}
}
},
'ports' => {
'ni_flit_out_wr' => {
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'range' => 'ni_Fw-1 : 0'
},
'uart_RxD_ready_sim' => {
'instance_name' => 'jtag_uart0',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'output',
'range' => ''
},
'uart_RxD_wr_sim' => {
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_wr_sim',
'range' => '',
'instance_name' => 'jtag_uart0'
},
'ni_current_x' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_x',
'type' => 'input'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'instance_name' => 'ni_master0'
},
'ss_clk_in' => {
'range' => '',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0'
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]'
},
'cpu_sys_int_i' => {
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input',
'intfc_name' => 'socket:interrupt_cpu[0]',
'intfc_port' => 'int_i'
},
'ni_irq' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'type' => 'output',
'range' => ''
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
},
'uart_irq' => {
'instance_name' => 'jtag_uart0',
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'type' => 'output',
'range' => ''
},
'ni_current_y' => {
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_y',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'uart_RxD_din_sim' => {
'instance_name' => 'jtag_uart0',
'range' => '7:0 ',
'type' => 'input',
'intfc_port' => 'RxD_din_sim',
'intfc_name' => 'socket:RxD_sim[0]'
},
'cpu_sys_ena_i' => {
'range' => '',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'instance_name' => 'aeMB0'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'range' => 'ni_V-1 : 0'
}
}
}, 'ip_gen' ),
'soc_name' => 'aemb_tile',
'instances' => {
'clk_source0' => {
'parameters_order' => [],
'sockets' => {
'clk' => {
'connection_num' => 'multi connection',
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk'
}
},
'value' => 1
},
'reset' => {
'value' => 1,
'nums' => {
'0' => {
'name' => 'reset'
}
},
'type' => 'num',
'connection_num' => 'multi connection'
}
},
'description_pdf' => undef,
'module' => 'clk_source',
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'reset',
'connect_socket_num' => undef,
'connect_socket' => undef
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'clk',
'connect_socket_num' => undef,
'connect_socket' => undef
}
},
'type' => 'num'
}
},
'parameters' => {},
'category' => 'Source',
'instance_name' => 'ss',
'module_name' => 'clk_source'
},
'aeMB0' => {
'module_name' => 'aeMB_top',
'instance_name' => 'cpu',
'category' => 'Processor',
'parameters' => {
'AEMB_ICH' => {
'value' => ' 11'
},
'AEMB_MUL' => {
'value' => ' 1'
},
'AEMB_DWB' => {
'value' => ' 32'
},
'AEMB_BSF' => {
'value' => ' 1'
},
'AEMB_IWB' => {
'value' => ' 32'
},
'HEAP_SIZE' => {
'value' => '0x400'
},
'AEMB_XWB' => {
'value' => ' 7'
},
'STACK_SIZE' => {
'value' => '0x400'
},
'AEMB_IDX' => {
'value' => ' 6'
}
},
'plugs' => {
'clk' => {
'nums' => {
'0' => {
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket_num' => '0'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'wb_master' => {
'value' => 2,
'nums' => {
'0' => {
'connect_socket_num' => '2',
'connect_id' => 'wishbone_bus0',
'name' => 'iwb',
'connect_socket' => 'wb_master'
},
'1' => {
'name' => 'dwb',
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master'
}
},
'type' => 'num',
'connection_num' => undef
},
'enable' => {
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_id' => 'IO',
'name' => 'enable',
'connect_socket' => undef
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'type' => 'num',
'value' => 1
}
},
'module' => 'aeMB',
'sockets' => {
'interrupt_cpu' => {
'value' => 1,
'nums' => {
'0' => {
'name' => 'interrupt_cpu'
}
},
'type' => 'num',
'connection_num' => 'single connection'
}
},
'description_pdf' => undef,
'parameters_order' => [
'AEMB_IWB',
'AEMB_DWB',
'AEMB_XWB',
'AEMB_ICH',
'AEMB_IDX',
'AEMB_BSF',
'AEMB_MUL',
'STACK_SIZE',
'HEAP_SIZE'
]
},
'single_port_ram0' => {
'instance_name' => 'ram',
'module_name' => 'wb_single_port_ram',
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf',
'sockets' => {},
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH'
],
'module' => 'single_port_ram',
'category' => 'RAM',
'parameters' => {
'Aw' => {
'value' => 14
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'SELw' => {
'value' => 'Dw/8'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
},
'BTEw' => {
'value' => '2'
},
'CTIw' => {
'value' => '3'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'TAGw' => {
'value' => '3'
},
'INITIAL_EN' => {
'value' => '"YES"'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'JTAG_CONNECT' => {
'value' => '"DISABLED"'
},
'Dw' => {
'value' => '32'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
}
},
'plugs' => {
'clk' => {
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
}
},
'value' => 1
},
'reset' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset'
}
},
'value' => 1,
'connection_num' => undef
},
'wb_slave' => {
'type' => 'num',
'nums' => {
'0' => {
'base' => 0,
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '2',
'end' => 65535,
'name' => 'wb',
'connect_socket' => 'wb_slave',
'width' => 'WB_Aw',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
}
},
'value' => 1,
'connection_num' => undef
}
}
},
'ni_master0' => {
'parameters_order' => [
'CLASS_HDR_WIDTH',
'ROUTING_HDR_WIDTH',
'DST_ADR_HDR_WIDTH',
'SRC_ADR_HDR_WIDTH',
'TOPOLOGY',
'ROUTE_NAME',
'NX',
'NY',
'C',
'V',
'B',
'Fpay',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'DEBUG_EN',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'Xw',
'Yw',
'Fw',
'CRC_EN'
],
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf',
'sockets' => {
'ni' => {
'value' => 1,
'nums' => {
'0' => {
'name' => 'ni'
}
},
'type' => 'num',
'connection_num' => 'single connection'
}
},
'module' => 'ni_master',
'parameters' => {
'Yw' => {
'value' => 'log2(NY)'
},
'DEBUG_EN' => {
'value' => '1'
},
'M_Aw' => {
'value' => '32'
},
'CRC_EN' => {
'value' => '"NO"'
},
'WEIGHTw' => {
'value' => '4'
},
'MAX_TRANSACTION_WIDTH' => {
'value' => '13'
},
'SSA_EN' => {
'value' => '"NO"'
},
'VC_REALLOCATION_TYPE' => {
'value' => '"NONATOMIC"'
},
'SELw' => {
'value' => '4'
},
'CONGESTION_INDEX' => {
'value' => 3
},
'ROUTE_NAME' => {
'value' => '"XY"'
},
'B' => {
'value' => '4'
},
'CLASS_HDR_WIDTH' => {
'value' => '8'
},
'Fw' => {
'value' => '2+V+Fpay'
},
'Dw' => {
'value' => '32'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 1
},
'MUX_TYPE' => {
'value' => '"BINARY"'
},
'TAGw' => {
'value' => '3'
},
'AVC_ATOMIC_EN' => {
'value' => 0
},
'SWA_ARBITER_TYPE' => {
'value' => '"RRA"'
},
'ESCAP_VC_MASK' => {
'value' => '2\'b01'
},
'Fpay' => {
'value' => '32'
},
'NX' => {
'value' => 2
},
'TOPOLOGY' => {
'value' => '"MESH"'
},
'Xw' => {
'value' => 'log2(NX)'
},
'DST_ADR_HDR_WIDTH' => {
'value' => '8'
},
'SRC_ADR_HDR_WIDTH' => {
'value' => '8'
},
'C' => {
'value' => 2
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => '1\'b0'
},
'NY' => {
'value' => ' 2'
},
'ROUTING_HDR_WIDTH' => {
'value' => '8'
},
'V' => {
'value' => '2'
},
'MAX_BURST_SIZE' => {
'value' => '16'
},
'COMBINATION_TYPE' => {
'value' => '"COMB_NONSPEC"'
},
'ROUTE_SUBFUNC' => {
'value' => '"XY"'
},
'S_Aw' => {
'value' => '8'
},
'MAX_SBP_NUM ' => {
'value' => 0
}
},
'plugs' => {
'interrupt_peripheral' => {
'nums' => {
'0' => {
'name' => 'interrupt',
'connect_socket_num' => undef,
'connect_id' => 'IO',
'connect_socket' => undef
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
},
'type' => 'num'
},
'reset' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'connection_num' => undef
},
'wb_master' => {
'type' => 'num',
'nums' => {
'1' => {
'connect_socket_num' => '1',
'name' => 'wb_receive',
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master'
},
'0' => {
'connect_id' => 'wishbone_bus0',
'name' => 'wb_send',
'connect_socket_num' => '0',
'connect_socket' => 'wb_master'
}
},
'value' => 2,
'connection_num' => undef
},
'wb_slave' => {
'nums' => {
'0' => {
'connect_socket' => 'wb_slave',
'end' => 3087008767,
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0',
'name' => 'wb_slave',
'base' => 3087007744,
'width' => 10,
'addr' => '0xb800_0000 0xbfff_ffff custom devices'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'category' => 'NoC',
'instance_name' => 'ni',
'module_name' => 'ni_master'
},
'jtag_uart0' => {
'parameters_order' => [
'FPGA_VENDOR',
'SIM_BUFFER_SIZE',
'SIM_WAIT_COUNT'
],
'sockets' => {
'RxD_sim' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'RxD_sim'
}
},
'connection_num' => 'single connection'
}
},
'description_pdf' => undef,
'plugs' => {
'interrupt_peripheral' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'interrupt_peripheral',
'connect_socket_num' => undef,
'connect_socket' => undef
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk'
}
},
'type' => 'num',
'connection_num' => undef
},
'reset' => {
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => 'wb_slave',
'name' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1',
'base' => 2415919104,
'end' => 2415919135,
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
'width' => 5
}
},
'type' => 'num'
}
},
'parameters' => {
'FPGA_VENDOR' => {
'value' => ' "ALTERA"'
},
'SIM_WAIT_COUNT' => {
'value' => '1000'
},
'SIM_BUFFER_SIZE' => {
'value' => '100'
}
},
'category' => 'Communication',
'module' => 'jtag_uart',
'module_name' => 'jtag_uart_wb',
'instance_name' => 'uart'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'category' => 'Bus',
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_socket' => 'reset',
'name' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'type' => 'num'
}
},
'parameters' => {
'S' => {
'value' => 3
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'CTIw' => {
'value' => '3'
},
'M' => {
'value' => ' 4'
},
'BTEw' => {
'value' => '2 '
},
'SELw' => {
'value' => 'Dw/8'
},
'Aw' => {
'value' => '32'
}
},
'description_pdf' => undef,
'sockets' => {
'wb_slave' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
},
'type' => 'param',
'value' => 'S'
},
'wb_addr_map' => {
'connection_num' => 'single connection',
'type' => 'num',
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'value' => 1
},
'wb_master' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'wb_master'
}
},
'type' => 'param',
'value' => 'M'
}
},
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'instance_name' => 'bus',
'module_name' => 'wishbone_bus'
}
},
'compile' => {
'quartus_bin' => '/home/alireza/intelFPGA_lite/17.1/quartus/bin',
'type' => 'Verilator',
'compilers' => 'QuartusII,Verilator,Modelsim',
'board' => 'DE2_115',
'modelsim_bin' => '/home/alireza/intelFPGA_lite/17.1/modelsim_ase/bin'
},
'sim_uart0' => {
'version' => 7
},
'instance_order' => [
'wishbone_bus0',
'single_port_ram0',
'clk_source0',
'jtag_uart0',
'ni_master0',
'aeMB0'
],
'aeMB0' => {
'version' => 2
},
'wishbone_bus0' => {
'version' => 0
},
'verilator' => {
'libs' => {
'Vtop' => 'aemb_tile.v'
}
},
'jtag_uart0' => {
'version' => 14
},
'tile_diagram' => {
'show_clk' => 1,
'show_unused' => 1,
'show_reset' => 1
},
'global_param' => {
'CORE_ID' => 0,
'SW_LOC' => '/home/alireza/mywork/mpsoc_work/SOC/aemb_tile/sw'
}
}, 'soc' );
/mor1k_tile.SOC
0,0 → 1,1762
#######################################################################
## File: mor1k_tile.SOC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.8.1
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$soc = bless( {
'Unset-intfc' => {
'bus-snoop_en_o' => 'NC',
'bus-snoop_adr_o' => 'NC',
'uart-RxD_ready_sim' => 'NC',
'uart-RxD_wr_sim' => 'NC',
'uart-RxD_din_sim' => 'NC'
},
'mor1kx0' => {
'version' => 17
},
'wishbone_bus0' => {
'version' => 1
},
'sim_uart0' => {
'version' => 7
},
'single_port_ram0' => {
'version' => 22
},
'global_param' => {
'SW_LOC' => '/home/alireza/mywork/mpsoc_work/SOC/mor1k_tile/sw',
'CORE_ID' => 3
},
'clk_source0' => {
'version' => 0
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'ni_master0' => {
'version' => 40
},
'timer0' => {
'version' => 9
},
'instances' => {
'wishbone_bus0' => {
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'category' => 'Bus',
'description_pdf' => undef,
'module' => 'wishbone_bus',
'instance_name' => 'bus',
'parameters' => {
'BTEw' => {
'value' => '2 '
},
'Dw' => {
'value' => '32'
},
'SELw' => {
'value' => 'Dw/8'
},
'Aw' => {
'value' => '32'
},
'CTIw' => {
'value' => '3'
},
'TAGw' => {
'value' => '3'
},
'S' => {
'value' => '4'
},
'M' => {
'value' => ' 4'
}
},
'plugs' => {
'reset' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'sockets' => {
'wb_slave' => {
'connection_num' => 'single connection',
'value' => 'S',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
},
'type' => 'param'
},
'wb_master' => {
'nums' => {
'0' => {
'name' => 'wb_master'
}
},
'type' => 'param',
'value' => 'M',
'connection_num' => 'single connection'
},
'wb_addr_map' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'type' => 'num'
},
'snoop' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'snoop'
}
}
}
},
'module_name' => 'wishbone_bus'
},
'single_port_ram0' => {
'parameters' => {
'JTAG_CONNECT' => {
'value' => '"DISABLED"'
},
'Aw' => {
'value' => 14
},
'SELw' => {
'value' => 'Dw/8'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
},
'INITIAL_EN' => {
'value' => '"YES"'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'BTEw' => {
'value' => '2'
},
'Dw' => {
'value' => '32'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'TAGw' => {
'value' => '3'
},
'CTIw' => {
'value' => '3'
}
},
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
},
'wb_slave' => {
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0',
'name' => 'wb',
'connect_socket' => 'wb_slave',
'base' => 0,
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'end' => 65535,
'width' => 'WB_Aw'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'clk' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk'
}
}
}
},
'module_name' => 'wb_single_port_ram',
'sockets' => {},
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH'
],
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf',
'category' => 'RAM',
'module' => 'single_port_ram',
'instance_name' => 'ram'
},
'jtag_uart0' => {
'plugs' => {
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '1',
'connect_id' => 'wishbone_bus0',
'width' => 5,
'end' => 2415919135,
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
'base' => 2415919104,
'connect_socket' => 'wb_slave',
'name' => 'wb_slave'
}
},
'type' => 'num'
},
'reset' => {
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'type' => 'num'
},
'interrupt_peripheral' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'NC',
'connect_socket_num' => undef,
'name' => 'interrupt_peripheral',
'connect_socket' => undef
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
}
}
},
'parameters' => {
'SIM_BUFFER_SIZE' => {
'value' => 1000
},
'SIM_WAIT_COUNT' => {
'value' => '1000'
},
'FPGA_VENDOR' => {
'value' => ' "ALTERA"'
}
},
'sockets' => {
'RxD_sim' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'RxD_sim'
}
},
'type' => 'num'
}
},
'module_name' => 'jtag_uart_wb',
'category' => 'Communication',
'description_pdf' => undef,
'parameters_order' => [
'FPGA_VENDOR',
'SIM_BUFFER_SIZE',
'SIM_WAIT_COUNT'
],
'module' => 'jtag_uart',
'instance_name' => 'uart'
},
'clk_source0' => {
'description_pdf' => undef,
'category' => 'Source',
'parameters_order' => [],
'module' => 'clk_source',
'instance_name' => 'ss',
'plugs' => {
'clk' => {
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => undef,
'connect_socket_num' => undef,
'connect_id' => 'IO'
}
},
'type' => 'num'
},
'reset' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_id' => 'IO',
'connect_socket' => undef,
'name' => 'reset'
}
},
'connection_num' => undef,
'value' => 1
}
},
'parameters' => {},
'sockets' => {
'clk' => {
'nums' => {
'0' => {
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => 'multi connection'
},
'reset' => {
'nums' => {
'0' => {
'name' => 'reset'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => 'multi connection'
}
},
'module_name' => 'clk_source'
},
'ni_master0' => {
'sockets' => {
'ni' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'ni'
}
},
'type' => 'num'
}
},
'module_name' => 'ni_master',
'parameters' => {
'WEIGHTw' => {
'value' => '4'
},
'COMBINATION_TYPE' => {
'value' => '"COMB_NONSPEC"'
},
'MUX_TYPE' => {
'value' => '"BINARY"'
},
'SELw' => {
'value' => '4'
},
'ESCAP_VC_MASK' => {
'value' => '2\'b01'
},
'MAX_TRANSACTION_WIDTH' => {
'value' => '13'
},
'ROUTING_HDR_WIDTH' => {
'value' => '8'
},
'NX' => {
'value' => 2
},
'NY' => {
'value' => ' 2'
},
'DST_ADR_HDR_WIDTH' => {
'value' => '8'
},
'S_Aw' => {
'value' => '8'
},
'B' => {
'value' => '4'
},
'MAX_SBP_NUM ' => {
'value' => 0
},
'M_Aw' => {
'value' => '32'
},
'Yw' => {
'value' => 'log2(NY)'
},
'DEBUG_EN' => {
'value' => '1'
},
'SSA_EN' => {
'value' => '"NO"'
},
'Xw' => {
'value' => 'log2(NX)'
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => '1\'b0'
},
'CONGESTION_INDEX' => {
'value' => 3
},
'TOPOLOGY' => {
'value' => '"MESH"'
},
'Dw' => {
'value' => '32'
},
'MAX_BURST_SIZE' => {
'value' => '16'
},
'ROUTE_SUBFUNC' => {
'value' => '"XY"'
},
'AVC_ATOMIC_EN' => {
'value' => 0
},
'SWA_ARBITER_TYPE' => {
'value' => '"RRA"'
},
'VC_REALLOCATION_TYPE' => {
'value' => '"NONATOMIC"'
},
'SRC_ADR_HDR_WIDTH' => {
'value' => '8'
},
'CLASS_HDR_WIDTH' => {
'value' => '8'
},
'Fpay' => {
'value' => '32'
},
'Fw' => {
'value' => '2+V+Fpay'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 1
},
'ROUTE_NAME' => {
'value' => '"XY"'
},
'V' => {
'value' => '2'
},
'CRC_EN' => {
'value' => '"NO"'
},
'TAGw' => {
'value' => '3'
},
'C' => {
'value' => 2
}
},
'plugs' => {
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0',
'width' => 10,
'end' => 3087008767,
'base' => 3087007744,
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'name' => 'wb_slave',
'connect_socket' => 'wb_slave'
}
},
'type' => 'num'
},
'wb_master' => {
'nums' => {
'1' => {
'connect_socket' => 'wb_master',
'name' => 'wb_receive',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1'
},
'0' => {
'name' => 'wb_send',
'connect_socket' => 'wb_master',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0'
}
},
'type' => 'num',
'value' => 2,
'connection_num' => undef
},
'reset' => {
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'type' => 'num'
},
'interrupt_peripheral' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'interrupt',
'connect_socket' => 'interrupt_peripheral',
'connect_socket_num' => '0',
'connect_id' => 'mor1kx0'
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
}
}
},
'module' => 'ni_master',
'instance_name' => 'ni',
'parameters_order' => [
'CLASS_HDR_WIDTH',
'ROUTING_HDR_WIDTH',
'DST_ADR_HDR_WIDTH',
'SRC_ADR_HDR_WIDTH',
'TOPOLOGY',
'ROUTE_NAME',
'NX',
'NY',
'C',
'V',
'B',
'Fpay',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'DEBUG_EN',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'Xw',
'Yw',
'Fw',
'CRC_EN'
],
'category' => 'NoC',
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf'
},
'mor1kx0' => {
'module' => 'mor1kx',
'instance_name' => 'cpu',
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM',
'OPTION_DCACHE_SNOOP',
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU'
],
'description_pdf' => undef,
'category' => 'Processor',
'sockets' => {
'interrupt_peripheral' => {
'connection_num' => 'single connection',
'value' => 'IRQ_NUM',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
},
'type' => 'param'
}
},
'module_name' => 'mor1k',
'parameters' => {
'IRQ_NUM' => {
'value' => '32'
},
'OPTION_OPERAND_WIDTH' => {
'value' => '32'
},
'FEATURE_DMMU' => {
'value' => '"ENABLED"'
},
'FEATURE_DATACACHE' => {
'value' => '"ENABLED"'
},
'FEATURE_INSTRUCTIONCACHE' => {
'value' => '"ENABLED"'
},
'FEATURE_IMMU' => {
'value' => '"ENABLED"'
},
'OPTION_DCACHE_SNOOP' => {
'value' => '"ENABLED"'
}
},
'plugs' => {
'wb_master' => {
'connection_num' => undef,
'value' => 2,
'nums' => {
'1' => {
'connect_socket' => 'wb_master',
'name' => 'dwb',
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0'
},
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '2',
'connect_socket' => 'wb_master',
'name' => 'iwb'
}
},
'type' => 'num'
},
'enable' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'enable',
'connect_socket' => undef,
'connect_socket_num' => undef,
'connect_id' => 'IO'
}
},
'value' => 1,
'connection_num' => undef
},
'snoop' => {
'nums' => {
'0' => {
'name' => 'snoop',
'connect_socket' => 'snoop',
'connect_socket_num' => '0',
'connect_id' => 'wishbone_bus0'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
},
'clk' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'value' => 1,
'connection_num' => undef
}
}
},
'timer0' => {
'instance_name' => 'timer',
'module' => 'timer',
'category' => 'Timer',
'description_pdf' => '/mpsoc/src_peripheral/timer/timer.pdf',
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw',
'PRESCALER_WIDTH'
],
'sockets' => {},
'module_name' => 'timer',
'plugs' => {
'interrupt_peripheral' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'intrp',
'connect_socket' => 'interrupt_peripheral',
'connect_socket_num' => '1',
'connect_id' => 'mor1kx0'
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'value' => 1,
'connection_num' => undef
},
'wb_slave' => {
'nums' => {
'0' => {
'connect_socket' => 'wb_slave',
'name' => 'wb',
'end' => 2516582431,
'width' => 5,
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl',
'base' => 2516582400,
'connect_socket_num' => '2',
'connect_id' => 'wishbone_bus0'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => 'reset',
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'type' => 'num'
}
},
'parameters' => {
'Aw' => {
'value' => '3'
},
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => '4'
},
'Dw' => {
'value' => '32'
},
'CNTw' => {
'value' => '32 '
},
'PRESCALER_WIDTH' => {
'value' => '8'
}
}
}
},
'verilator' => {
'libs' => {
'Vtop' => 'mor1k_tile.v'
}
},
'compile' => {
'board' => 'DE10_Nano_VB2',
'modelsim_bin' => '/home/alireza/intelFPGA_lite/17.1/modelsim_ase/bin',
'compilers' => 'QuartusII,Verilator,Modelsim',
'type' => 'Verilator',
'quartus_bin' => '/home/alireza/intelFPGA_lite/17.1/quartus/bin'
},
'top_ip' => bless( {
'ports' => {
'ss_clk_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni_master0'
},
'ni_flit_out' => {
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'instance_name' => 'ni_master0'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'flit_in',
'instance_name' => 'ni_master0'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'instance_name' => 'mor1kx0'
},
'ni_current_y' => {
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_y',
'instance_name' => 'ni_master0'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0'
}
},
'instance_ids' => {
'mor1kx0' => {
'module' => 'mor1kx',
'instance' => 'cpu',
'module_name' => 'mor1k',
'ports' => {
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => ''
}
},
'category' => 'Processor',
'parameters' => {
'cpu_OPTION_OPERAND_WIDTH' => {
'info' => 'Parameter',
'default' => '32',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'cpu_FEATURE_DMMU' => {
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'cpu_FEATURE_IMMU' => {
'default' => '"ENABLED"',
'info' => '',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'cpu_FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'cpu_IRQ_NUM' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'info' => undef,
'default' => '32'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'info' => '',
'default' => '"ENABLED"',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1
}
}
},
'timer0' => {
'module' => 'timer',
'instance' => 'timer',
'localparam' => {
'timer_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '4',
'info' => undef,
'content' => ''
},
'timer_Aw' => {
'default' => '3',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'timer_TAGw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'info' => undef,
'default' => '3',
'content' => ''
},
'timer_CNTw' => {
'info' => undef,
'default' => '32 ',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'timer_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '32',
'info' => undef,
'content' => ''
}
},
'module_name' => 'timer',
'category' => 'Timer',
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button',
'content' => '1,32,1',
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
'
}
}
},
'clk_source0' => {
'instance' => 'ss',
'module' => 'clk_source',
'module_name' => 'clk_source',
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
},
'category' => 'Source'
},
'ni_master0' => {
'parameters' => {
'ni_B' => {
'content' => '',
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_NX' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => 'Parameter',
'default' => 2
},
'ni_NY' => {
'content' => '',
'default' => ' 2',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_TOPOLOGY' => {
'content' => '',
'default' => '"MESH"',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_V' => {
'content' => '',
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_Fpay' => {
'default' => '32',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ni_C' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => 2,
'info' => 'Parameter',
'content' => ''
},
'ni_ROUTE_NAME' => {
'info' => 'Parameter',
'default' => '"XY"',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'default' => '1',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
}
},
'category' => 'NoC',
'ports' => {
'ni_flit_out_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_flit_in_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_x' => {
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_x'
}
},
'module_name' => 'ni_master',
'localparam' => {
'ni_DST_ADR_HDR_WIDTH' => {
'default' => '8',
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_CRC_EN' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'content' => '"YES","NO"'
},
'ni_S_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8',
'info' => 'Parameter',
'content' => ''
},
'ni_M_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw'
},
'ni_SRC_ADR_HDR_WIDTH' => {
'content' => '',
'info' => 'Parameter',
'default' => '8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_Fw' => {
'type' => 'Fixed',
'redefine_param' => 0,
'global_param' => 'Localparam',
'content' => '',
'default' => '2+ni_V+ni_Fpay',
'info' => undef
},
'ni_Xw' => {
'global_param' => 'Localparam',
'redefine_param' => 0,
'type' => 'Fixed',
'default' => 'log2(ni_NX)',
'info' => undef,
'content' => ''
},
'ni_TAGw' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'default' => '3',
'info' => 'Parameter'
},
'ni_SELw' => {
'content' => '',
'info' => 'Parameter',
'default' => '4',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_ROUTING_HDR_WIDTH' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '8',
'content' => ''
},
'ni_MAX_TRANSACTION_WIDTH' => {
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16'
},
'ni_Dw' => {
'content' => '32,256,8',
'info' => 'wishbone_bus data width in bits.',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'ni_CLASS_HDR_WIDTH' => {
'default' => '8',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Yw' => {
'default' => 'log2(ni_NY)',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 0
}
},
'module' => 'ni_master',
'instance' => 'ni'
},
'jtag_uart0' => {
'category' => 'Communication',
'module_name' => 'jtag_uart_wb',
'localparam' => {
'uart_FPGA_VENDOR' => {
'default' => ' "ALTERA"',
'info' => 'FPGA VENDOR name. Only Altera FPGA is supported. Currently the Generic serial port is not supported. ',
'content' => ' "ALTERA"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box'
},
'uart_SIM_BUFFER_SIZE' => {
'info' => 'Internal buffer size.
This parameter is valid only in simulation.
If internal buffer overflows, the buffer content are displayed on simulator terminal.',
'default' => 1000,
'content' => '10,10000,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'uart_SIM_WAIT_COUNT' => {
'content' => '2,100000,1',
'info' => 'This parameter is valid only in simulation.
If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.',
'default' => '1000',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'module' => 'jtag_uart',
'instance' => 'uart'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'instance' => 'bus',
'localparam' => {
'bus_CTIw' => {
'default' => '3',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'bus_M' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '1,256,1',
'default' => ' 4',
'info' => 'Number of wishbone master interface'
},
'bus_BTEw' => {
'content' => '',
'default' => '2 ',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_Aw' => {
'default' => '32',
'info' => 'The wishbone Bus address width',
'content' => '4,128,1',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'bus_TAGw' => {
'content' => '',
'info' => undef,
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'bus_S' => {
'content' => '1,256,1',
'default' => '4',
'info' => 'Number of wishbone slave interface',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'bus_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'content' => '8,512,8'
},
'bus_SELw' => {
'content' => '',
'default' => 'bus_Dw/8',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'module_name' => 'wishbone_bus',
'category' => 'Bus'
},
'single_port_ram0' => {
'category' => 'RAM',
'parameters' => {
'ram_Dw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Spin-button',
'default' => '32',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1'
},
'ram_Aw' => {
'default' => 14,
'info' => 'Memory address width',
'content' => '4,31,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'redefine_param' => 1
}
},
'module_name' => 'wb_single_port_ram',
'localparam' => {
'ram_SELw' => {
'content' => '',
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_FPGA_VENDOR' => {
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"ALTERA","GENERIC"',
'info' => '',
'default' => '"ALTERA"'
},
'ram_BURST_MODE' => {
'content' => '"DISABLED","ENABLED"',
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Entry'
},
'ram_INITIAL_EN' => {
'content' => '"YES","NO"',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_BTEw' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'default' => '2',
'info' => 'Parameter'
},
'ram_JTAG_CONNECT' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"DISABLED"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"'
},
'ram_JTAG_INDEX' => {
'type' => 'Entry',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'content' => ''
},
'ram_INIT_FILE_PATH' => {
'info' => undef,
'default' => 'SW_LOC',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ram_BYTE_WR_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'info' => 'Byte enable',
'default' => '"YES"'
},
'ram_TAGw' => {
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter',
'default' => '3'
},
'ram_CTIw' => {
'content' => '',
'default' => '3',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'instance' => 'ram',
'module' => 'single_port_ram'
}
},
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_current_x' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_x'
},
'ni_flit_in_wr' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni_master0'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'range' => 'ni_Yw-1 : 0',
'type' => 'input',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_in',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_flit_out_wr' => {
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni_master0'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_out',
'range' => 'ni_V-1 : 0',
'type' => 'output'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
}
}
}, 'ip_gen' ),
'tile_diagram' => {
'show_unused' => 1,
'show_clk' => 1,
'show_reset' => 1
},
'soc_name' => 'mor1k_tile',
'instance_order' => [
'single_port_ram0',
'clk_source0',
'jtag_uart0',
'timer0',
'ni_master0',
'wishbone_bus0',
'mor1kx0'
],
'compile_pin_pos' => {},
'jtag_uart0' => {
'version' => 14
},
'hdl_files' => undef,
'parameters_order' => {
'Unset-intfc' => [
'uart-RxD_din_sim',
'uart-RxD_ready_sim',
'uart-RxD_wr_sim',
'bus-snoop_adr_o',
'bus-snoop_en_o'
]
},
'compile_assign_type' => {
'ss_clk_in' => 'Direct',
'ni_credit_in' => 'Direct',
'ni_flit_in' => 'Direct',
'ni_flit_in_wr' => 'Direct',
'cpu_cpu_en' => 'Direct',
'ni_current_y' => 'Direct',
'ni_current_x' => 'Direct',
'ss_reset_in' => 'Direct'
},
'dma0' => {
'version' => 4
},
'modules' => {}
}, 'soc' );

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