URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/soc
- from Rev 48 to Rev 54
- ↔ Reverse comparison
Rev 48 → Rev 54
/mor1k_tile.SOC
10,285 → 10,809
################################################################################ |
|
$soc = bless( { |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
'timer0' => { |
'version' => 12 |
}, |
'current_module_param_type' => undef, |
'SOURCE_SET' => { |
'SOC' => bless( { |
'modules' => {}, |
'hdl_files_ticked' => undef, |
'SOURCE_SET' => { |
'IP' => bless( { |
'parameters_order' => [], |
'hdl_files' => [], |
'GUI_REMOVE_SET' => 'DISABLE', |
'file_name' => undef, |
'hdl_files_ticked' => [], |
'category' => 'TOP', |
'ports' => { |
'source_clk_in' => { |
'range' => undef, |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input', |
'intfc_port' => 'clk_i' |
}, |
'source_reset_in' => { |
'intfc_port' => 'reset_i', |
'type' => 'input', |
'intfc_name' => 'plug:reset[0]', |
'range' => undef |
} |
}, |
'plugs' => { |
'reset' => { |
'1' => {}, |
'0' => { |
'name' => 'source_reset_in' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'value' => 1, |
'0' => { |
'name' => 'source_clk_in' |
}, |
'1' => {}, |
'type' => 'num' |
} |
}, |
'module_name' => 'TOP', |
'ip_name' => 'TOP', |
'ports_order' => [] |
}, 'ip_gen' ) |
}, |
'soc_name' => { |
'TOP' => undef |
}, |
'TOP' => { |
'version' => 0 |
}, |
'hdl_files' => undef, |
'gui_status' => { |
'status' => 'refresh_soc', |
'timeout' => 0 |
}, |
'instances' => { |
'TOP' => { |
'instance_name' => 'TOP', |
'plugs' => { |
'reset' => { |
'connection_num' => undef, |
'nums' => { |
'0' => { |
'connect_socket_num' => undef, |
'connect_socket' => undef, |
'name' => 'source_reset_in', |
'connect_id' => 'IO' |
} |
}, |
'type' => 'num', |
'value' => 1 |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket' => undef, |
'connect_socket_num' => undef, |
'connect_id' => 'IO', |
'name' => 'source_clk_in' |
} |
}, |
'type' => 'num' |
} |
}, |
'module_name' => 'TOP', |
'parameters_order' => [], |
'category' => 'TOP', |
'description_pdf' => undef, |
'module' => 'TOP' |
} |
}, |
'instance_order' => [ |
'TOP' |
] |
}, 'soc' ), |
'REDEFINE_TOP' => 0 |
}, |
'global_param' => { |
'CORE_ID' => 3, |
'SW_LOC' => '/home/alireza/work/git/hca_git/mpsoc_work/SOC/mor1k_tile/sw' |
}, |
'current_module_param' => undef, |
'wishbone_bus0' => { |
'version' => 1 |
}, |
'instance_order' => [ |
'clk_source0', |
'wishbone_bus0', |
'mor1kx0', |
'single_port_ram0', |
'ni_master0', |
'timer0', |
'ProNoC_jtag_uart0' |
], |
'instances' => { |
'ni_master0' => { |
'category' => 'NoC', |
'parameters_type' => { |
'T1' => { |
'value' => 'Parameter' |
}, |
'SELF_LOOP_EN' => { |
'value' => 'Parameter' |
}, |
'M_Aw' => {}, |
'TAGw' => {}, |
'T3' => { |
'value' => 'Parameter' |
}, |
'EAw' => {}, |
'T2' => { |
'value' => 'Parameter' |
}, |
'V' => { |
'value' => 'Parameter' |
'timer0' => { |
'sockets' => {}, |
'parameters' => { |
'Aw' => { |
'value' => '3' |
}, |
'CNTw' => { |
'value' => '32 ' |
}, |
'TAGw' => { |
'value' => '3' |
}, |
'Dw' => { |
'value' => '32' |
}, |
'SELw' => { |
'value' => '4' |
}, |
'PRESCALER_WIDTH' => { |
'value' => '8' |
} |
}, |
'parameters_order' => [ |
'CNTw', |
'Dw', |
'Aw', |
'TAGw', |
'SELw', |
'PRESCALER_WIDTH' |
], |
'module' => 'timer', |
'category' => 'Timer', |
'parameters_type' => { |
'Dw' => {}, |
'TAGw' => {}, |
'CNTw' => {}, |
'Aw' => {}, |
'PRESCALER_WIDTH' => { |
'value' => 'Localparam' |
}, |
'SELw' => {} |
}, |
'description_pdf' => '/mpsoc/rtl/src_peripheral/timer/timer.pdf', |
'module_name' => 'timer', |
'plugs' => { |
'clk' => { |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_id' => 'clk_source0', |
'name' => 'clk', |
'connect_socket' => 'clk', |
'connect_socket_num' => '0' |
} |
}, |
'WEIGHTw' => { |
'value' => 'Parameter' |
'value' => 1, |
'connection_num' => undef |
}, |
'interrupt_peripheral' => { |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_id' => 'mor1kx0', |
'name' => 'intrp', |
'connect_socket_num' => '1', |
'connect_socket' => 'interrupt_peripheral' |
} |
}, |
'connection_num' => undef |
}, |
'wb_slave' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'end' => 2516582431, |
'connect_socket' => 'wb_slave', |
'base' => 2516582400, |
'connect_socket_num' => '2', |
'connect_id' => 'wishbone_bus0', |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl' |
} |
}, |
'type' => 'num' |
}, |
'reset' => { |
'connection_num' => undef, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_socket' => 'reset', |
'connect_id' => 'clk_source0', |
'name' => 'reset' |
} |
}, |
'type' => 'num', |
'value' => 1 |
} |
}, |
'instance_name' => 'timer' |
}, |
'ProNoC_jtag_uart0' => { |
'sockets' => { |
'jtag_to_wb' => { |
'connection_num' => 'single connection', |
'value' => 1, |
'nums' => { |
'0' => { |
'name' => 'jtag_to_wb' |
} |
}, |
'type' => 'num' |
}, |
'RxD_sim' => { |
'connection_num' => 'single connection', |
'value' => 1, |
'nums' => { |
'0' => { |
'name' => 'RxD_sim' |
} |
}, |
'type' => 'num' |
} |
}, |
'parameters' => { |
'SELw' => { |
'value' => '4' |
}, |
'JTAG_CONNECT' => { |
'value' => '"ALTERA_JTAG_WB"' |
}, |
'JSTATUSw' => { |
'value' => '8' |
}, |
'BUFF_Aw' => { |
'value' => '4' |
}, |
'J2WBw' => { |
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1' |
}, |
'LB' => { |
'value' => 'Parameter' |
}, |
'VC_REALLOCATION_TYPE' => { |
'value' => 'Parameter' |
'JDw' => { |
'value' => '32' |
}, |
'Dw' => { |
'value' => '32' |
}, |
'TAGw' => { |
'value' => '3' |
}, |
'INCLUDE_SIM_PRINTF' => { |
'value' => 'SIMPLE_PRINTF' |
}, |
'Fpay' => { |
'value' => 'Parameter' |
'JAw' => { |
'value' => '32' |
}, |
'WB2Jw' => { |
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1' |
}, |
'JTAG_CHAIN' => { |
'value' => '3' |
}, |
'Aw' => { |
'value' => '1' |
}, |
'SMART_MAX' => { |
'value' => 'Parameter' |
'JINDEXw' => { |
'value' => '8' |
}, |
'CONGESTION_INDEX' => { |
'value' => 'Parameter' |
}, |
'SSA_EN' => { |
'value' => 'Parameter' |
'JTAG_INDEX' => { |
'value' => '126-CORE_ID' |
} |
}, |
'parameters_order' => [ |
'Aw', |
'SELw', |
'TAGw', |
'Dw', |
'BUFF_Aw', |
'JTAG_INDEX', |
'JDw', |
'JAw', |
'JINDEXw', |
'JSTATUSw', |
'JTAG_CHAIN', |
'JTAG_CONNECT', |
'J2WBw', |
'WB2Jw', |
'INCLUDE_SIM_PRINTF' |
], |
'module_name' => 'pronoc_jtag_uart', |
'plugs' => { |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_id' => 'clk_source0', |
'name' => 'clk', |
'connect_socket_num' => '0', |
'connect_socket' => 'clk' |
} |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'nums' => { |
'0' => { |
'width' => 4, |
'name' => 'wb_slave', |
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller', |
'connect_socket' => 'wb_slave', |
'end' => 2415919119, |
'base' => 2415919104, |
'connect_socket_num' => '3', |
'connect_id' => 'wishbone_bus0' |
} |
}, |
'type' => 'num', |
'value' => 1, |
'connection_num' => undef |
}, |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_socket' => 'reset', |
'connect_socket_num' => '0', |
'name' => 'reset', |
'connect_id' => 'clk_source0' |
} |
} |
} |
}, |
'instance_name' => 'uart', |
'module' => 'ProNoC_jtag_uart', |
'parameters_type' => { |
'SELw' => {}, |
'BUFF_Aw' => { |
'value' => 'Localparam' |
}, |
'JSTATUSw' => {}, |
'J2WBw' => {}, |
'JTAG_CONNECT' => { |
'value' => 'Localparam' |
}, |
'Dw' => {}, |
'JDw' => {}, |
'TAGw' => {}, |
'WB2Jw' => {}, |
'JAw' => {}, |
'JTAG_CHAIN' => { |
'value' => 'Localparam' |
}, |
'INCLUDE_SIM_PRINTF' => { |
'value' => 'Localparam' |
}, |
'Aw' => {}, |
'JTAG_INDEX' => { |
'value' => 'Localparam' |
}, |
'JINDEXw' => {} |
}, |
'description_pdf' => undef, |
'category' => 'Communication' |
}, |
'wishbone_bus0' => { |
'parameters_order' => [ |
'M', |
'S', |
'Dw', |
'Aw', |
'SELw', |
'TAGw', |
'CTIw', |
'BTEw' |
], |
'sockets' => { |
'wb_addr_map' => { |
'connection_num' => 'single connection', |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'name' => 'wb_addr_map' |
} |
} |
}, |
'Dw' => { |
'value' => 'Localparam' |
'wb_master' => { |
'connection_num' => 'single connection', |
'value' => 'M', |
'type' => 'param', |
'nums' => { |
'0' => { |
'name' => 'wb_master' |
} |
} |
}, |
'wb_slave' => { |
'value' => 'S', |
'type' => 'param', |
'nums' => { |
'0' => { |
'name' => 'wb_slave' |
} |
}, |
'connection_num' => 'single connection' |
}, |
'snoop' => { |
'connection_num' => 'single connection', |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'name' => 'snoop' |
} |
} |
} |
}, |
'parameters' => { |
'CTIw' => { |
'value' => '3' |
}, |
'AVC_ATOMIC_EN' => { |
'value' => 'Parameter' |
}, |
'ESCAP_VC_MASK' => { |
'value' => 'Parameter' |
}, |
'COMBINATION_TYPE' => { |
'value' => 'Parameter' |
}, |
'SELw' => {}, |
'ROUTE_NAME' => { |
'value' => 'Parameter' |
'Aw' => { |
'value' => '32' |
}, |
'M' => { |
'value' => ' 4' |
}, |
'SELw' => { |
'value' => 'Dw/8' |
}, |
'BTEw' => { |
'value' => '2 ' |
}, |
'S' => { |
'value' => '4' |
}, |
'TAGw' => { |
'value' => '3' |
}, |
'Dw' => { |
'value' => '32' |
} |
}, |
'category' => 'Bus', |
'parameters_type' => { |
'Aw' => { |
'value' => 'Localparam' |
}, |
'M' => { |
'value' => 'Localparam' |
}, |
'CTIw' => {}, |
'S' => { |
'value' => 'Localparam' |
}, |
'Dw' => { |
'value' => 'Localparam' |
}, |
'TAGw' => {}, |
'SELw' => {}, |
'BTEw' => {} |
}, |
'description_pdf' => undef, |
'module' => 'wishbone_bus', |
'plugs' => { |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'name' => 'reset', |
'connect_id' => 'clk_source0', |
'connect_socket' => 'reset', |
'connect_socket_num' => '0' |
} |
}, |
'CRC_EN' => { |
'value' => 'Localparam' |
}, |
'ADD_PIPREG_AFTER_CROSSBAR' => { |
'value' => 'Parameter' |
}, |
'RAw' => {}, |
'MAX_BURST_SIZE' => { |
'value' => 'Localparam' |
}, |
'TOPOLOGY' => { |
'value' => 'Parameter' |
'type' => 'num' |
}, |
'clk' => { |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_id' => 'clk_source0', |
'name' => 'clk', |
'connect_socket' => 'clk', |
'connect_socket_num' => '0' |
} |
}, |
'HDATA_PRECAPw' => { |
'value' => 'Localparam' |
}, |
'DEBUG_EN' => { |
'value' => 'Parameter' |
'connection_num' => undef |
} |
}, |
'module_name' => 'wishbone_bus', |
'instance_name' => 'bus' |
}, |
'clk_source0' => { |
'parameters_order' => [ |
'FPGA_VENDOR' |
], |
'sockets' => { |
'reset' => { |
'connection_num' => 'multi connection', |
'nums' => { |
'0' => { |
'name' => 'reset' |
} |
}, |
'type' => 'num', |
'value' => 1 |
}, |
'clk' => { |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'name' => 'clk' |
} |
}, |
'BYTE_EN' => { |
'value' => 'Parameter' |
}, |
'MIN_PCK_SIZE' => { |
'value' => 'Parameter' |
}, |
'SWA_ARBITER_TYPE' => { |
'value' => 'Parameter' |
}, |
'FIRST_ARBITER_EXT_P_EN' => { |
'value' => 'Parameter' |
}, |
'B' => { |
'value' => 'Parameter' |
}, |
'C' => { |
'value' => 'Parameter' |
}, |
'MAX_TRANSACTION_WIDTH' => { |
'value' => 'Localparam' |
}, |
'MUX_TYPE' => { |
'value' => 'Parameter' |
'connection_num' => 'multi connection' |
} |
}, |
'parameters' => { |
'FPGA_VENDOR' => { |
'value' => '"ALTERA"' |
} |
}, |
'description_pdf' => undef, |
'category' => 'Source', |
'parameters_type' => { |
'FPGA_VENDOR' => { |
'value' => 'Localparam' |
} |
}, |
'module' => 'clk_source', |
'module_name' => 'clk_source', |
'plugs' => { |
'reset' => { |
'connection_num' => undef, |
'nums' => { |
'0' => { |
'connect_id' => 'IO', |
'name' => 'reset', |
'connect_socket_num' => undef, |
'connect_socket' => undef |
} |
}, |
'S_Aw' => {}, |
'PCK_TYPE' => { |
'value' => 'Parameter' |
} |
}, |
'parameters_order' => [ |
'MAX_TRANSACTION_WIDTH', |
'MAX_BURST_SIZE', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'CRC_EN', |
'RAw', |
'EAw', |
'HDATA_PRECAPw' |
], |
'sockets' => { |
'ni' => { |
'type' => 'num', |
'value' => 1 |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'name' => 'ni' |
'connect_socket_num' => undef, |
'connect_socket' => undef, |
'name' => 'clk', |
'connect_id' => 'IO' |
} |
}, |
'type' => 'num', |
'connection_num' => 'single connection', |
'value' => 1 |
'type' => 'num' |
} |
}, |
'description_pdf' => '/mpsoc/rtl/src_peripheral/ni/NI.pdf', |
'module' => 'ni_master', |
'instance_name' => 'ni', |
}, |
'instance_name' => 'source' |
}, |
'ni_master0' => { |
'parameters' => { |
'S_Aw' => { |
'value' => '8' |
}, |
'Dw' => { |
'value' => '32' |
}, |
'COMBINATION_TYPE' => { |
'value' => '"COMB_NONSPEC"' |
}, |
'SWA_ARBITER_TYPE' => { |
'value' => '"RRA"' |
}, |
'WEIGHTw' => { |
'value' => '4' |
}, |
'CONGESTION_INDEX' => { |
'value' => 3 |
}, |
'MAX_TRANSACTION_WIDTH' => { |
'value' => '13' |
}, |
'PCK_TYPE' => { |
'value' => '"MULTI_FLIT"' |
}, |
'MUX_TYPE' => { |
'value' => '"BINARY"' |
'FIRST_ARBITER_EXT_P_EN' => { |
'value' => 1 |
}, |
'SELF_LOOP_EN' => { |
'value' => '"NO"' |
}, |
'CRC_EN' => { |
'value' => '"NO"' |
}, |
'EAw' => { |
'value' => '16' |
}, |
'B' => { |
'value' => '4' |
}, |
'TOPOLOGY' => { |
'value' => '"MESH"' |
}, |
'MAX_TRANSACTION_WIDTH' => { |
'value' => '13' |
}, |
'V' => { |
'value' => '2' |
}, |
'C' => { |
'value' => 0 |
}, |
'B' => { |
'value' => '4' |
}, |
'FIRST_ARBITER_EXT_P_EN' => { |
'value' => 1 |
}, |
'MIN_PCK_SIZE' => { |
'value' => '2' |
}, |
'SWA_ARBITER_TYPE' => { |
'value' => '"RRA"' |
}, |
'BYTE_EN' => { |
'value' => 0 |
}, |
'T3' => { |
'value' => '1' |
}, |
'VC_REALLOCATION_TYPE' => { |
'value' => '"NONATOMIC"' |
}, |
'ROUTE_NAME' => { |
'value' => '"XY"' |
}, |
'SMART_MAX' => { |
'value' => '0' |
}, |
'DEBUG_EN' => { |
'value' => '0' |
}, |
'HDATA_PRECAPw' => { |
'value' => '0' |
}, |
'TOPOLOGY' => { |
'value' => '"MESH"' |
}, |
'SSA_EN' => { |
'value' => '"NO"' |
}, |
'ADD_PIPREG_AFTER_CROSSBAR' => { |
'value' => '1\'b0' |
}, |
'MAX_BURST_SIZE' => { |
'value' => '16' |
}, |
'RAw' => { |
'value' => '16' |
}, |
'ADD_PIPREG_AFTER_CROSSBAR' => { |
'value' => '1\'b0' |
}, |
'CRC_EN' => { |
'value' => '"NO"' |
}, |
'ROUTE_NAME' => { |
'value' => '"XY"' |
}, |
'COMBINATION_TYPE' => { |
'value' => '"COMB_NONSPEC"' |
}, |
'SELw' => { |
'value' => '4' |
'TAGw' => { |
'value' => '3' |
}, |
'ESCAP_VC_MASK' => { |
'value' => '2\'b01' |
}, |
'AVC_ATOMIC_EN' => { |
'value' => 0 |
}, |
'Dw' => { |
'value' => '32' |
}, |
'CONGESTION_INDEX' => { |
'value' => 3 |
}, |
'SSA_EN' => { |
'value' => '"NO"' |
}, |
'SMART_MAX' => { |
'value' => '0' |
}, |
'MIN_PCK_SIZE' => { |
'value' => '2' |
}, |
'S_Aw' => { |
'value' => '8' |
}, |
'Fpay' => { |
'value' => '32' |
}, |
'VC_REALLOCATION_TYPE' => { |
'value' => '"NONATOMIC"' |
}, |
'T1' => { |
'value' => '2' |
}, |
'MUX_TYPE' => { |
'value' => '"BINARY"' |
}, |
'SELw' => { |
'value' => '4' |
}, |
'BYTE_EN' => { |
'value' => '1' |
}, |
'M_Aw' => { |
'value' => '32' |
}, |
'LB' => { |
'value' => '4' |
}, |
'V' => { |
'value' => '2' |
}, |
'WEIGHTw' => { |
'value' => '4' |
}, |
'HDATA_PRECAPw' => { |
'value' => '0' |
}, |
'ESCAP_VC_MASK' => { |
'value' => '2\'b01' |
}, |
'T2' => { |
'value' => '2' |
}, |
'EAw' => { |
'RAw' => { |
'value' => '16' |
}, |
'T3' => { |
'value' => '1' |
}, |
'TAGw' => { |
'value' => '3' |
}, |
'M_Aw' => { |
'value' => '32' |
}, |
'SELF_LOOP_EN' => { |
'value' => '"NO"' |
}, |
'T1' => { |
'value' => '2' |
} |
'CAST_TYPE' => { |
'value' => '"UNICAST"' |
} |
}, |
'module_name' => 'ni_master', |
'sockets' => { |
'ni' => { |
'connection_num' => 'single connection', |
'nums' => { |
'0' => { |
'name' => 'ni' |
} |
}, |
'type' => 'num', |
'value' => 1 |
} |
}, |
'parameters_order' => [ |
'MAX_TRANSACTION_WIDTH', |
'MAX_BURST_SIZE', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'CRC_EN', |
'RAw', |
'EAw', |
'HDATA_PRECAPw' |
], |
'instance_name' => 'ni', |
'plugs' => { |
'reset' => { |
'connection_num' => undef, |
'nums' => { |
'0' => { |
'name' => 'reset', |
'connect_id' => 'clk_source0', |
'connect_socket' => 'reset', |
'connect_socket_num' => '0' |
} |
}, |
'type' => 'num', |
'value' => 1 |
}, |
'wb_master' => { |
'connection_num' => undef, |
'value' => 2, |
'type' => 'num', |
'nums' => { |
'0' => { |
'name' => 'wb_send', |
'connect_id' => 'wishbone_bus0', |
'connect_socket_num' => '2', |
'connect_socket' => 'wb_master' |
}, |
'1' => { |
'name' => 'wb_receive', |
'connect_id' => 'wishbone_bus0', |
'connect_socket' => 'wb_master', |
'connect_socket_num' => '3' |
} |
} |
}, |
'wb_slave' => { |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_socket_num' => '1', |
'end' => 3087008767, |
'connect_socket_num' => '1', |
'width' => 10, |
'connect_socket' => 'wb_slave', |
'base' => 3087007744, |
'connect_id' => 'wishbone_bus0', |
'name' => 'wb_slave', |
'width' => 10, |
'addr' => '0xb800_0000 0xbfff_ffff custom devices', |
'base' => 3087007744 |
'name' => 'wb_slave' |
} |
}, |
'type' => 'num', |
'value' => 1, |
'connection_num' => undef |
}, |
'interrupt_peripheral' => { |
'connection_num' => undef, |
'type' => 'num', |
'nums' => { |
'0' => { |
'name' => 'interrupt', |
'connect_id' => 'mor1kx0', |
'connect_socket_num' => '0', |
'connect_socket' => 'interrupt_peripheral' |
} |
}, |
'value' => 1 |
}, |
'clk' => { |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
298,626 → 822,372
} |
}, |
'type' => 'num', |
'connection_num' => undef, |
'value' => 1 |
}, |
'wb_master' => { |
'nums' => { |
'1' => { |
'connect_socket_num' => '3', |
'connect_socket' => 'wb_master', |
'connect_id' => 'wishbone_bus0', |
'name' => 'wb_receive' |
}, |
'0' => { |
'name' => 'wb_send', |
'connect_id' => 'wishbone_bus0', |
'connect_socket' => 'wb_master', |
'connect_socket_num' => '2' |
} |
}, |
'type' => 'num', |
'value' => 2, |
'connection_num' => undef |
}, |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'name' => 'reset', |
'connect_id' => 'clk_source0', |
'connect_socket' => 'reset', |
'connect_socket_num' => '0' |
} |
} |
}, |
'interrupt_peripheral' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'name' => 'interrupt', |
'connect_id' => 'mor1kx0', |
'connect_socket' => 'interrupt_peripheral' |
} |
} |
} |
} |
}, |
'clk_source0' => { |
'parameters' => { |
'FPGA_VENDOR' => { |
'value' => '"ALTERA"' |
} |
}, |
'module_name' => 'clk_source', |
'plugs' => { |
'reset' => { |
'nums' => { |
'0' => { |
'connect_socket' => undef, |
'name' => 'reset', |
'connect_id' => 'IO', |
'connect_socket_num' => undef |
} |
'connection_num' => undef |
} |
}, |
'module_name' => 'ni_master', |
'module' => 'ni_master', |
'description_pdf' => '/mpsoc/rtl/src_peripheral/ni/NI.pdf', |
'parameters_type' => { |
'EAw' => {}, |
'B' => { |
'value' => 'Parameter' |
}, |
'TOPOLOGY' => { |
'value' => 'Parameter' |
}, |
'value' => 1, |
'connection_num' => undef, |
'type' => 'num' |
}, |
'clk' => { |
'nums' => { |
'0' => { |
'connect_socket_num' => undef, |
'connect_socket' => undef, |
'name' => 'clk', |
'connect_id' => 'IO' |
} |
}, |
'type' => 'num', |
'connection_num' => undef, |
'value' => 1 |
} |
}, |
'instance_name' => 'source', |
'description_pdf' => undef, |
'sockets' => { |
'clk' => { |
'nums' => { |
'0' => { |
'name' => 'clk' |
} |
'MAX_TRANSACTION_WIDTH' => { |
'value' => 'Localparam' |
}, |
'PCK_TYPE' => { |
'value' => 'Parameter' |
}, |
'type' => 'num', |
'connection_num' => 'multi connection', |
'value' => 1 |
}, |
'reset' => { |
'connection_num' => 'multi connection', |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'name' => 'reset' |
} |
} |
} |
}, |
'module' => 'clk_source', |
'category' => 'Source', |
'parameters_type' => { |
'FPGA_VENDOR' => { |
'value' => 'Localparam' |
} |
}, |
'parameters_order' => [ |
'FPGA_VENDOR' |
] |
}, |
'ProNoC_jtag_uart0' => { |
'parameters_order' => [ |
'Aw', |
'SELw', |
'TAGw', |
'Dw', |
'BUFF_Aw', |
'JTAG_INDEX', |
'JDw', |
'JAw', |
'JINDEXw', |
'JSTATUSw', |
'JTAG_CHAIN', |
'JTAG_CONNECT', |
'J2WBw', |
'WB2Jw', |
'INCLUDE_SIM_PRINTF' |
], |
'category' => 'Communication', |
'parameters_type' => { |
'JTAG_CHAIN' => { |
'value' => 'Localparam' |
}, |
'JINDEXw' => {}, |
'BUFF_Aw' => { |
'value' => 'Localparam' |
}, |
'SELw' => {}, |
'TAGw' => {}, |
'JDw' => {}, |
'Dw' => {}, |
'J2WBw' => {}, |
'JTAG_INDEX' => { |
'value' => 'Localparam' |
}, |
'JTAG_CONNECT' => { |
'value' => 'Localparam' |
}, |
'Aw' => {}, |
'WB2Jw' => {}, |
'JAw' => {}, |
'INCLUDE_SIM_PRINTF' => { |
'value' => 'Localparam' |
}, |
'JSTATUSw' => {} |
}, |
'module' => 'ProNoC_jtag_uart', |
'sockets' => { |
'RxD_sim' => { |
'nums' => { |
'0' => { |
'name' => 'RxD_sim' |
} |
}, |
'type' => 'num', |
'connection_num' => 'single connection', |
'value' => 1 |
'SELF_LOOP_EN' => { |
'value' => 'Parameter' |
}, |
'FIRST_ARBITER_EXT_P_EN' => { |
'value' => 'Parameter' |
}, |
'CRC_EN' => { |
'value' => 'Localparam' |
}, |
'jtag_to_wb' => { |
'nums' => { |
'0' => { |
'name' => 'jtag_to_wb' |
} |
}, |
'type' => 'num', |
'value' => 1, |
'connection_num' => 'single connection' |
} |
}, |
'description_pdf' => undef, |
'instance_name' => 'uart', |
'module_name' => 'pronoc_jtag_uart', |
'parameters' => { |
'SELw' => { |
'value' => '4' |
}, |
'BUFF_Aw' => { |
'value' => '4' |
'SWA_ARBITER_TYPE' => { |
'value' => 'Parameter' |
}, |
'WEIGHTw' => { |
'value' => 'Parameter' |
}, |
'CONGESTION_INDEX' => { |
'value' => 'Parameter' |
}, |
'Dw' => { |
'value' => 'Localparam' |
}, |
'COMBINATION_TYPE' => { |
'value' => 'Parameter' |
}, |
'LB' => { |
'value' => 'Parameter' |
}, |
'M_Aw' => {}, |
'HDATA_PRECAPw' => { |
'value' => 'Localparam' |
}, |
'T2' => { |
'value' => 'Parameter' |
}, |
'ESCAP_VC_MASK' => { |
'value' => 'Parameter' |
}, |
'RAw' => {}, |
'CAST_TYPE' => { |
'value' => 'Parameter' |
}, |
'JTAG_CHAIN' => { |
'value' => '3' |
'AVC_ATOMIC_EN' => { |
'value' => 'Parameter' |
}, |
'TAGw' => {}, |
'MIN_PCK_SIZE' => { |
'value' => 'Parameter' |
}, |
'JINDEXw' => { |
'value' => '8' |
}, |
'Dw' => { |
'value' => '32' |
'S_Aw' => {}, |
'MUX_TYPE' => { |
'value' => 'Parameter' |
}, |
'Fpay' => { |
'value' => 'Parameter' |
}, |
'J2WBw' => { |
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1' |
'T1' => { |
'value' => 'Parameter' |
}, |
'SELw' => {}, |
'BYTE_EN' => { |
'value' => 'Parameter' |
}, |
'TAGw' => { |
'value' => '3' |
'SMART_MAX' => { |
'value' => 'Parameter' |
}, |
'DEBUG_EN' => { |
'value' => 'Parameter' |
}, |
'SSA_EN' => { |
'value' => 'Parameter' |
}, |
'JDw' => { |
'value' => '32' |
}, |
'JTAG_CONNECT' => { |
'value' => '"ALTERA_JTAG_WB"' |
'ADD_PIPREG_AFTER_CROSSBAR' => { |
'value' => 'Parameter' |
}, |
'MAX_BURST_SIZE' => { |
'value' => 'Localparam' |
}, |
'JTAG_INDEX' => { |
'value' => '126-CORE_ID' |
}, |
'JSTATUSw' => { |
'value' => '8' |
}, |
'INCLUDE_SIM_PRINTF' => { |
'value' => 'SIMPLE_PRINTF' |
'V' => { |
'value' => 'Parameter' |
}, |
'C' => { |
'value' => 'Parameter' |
}, |
'T3' => { |
'value' => 'Parameter' |
}, |
'VC_REALLOCATION_TYPE' => { |
'value' => 'Parameter' |
}, |
'JAw' => { |
'value' => '32' |
}, |
'Aw' => { |
'value' => '1' |
}, |
'WB2Jw' => { |
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1' |
} |
}, |
'plugs' => { |
'wb_slave' => { |
'nums' => { |
'0' => { |
'base' => 2415919104, |
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller', |
'connect_id' => 'wishbone_bus0', |
'name' => 'wb_slave', |
'connect_socket' => 'wb_slave', |
'width' => 4, |
'connect_socket_num' => '3', |
'end' => 2415919119 |
} |
}, |
'type' => 'num', |
'connection_num' => undef, |
'value' => 1 |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'clk', |
'connect_socket' => 'clk' |
} |
} |
}, |
'reset' => { |
'type' => 'num', |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_id' => 'clk_source0', |
'name' => 'reset', |
'connect_socket' => 'reset', |
'connect_socket_num' => '0' |
} |
} |
} |
} |
}, |
'ROUTE_NAME' => { |
'value' => 'Parameter' |
} |
}, |
'category' => 'NoC' |
}, |
'mor1kx0' => { |
'parameters_order' => [ |
'OPTION_OPERAND_WIDTH', |
'IRQ_NUM', |
'OPTION_DCACHE_SNOOP', |
'FEATURE_INSTRUCTIONCACHE', |
'FEATURE_DATACACHE', |
'FEATURE_IMMU', |
'FEATURE_DMMU', |
'FEATURE_MULTIPLIER', |
'FEATURE_DIVIDER', |
'OPTION_SHIFTER' |
], |
'description_pdf' => undef, |
'parameters_type' => { |
'OPTION_OPERAND_WIDTH' => {}, |
'IRQ_NUM' => {}, |
'FEATURE_MULTIPLIER' => { |
'value' => 'Localparam' |
}, |
'OPTION_DCACHE_SNOOP' => { |
'value' => 'Localparam' |
}, |
'FEATURE_DMMU' => { |
'value' => 'Localparam' |
}, |
'FEATURE_IMMU' => { |
'value' => 'Localparam' |
}, |
'IRQ_NUM' => {}, |
'FEATURE_DIVIDER' => { |
'value' => 'Localparam' |
}, |
'OPTION_SHIFTER' => { |
'value' => 'Localparam' |
}, |
'OPTION_OPERAND_WIDTH' => {}, |
'FEATURE_DATACACHE' => { |
'value' => 'Localparam' |
}, |
'OPTION_SHIFTER' => { |
'value' => 'Localparam' |
}, |
'FEATURE_DIVIDER' => { |
'value' => 'Localparam' |
}, |
'FEATURE_IMMU' => { |
'value' => 'Localparam' |
}, |
'FEATURE_INSTRUCTIONCACHE' => { |
'value' => 'Localparam' |
}, |
'OPTION_DCACHE_SNOOP' => { |
'value' => 'Localparam' |
}, |
'FEATURE_DMMU' => { |
'value' => 'Localparam' |
} |
} |
}, |
'category' => 'Processor', |
'module' => 'mor1kx', |
'description_pdf' => undef, |
'sockets' => { |
'interrupt_peripheral' => { |
'value' => 'IRQ_NUM', |
'connection_num' => 'single connection', |
'type' => 'param', |
'nums' => { |
'0' => { |
'name' => 'interrupt_peripheral' |
} |
} |
} |
}, |
'instance_name' => 'cpu', |
'plugs' => { |
'enable' => { |
'nums' => { |
'0' => { |
'connect_socket_num' => undef, |
'connect_socket' => undef, |
'name' => 'enable', |
'connect_id' => 'IO' |
} |
}, |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_master' => { |
'value' => 2, |
'nums' => { |
'1' => { |
'connect_socket_num' => '1', |
'connect_socket' => 'wb_master', |
'name' => 'dwb', |
'connect_id' => 'wishbone_bus0' |
}, |
'0' => { |
'connect_socket' => 'wb_master', |
'connect_socket_num' => '0', |
'connect_socket' => 'wb_master', |
'name' => 'iwb', |
'connect_id' => 'wishbone_bus0' |
}, |
'1' => { |
'connect_socket' => 'wb_master', |
'name' => 'dwb', |
'connect_id' => 'wishbone_bus0', |
'connect_socket_num' => '1' |
} |
}, |
'connection_num' => undef, |
'value' => 2, |
'type' => 'num' |
'type' => 'num', |
'connection_num' => undef |
}, |
'reset' => { |
'value' => 1, |
'connection_num' => undef, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'reset', |
'connect_socket' => 'reset' |
} |
} |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_socket' => 'clk', |
'connect_socket_num' => '0', |
'name' => 'clk', |
'connect_id' => 'clk_source0', |
'connect_socket' => 'clk' |
'name' => 'clk' |
} |
} |
}, |
'type' => 'num' |
}, |
'snoop' => { |
'nums' => { |
'0' => { |
'connect_socket' => 'snoop', |
'connect_socket_num' => '0', |
'connect_id' => 'wishbone_bus0', |
'name' => 'snoop', |
'connect_socket' => 'snoop', |
'connect_socket_num' => '0' |
'name' => 'snoop' |
} |
}, |
'type' => 'num', |
'value' => 1, |
'connection_num' => undef |
}, |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num' |
} |
'type' => 'num', |
'nums' => { |
'0' => { |
'name' => 'reset', |
'connect_id' => 'clk_source0', |
'connect_socket_num' => '0', |
'connect_socket' => 'reset' |
} |
} |
}, |
'enable' => { |
'nums' => { |
'0' => { |
'name' => 'enable', |
'connect_id' => 'IO', |
'connect_socket' => undef, |
'connect_socket_num' => undef |
} |
}, |
'type' => 'num', |
'value' => 1, |
'connection_num' => undef |
} |
}, |
'module_name' => 'mor1k', |
'parameters_order' => [ |
'OPTION_OPERAND_WIDTH', |
'IRQ_NUM', |
'OPTION_DCACHE_SNOOP', |
'FEATURE_INSTRUCTIONCACHE', |
'FEATURE_DATACACHE', |
'FEATURE_IMMU', |
'FEATURE_DMMU', |
'FEATURE_MULTIPLIER', |
'FEATURE_DIVIDER', |
'OPTION_SHIFTER' |
], |
'parameters' => { |
'FEATURE_INSTRUCTIONCACHE' => { |
'value' => '"ENABLED"' |
}, |
'FEATURE_DATACACHE' => { |
'value' => '"ENABLED"' |
}, |
'OPTION_SHIFTER' => { |
'value' => '"BARREL"' |
}, |
'OPTION_OPERAND_WIDTH' => { |
'value' => '32' |
}, |
'FEATURE_DIVIDER' => { |
'value' => '"SERIAL"' |
}, |
'IRQ_NUM' => { |
'value' => '32' |
}, |
'FEATURE_MULTIPLIER' => { |
'value' => '"THREESTAGE"' |
}, |
'FEATURE_DATACACHE' => { |
'value' => '"ENABLED"' |
}, |
'FEATURE_IMMU' => { |
'value' => '"ENABLED"' |
}, |
'FEATURE_DIVIDER' => { |
'value' => '"SERIAL"' |
}, |
'OPTION_SHIFTER' => { |
'value' => '"BARREL"' |
}, |
'FEATURE_INSTRUCTIONCACHE' => { |
'value' => '"ENABLED"' |
}, |
'OPTION_DCACHE_SNOOP' => { |
'value' => '"ENABLED"' |
}, |
'FEATURE_DMMU' => { |
'value' => '"ENABLED"' |
}, |
'OPTION_DCACHE_SNOOP' => { |
'value' => '"ENABLED"' |
} |
} |
'FEATURE_MULTIPLIER' => { |
'value' => '"THREESTAGE"' |
} |
}, |
'sockets' => { |
'interrupt_peripheral' => { |
'connection_num' => 'single connection', |
'value' => 'IRQ_NUM', |
'nums' => { |
'0' => { |
'name' => 'interrupt_peripheral' |
} |
}, |
'type' => 'param' |
} |
} |
}, |
'single_port_ram0' => { |
'instance_name' => 'ram', |
'plugs' => { |
'clk' => { |
'type' => 'num', |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'name' => 'clk', |
'connect_id' => 'clk_source0', |
'connect_socket' => 'clk' |
} |
} |
}, |
'wb_slave' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'width' => 'WB_Byte_Aw', |
'connect_socket' => 'wb_slave', |
'name' => 'wb', |
'connect_id' => 'wishbone_bus0', |
'end' => 4194303, |
'connect_socket_num' => '0', |
'addr' => '0x0000_0000 0x3fff_ffff RAM', |
'base' => 0 |
} |
} |
}, |
'reset' => { |
'type' => 'num', |
'value' => 1, |
'connection_num' => undef, |
'nums' => { |
'0' => { |
'connect_id' => 'clk_source0', |
'name' => 'reset', |
'connect_socket' => 'reset', |
'connect_socket_num' => '0' |
} |
} |
} |
}, |
'sockets' => { |
'jtag_to_wb' => { |
'connection_num' => 'single connection', |
'value' => 1, |
'nums' => { |
'0' => { |
'name' => 'jtag_to_wb' |
} |
}, |
'type' => 'num' |
} |
}, |
'parameters' => { |
'JTAG_CHAIN' => { |
'value' => '4' |
'BURST_MODE' => { |
'value' => '"ENABLED"' |
}, |
'SELw' => { |
'value' => 'Dw/8' |
}, |
'JDw' => { |
'value' => 'Dw' |
}, |
'BYTE_WR_EN' => { |
'value' => '"YES"' |
}, |
'Dw' => { |
'value' => '32' |
}, |
'BTEw' => { |
'value' => '2' |
}, |
'JTAG_CONNECT' => { |
'value' => '"ALTERA_JTAG_WB"' |
}, |
'Aw' => { |
'value' => '14' |
}, |
'BURST_MODE' => { |
'value' => '"ENABLED"' |
'INITIAL_EN' => { |
'value' => '"YES"' |
}, |
'WB_Aw' => { |
'value' => '20' |
}, |
'INIT_FILE_PATH' => { |
'value' => 'SW_LOC' |
}, |
'JSTATUSw' => { |
'value' => '8' |
}, |
'JAw' => { |
'value' => '32' |
}, |
'JSTATUSw' => { |
'value' => '8' |
}, |
'INITIAL_EN' => { |
'value' => '"YES"' |
}, |
'CTIw' => { |
'value' => '3' |
}, |
'CORE_NUM' => { |
'value' => 'CORE_ID' |
}, |
'JINDEXw' => { |
'value' => '8' |
}, |
'JTAG_CHAIN' => { |
'value' => '4' |
}, |
'INIT_FILE_PATH' => { |
'value' => 'SW_LOC' |
}, |
'FPGA_VENDOR' => { |
'value' => '"ALTERA"' |
}, |
'JTAG_INDEX' => { |
'value' => 'CORE_ID' |
}, |
'WB_Byte_Aw' => { |
'value' => 'WB_Aw+2' |
}, |
'BYTE_WR_EN' => { |
'value' => '"YES"' |
}, |
'BTEw' => { |
'value' => '2' |
}, |
'SELw' => { |
'value' => 'Dw/8' |
}, |
'TAGw' => { |
'value' => '3' |
}, |
'JDw' => { |
'value' => 'Dw' |
}, |
'J2WBw' => { |
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1' |
}, |
'JTAG_INDEX' => { |
'value' => 'CORE_ID' |
}, |
'JTAG_CONNECT' => { |
'value' => '"ALTERA_JTAG_WB"' |
}, |
'CORE_NUM' => { |
'value' => 'CORE_ID' |
}, |
'WB2Jw' => { |
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1' |
}, |
'JINDEXw' => { |
'value' => '8' |
}, |
'MEM_CONTENT_FILE_NAME' => { |
'value' => '"ram0"' |
}, |
'WB2Jw' => { |
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1' |
'WB_Aw' => { |
'value' => '20' |
}, |
'FPGA_VENDOR' => { |
'value' => '"ALTERA"' |
} |
'Aw' => { |
'value' => '14' |
} |
}, |
'module_name' => 'wb_single_port_ram', |
'parameters_type' => { |
'JTAG_CHAIN' => { |
'value' => 'Localparam' |
}, |
'SELw' => {}, |
'JDw' => {}, |
'BYTE_WR_EN' => { |
'value' => 'Localparam' |
}, |
'Dw' => { |
'value' => 'Localparam' |
}, |
'BTEw' => {}, |
'JTAG_CONNECT' => { |
'value' => 'Localparam' |
}, |
'BURST_MODE' => { |
'value' => 'Localparam' |
}, |
'Aw' => { |
'value' => 'Localparam' |
}, |
'INIT_FILE_PATH' => {}, |
'JAw' => {}, |
'WB_Aw' => { |
'value' => 'Localparam' |
}, |
'JSTATUSw' => {}, |
'INITIAL_EN' => { |
'value' => 'Localparam' |
}, |
'JINDEXw' => {}, |
'CORE_NUM' => {}, |
'CTIw' => {}, |
'WB_Byte_Aw' => {}, |
'TAGw' => {}, |
'J2WBw' => {}, |
'JTAG_INDEX' => { |
'value' => 'Localparam' |
}, |
'MEM_CONTENT_FILE_NAME' => { |
'value' => 'Localparam' |
}, |
'WB2Jw' => {}, |
'FPGA_VENDOR' => { |
'value' => 'Localparam' |
} |
}, |
'category' => 'RAM', |
'parameters_order' => [ |
'Dw', |
'Aw', |
944,875 → 1214,842
'WB2Jw', |
'JTAG_CHAIN' |
], |
'module' => 'single_port_ram', |
'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf', |
'sockets' => { |
'jtag_to_wb' => { |
'nums' => { |
'0' => { |
'name' => 'jtag_to_wb' |
} |
}, |
'connection_num' => 'single connection', |
'value' => 1, |
'type' => 'num' |
} |
}, |
'module' => 'single_port_ram' |
}, |
'timer0' => { |
'instance_name' => 'timer', |
'plugs' => { |
'wb_slave' => { |
'type' => 'num', |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'end' => 2516582431, |
'connect_socket_num' => '2', |
'connect_socket' => 'wb_slave', |
'width' => 5, |
'connect_id' => 'wishbone_bus0', |
'name' => 'wb', |
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl', |
'base' => 2516582400 |
} |
} |
}, |
'clk' => { |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'name' => 'clk', |
'connect_id' => 'clk_source0', |
'connect_socket' => 'clk' |
} |
}, |
'value' => 1, |
'connection_num' => undef, |
'type' => 'num' |
}, |
'reset' => { |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'reset', |
'connect_socket' => 'reset' |
} |
}, |
'value' => 1, |
'connection_num' => undef, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'nums' => { |
'0' => { |
'connect_socket' => 'interrupt_peripheral', |
'connect_id' => 'mor1kx0', |
'name' => 'intrp', |
'connect_socket_num' => '1' |
} |
}, |
'type' => 'num', |
'connection_num' => undef, |
'value' => 1 |
} |
}, |
'module_name' => 'timer', |
'parameters' => { |
'Aw' => { |
'value' => '3' |
}, |
'Dw' => { |
'value' => '32' |
}, |
'TAGw' => { |
'value' => '3' |
}, |
'PRESCALER_WIDTH' => { |
'value' => '8' |
}, |
'CNTw' => { |
'value' => '32 ' |
}, |
'SELw' => { |
'value' => '4' |
} |
}, |
'parameters_type' => { |
'Dw' => {}, |
'TAGw' => {}, |
'PRESCALER_WIDTH' => { |
'category' => 'RAM', |
'parameters_type' => { |
'JAw' => {}, |
'JTAG_CHAIN' => { |
'value' => 'Localparam' |
}, |
'CTIw' => {}, |
'INIT_FILE_PATH' => {}, |
'FPGA_VENDOR' => { |
'value' => 'Localparam' |
}, |
'JTAG_INDEX' => { |
'value' => 'Localparam' |
}, |
'BURST_MODE' => { |
'value' => 'Localparam' |
}, |
'Dw' => { |
'value' => 'Localparam' |
}, |
'INITIAL_EN' => { |
'value' => 'Localparam' |
}, |
'JSTATUSw' => {}, |
'CORE_NUM' => {}, |
'WB2Jw' => {}, |
'JINDEXw' => {}, |
'MEM_CONTENT_FILE_NAME' => { |
'value' => 'Localparam' |
}, |
'WB_Aw' => { |
'value' => 'Localparam' |
}, |
'Aw' => {}, |
'SELw' => {}, |
'CNTw' => {} |
}, |
'category' => 'Timer', |
'parameters_order' => [ |
'CNTw', |
'Dw', |
'Aw', |
'TAGw', |
'SELw', |
'PRESCALER_WIDTH' |
], |
'sockets' => {}, |
'description_pdf' => '/mpsoc/rtl/src_peripheral/timer/timer.pdf', |
'module' => 'timer' |
}, |
'wishbone_bus0' => { |
'instance_name' => 'bus', |
'module_name' => 'wishbone_bus', |
'parameters' => { |
'S' => { |
'value' => '4' |
}, |
'Aw' => { |
'value' => '32' |
}, |
'M' => { |
'value' => ' 4' |
}, |
'Dw' => { |
'value' => '32' |
}, |
'BTEw' => { |
'value' => '2 ' |
}, |
'TAGw' => { |
'value' => '3' |
}, |
'SELw' => { |
'value' => 'Dw/8' |
}, |
'CTIw' => { |
'value' => '3' |
} |
}, |
'plugs' => { |
'clk' => { |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_socket' => 'clk', |
'name' => 'clk', |
'connect_id' => 'clk_source0' |
} |
'Aw' => { |
'value' => 'Localparam' |
}, |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'nums' => { |
'0' => { |
'name' => 'reset', |
'connect_id' => 'clk_source0', |
'connect_socket' => 'reset', |
'connect_socket_num' => '0' |
} |
}, |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num' |
} |
}, |
'category' => 'Bus', |
'parameters_type' => { |
'TAGw' => {}, |
'Dw' => { |
'value' => 'Localparam' |
}, |
'BTEw' => {}, |
'CTIw' => {}, |
'SELw' => {}, |
'Aw' => { |
'value' => 'Localparam' |
}, |
'S' => { |
'value' => 'Localparam' |
}, |
'M' => { |
'value' => 'Localparam' |
} |
}, |
'parameters_order' => [ |
'M', |
'S', |
'Dw', |
'Aw', |
'SELw', |
'TAGw', |
'CTIw', |
'BTEw' |
], |
'sockets' => { |
'snoop' => { |
'nums' => { |
'0' => { |
'name' => 'snoop' |
} |
}, |
'type' => 'num', |
'value' => 1, |
'connection_num' => 'single connection' |
}, |
'wb_slave' => { |
'type' => 'param', |
'connection_num' => 'single connection', |
'value' => 'S', |
'nums' => { |
'0' => { |
'name' => 'wb_slave' |
} |
} |
}, |
'wb_master' => { |
'WB_Byte_Aw' => {}, |
'BTEw' => {}, |
'BYTE_WR_EN' => { |
'value' => 'Localparam' |
}, |
'SELw' => {}, |
'JDw' => {}, |
'TAGw' => {}, |
'JTAG_CONNECT' => { |
'value' => 'Localparam' |
}, |
'J2WBw' => {} |
}, |
'plugs' => { |
'wb_slave' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'name' => 'wb_master' |
'width' => 'WB_Byte_Aw', |
'name' => 'wb', |
'addr' => '0x0000_0000 0x3fff_ffff RAM', |
'base' => 0, |
'end' => 4194303, |
'connect_socket' => 'wb_slave', |
'connect_socket_num' => '0', |
'connect_id' => 'wishbone_bus0' |
} |
}, |
'connection_num' => 'single connection', |
'value' => 'M', |
'type' => 'param' |
} |
}, |
'wb_addr_map' => { |
'connection_num' => 'single connection', |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'name' => 'wb_addr_map' |
} |
} |
} |
}, |
'description_pdf' => undef, |
'module' => 'wishbone_bus' |
} |
'clk' => { |
'nums' => { |
'0' => { |
'connect_socket' => 'clk', |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'clk' |
} |
}, |
'type' => 'num', |
'value' => 1, |
'connection_num' => undef |
}, |
'reset' => { |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_id' => 'clk_source0', |
'name' => 'reset', |
'connect_socket_num' => '0', |
'connect_socket' => 'reset' |
} |
}, |
'connection_num' => undef |
} |
}, |
'module_name' => 'wb_single_port_ram', |
'instance_name' => 'ram' |
} |
}, |
'single_port_ram0' => { |
'version' => 39 |
}, |
'current_module_param_type' => undef, |
'device_win_adj' => { |
'ha' => '0', |
'va' => '0' |
}, |
'RAM0' => { |
'end' => 65536, |
'start' => 49152 |
}, |
'soc_name' => 'mor1k_tile', |
'compile' => { |
'modelsim_bin' => '/home/alireza/intelFPGA_lite/questa/questasim/bin', |
'type' => 'Modelsim', |
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin', |
'board' => 'DE5', |
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim' |
}, |
'hdl_files' => undef, |
'tile_diagram' => { |
'show_clk' => 0, |
'show_unused' => 1, |
'show_reset' => 0 |
}, |
'Unset-intfc' => {}, |
'parameters_order' => { |
'current_module_param' => [ |
'FPGA_VENDOR', |
'M', |
'S', |
'Dw', |
'Aw', |
'SELw', |
'TAGw', |
'CTIw', |
'BTEw', |
'OPTION_OPERAND_WIDTH', |
'IRQ_NUM', |
'OPTION_DCACHE_SNOOP', |
'FEATURE_INSTRUCTIONCACHE', |
'FEATURE_DATACACHE', |
'FEATURE_IMMU', |
'FEATURE_DMMU', |
'FEATURE_MULTIPLIER', |
'FEATURE_DIVIDER', |
'OPTION_SHIFTER', |
'WB_Aw', |
'BYTE_WR_EN', |
'JTAG_CONNECT', |
'JTAG_INDEX', |
'CORE_NUM', |
'WB_Byte_Aw', |
'BURST_MODE', |
'MEM_CONTENT_FILE_NAME', |
'INITIAL_EN', |
'INIT_FILE_PATH', |
'JDw', |
'JAw', |
'JSTATUSw', |
'JINDEXw', |
'J2WBw', |
'WB2Jw', |
'JTAG_CHAIN', |
'MAX_TRANSACTION_WIDTH', |
'MAX_BURST_SIZE', |
'S_Aw', |
'M_Aw', |
'CRC_EN', |
'RAw', |
'EAw', |
'HDATA_PRECAPw', |
'CNTw', |
'PRESCALER_WIDTH', |
'BUFF_Aw', |
'INCLUDE_SIM_PRINTF' |
] |
}, |
'ROM0' => { |
'start' => 0, |
'end' => 49152 |
}, |
'SOURCE_SET' => { |
'REDEFINE_TOP' => 0, |
'SOC' => bless( { |
'modules' => {}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'refresh_soc' |
}, |
'instances' => { |
'TOP' => { |
'parameters_order' => [], |
'instance_name' => 'TOP', |
'category' => 'TOP', |
'module_name' => 'TOP', |
'plugs' => { |
'reset' => { |
'nums' => { |
'0' => { |
'connect_id' => 'IO', |
'name' => 'source_reset_in', |
'connect_socket' => undef, |
'connect_socket_num' => undef |
} |
}, |
'type' => 'num', |
'connection_num' => undef, |
'value' => 1 |
}, |
'clk' => { |
'type' => 'num', |
'value' => 1, |
'connection_num' => undef, |
'nums' => { |
'0' => { |
'connect_socket_num' => undef, |
'connect_id' => 'IO', |
'name' => 'source_clk_in', |
'connect_socket' => undef |
} |
} |
} |
}, |
'module' => 'TOP', |
'description_pdf' => undef |
} |
}, |
'soc_name' => { |
'TOP' => undef |
}, |
'hdl_files' => undef, |
'hdl_files_ticked' => undef, |
'instance_order' => [ |
'TOP' |
], |
'SOURCE_SET' => { |
'IP' => bless( { |
'ports_order' => [], |
'hdl_files' => [], |
'plugs' => { |
'reset' => { |
'1' => {}, |
'0' => { |
'name' => 'source_reset_in' |
}, |
'type' => 'num', |
'value' => 1 |
}, |
'clk' => { |
'1' => {}, |
'type' => 'num', |
'0' => { |
'name' => 'source_clk_in' |
}, |
'value' => 1 |
} |
}, |
'module_name' => 'TOP', |
'category' => 'TOP', |
'file_name' => undef, |
'GUI_REMOVE_SET' => 'DISABLE', |
'ports' => { |
'source_clk_in' => { |
'range' => undef, |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]' |
}, |
'source_reset_in' => { |
'range' => undef, |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
} |
}, |
'parameters_order' => [], |
'ip_name' => 'TOP', |
'hdl_files_ticked' => [] |
}, 'ip_gen' ) |
}, |
'TOP' => { |
'version' => 0 |
} |
}, 'soc' ) |
'gui_status' => { |
'timeout' => 0, |
'status' => 'save_project' |
}, |
'current_module_param' => undef, |
'graph_save' => {}, |
'noc_param' => {}, |
'modules' => {}, |
'top_ip' => bless( { |
'instance_ids' => { |
'ni_master0' => { |
'ports' => { |
'ni_current_r_addr' => { |
'type' => 'input', |
'intfc_name' => 'socket:ni[0]', |
'range' => 'ni_RAw-1 : 0', |
'intfc_port' => 'current_r_addr' |
}, |
'ni_chan_out' => { |
'range' => 'smartflit_chanel_t', |
'intfc_port' => 'chan_out', |
'intfc_name' => 'socket:ni[0]', |
'type' => 'output' |
}, |
'ni_current_e_addr' => { |
'intfc_name' => 'socket:ni[0]', |
'type' => 'input', |
'intfc_port' => 'current_e_addr', |
'range' => 'ni_EAw-1 : 0' |
}, |
'ni_chan_in' => { |
'interface' => { |
'socket:ni[0]' => { |
'ports' => { |
'ni_current_r_addr' => { |
'intfc_port' => 'current_r_addr', |
'type' => 'input', |
'instance_name' => 'ni_master0', |
'range' => 'ni_RAw-1 : 0' |
}, |
'ni_chan_in' => { |
'range' => 'smartflit_chanel_t', |
'intfc_port' => 'chan_in', |
'instance_name' => 'ni_master0', |
'type' => 'input' |
}, |
'ni_current_e_addr' => { |
'intfc_port' => 'current_e_addr', |
'type' => 'input', |
'instance_name' => 'ni_master0', |
'range' => 'ni_EAw-1 : 0' |
}, |
'ni_chan_out' => { |
'range' => 'smartflit_chanel_t', |
'intfc_port' => 'chan_in', |
'type' => 'input', |
'intfc_name' => 'socket:ni[0]' |
'instance_name' => 'ni_master0', |
'intfc_port' => 'chan_out', |
'type' => 'output' |
} |
}, |
'category' => 'NoC', |
'module' => 'ni_master', |
'localparam' => { |
'ni_M_Aw' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'content' => 'Dw', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '32' |
}, |
'ni_MAX_BURST_SIZE' => { |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'global_param' => 'Localparam', |
'type' => 'Combo-box', |
'default' => '16', |
'redefine_param' => 1, |
'info' => 'Maximum burst size in words. |
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ' |
}, |
'ni_TAGw' => { |
'content' => '', |
'default' => '3', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'redefine_param' => 1 |
}, |
'ni_Dw' => { |
'type' => 'Spin-button', |
'default' => '32', |
'global_param' => 'Localparam', |
'content' => '32,256,8', |
'redefine_param' => 1, |
'info' => 'wishbone_bus data width in bits.' |
}, |
'ni_SELw' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '4', |
'content' => '' |
}, |
'ni_MAX_TRANSACTION_WIDTH' => { |
'content' => '4,32,1', |
'global_param' => 'Localparam', |
'default' => '13', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'info' => 'maximum packet size width in words. |
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.' |
}, |
'ni_CRC_EN' => { |
'info' => 'The parameter can be selected as "YES" or "NO". |
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ', |
'redefine_param' => 1, |
'content' => '"YES","NO"', |
'global_param' => 'Localparam', |
'type' => 'Combo-box', |
'default' => '"NO"' |
}, |
'ni_HDATA_PRECAPw' => { |
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.', |
'redefine_param' => 1, |
'content' => '0,8,1', |
'default' => '0', |
'type' => 'Spin-button', |
'global_param' => 'Localparam' |
}, |
'ni_S_Aw' => { |
'content' => '', |
'global_param' => 'Localparam', |
'default' => '8', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'info' => 'Parameter' |
} |
}, |
'module_name' => 'ni_master', |
'parameters' => { |
'ni_EAw' => { |
'global_param' => 'Parameter', |
'default' => '16', |
'type' => 'Fixed', |
'content' => '', |
'redefine_param' => 0, |
'info' => undef |
}, |
'ni_RAw' => { |
'content' => '', |
'default' => '16', |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'info' => undef, |
'redefine_param' => 0 |
} |
}, |
'socket:RxD_sim[0]' => { |
'ports' => { |
'uart_RxD_wr_sim' => { |
'instance_name' => 'ProNoC_jtag_uart0', |
'intfc_port' => 'RxD_wr_sim', |
'type' => 'input', |
'range' => '' |
}, |
'uart_RxD_din_sim' => { |
'instance_name' => 'ProNoC_jtag_uart0', |
'intfc_port' => 'RxD_din_sim', |
'type' => 'input', |
'range' => '7:0 ' |
}, |
'uart_RxD_ready_sim' => { |
'intfc_port' => 'RxD_ready_sim', |
'instance_name' => 'ProNoC_jtag_uart0', |
'type' => 'output', |
'range' => '' |
} |
} |
}, |
'plug:clk[0]' => { |
'ports' => { |
'source_clk_in' => { |
'range' => '', |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'instance_name' => 'clk_source0' |
} |
}, |
'instance' => 'ni' |
}, |
'clk_source0' => { |
'category' => 'Source', |
} |
}, |
'plug:enable[0]' => { |
'ports' => { |
'source_reset_in' => { |
'range' => '', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
}, |
'source_clk_in' => { |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'intfc_port' => 'clk_i' |
} |
}, |
'instance' => 'source', |
'module_name' => 'clk_source', |
'module' => 'clk_source', |
'localparam' => { |
'source_FPGA_VENDOR' => { |
'info' => '', |
'redefine_param' => 1, |
'content' => '"ALTERA","XILINX"', |
'global_param' => 'Localparam', |
'type' => 'Combo-box', |
'default' => '"ALTERA"' |
} |
} |
'cpu_cpu_en' => { |
'instance_name' => 'mor1kx0', |
'intfc_port' => 'enable_i', |
'type' => 'input', |
'range' => '' |
} |
} |
}, |
'ProNoC_jtag_uart0' => { |
'category' => 'Communication', |
'socket:jtag_to_wb[0]' => { |
'ports' => { |
'ram_wb_to_jtag' => { |
'intfc_port' => 'jwb_o', |
'type' => 'output', |
'instance_name' => 'single_port_ram0', |
'range' => 'ram_WB2Jw-1 : 0' |
}, |
'uart_wb_to_jtag' => { |
'range' => 'uart_WB2Jw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'jwb_o', |
'range' => 'uart_WB2Jw-1 : 0', |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'type' => 'output' |
'instance_name' => 'ProNoC_jtag_uart0' |
}, |
'uart_jtag_to_wb' => { |
'range' => 'uart_J2WBw-1 : 0', |
'intfc_port' => 'jwb_i', |
'type' => 'input', |
'instance_name' => 'ProNoC_jtag_uart0' |
}, |
'ram_jtag_to_wb' => { |
'intfc_port' => 'jwb_i', |
'type' => 'input', |
'instance_name' => 'single_port_ram0', |
'range' => 'ram_J2WBw-1 : 0' |
} |
} |
}, |
'plug:reset[0]' => { |
'ports' => { |
'source_reset_in' => { |
'instance_name' => 'clk_source0', |
'intfc_port' => 'reset_i', |
'type' => 'input', |
'range' => '' |
} |
} |
} |
}, |
'instance_ids' => { |
'ProNoC_jtag_uart0' => { |
'instance' => 'uart', |
'ports' => { |
'uart_RxD_ready_sim' => { |
'type' => 'output', |
'intfc_name' => 'socket:RxD_sim[0]', |
'range' => '', |
'intfc_port' => 'RxD_ready_sim', |
'range' => '' |
'type' => 'output' |
}, |
'uart_jtag_to_wb' => { |
'intfc_port' => 'jwb_i', |
'type' => 'input', |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'range' => 'uart_J2WBw-1 : 0', |
'intfc_port' => 'jwb_i' |
'intfc_name' => 'socket:jtag_to_wb[0]' |
}, |
'uart_RxD_wr_sim' => { |
'type' => 'input', |
'intfc_name' => 'socket:RxD_sim[0]', |
'range' => '', |
'intfc_port' => 'RxD_wr_sim' |
}, |
'uart_RxD_din_sim' => { |
'intfc_name' => 'socket:RxD_sim[0]', |
'range' => '7:0 ', |
'type' => 'input', |
'range' => '7:0 ', |
'intfc_port' => 'RxD_din_sim' |
} |
}, |
'uart_wb_to_jtag' => { |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'range' => 'uart_WB2Jw-1 : 0', |
'type' => 'output', |
'intfc_port' => 'jwb_o' |
}, |
'uart_RxD_wr_sim' => { |
'type' => 'input', |
'intfc_port' => 'RxD_wr_sim', |
'range' => '', |
'intfc_name' => 'socket:RxD_sim[0]' |
} |
}, |
'instance' => 'uart', |
'module_name' => 'pronoc_jtag_uart', |
'localparam' => { |
'uart_TAGw' => { |
'content' => '', |
'info' => 'Parameter', |
'redefine_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'default' => '3', |
'global_param' => 'Localparam' |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'uart_SELw' => { |
'info' => 'Parameter', |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '4', |
'type' => 'Fixed' |
}, |
'uart_Aw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '1', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'content' => '' |
}, |
'uart_BUFF_Aw' => { |
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.', |
'content' => '2,16,1', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => '4', |
'type' => 'Spin-button', |
'content' => '2,16,1' |
'type' => 'Spin-button' |
}, |
'uart_SELw' => { |
'global_param' => 'Localparam', |
'default' => '4', |
'type' => 'Fixed', |
'content' => '', |
'info' => 'Parameter', |
'redefine_param' => 1 |
}, |
'uart_Dw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '32', |
'type' => 'Fixed', |
'content' => '', |
'info' => 'Parameter', |
'redefine_param' => 1 |
}, |
'uart_Aw' => { |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '1', |
'info' => 'Parameter', |
'redefine_param' => 1 |
'content' => '' |
} |
}, |
'module' => 'ProNoC_jtag_uart', |
'parameters' => { |
'uart_JTAG_CONNECT' => { |
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC. |
|
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.', |
'redefine_param' => 1, |
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"', |
'type' => 'Combo-box', |
'default' => '"ALTERA_JTAG_WB"', |
'global_param' => 'Parameter' |
}, |
'uart_JINDEXw' => { |
'info' => 'Parameter', |
'content' => '', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'default' => '8', |
'global_param' => 'Parameter' |
'type' => 'Fixed' |
}, |
'uart_JAw' => { |
'content' => '', |
'info' => 'Parameter', |
'default' => '32', |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'redefine_param' => 1 |
}, |
'uart_JTAG_INDEX' => { |
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.', |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'type' => 'Entry', |
'default' => '126-CORE_ID' |
}, |
'uart_JTAG_CHAIN' => { |
'content' => '1,2,3,4', |
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are: |
4: JTAG runtime memory programmers. |
3: UART |
1,2: reserved', |
'default' => '3', |
'type' => 'Combo-box', |
'redefine_param' => 0, |
'global_param' => 'Parameter' |
}, |
'uart_WB2Jw' => { |
'content' => '', |
'info' => '', |
'type' => 'Fixed', |
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1', |
'global_param' => 'Parameter', |
'info' => '', |
'redefine_param' => 1 |
}, |
'uart_JTAG_INDEX' => { |
'content' => '', |
'global_param' => 'Parameter', |
'type' => 'Entry', |
'default' => '126-CORE_ID', |
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.', |
'redefine_param' => 1 |
}, |
'uart_JSTATUSw' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'content' => '', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => '8', |
'content' => '' |
'default' => '8' |
}, |
'uart_JTAG_CHAIN' => { |
'default' => '3', |
'type' => 'Combo-box', |
'global_param' => 'Parameter', |
'content' => '1,2,3,4', |
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are: |
4: JTAG runtime memory programmers. |
3: UART |
1,2: reserved', |
'redefine_param' => 0 |
}, |
'uart_JAw' => { |
'default' => '32', |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'uart_JTAG_CONNECT' => { |
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"', |
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC. |
|
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.', |
'default' => '"ALTERA_JTAG_WB"', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'global_param' => 'Parameter' |
}, |
'uart_J2WBw' => { |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1', |
'type' => 'Fixed', |
'info' => undef, |
'content' => '' |
}, |
'uart_JDw' => { |
'content' => '', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'uart_JDw' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => '32', |
'content' => '' |
}, |
'uart_J2WBw' => { |
'info' => undef, |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1' |
} |
'redefine_param' => 1, |
'global_param' => 'Parameter' |
} |
}, |
'module_name' => 'pronoc_jtag_uart' |
'category' => 'Communication' |
}, |
'mor1kx0' => { |
'instance' => 'cpu', |
'localparam' => { |
'cpu_FEATURE_IMMU' => { |
'redefine_param' => 1, |
'info' => '', |
'default' => '"ENABLED"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'content' => '"NONE","ENABLED"' |
}, |
'cpu_OPTION_SHIFTER' => { |
'timer0' => { |
'module' => 'timer', |
'localparam' => { |
'timer_Aw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => '3', |
'info' => undef, |
'content' => '' |
}, |
'timer_CNTw' => { |
'info' => undef, |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '32 ' |
}, |
'timer_SELw' => { |
'default' => '4', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'content' => '', |
'info' => undef |
}, |
'timer_TAGw' => { |
'info' => undef, |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '3', |
'type' => 'Fixed' |
}, |
'timer_PRESCALER_WIDTH' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'default' => '8', |
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured. |
|
|
', |
'content' => '1,32,1' |
}, |
'timer_Dw' => { |
'content' => '', |
'info' => undef, |
'type' => 'Fixed', |
'default' => '32', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
} |
}, |
'category' => 'Timer', |
'instance' => 'timer', |
'module_name' => 'timer' |
}, |
'wishbone_bus0' => { |
'instance' => 'bus', |
'module_name' => 'wishbone_bus', |
'category' => 'Bus', |
'localparam' => { |
'bus_Dw' => { |
'info' => 'The wishbone Bus data width in bits.', |
'content' => '8,512,8', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'default' => '32' |
}, |
'bus_Aw' => { |
'default' => '32', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '4,128,1', |
'info' => 'The wishbone Bus address width' |
}, |
'bus_BTEw' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'default' => '2 ', |
'info' => undef, |
'content' => '' |
}, |
'bus_CTIw' => { |
'content' => '', |
'info' => undef, |
'type' => 'Fixed', |
'default' => '3', |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'bus_SELw' => { |
'info' => undef, |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => 'bus_Dw/8', |
'type' => 'Fixed' |
}, |
'bus_S' => { |
'info' => 'Number of wishbone slave interface', |
'content' => '1,256,1', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => '4', |
'type' => 'Spin-button' |
}, |
'bus_M' => { |
'content' => '1,256,1', |
'info' => 'Number of wishbone master interface', |
'default' => ' 4', |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'bus_TAGw' => { |
'content' => '', |
'info' => undef, |
'default' => '3', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
} |
}, |
'module' => 'wishbone_bus' |
}, |
'clk_source0' => { |
'category' => 'Source', |
'localparam' => { |
'source_FPGA_VENDOR' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '"ALTERA"', |
'type' => 'Combo-box', |
'info' => '', |
'content' => '"ALTERA","XILINX"' |
} |
}, |
'module' => 'clk_source', |
'module_name' => 'clk_source', |
'ports' => { |
'source_clk_in' => { |
'intfc_port' => 'clk_i', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]', |
'range' => '' |
}, |
'source_reset_in' => { |
'intfc_port' => 'reset_i', |
'type' => 'input', |
'range' => '', |
'intfc_name' => 'plug:reset[0]' |
} |
}, |
'instance' => 'source' |
}, |
'ni_master0' => { |
'category' => 'NoC', |
'localparam' => { |
'ni_CRC_EN' => { |
'default' => '"NO"', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '"YES","NO"', |
'info' => 'The parameter can be selected as "YES" or "NO". |
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ' |
}, |
'ni_Dw' => { |
'info' => 'wishbone_bus data width in bits.', |
'content' => '32,256,8', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'default' => '32' |
}, |
'ni_HDATA_PRECAPw' => { |
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.', |
'content' => '0,8,1', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '0', |
'type' => 'Spin-button' |
}, |
'ni_MAX_BURST_SIZE' => { |
'info' => 'Maximum burst size in words. |
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ', |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => '16', |
'type' => 'Combo-box' |
}, |
'ni_MAX_TRANSACTION_WIDTH' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'default' => '13', |
'info' => 'maximum packet size width in words. |
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.', |
'content' => '4,32,1' |
}, |
'ni_M_Aw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '32', |
'info' => 'Parameter', |
'content' => 'Dw' |
}, |
'ni_S_Aw' => { |
'default' => '8', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '', |
'info' => 'Parameter' |
}, |
'ni_SELw' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '4', |
'info' => 'Parameter', |
'content' => '' |
}, |
'ni_TAGw' => { |
'info' => 'Parameter', |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '3', |
'type' => 'Fixed' |
} |
}, |
'parameters' => { |
'ni_EAw' => { |
'redefine_param' => 0, |
'global_param' => 'Parameter', |
'default' => '16', |
'type' => 'Fixed', |
'info' => undef, |
'content' => '' |
}, |
'ni_RAw' => { |
'info' => undef, |
'content' => '', |
'redefine_param' => 0, |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => '16' |
} |
}, |
'module' => 'ni_master', |
'instance' => 'ni', |
'ports' => { |
'ni_current_e_addr' => { |
'range' => 'ni_EAw-1 : 0', |
'intfc_name' => 'socket:ni[0]', |
'type' => 'input', |
'intfc_port' => 'current_e_addr' |
}, |
'ni_chan_in' => { |
'type' => 'input', |
'intfc_port' => 'chan_in', |
'range' => 'smartflit_chanel_t', |
'intfc_name' => 'socket:ni[0]' |
}, |
'ni_chan_out' => { |
'intfc_port' => 'chan_out', |
'type' => 'output', |
'intfc_name' => 'socket:ni[0]', |
'range' => 'smartflit_chanel_t' |
}, |
'ni_current_r_addr' => { |
'range' => 'ni_RAw-1 : 0', |
'intfc_name' => 'socket:ni[0]', |
'type' => 'input', |
'intfc_port' => 'current_r_addr' |
} |
}, |
'module_name' => 'ni_master' |
}, |
'single_port_ram0' => { |
'category' => 'RAM', |
'localparam' => { |
'ram_INIT_FILE_PATH' => { |
'info' => undef, |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => 'SW_LOC', |
'type' => 'Fixed' |
}, |
'ram_INITIAL_EN' => { |
'content' => '"YES","NO"', |
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', |
'type' => 'Combo-box', |
'default' => '"YES"', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'ram_WB_Aw' => { |
'type' => 'Spin-button', |
'default' => '20', |
'global_param' => 'Localparam', |
'default' => '"BARREL"', |
'type' => 'Combo-box', |
'content' => '"BARREL","SERIAL"', |
'info' => 'Specify the shifter implementation', |
'redefine_param' => 1 |
'redefine_param' => 1, |
'content' => '4,31,1', |
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ' |
}, |
'cpu_FEATURE_INSTRUCTIONCACHE' => { |
'info' => '', |
'redefine_param' => 1, |
'content' => '"NONE","ENABLED"', |
'global_param' => 'Localparam', |
'type' => 'Combo-box', |
'default' => '"ENABLED"' |
}, |
'cpu_OPTION_OPERAND_WIDTH' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '32', |
'content' => '' |
}, |
'cpu_OPTION_DCACHE_SNOOP' => { |
'content' => '"NONE","ENABLED"', |
'ram_Aw' => { |
'content' => '4,31,1', |
'info' => 'Memory address width', |
'default' => '14', |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'ram_MEM_CONTENT_FILE_NAME' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'type' => 'Entry', |
'default' => '"ram0"', |
'info' => 'MEM_FILE_NAME: |
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time. |
|
File Path: |
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}. |
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME} |
|
file_type: |
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime. |
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command. |
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ', |
'content' => '' |
}, |
'ram_BURST_MODE' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Combo-box', |
'default' => '"ENABLED"', |
'global_param' => 'Localparam', |
'info' => '', |
'redefine_param' => 1 |
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ', |
'content' => '"DISABLED","ENABLED"' |
}, |
'cpu_FEATURE_DMMU' => { |
'content' => '"NONE","ENABLED"', |
'type' => 'Combo-box', |
'default' => '"ENABLED"', |
'global_param' => 'Localparam', |
'info' => '', |
'redefine_param' => 1 |
}, |
'cpu_FEATURE_MULTIPLIER' => { |
'type' => 'Combo-box', |
'default' => '"THREESTAGE"', |
'global_param' => 'Localparam', |
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"', |
'info' => 'Specify the multiplier implementation', |
'redefine_param' => 1 |
}, |
'cpu_FEATURE_DIVIDER' => { |
'redefine_param' => 1, |
'info' => 'Specify the divider implementation', |
'global_param' => 'Localparam', |
'default' => '"SERIAL"', |
'type' => 'Combo-box', |
'content' => '"SERIAL","NONE"' |
}, |
'cpu_FEATURE_DATACACHE' => { |
'ram_BTEw' => { |
'info' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => '2', |
'type' => 'Fixed' |
}, |
'ram_CTIw' => { |
'content' => '', |
'info' => 'Parameter', |
'default' => '3', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'ram_SELw' => { |
'info' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => 'ram_Dw/8', |
'type' => 'Fixed' |
}, |
'ram_TAGw' => { |
'info' => 'Parameter', |
'content' => '', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '3', |
'type' => 'Fixed' |
}, |
'ram_BYTE_WR_EN' => { |
'content' => '"YES","NO"', |
'info' => 'Byte enable', |
'default' => '"YES"', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'ram_CORE_NUM' => { |
'info' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Combo-box', |
'default' => '"ENABLED"', |
'content' => '"NONE","ENABLED"', |
'info' => '', |
'redefine_param' => 1 |
'type' => 'Fixed', |
'default' => 'CORE_ID' |
}, |
'cpu_IRQ_NUM' => { |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '32', |
'info' => undef, |
'redefine_param' => 1 |
} |
}, |
'module' => 'mor1kx', |
'module_name' => 'mor1k', |
'category' => 'Processor', |
'ports' => { |
'cpu_cpu_en' => { |
'range' => '', |
'intfc_port' => 'enable_i', |
'intfc_name' => 'plug:enable[0]', |
'type' => 'input' |
} |
} |
}, |
'single_port_ram0' => { |
'ports' => { |
'ram_jtag_to_wb' => { |
'range' => 'ram_J2WBw-1 : 0', |
'intfc_port' => 'jwb_i', |
'type' => 'input', |
'intfc_name' => 'socket:jtag_to_wb[0]' |
}, |
'ram_wb_to_jtag' => { |
'range' => 'ram_WB2Jw-1 : 0', |
'intfc_port' => 'jwb_o', |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'type' => 'output' |
} |
}, |
'category' => 'RAM', |
'module_name' => 'wb_single_port_ram', |
'ram_FPGA_VENDOR' => { |
'content' => '"ALTERA","XILINX","GENERIC"', |
'info' => '', |
'default' => '"ALTERA"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
} |
}, |
'parameters' => { |
'ram_JDw' => { |
'default' => 'ram_Dw', |
'type' => 'Fixed', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'info' => 'Parameter' |
}, |
'ram_JTAG_CHAIN' => { |
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are: |
4: JTAG runtime memory programmers. |
3: UART |
1,2: reserved', |
'content' => '1,2,3,4', |
'redefine_param' => 0, |
'global_param' => 'Parameter', |
'default' => '4', |
'type' => 'Combo-box' |
}, |
'ram_JAw' => { |
'info' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'type' => 'Fixed', |
'default' => '32' |
}, |
'ram_JTAG_CONNECT' => { |
'type' => 'Combo-box', |
'default' => '"ALTERA_JTAG_WB"', |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"', |
'info' => 'JTAG_CONNECT: |
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ' |
}, |
'ram_Dw' => { |
'content' => '8,1024,1', |
'info' => 'Memory data width in Bits.', |
'default' => '32', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'global_param' => 'Parameter' |
}, |
'ram_JTAG_INDEX' => { |
'redefine_param' => 1, |
'content' => '', |
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory. |
|
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1). |
1820,583 → 2057,359
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units). |
|
', |
'content' => '', |
'global_param' => 'Parameter', |
'default' => 'CORE_ID', |
'type' => 'Entry', |
'default' => 'CORE_ID' |
'redefine_param' => 1, |
'global_param' => 'Parameter' |
}, |
'ram_JDw' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'content' => '', |
'type' => 'Fixed', |
'default' => 'ram_Dw', |
'global_param' => 'Parameter' |
}, |
'ram_JAw' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'content' => '', |
'global_param' => 'Parameter', |
'default' => '32', |
'type' => 'Fixed' |
}, |
'ram_JINDEXw' => { |
'default' => '8', |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'content' => '', |
'info' => 'Parameter', |
'redefine_param' => 1 |
'type' => 'Fixed', |
'default' => '8', |
'redefine_param' => 1, |
'global_param' => 'Parameter' |
}, |
'ram_JSTATUSw' => { |
'content' => '', |
'redefine_param' => 1, |
'global_param' => 'Parameter', |
'default' => '8', |
'type' => 'Fixed', |
'global_param' => 'Parameter', |
'info' => 'Parameter', |
'redefine_param' => 1 |
'content' => '' |
}, |
'ram_JTAG_CHAIN' => { |
'content' => '1,2,3,4', |
'global_param' => 'Parameter', |
'default' => '4', |
'type' => 'Combo-box', |
'redefine_param' => 0, |
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are: |
4: JTAG runtime memory programmers. |
3: UART |
1,2: reserved' |
}, |
'ram_WB2Jw' => { |
'info' => undef, |
'global_param' => 'Parameter', |
'redefine_param' => 1, |
'content' => '', |
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1', |
'type' => 'Fixed', |
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1', |
'global_param' => 'Parameter' |
'info' => undef, |
'content' => '' |
}, |
'ram_Dw' => { |
'redefine_param' => 1, |
'info' => 'Memory data width in Bits.', |
'global_param' => 'Parameter', |
'default' => '32', |
'type' => 'Spin-button', |
'content' => '8,1024,1' |
}, |
'ram_J2WBw' => { |
'redefine_param' => 1, |
'info' => undef, |
'global_param' => 'Parameter', |
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1', |
'type' => 'Fixed', |
'info' => undef, |
'content' => '' |
}, |
'ram_JTAG_CONNECT' => { |
'default' => '"ALTERA_JTAG_WB"', |
'type' => 'Combo-box', |
'global_param' => 'Parameter', |
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"', |
'info' => 'JTAG_CONNECT: |
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ', |
'redefine_param' => 1 |
} |
} |
}, |
'module' => 'single_port_ram', |
'localparam' => { |
'ram_CTIw' => { |
'type' => 'Fixed', |
'default' => '3', |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'info' => 'Parameter' |
}, |
'ram_Aw' => { |
'global_param' => 'Localparam', |
'default' => '14', |
'type' => 'Spin-button', |
'content' => '4,31,1', |
'info' => 'Memory address width', |
'redefine_param' => 1 |
}, |
'ram_FPGA_VENDOR' => { |
'redefine_param' => 1, |
'info' => '', |
'content' => '"ALTERA","XILINX","GENERIC"', |
'global_param' => 'Localparam', |
'default' => '"ALTERA"', |
'type' => 'Combo-box' |
}, |
'ram_BYTE_WR_EN' => { |
'redefine_param' => 1, |
'info' => 'Byte enable', |
'global_param' => 'Localparam', |
'type' => 'Combo-box', |
'default' => '"YES"', |
'content' => '"YES","NO"' |
}, |
'ram_SELw' => { |
'info' => 'Parameter', |
'redefine_param' => 1, |
'content' => '', |
'type' => 'Fixed', |
'default' => 'ram_Dw/8', |
'global_param' => 'Localparam' |
}, |
'ram_INITIAL_EN' => { |
'redefine_param' => 1, |
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', |
'content' => '"YES","NO"', |
'global_param' => 'Localparam', |
'type' => 'Combo-box', |
'default' => '"YES"' |
}, |
'ram_BTEw' => { |
'redefine_param' => 1, |
'info' => 'Parameter', |
'default' => '2', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'content' => '' |
}, |
'ram_INIT_FILE_PATH' => { |
'info' => undef, |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => 'SW_LOC', |
'content' => '' |
}, |
'ram_WB_Aw' => { |
'module_name' => 'wb_single_port_ram', |
'ports' => { |
'ram_wb_to_jtag' => { |
'type' => 'output', |
'intfc_port' => 'jwb_o', |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'range' => 'ram_WB2Jw-1 : 0' |
}, |
'ram_jtag_to_wb' => { |
'type' => 'input', |
'intfc_port' => 'jwb_i', |
'range' => 'ram_J2WBw-1 : 0', |
'intfc_name' => 'socket:jtag_to_wb[0]' |
} |
}, |
'instance' => 'ram' |
}, |
'mor1kx0' => { |
'module' => 'mor1kx', |
'localparam' => { |
'cpu_FEATURE_DIVIDER' => { |
'default' => '"SERIAL"', |
'type' => 'Combo-box', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'content' => '"SERIAL","NONE"', |
'info' => 'Specify the divider implementation' |
}, |
'cpu_IRQ_NUM' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '32', |
'type' => 'Fixed', |
'info' => undef, |
'content' => '' |
}, |
'cpu_FEATURE_IMMU' => { |
'info' => '', |
'content' => '"NONE","ENABLED"', |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => '"ENABLED"', |
'type' => 'Combo-box' |
}, |
'cpu_FEATURE_DATACACHE' => { |
'content' => '"NONE","ENABLED"', |
'info' => '', |
'default' => '"ENABLED"', |
'type' => 'Combo-box', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'cpu_FEATURE_INSTRUCTIONCACHE' => { |
'info' => '', |
'content' => '"NONE","ENABLED"', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '"ENABLED"', |
'type' => 'Combo-box' |
}, |
'cpu_FEATURE_DMMU' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '"ENABLED"', |
'type' => 'Combo-box', |
'info' => '', |
'content' => '"NONE","ENABLED"' |
}, |
'cpu_OPTION_SHIFTER' => { |
'content' => '"BARREL","SERIAL"', |
'info' => 'Specify the shifter implementation', |
'type' => 'Combo-box', |
'default' => '"BARREL"', |
'global_param' => 'Localparam', |
'type' => 'Spin-button', |
'default' => '20', |
'content' => '4,31,1', |
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ', |
'redefine_param' => 1 |
}, |
'ram_BURST_MODE' => { |
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ', |
'cpu_FEATURE_MULTIPLIER' => { |
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"', |
'info' => 'Specify the multiplier implementation', |
'type' => 'Combo-box', |
'default' => '"THREESTAGE"', |
'global_param' => 'Localparam', |
'redefine_param' => 1 |
}, |
'cpu_OPTION_OPERAND_WIDTH' => { |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'default' => '32', |
'type' => 'Fixed', |
'info' => 'Parameter', |
'content' => '' |
}, |
'cpu_OPTION_DCACHE_SNOOP' => { |
'redefine_param' => 1, |
'global_param' => 'Localparam', |
'default' => '"ENABLED"', |
'type' => 'Combo-box', |
'content' => '"DISABLED","ENABLED"' |
}, |
'ram_CORE_NUM' => { |
'content' => '', |
'default' => 'CORE_ID', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'redefine_param' => 1 |
}, |
'ram_MEM_CONTENT_FILE_NAME' => { |
'content' => '', |
'global_param' => 'Localparam', |
'default' => '"ram0"', |
'type' => 'Entry', |
'info' => 'MEM_FILE_NAME: |
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time. |
|
File Path: |
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}. |
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME} |
|
file_type: |
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime. |
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command. |
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ', |
'redefine_param' => 1 |
}, |
'ram_TAGw' => { |
'content' => '', |
'type' => 'Fixed', |
'default' => '3', |
'global_param' => 'Localparam', |
'redefine_param' => 1, |
'info' => 'Parameter' |
} |
}, |
'instance' => 'ram' |
}, |
'wishbone_bus0' => { |
'instance' => 'bus', |
'module_name' => 'wishbone_bus', |
'localparam' => { |
'bus_M' => { |
'default' => ' 4', |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'content' => '1,256,1', |
'info' => 'Number of wishbone master interface', |
'redefine_param' => 1 |
}, |
'bus_SELw' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => 'bus_Dw/8', |
'content' => '', |
'redefine_param' => 1, |
'info' => undef |
}, |
'bus_Dw' => { |
'info' => 'The wishbone Bus data width in bits.', |
'redefine_param' => 1, |
'type' => 'Spin-button', |
'default' => '32', |
'global_param' => 'Localparam', |
'content' => '8,512,8' |
}, |
'bus_TAGw' => { |
'redefine_param' => 1, |
'info' => undef, |
'type' => 'Fixed', |
'default' => '3', |
'global_param' => 'Localparam', |
'content' => '' |
}, |
'bus_Aw' => { |
'redefine_param' => 1, |
'info' => 'The wishbone Bus address width', |
'default' => '32', |
'type' => 'Spin-button', |
'global_param' => 'Localparam', |
'content' => '4,128,1' |
}, |
'bus_CTIw' => { |
'content' => '', |
'default' => '3', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'bus_S' => { |
'global_param' => 'Localparam', |
'default' => '4', |
'type' => 'Spin-button', |
'content' => '1,256,1', |
'info' => 'Number of wishbone slave interface', |
'redefine_param' => 1 |
}, |
'bus_BTEw' => { |
'redefine_param' => 1, |
'info' => undef, |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '2 ' |
} |
}, |
'module' => 'wishbone_bus', |
'category' => 'Bus' |
}, |
'timer0' => { |
'category' => 'Timer', |
'module_name' => 'timer', |
'module' => 'timer', |
'localparam' => { |
'timer_CNTw' => { |
'content' => '', |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '32 ', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'timer_Dw' => { |
'redefine_param' => 1, |
'info' => undef, |
'global_param' => 'Localparam', |
'default' => '32', |
'type' => 'Fixed', |
'content' => '' |
}, |
'timer_PRESCALER_WIDTH' => { |
'redefine_param' => 1, |
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured. |
|
|
', |
'global_param' => 'Localparam', |
'default' => '8', |
'type' => 'Spin-button', |
'content' => '1,32,1' |
}, |
'timer_SELw' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'default' => '4', |
'content' => '', |
'redefine_param' => 1, |
'info' => undef |
}, |
'timer_TAGw' => { |
'content' => '', |
'default' => '3', |
'type' => 'Fixed', |
'global_param' => 'Localparam', |
'info' => undef, |
'redefine_param' => 1 |
}, |
'timer_Aw' => { |
'content' => '', |
'type' => 'Fixed', |
'default' => '3', |
'global_param' => 'Localparam', |
'info' => undef, |
'redefine_param' => 1 |
} |
}, |
'instance' => 'timer' |
} |
'info' => '', |
'content' => '"NONE","ENABLED"' |
} |
}, |
'category' => 'Processor', |
'ports' => { |
'cpu_cpu_en' => { |
'range' => '', |
'intfc_name' => 'plug:enable[0]', |
'intfc_port' => 'enable_i', |
'type' => 'input' |
} |
}, |
'instance' => 'cpu', |
'module_name' => 'mor1k' |
} |
}, |
'ports' => { |
'ram_jtag_to_wb' => { |
'type' => 'input', |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'intfc_port' => 'jwb_i', |
'range' => 'ram_J2WBw-1 : 0', |
'instance_name' => 'single_port_ram0' |
}, |
'uart_wb_to_jtag' => { |
'range' => 'uart_WB2Jw-1 : 0', |
'instance_name' => 'ProNoC_jtag_uart0', |
'intfc_port' => 'jwb_o', |
'type' => 'output', |
'intfc_name' => 'socket:jtag_to_wb[0]' |
}, |
'source_clk_in' => { |
'range' => '', |
'intfc_name' => 'plug:clk[0]', |
'instance_name' => 'clk_source0', |
'type' => 'input', |
'intfc_port' => 'clk_i' |
}, |
'ram_wb_to_jtag' => { |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'range' => 'ram_WB2Jw-1 : 0', |
'type' => 'output', |
'range' => 'ram_WB2Jw-1 : 0', |
'instance_name' => 'single_port_ram0', |
'intfc_port' => 'jwb_o' |
}, |
'uart_RxD_din_sim' => { |
'intfc_port' => 'RxD_din_sim', |
'instance_name' => 'ProNoC_jtag_uart0', |
'type' => 'input', |
'intfc_name' => 'socket:RxD_sim[0]', |
'range' => '7:0 ' |
}, |
'source_reset_in' => { |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'intfc_port' => 'reset_i', |
'instance_name' => 'clk_source0', |
'type' => 'input' |
}, |
'uart_jtag_to_wb' => { |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'range' => 'uart_J2WBw-1 : 0', |
'intfc_port' => 'jwb_i', |
'instance_name' => 'ProNoC_jtag_uart0', |
'type' => 'input' |
}, |
'uart_RxD_ready_sim' => { |
'type' => 'output', |
'intfc_name' => 'socket:RxD_sim[0]', |
'intfc_port' => 'RxD_ready_sim', |
'range' => '', |
'instance_name' => 'ProNoC_jtag_uart0', |
'range' => '' |
'type' => 'output', |
'intfc_port' => 'RxD_ready_sim' |
}, |
'ni_current_e_addr' => { |
'intfc_name' => 'socket:ni[0]', |
'range' => 'ni_EAw-1 : 0', |
'instance_name' => 'ni_master0', |
'type' => 'input', |
'intfc_port' => 'current_e_addr' |
}, |
'ni_chan_in' => { |
'instance_name' => 'ni_master0', |
'intfc_port' => 'chan_in', |
'type' => 'input', |
'intfc_name' => 'socket:ni[0]', |
'range' => 'smartflit_chanel_t' |
}, |
'ni_chan_out' => { |
'instance_name' => 'ni_master0', |
'range' => 'smartflit_chanel_t', |
'type' => 'output', |
'intfc_port' => 'chan_out', |
'type' => 'output', |
'intfc_name' => 'socket:ni[0]' |
'intfc_name' => 'socket:ni[0]', |
'range' => 'smartflit_chanel_t' |
}, |
'cpu_cpu_en' => { |
'instance_name' => 'mor1kx0', |
'range' => '', |
'intfc_port' => 'enable_i', |
'type' => 'input', |
'intfc_name' => 'plug:enable[0]' |
}, |
'uart_RxD_din_sim' => { |
'type' => 'input', |
'intfc_name' => 'socket:RxD_sim[0]', |
'intfc_port' => 'RxD_din_sim', |
'range' => '7:0 ', |
'instance_name' => 'ProNoC_jtag_uart0' |
}, |
'ni_current_r_addr' => { |
'range' => 'ni_RAw-1 : 0', |
'intfc_name' => 'socket:ni[0]', |
'instance_name' => 'ni_master0', |
'range' => 'ni_RAw-1 : 0', |
'intfc_port' => 'current_r_addr', |
'intfc_name' => 'socket:ni[0]', |
'type' => 'input' |
}, |
'uart_jtag_to_wb' => { |
'intfc_name' => 'socket:jtag_to_wb[0]', |
'type' => 'input', |
'instance_name' => 'ProNoC_jtag_uart0', |
'range' => 'uart_J2WBw-1 : 0', |
'intfc_port' => 'jwb_i' |
}, |
'uart_RxD_wr_sim' => { |
'range' => '', |
'intfc_name' => 'socket:RxD_sim[0]', |
'type' => 'input', |
'intfc_port' => 'RxD_wr_sim', |
'range' => '', |
'instance_name' => 'ProNoC_jtag_uart0' |
'instance_name' => 'ProNoC_jtag_uart0', |
'intfc_port' => 'RxD_wr_sim' |
}, |
'ni_current_e_addr' => { |
'intfc_name' => 'socket:ni[0]', |
'type' => 'input', |
'intfc_port' => 'current_e_addr', |
'range' => 'ni_EAw-1 : 0', |
'instance_name' => 'ni_master0' |
}, |
'source_clk_in' => { |
'intfc_port' => 'clk_i', |
'range' => '', |
'instance_name' => 'clk_source0', |
'type' => 'input', |
'intfc_name' => 'plug:clk[0]' |
}, |
'ni_chan_in' => { |
'range' => 'smartflit_chanel_t', |
'instance_name' => 'ni_master0', |
'intfc_port' => 'chan_in', |
'intfc_name' => 'socket:ni[0]', |
'uart_wb_to_jtag' => { |
'intfc_port' => 'jwb_o', |
'instance_name' => 'ProNoC_jtag_uart0', |
'type' => 'output', |
'range' => 'uart_WB2Jw-1 : 0', |
'intfc_name' => 'socket:jtag_to_wb[0]' |
}, |
'cpu_cpu_en' => { |
'intfc_name' => 'plug:enable[0]', |
'range' => '', |
'instance_name' => 'mor1kx0', |
'intfc_port' => 'enable_i', |
'type' => 'input' |
}, |
'source_reset_in' => { |
'instance_name' => 'clk_source0', |
'range' => '', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'type' => 'input' |
} |
}, |
'interface' => { |
'plug:enable[0]' => { |
'ports' => { |
'cpu_cpu_en' => { |
'range' => '', |
'instance_name' => 'mor1kx0', |
'intfc_port' => 'enable_i', |
'type' => 'input' |
} |
} |
}, |
'socket:RxD_sim[0]' => { |
'ports' => { |
'uart_RxD_wr_sim' => { |
'intfc_port' => 'RxD_wr_sim', |
'range' => '', |
'instance_name' => 'ProNoC_jtag_uart0', |
'type' => 'input' |
}, |
'uart_RxD_din_sim' => { |
'range' => '7:0 ', |
'instance_name' => 'ProNoC_jtag_uart0', |
'intfc_port' => 'RxD_din_sim', |
'type' => 'input' |
}, |
'uart_RxD_ready_sim' => { |
'intfc_port' => 'RxD_ready_sim', |
'range' => '', |
'instance_name' => 'ProNoC_jtag_uart0', |
'type' => 'output' |
} |
} |
}, |
'socket:jtag_to_wb[0]' => { |
'ports' => { |
'uart_jtag_to_wb' => { |
'type' => 'input', |
'instance_name' => 'ProNoC_jtag_uart0', |
'range' => 'uart_J2WBw-1 : 0', |
'intfc_port' => 'jwb_i' |
}, |
'ram_wb_to_jtag' => { |
'type' => 'output', |
'instance_name' => 'single_port_ram0', |
'range' => 'ram_WB2Jw-1 : 0', |
'intfc_port' => 'jwb_o' |
}, |
'ram_jtag_to_wb' => { |
'range' => 'ram_J2WBw-1 : 0', |
'instance_name' => 'single_port_ram0', |
'intfc_port' => 'jwb_i', |
'type' => 'input' |
}, |
'uart_wb_to_jtag' => { |
'type' => 'output', |
'range' => 'uart_WB2Jw-1 : 0', |
'instance_name' => 'ProNoC_jtag_uart0', |
'intfc_port' => 'jwb_o' |
} |
} |
}, |
'plug:clk[0]' => { |
'ports' => { |
'source_clk_in' => { |
'instance_name' => 'clk_source0', |
'range' => '', |
'intfc_port' => 'clk_i', |
'type' => 'input' |
} |
} |
}, |
'socket:ni[0]' => { |
'ports' => { |
'ni_chan_in' => { |
'type' => 'input', |
'intfc_port' => 'chan_in', |
'range' => 'smartflit_chanel_t', |
'instance_name' => 'ni_master0' |
}, |
'ni_current_e_addr' => { |
'intfc_port' => 'current_e_addr', |
'range' => 'ni_EAw-1 : 0', |
'instance_name' => 'ni_master0', |
'type' => 'input' |
}, |
'ni_chan_out' => { |
'instance_name' => 'ni_master0', |
'range' => 'smartflit_chanel_t', |
'intfc_port' => 'chan_out', |
'type' => 'output' |
}, |
'ni_current_r_addr' => { |
'intfc_port' => 'current_r_addr', |
'range' => 'ni_RAw-1 : 0', |
'instance_name' => 'ni_master0', |
'type' => 'input' |
} |
} |
}, |
'plug:reset[0]' => { |
'ports' => { |
'source_reset_in' => { |
'type' => 'input', |
'range' => '', |
'instance_name' => 'clk_source0', |
'intfc_port' => 'reset_i' |
} |
} |
} |
} |
'ram_jtag_to_wb' => { |
'intfc_port' => 'jwb_i', |
'instance_name' => 'single_port_ram0', |
'type' => 'input', |
'range' => 'ram_J2WBw-1 : 0', |
'intfc_name' => 'socket:jtag_to_wb[0]' |
} |
} |
}, 'ip_gen' ), |
'modules' => {}, |
'ROM0' => { |
'start' => 0, |
'end' => 49152 |
}, |
'device_win_adj' => { |
'ha' => '0', |
'va' => '0' |
}, |
'global_param' => { |
'CORE_ID' => 3, |
'SW_LOC' => '/home/alireza/work/git/hca_git/mpsoc_work/SOC/mor1k_tile/sw' |
}, |
'clk_source0' => { |
'version' => 1 |
}, |
'graph_save' => {}, |
'mor1kx0' => { |
'version' => 26 |
}, |
'wishbone_bus0' => { |
'version' => 1 |
}, |
'MEM0' => { |
'width' => '14', |
'percent' => 75 |
}, |
'timer0' => { |
'version' => 12 |
}, |
'single_port_ram0' => { |
'version' => 39 |
}, |
'soc_name' => 'mor1k_tile', |
'tile_diagram' => { |
'show_clk' => 0, |
'show_reset' => 0, |
'show_unused' => 1 |
}, |
'noc_param' => {}, |
'hdl_files_ticked' => undef, |
'parameters_order' => { |
'current_module_param' => [ |
'FPGA_VENDOR', |
'M', |
'S', |
'Dw', |
'Aw', |
'SELw', |
'TAGw', |
'CTIw', |
'BTEw', |
'OPTION_OPERAND_WIDTH', |
'IRQ_NUM', |
'OPTION_DCACHE_SNOOP', |
'FEATURE_INSTRUCTIONCACHE', |
'FEATURE_DATACACHE', |
'FEATURE_IMMU', |
'FEATURE_DMMU', |
'FEATURE_MULTIPLIER', |
'FEATURE_DIVIDER', |
'OPTION_SHIFTER', |
'WB_Aw', |
'BYTE_WR_EN', |
'JTAG_CONNECT', |
'JTAG_INDEX', |
'CORE_NUM', |
'WB_Byte_Aw', |
'BURST_MODE', |
'MEM_CONTENT_FILE_NAME', |
'INITIAL_EN', |
'INIT_FILE_PATH', |
'JDw', |
'JAw', |
'JSTATUSw', |
'JINDEXw', |
'J2WBw', |
'WB2Jw', |
'JTAG_CHAIN', |
'MAX_TRANSACTION_WIDTH', |
'MAX_BURST_SIZE', |
'S_Aw', |
'M_Aw', |
'CRC_EN', |
'RAw', |
'EAw', |
'HDATA_PRECAPw', |
'CNTw', |
'PRESCALER_WIDTH', |
'BUFF_Aw', |
'INCLUDE_SIM_PRINTF' |
] |
}, |
'JTAG' => { |
'M_CHAIN' => '0' |
}, |
'hdl_files_ticked' => undef, |
'MEM0' => { |
'percent' => 75, |
'width' => '14' |
}, |
'ProNoC_jtag_uart0' => { |
'version' => 11 |
}, |
'Unset-intfc' => {}, |
'RAM0' => { |
'end' => 65536, |
'start' => 49152 |
}, |
'ni_master0' => { |
'version' => 84 |
}, |
'instance_order' => [ |
'clk_source0', |
'wishbone_bus0', |
'mor1kx0', |
'single_port_ram0', |
'ni_master0', |
'timer0', |
'ProNoC_jtag_uart0' |
], |
'clk_source0' => { |
'version' => 1 |
} |
} |
}, 'soc' ); |