OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib
    from Rev 55 to Rev 56
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  •

Rev 55 → Rev 56

/mpsoc/mor1k_mpsoc.MPSOC
1,9 → 1,9
#######################################################################
## File: mor1k_mpsoc.MPSOC
##
## Copyright (C) 2014-2019 Alireza Monemi
## Copyright (C) 2014-2021 Alireza Monemi
##
## This file is part of ProNoC 1.9.1
## This file is part of ProNoC 2.1.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAVIOR.
10,1213 → 10,1365
################################################################################
 
$mor1k_mpsoc = bless( {
'RAM3' => {
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'compile_pin_pos' => {
'processors_en' => [
6,
0
],
'TOP_reset' => [
0,
0
],
'jtag_debug_reset_in' => [
0,
0
],
'TOP_clk' => [
4,
0
]
},
'MEM2' => {
'width' => '14',
'percent' => '75'
},
'RAM2' => {
'end' => 65536,
'start' => 49152
},
'mpsoc_name' => 'mor1k_mpsoc',
'compile_pin_range_lsb' => {
'processors_en' => 0
},
'ROM3' => {
'end' => 49152,
'start' => 0
},
'compile' => {
'cpu_num' => '4',
'modelsim_bin' => 'export LM_LICENSE_FILE=1717@epi03.bsc.es; /home/alireza/intelFPGA_lite/questa/questasim/bin',
'type' => 'QuartusII',
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim',
'board' => 'DE10_Nano_VB2',
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin'
},
'MEM2' => {
'percent' => '75',
'width' => '14'
},
'noc_param' => {
'T2' => '2',
'TOPOLOGY' => '"MESH"',
'SELF_LOOP_EN' => '"NO"',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'WEIGHTw' => '4',
'BYTE_EN' => '1',
'SMART_MAX' => '0',
'FIRST_ARBITER_EXT_P_EN' => 1,
'ESCAP_VC_MASK' => '2\'b01',
'PCK_TYPE' => '"MULTI_FLIT"',
'DEBUG_EN' => '0',
'CONGESTION_INDEX' => 3,
'T3' => '1',
'MCAST_ENDP_LIST' => '\'hf',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'T1' => '2',
'MIN_PCK_SIZE' => '2',
'B' => '4',
'MUX_TYPE' => '"BINARY"',
'ROUTE_NAME' => '"XY"',
'CAST_TYPE' => '"UNICAST"',
'SWA_ARBITER_TYPE' => '"RRA"',
'C' => 0,
'Fpay' => '32',
'V' => '2',
'AVC_ATOMIC_EN' => 0,
'LB' => '4',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'SSA_EN' => '"NO"'
},
'compile_assign_type' => {
'processors_en' => 'Direct',
'TOP_clk' => 'Direct',
'jtag_debug_reset_in' => 'Direct',
'TOP_reset' => 'Direct'
},
'fpga_param' => {},
'socs' => {
'mor1k_tile' => {
'tile_nums' => [
0,
1,
2,
3
],
'top' => bless( {
'interface' => {
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input'
'parameters' => {
'uart_JDw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'uart_JTAG_CHAIN' => '3',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'uart_JINDEXw' => '8',
'uart_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Dw' => '32',
'ram_JSTATUSw' => '8',
'uart_JSTATUSw' => '8',
'ram_JAw' => '32'
},
'tiles' => {
'1' => {
'parameters' => {
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JSTATUSw' => '8',
'uart_JSTATUSw' => '8',
'ram_JAw' => '32',
'ram_Dw' => '32',
'uart_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_JTAG_CHAIN' => '4',
'uart_JTAG_CHAIN' => '3',
'ram_JDw' => 'ram_Dw',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JINDEXw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"'
}
},
'2' => {
'parameters' => {
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JSTATUSw' => '8',
'ram_JAw' => '32',
'uart_JSTATUSw' => '8',
'ram_Dw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_JTAG_CHAIN' => '4',
'uart_JTAG_CHAIN' => '3',
'ram_JDw' => 'ram_Dw',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JINDEXw' => '8',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"'
}
},
'0' => {
'parameters' => {
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Dw' => '32',
'ram_JSTATUSw' => '8',
'ram_JAw' => '32',
'uart_JSTATUSw' => '8',
'uart_JDw' => '32',
'ram_Aw' => '14',
'uart_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'uart_JTAG_CHAIN' => '3',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JINDEXw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"'
}
},
'3' => {
'parameters' => {
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JINDEXw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JTAG_CHAIN' => '4',
'uart_JTAG_CHAIN' => '3',
'ram_JDw' => 'ram_Dw',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Dw' => '32',
'ram_JSTATUSw' => '8',
'ram_JAw' => '32',
'uart_JSTATUSw' => '8',
'ram_JINDEXw' => '8'
}
}
},
'instance_ids' => {
'mor1kx0' => {
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'module' => 'mor1kx',
'instance' => 'cpu',
'module_name' => 'mor1k',
'category' => 'Processor',
'localparam' => {
'cpu_FEATURE_IMMU' => {
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box'
},
'cpu_FEATURE_DIVIDER' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"SERIAL","NONE"',
'info' => 'Specify the divider implementation',
'type' => 'Combo-box',
'default' => '"SERIAL"'
},
'cpu_FEATURE_DMMU' => {
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => '',
'content' => '"NONE","ENABLED"'
},
'cpu_FEATURE_MULTIPLIER' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Specify the multiplier implementation',
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'type' => 'Combo-box',
'default' => '"THREESTAGE"'
},
'cpu_OPTION_OPERAND_WIDTH' => {
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'cpu_OPTION_SHIFTER' => {
'type' => 'Combo-box',
'default' => '"BARREL"',
'info' => 'Specify the shifter implementation',
'content' => '"BARREL","SERIAL"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'uart_RxD_ready_sim' => {
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'range' => ''
'cpu_FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'info' => '',
'default' => '"ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'cpu_IRQ_NUM' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'content' => '',
'default' => '32',
'type' => 'Fixed'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => '',
'default' => '"ENABLED"',
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box'
}
}
},
'ProNoC_jtag_uart0' => {
'instance' => 'uart',
'module' => 'ProNoC_jtag_uart',
'ports' => {
'uart_RxD_wr_sim' => {
'range' => '',
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]'
},
'uart_RxD_wr_sim' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'instance_name' => 'ProNoC_jtag_uart0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'range' => '',
'type' => 'input',
'instance_name' => 'clk_source0',
'intfc_port' => 'clk_i'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'instance_name' => 'mor1kx0',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_port' => 'jwb_i'
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'single_port_ram0',
'type' => 'input'
},
'uart_wb_to_jtag' => {
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0'
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o'
},
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'output',
'intfc_port' => 'jwb_o'
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_din_sim'
},
'uart_RxD_ready_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output',
'range' => ''
}
},
'module_name' => 'pronoc_jtag_uart',
'category' => 'Communication',
'localparam' => {
'uart_BUFF_Aw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '2,16,1',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'type' => 'Spin-button',
'default' => '4'
},
'uart_Aw' => {
'type' => 'Fixed',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '1',
'info' => 'Parameter'
},
'uart_Dw' => {
'content' => '',
'info' => 'Parameter',
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'uart_SELw' => {
'type' => 'Fixed',
'default' => '4',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'uart_TAGw' => {
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '3',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr',
'instance_name' => 'ni_master0'
},
'ni_chan_in' => {
'range' => 'smartflit_chanel_t',
'intfc_port' => 'chan_in',
'instance_name' => 'ni_master0',
'type' => 'input'
},
'ni_chan_out' => {
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'chan_out'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'intfc_port' => 'current_r_addr',
'type' => 'input',
'instance_name' => 'ni_master0'
}
}
}
},
'parameters' => {
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_JAw' => '32',
'ram_Dw' => '32',
'uart_JAw' => '32',
'uart_JTAG_CHAIN' => '3',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JSTATUSw' => '8',
'uart_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'ram_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1'
},
'instance_ids' => {
'timer0' => {
'module' => 'timer',
'localparam' => {
'timer_CNTw' => {
'content' => '',
'info' => undef,
'default' => '32 ',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'timer_SELw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '4',
'type' => 'Fixed'
},
'timer_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'content' => ''
},
'timer_PRESCALER_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8',
'type' => 'Spin-button',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'content' => '1,32,1'
},
'timer_Dw' => {
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => undef
},
'timer_TAGw' => {
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => undef
}
},
'category' => 'Timer',
'instance' => 'timer',
'module_name' => 'timer'
},
'ProNoC_jtag_uart0' => {
'category' => 'Communication',
},
'parameters' => {
'uart_JTAG_CONNECT' => {
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box'
},
'uart_JSTATUSw' => {
'type' => 'Fixed',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '8',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
'info' => 'Parameter'
},
'uart_J2WBw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'type' => 'Fixed'
},
'uart_JDw' => {
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JINDEXw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => 'Parameter',
'default' => '8',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
'default' => '8'
},
'uart_JTAG_CONNECT' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box',
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"'
},
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '126-CORE_ID',
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'type' => 'Entry',
'default' => '126-CORE_ID'
'content' => ''
},
'uart_JAw' => {
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => 'Parameter'
},
'uart_J2WBw' => {
'type' => 'Fixed',
'content' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'content' => '1,2,3,4',
'global_param' => 'Parameter',
'default' => '3',
'type' => 'Combo-box',
'redefine_param' => 0,
'default' => '3',
'type' => 'Combo-box'
'global_param' => 'Parameter'
},
'uart_WB2Jw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'info' => '',
'content' => ''
}
},
'module' => 'ProNoC_jtag_uart',
'localparam' => {
'uart_BUFF_Aw' => {
'default' => '4',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '2,16,1',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.'
},
'uart_Dw' => {
},
'uart_JAw' => {
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'uart_JDw' => {
'content' => '',
'info' => 'Parameter',
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
}
}
},
'single_port_ram0' => {
'localparam' => {
'ram_BYTE_WR_EN' => {
'default' => '"YES"',
'type' => 'Combo-box',
'info' => 'Byte enable',
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_TAGw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'default' => '3',
'content' => '',
'info' => 'Parameter'
},
'ram_INIT_FILE_PATH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'content' => '',
'default' => 'SW_LOC',
'type' => 'Fixed'
},
'ram_BURST_MODE' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'type' => 'Combo-box',
'content' => '"DISABLED","ENABLED"'
},
'ram_INITIAL_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'default' => '"YES"',
'content' => '"YES","NO"',
'type' => 'Combo-box'
},
'ram_CTIw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '3'
},
'ram_CORE_NUM' => {
'content' => '',
'info' => 'Parameter',
'default' => 'CORE_ID',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_WB_Aw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'content' => '4,31,1',
'type' => 'Spin-button',
'default' => '20'
},
'ram_SELw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'type' => 'Fixed',
'content' => ''
},
'uart_TAGw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '3',
'info' => 'Parameter',
'content' => ''
},
'uart_SELw' => {
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '4',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'uart_Aw' => {
'ram_Aw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Memory address width',
'content' => '4,31,1',
'default' => '14',
'type' => 'Spin-button'
},
'ram_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ALTERA"',
'content' => '"ALTERA","XILINX","GENERIC"',
'info' => ''
},
'ram_BTEw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'default' => '2',
'type' => 'Fixed',
'redefine_param' => 1,
'default' => '1',
'type' => 'Fixed'
}
},
'instance' => 'uart',
'module_name' => 'pronoc_jtag_uart',
'ports' => {
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
'global_param' => 'Localparam'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'type' => 'Entry',
'content' => ''
}
},
'parameters' => {
'ram_JSTATUSw' => {
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0'
'ram_JAw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '32',
'content' => '',
'type' => 'Fixed'
},
'ram_JTAG_CONNECT' => {
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"ALTERA_JTAG_WB"'
},
'ram_Dw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '32',
'type' => 'Spin-button',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1'
},
'ram_WB2Jw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'info' => undef,
'type' => 'Fixed',
'content' => ''
},
'ram_J2WBw' => {
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'info' => undef,
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => ''
},
'ram_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'type' => 'Combo-box',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'redefine_param' => 0,
'global_param' => 'Parameter'
},
'ram_JDw' => {
'info' => 'Parameter',
'content' => '',
'default' => 'ram_Dw',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram_JINDEXw' => {
'default' => '8',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
'ram_JTAG_INDEX' => {
'default' => 'CORE_ID',
'type' => 'Entry',
'content' => '',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'global_param' => 'Parameter',
'redefine_param' => 1
}
}
},
'wishbone_bus0' => {
'localparam' => {
'bus_SELw' => {
'type' => 'Fixed',
'default' => 'bus_Dw/8',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => undef
},
'bus_CTIw' => {
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => undef
},
'bus_S' => {
'content' => '1,256,1',
'info' => 'Number of wishbone slave interface',
'default' => '4',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'bus_TAGw' => {
'content' => '',
'info' => undef,
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'bus_M' => {
'content' => '1,256,1',
'info' => 'Number of wishbone master interface',
'type' => 'Spin-button',
'default' => ' 4',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'bus_Dw' => {
'info' => 'The wishbone Bus data width in bits.',
'content' => '8,512,8',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'default' => '32'
},
'bus_Aw' => {
'info' => 'The wishbone Bus address width',
'content' => '4,128,1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '32',
'type' => 'Spin-button'
},
'bus_BTEw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '2 ',
'type' => 'Fixed'
}
},
'module' => 'wishbone_bus',
'category' => 'Bus',
'module_name' => 'wishbone_bus',
'instance' => 'bus'
},
},
'ports' => {
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0'
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input'
}
},
'module' => 'single_port_ram',
'instance' => 'ram',
'module_name' => 'wb_single_port_ram',
'category' => 'RAM'
},
'clk_source0' => {
'category' => 'Source',
'module' => 'clk_source',
'localparam' => {
'source_FPGA_VENDOR' => {
'default' => '"ALTERA"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX"',
'info' => ''
}
},
'ports' => {
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_port' => 'clk_i'
'intfc_name' => 'plug:clk[0]'
},
'source_reset_in' => {
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => ''
'type' => 'input'
}
},
'localparam' => {
'source_FPGA_VENDOR' => {
'content' => '"ALTERA","XILINX"',
'info' => '',
'default' => '"ALTERA"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'module' => 'clk_source',
'instance' => 'source',
'module_name' => 'clk_source'
'module_name' => 'clk_source',
'category' => 'Source'
},
'ni_master0' => {
'ports' => {
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0'
},
'ni_chan_out' => {
'type' => 'output',
'intfc_port' => 'chan_out',
'range' => 'smartflit_chanel_t',
'intfc_name' => 'socket:ni[0]'
},
'ni_chan_in' => {
'intfc_port' => 'chan_in',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_e_addr',
'type' => 'input'
}
},
'instance' => 'ni',
'module_name' => 'ni_master',
'category' => 'NoC',
'parameters' => {
'ni_RAw' => {
'content' => '',
'info' => undef,
'default' => '16',
'type' => 'Fixed',
'redefine_param' => 0,
'global_param' => 'Parameter'
},
'ni_EAw' => {
'global_param' => 'Parameter',
'redefine_param' => 0,
'default' => '16',
'type' => 'Fixed',
'info' => undef,
'content' => ''
}
},
'module' => 'ni_master',
'localparam' => {
'ni_TAGw' => {
'default' => '3',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_CRC_EN' => {
'default' => '"NO"',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter',
'default' => '4',
'type' => 'Fixed'
},
'ni_MAX_BURST_SIZE' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '16',
'type' => 'Combo-box'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'default' => '13',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.'
'type' => 'Spin-button',
'default' => '13'
},
'ni_M_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw'
'content' => 'Dw',
'info' => 'Parameter'
},
'ni_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'info' => 'wishbone_bus data width in bits.',
'type' => 'Spin-button',
'content' => '32,256,8'
},
'ni_S_Aw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '8',
'type' => 'Fixed'
},
'ni_SELw' => {
'type' => 'Fixed',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '4'
'redefine_param' => 1
},
'ni_TAGw' => {
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ni_CRC_EN' => {
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"NO"'
},
'ni_Dw' => {
'default' => '32',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '32,256,8',
'info' => 'wishbone_bus data width in bits.'
},
'ni_HDATA_PRECAPw' => {
'type' => 'Spin-button',
'default' => '0',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '0,8,1',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.'
'type' => 'Spin-button',
'content' => '0,8,1'
}
}
},
'parameters' => {
'ni_EAw' => {
'redefine_param' => 0,
'global_param' => 'Parameter',
'info' => undef,
'content' => '',
'default' => '16',
'type' => 'Fixed'
},
'ni_RAw' => {
'type' => 'Fixed',
'default' => '16',
'content' => '',
'info' => undef,
'global_param' => 'Parameter',
'redefine_param' => 0
}
},
'module' => 'ni_master',
'instance' => 'ni',
'ports' => {
'ni_chan_in' => {
'type' => 'input',
'intfc_port' => 'chan_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_e_addr',
'range' => 'ni_EAw-1 : 0'
},
'ni_chan_out' => {
'range' => 'smartflit_chanel_t',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'chan_out'
}
},
'module_name' => 'ni_master',
'category' => 'NoC'
},
'mor1kx0' => {
'category' => 'Processor',
'localparam' => {
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"'
},
'cpu_OPTION_SHIFTER' => {
'info' => 'Specify the shifter implementation',
'content' => '"BARREL","SERIAL"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"BARREL"'
},
'cpu_FEATURE_DMMU' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'type' => 'Combo-box'
},
'cpu_FEATURE_MULTIPLIER' => {
'type' => 'Combo-box',
'default' => '"THREESTAGE"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'info' => 'Specify the multiplier implementation'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'default' => '"ENABLED"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'info' => ''
},
'cpu_OPTION_OPERAND_WIDTH' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32'
},
'cpu_FEATURE_IMMU' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"'
},
'cpu_FEATURE_DIVIDER' => {
'default' => '"SERIAL"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"SERIAL","NONE"',
'info' => 'Specify the divider implementation'
},
'cpu_IRQ_NUM' => {
'info' => undef,
'content' => '',
'timer0' => {
'category' => 'Timer',
'module_name' => 'timer',
'module' => 'timer',
'instance' => 'timer',
'localparam' => {
'timer_Aw' => {
'default' => '3',
'type' => 'Fixed',
'content' => '',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1
},
'timer_Dw' => {
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'timer_CNTw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => undef,
'default' => '32 ',
'type' => 'Fixed'
},
'timer_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'content' => '',
'default' => '4',
'type' => 'Fixed'
},
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'default' => '8',
'content' => '1,32,1',
'type' => 'Spin-button'
},
'timer_TAGw' => {
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
}
}
},
'wishbone_bus0' => {
'localparam' => {
'bus_S' => {
'content' => '1,256,1',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Number of wishbone slave interface',
'default' => '4'
},
'bus_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => 'bus_Dw/8',
'content' => '',
'type' => 'Fixed'
},
'bus_Aw' => {
'type' => 'Spin-button',
'default' => '32',
'info' => 'The wishbone Bus address width',
'content' => '4,128,1',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'bus_TAGw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'default' => '3',
'content' => '',
'type' => 'Fixed'
},
'bus_M' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '32'
'type' => 'Spin-button',
'default' => ' 4',
'info' => 'Number of wishbone master interface',
'content' => '1,256,1'
},
'cpu_FEATURE_DATACACHE' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Combo-box'
}
},
'module' => 'mor1kx',
'module_name' => 'mor1k',
'ports' => {
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'instance' => 'cpu'
},
'single_port_ram0' => {
'instance' => 'ram',
'module_name' => 'wb_single_port_ram',
'ports' => {
'ram_jtag_to_wb' => {
'bus_BTEw' => {
'default' => '2 ',
'info' => undef,
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => ''
},
'bus_CTIw' => {
'content' => '',
'info' => undef,
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'bus_Dw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '8,512,8',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'type' => 'Spin-button'
}
},
'instance' => 'bus',
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus'
}
},
'interface' => {
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_din_sim' => {
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
},
'category' => 'RAM',
'module' => 'single_port_ram',
'parameters' => {
'ram_JSTATUSw' => {
'content' => '',
'info' => 'Parameter',
'default' => '8',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ram_JINDEXw' => {
'default' => '8',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => 'Parameter'
'uart_RxD_ready_sim' => {
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output'
},
'ram_J2WBw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'info' => undef,
'content' => ''
},
'ram_WB2Jw' => {
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => undef
},
'ram_Dw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button',
'default' => '32',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1'
},
'ram_JTAG_INDEX' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => 'CORE_ID',
'type' => 'Entry',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'content' => ''
},
'ram_JAw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed'
},
'ram_JTAG_CONNECT' => {
'type' => 'Combo-box',
'default' => '"ALTERA_JTAG_WB"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
},
'ram_JDw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => 'ram_Dw',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
},
'ram_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 0
}
},
'localparam' => {
'ram_CTIw' => {
'content' => '',
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_TAGw' => {
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ram_SELw' => {
'default' => 'ram_Dw/8',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ram_FPGA_VENDOR' => {
'type' => 'Combo-box',
'default' => '"ALTERA"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"',
'info' => ''
},
'ram_BYTE_WR_EN' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"YES"',
'type' => 'Combo-box',
'info' => 'Byte enable',
'content' => '"YES","NO"'
},
'ram_CORE_NUM' => {
'default' => 'CORE_ID',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ram_INIT_FILE_PATH' => {
'content' => '',
'info' => undef,
'default' => 'SW_LOC',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_INITIAL_EN' => {
'default' => '"YES"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"YES","NO"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram_WB_Aw' => {
'content' => '4,31,1',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'default' => '20',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_Aw' => {
'content' => '4,31,1',
'info' => 'Memory address width',
'type' => 'Spin-button',
'default' => '14',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'content' => '',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'type' => 'Entry',
'default' => '"ram0"',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_BTEw' => {
'default' => '2',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter'
},
'ram_BURST_MODE' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Combo-box',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'content' => '"DISABLED","ENABLED"'
}
}
}
},
'tiles' => {
'0' => {
'parameters' => {
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_JINDEXw' => '8',
'ram_JSTATUSw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_JTAG_CHAIN' => '3',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_JAw' => '32',
'uart_JAw' => '32',
'ram_Dw' => '32'
}
},
'1' => {
'parameters' => {
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Aw' => '14',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'ram_JINDEXw' => '8',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JAw' => '32',
'ram_Dw' => '32',
'uart_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_CHAIN' => '3',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1'
}
},
'2' => {
'parameters' => {
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_Dw' => '32',
'uart_JAw' => '32',
'uart_JTAG_CHAIN' => '3',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JINDEXw' => '8',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'ram_Aw' => '14',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JSTATUSw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"'
}
},
'3' => {
'parameters' => {
'ram_Dw' => '32',
'ram_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JDw' => 'ram_Dw',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'uart_JTAG_CHAIN' => '3',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Aw' => '14',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JINDEXw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'uart_JSTATUSw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1'
}
}
},
'uart_RxD_wr_sim' => {
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'RxD_wr_sim',
'type' => 'input'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input'
}
}
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0'
},
'uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0'
},
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_o',
'type' => 'output'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_chan_out' => {
'instance_name' => 'ni_master0',
'range' => 'smartflit_chanel_t',
'type' => 'output',
'intfc_port' => 'chan_out'
},
'ni_chan_in' => {
'intfc_port' => 'chan_in',
'type' => 'input',
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0'
},
'ni_current_e_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0'
}
}
}
},
'ports' => {
'uart_RxD_ready_sim' => {
'instance_name' => 'ProNoC_jtag_uart0',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'output',
'intfc_port' => 'RxD_ready_sim'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_chan_in' => {
'intfc_port' => 'chan_in',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0'
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => ''
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'intfc_port' => 'RxD_din_sim',
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'source_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
},
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'type' => 'output',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'mor1kx0',
'range' => ''
},
'uart_jtag_to_wb' => {
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'uart_RxD_wr_sim' => {
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0'
},
'uart_wb_to_jtag' => {
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim'
'range' => 'uart_WB2Jw-1 : 0'
},
'ni_chan_out' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'chan_out',
'range' => 'smartflit_chanel_t',
'intfc_name' => 'socket:ni[0]'
},
'ni_chan_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t',
'type' => 'input',
'intfc_port' => 'chan_in',
'instance_name' => 'ni_master0'
},
'source_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
},
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'intfc_port' => 'enable_i',
'instance_name' => 'mor1kx0',
'type' => 'input'
}
'ni_chan_out' => {
'type' => 'output',
'intfc_port' => 'chan_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'smartflit_chanel_t'
}
}
}, 'ip_gen' )
}, 'ip_gen' ),
'tile_nums' => [
0,
1,
2,
3
]
}
},
'MEM1' => {
'percent' => '75',
'width' => '14'
'width' => '14',
'percent' => '75'
},
'ROM0' => {
'start' => 0,
'end' => 22937
},
'file_name' => undef,
'RAM1' => {
'end' => 65536,
'start' => 49152
},
'MEM3' => {
'width' => '14',
'percent' => '75'
},
'SOURCE_SET_CONNECT' => {
'T3_cs_clk_in' => 'clk',
'T0_cs_reset_in' => 'reset',
'T3_ss_clk_in' => 'clk0',
'T0_ss_reset_in' => 'reset0',
'NoC_reset' => 'reset',
'T1_ss_reset_in' => 'reset0',
'T2_ss_reset_in' => 'reset0',
'T1_cs_reset_in' => 'reset',
'T2_cs_reset_in' => 'reset',
'T2_ss_clk_in' => 'clk0',
'T1_ss_clk_in' => 'clk0',
'T2_cs_clk_in' => 'clk',
'T1_cs_clk_in' => 'clk',
'T0_cs_clk_in' => 'clk',
'T3_cs_reset_in' => 'reset',
'T0_ss_clk_in' => 'clk0',
'T3_ss_reset_in' => 'reset0',
'NoC_clk' => 'clk'
},
'ROM2' => {
'start' => 0,
'end' => 49152
},
'get_config_adj' => {
'ha' => '0',
'va' => '0'
},
'RAM3' => {
'end' => 65536,
'start' => 49152
},
'compile_pin' => {
'jtag_debug_reset_in' => '*GND',
'TOP_reset' => '*GND',
'TOP_clk' => 'FPGA_CLK1_50',
'processors_en' => 'KEY'
},
'RAM0' => {
'start' => 22937,
'end' => 32768
},
'ROM1' => {
'end' => 49152,
'start' => 0
},
'MEM0' => {
'percent' => '70',
'width' => '13'
},
'compile_pin_range_lsb' => {
'processors_en' => 0
},
'compile' => {
'type' => 'Modelsim',
'board' => 'DE10_Nano_VB2',
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin',
'cpu_num' => '4',
'modelsim_bin' => 'export LM_LICENSE_FILE=1717@epi03.bsc.es; /home/alireza/intelFPGA_lite/questa/questasim/bin',
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim'
},
'tile' => {
'0' => {},
'2' => {},
'1' => {},
'3' => {}
},
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
},
'SOURCE_SET' => {
'reset_0_name' => 'reset',
'clk_number' => 1,
'reset_number' => 1,
'reset_0_name' => 'reset',
'REDEFINE_TOP' => 0,
'clk_0_name' => 'clk',
'SOC' => bless( {
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'TOP' => {
'version' => 0
},
'hdl_files' => undef,
'instance_order' => [
'TOP'
],
'instances' => {
'TOP' => {
'parameters_order' => [],
'sockets' => {},
'module_name' => 'TOP',
'category' => 'TOP',
'description_pdf' => undef,
'module' => 'TOP',
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'reset',
'connect_socket' => undef,
'connect_socket_num' => undef
}
}
},
'clk' => {
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'clk',
'connect_id' => 'IO',
'connect_socket' => undef,
'connect_socket_num' => undef
'connect_socket' => undef
}
},
'value' => 1
}
'value' => 1,
'type' => 'num'
},
'reset' => {
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_id' => 'IO',
'connect_socket' => undef,
'name' => 'reset'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
}
},
'module_name' => 'TOP',
'instance_name' => 'TOP'
'description_pdf' => undef,
'instance_name' => 'TOP',
'parameters_order' => [],
'module' => 'TOP',
'sockets' => {}
}
},
'instance_order' => [
'TOP'
],
'modules' => {},
'soc_name' => {
'TOP' => undef
},
'SOURCE_SET' => {
'IP' => bless( {
'ip_name' => 'TOP',
'ports_order' => [],
'ports' => {
'reset' => {
'range' => undef,
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => undef
}
},
'file_name' => undef,
'hdl_files_ticked' => [],
'parameters_order' => [],
'GUI_REMOVE_SET' => 'DISABLE',
'module_name' => 'TOP',
'category' => 'TOP',
'hdl_files' => [],
'plugs' => {
'reset' => {
'1' => {},
'type' => 'num',
'1' => {},
'value' => 1,
'0' => {
'name' => 'reset'
1223,698 → 1375,548
}
},
'clk' => {
'1' => {},
'type' => 'num',
'value' => 1,
'1' => {},
'0' => {
'name' => 'clk'
}
}
},
'module_name' => 'TOP',
'ports' => {
'clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => undef,
'type' => 'input',
'intfc_port' => 'clk_i'
},
'reset' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => undef
}
},
'ip_name' => 'TOP',
'ports_order' => [],
'category' => 'TOP'
}
}, 'ip_gen' )
},
'TOP' => {
'version' => 0
},
'soc_name' => {
'TOP' => undef
},
'device_win_adj' => {
'va' => '0',
'ha' => '0'
},
'modules' => {}
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
}
}, 'soc' )
},
'tile' => {
'2' => {},
'0' => {},
'1' => {},
'3' => {}
},
'compile_pin_pos' => {
'TOP_reset' => [
0,
0
],
'jtag_debug_reset_in' => [
0,
0
],
'TOP_clk' => [
4,
0
],
'processors_en' => [
6,
0
]
},
'noc_indept_param' => {},
'verilator' => {
'libs' => {
'Vtile1' => '--top-module tile_1',
'Vtile3' => '--top-module tile_3',
'Vtile0' => '--top-module tile_0',
'Vrouter1' => '--top-module router_top_v -GP=5 ',
'Vtile2' => '--top-module tile_2'
}
},
'soc_param' => {
'default' => {
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JINDEXw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_CHAIN' => '3',
'ram_JTAG_CHAIN' => '4',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_JAw' => '32',
'uart_JSTATUSw' => '8',
'ram_JSTATUSw' => '8',
'ram_Dw' => '32',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JINDEXw' => '8'
}
},
'current_tile_param' => undef,
'compile_pin_range_hsb' => {},
'mpsoc_name' => 'mor1k_mpsoc',
'gen_tiles_adj' => {
'ha' => '0',
'va' => '0'
'va' => '0',
'ha' => '0'
},
'parameters_order' => {
'noc_param' => [
'TOPOLOGY',
'T1',
'T2',
'T3',
'V',
'B',
'Fpay',
'ROUTE_NAME',
'MIN_PCK_SIZE',
'BYTE_EN',
'SSA_EN',
'CONGESTION_INDEX',
'ESCAP_VC_MASK',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'SWA_ARBITER_TYPE',
'WEIGHTw',
'AVC_ATOMIC_EN',
'LB',
'PCK_TYPE',
'CAST_TYPE',
'SMART_MAX',
'SELF_LOOP_EN'
],
'SOURCE_SET' => [
'clk_number',
'clk_0_name',
'reset_number',
'reset_0_name'
],
'noc_type' => [
'ROUTER_TYPE'
],
'compile' => [
'cpu_num'
],
'SOURCE_SET_CONNECT' => [
'NoC_clk',
'T0_ss_clk_in',
'T1_ss_clk_in',
'T2_ss_clk_in',
'T3_ss_clk_in',
'NoC_reset',
'T0_ss_reset_in',
'T1_ss_reset_in',
'T2_ss_reset_in',
'T3_ss_reset_in',
'T0_cs_clk_in',
'T1_cs_clk_in',
'T2_cs_clk_in',
'T3_cs_clk_in',
'T0_cs_reset_in',
'T1_cs_reset_in',
'T2_cs_reset_in',
'T3_cs_reset_in'
]
},
'noc_indept_param' => {},
'file_name' => undef,
'noc_param' => {
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'T3' => '1',
'ROUTE_NAME' => '"XY"',
'C' => 0,
'V' => '2',
'SSA_EN' => '"NO"',
'CONGESTION_INDEX' => 3,
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'WEIGHTw' => '4',
'DEBUG_EN' => '0',
'SMART_MAX' => '0',
'SWA_ARBITER_TYPE' => '"RRA"',
'FIRST_ARBITER_EXT_P_EN' => 1,
'SELF_LOOP_EN' => '"NO"',
'Fpay' => '32',
'T1' => '2',
'MUX_TYPE' => '"BINARY"',
'PCK_TYPE' => '"MULTI_FLIT"',
'BYTE_EN' => '1',
'AVC_ATOMIC_EN' => 0,
'MIN_PCK_SIZE' => '2',
'ESCAP_VC_MASK' => '2\'b01',
'T2' => '2',
'B' => '4',
'CAST_TYPE' => '"UNICAST"',
'TOPOLOGY' => '"MESH"',
'LB' => '4'
},
'compile_pin' => {
'TOP_reset' => '*GND',
'jtag_debug_reset_in' => '*GND',
'TOP_clk' => 'FPGA_CLK1_50',
'processors_en' => 'KEY'
},
'ROM2' => {
'start' => 0,
'end' => 49152
},
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
},
'SOURCE_SET_CONNECT' => {
'T2_cs_clk_in' => 'clk',
'T1_cs_clk_in' => 'clk',
'T0_cs_clk_in' => 'clk',
'T0_ss_clk_in' => 'clk0',
'T3_ss_clk_in' => 'clk0',
'T2_ss_reset_in' => 'reset0',
'T2_cs_reset_in' => 'reset',
'T0_ss_reset_in' => 'reset0',
'T1_ss_clk_in' => 'clk0',
'T3_cs_clk_in' => 'clk',
'T3_cs_reset_in' => 'reset',
'T1_ss_reset_in' => 'reset0',
'T2_ss_clk_in' => 'clk0',
'T0_cs_reset_in' => 'reset',
'NoC_clk' => 'clk',
'T1_cs_reset_in' => 'reset',
'T3_ss_reset_in' => 'reset0',
'NoC_reset' => 'reset'
},
'compile_pin_range_hsb' => {},
'setting' => {
'show_noc_setting' => 1,
'show_adv_setting' => 0,
'show_noc_setting' => 1,
'show_tile_setting' => 1,
'soc_path' => 'lib/soc'
},
'RAM2' => {
'start' => 49152,
'end' => 65536
},
'top_ip' => bless( {
'ports' => {
'T2_uart_wb_to_jtag' => {
'range' => 'T2_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T1_uart_jtag_to_wb' => {
'instance_name' => 'T1',
'range' => 'T1_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'T1',
'intfc_port' => 'jwb_i'
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i',
'instance_name' => 'IO',
'type' => 'input'
},
'T2_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'range' => 'T2_ram_J2WBw-1 : 0'
},
'T3_ram_wb_to_jtag' => {
'instance_name' => 'T3',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T3',
'range' => 'T3_ram_WB2Jw-1 : 0'
},
'T3_ram_jtag_to_wb' => {
'range' => 'T3_ram_J2WBw-1 : 0',
'T1_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T3',
'intfc_port' => 'jwb_i',
'type' => 'input'
'instance_name' => 'T1',
'range' => 'T1_ram_J2WBw-1 : 0'
},
'T1_uart_wb_to_jtag' => {
'T2_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_uart_WB2Jw-1 : 0',
'type' => 'output',
'instance_name' => 'T1',
'intfc_port' => 'jwb_o'
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'T2',
'range' => 'T2_uart_J2WBw-1 : 0'
},
'clk' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'IO'
},
'T3_uart_wb_to_jtag' => {
'instance_name' => 'T3',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T3',
'range' => 'T3_uart_WB2Jw-1 : 0'
},
'T0_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'instance_name' => 'T0',
'range' => 'T0_ram_J2WBw-1 : 0'
},
'T0_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'instance_name' => 'T0',
'range' => 'T0_uart_J2WBw-1 : 0'
},
'processors_en' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'range' => '',
'instance_name' => 'IO',
'intfc_port' => 'enable_i',
'type' => 'input'
'instance_name' => 'IO'
},
'reset' => {
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'IO',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => ''
},
'T0_ram_jtag_to_wb' => {
'range' => 'T0_ram_J2WBw-1 : 0',
'T2_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_ram_WB2Jw-1 : 0',
'instance_name' => 'T2'
},
'T3_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'instance_name' => 'T0',
'type' => 'input'
'type' => 'input',
'instance_name' => 'T3',
'range' => 'T3_ram_J2WBw-1 : 0'
},
'T0_uart_jtag_to_wb' => {
'T0_uart_wb_to_jtag' => {
'instance_name' => 'T0',
'range' => 'T0_uart_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_J2WBw-1 : 0',
'instance_name' => 'T0',
'type' => 'input',
'intfc_port' => 'jwb_i'
'type' => 'output'
},
'T1_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_J2WBw-1 : 0',
'type' => 'input',
'instance_name' => 'T1',
'intfc_port' => 'jwb_i'
},
'T3_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T3',
'range' => 'T3_uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'T3',
'type' => 'input'
},
'T2_uart_jtag_to_wb' => {
'instance_name' => 'T2',
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_J2WBw-1 : 0'
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_ram_jtag_to_wb' => {
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T1_ram_wb_to_jtag' => {
'range' => 'T1_ram_WB2Jw-1 : 0',
'instance_name' => 'T1',
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output'
},
'T0_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'instance_name' => 'T0',
'type' => 'output'
'instance_name' => 'T0'
},
'T0_uart_wb_to_jtag' => {
'T2_uart_wb_to_jtag' => {
'range' => 'T2_uart_WB2Jw-1 : 0',
'instance_name' => 'T2',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_WB2Jw-1 : 0',
'type' => 'output',
'instance_name' => 'T0',
'intfc_port' => 'jwb_o'
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T2_ram_wb_to_jtag' => {
'type' => 'output',
'instance_name' => 'T2',
'intfc_port' => 'jwb_o',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
'T1_uart_wb_to_jtag' => {
'instance_name' => 'T1',
'range' => 'T1_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
}
},
'interface' => {
'plug:clk[0]' => {
'ports' => {
'clk' => {
'intfc_port' => 'clk_i',
'instance_name' => 'IO',
'type' => 'input',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'reset' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'IO'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'T0_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T0',
'range' => 'T0_ram_J2WBw-1 : 0'
},
'T3_uart_wb_to_jtag' => {
'instance_name' => 'T3',
'range' => 'T3_uart_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T0_uart_jtag_to_wb' => {
'instance_name' => 'T0',
'range' => 'T0_uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'T0',
'type' => 'input',
'range' => 'T0_uart_J2WBw-1 : 0'
'type' => 'input'
},
'T0_ram_jtag_to_wb' => {
'range' => 'T0_ram_J2WBw-1 : 0',
'T3_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T3',
'range' => 'T3_ram_WB2Jw-1 : 0'
},
'T2_ram_jtag_to_wb' => {
'instance_name' => 'T2',
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'T0'
'type' => 'input'
},
'T3_uart_jtag_to_wb' => {
'range' => 'T3_uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'T1_uart_jtag_to_wb' => {
'range' => 'T1_uart_J2WBw-1 : 0',
'instance_name' => 'T1',
'type' => 'input',
'instance_name' => 'T3'
'intfc_port' => 'jwb_i'
},
'T2_uart_jtag_to_wb' => {
'range' => 'T2_uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T2'
'instance_name' => 'T2',
'range' => 'T2_uart_J2WBw-1 : 0'
},
'T1_ram_jtag_to_wb' => {
'instance_name' => 'T1',
'range' => 'T1_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T1',
'range' => 'T1_ram_J2WBw-1 : 0'
'intfc_port' => 'jwb_i'
},
'T2_ram_jtag_to_wb' => {
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'T2',
'type' => 'input'
},
'T1_ram_wb_to_jtag' => {
'T2_uart_wb_to_jtag' => {
'instance_name' => 'T2',
'range' => 'T2_uart_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T0_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'instance_name' => 'T1',
'type' => 'output',
'range' => 'T1_ram_WB2Jw-1 : 0'
},
'T0_ram_wb_to_jtag' => {
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T0'
},
'T0_uart_wb_to_jtag' => {
'T1_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T0',
'range' => 'T0_uart_WB2Jw-1 : 0'
'instance_name' => 'T1',
'range' => 'T1_uart_WB2Jw-1 : 0'
},
'T3_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'T3_ram_J2WBw-1 : 0',
'instance_name' => 'T3'
},
'T2_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T2_ram_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T2'
},
'T2_uart_wb_to_jtag' => {
'T0_uart_wb_to_jtag' => {
'instance_name' => 'T0',
'range' => 'T0_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T2',
'range' => 'T2_uart_WB2Jw-1 : 0'
'intfc_port' => 'jwb_o'
},
'T1_uart_jtag_to_wb' => {
'T1_ram_wb_to_jtag' => {
'instance_name' => 'T1',
'range' => 'T1_ram_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T3_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T1',
'range' => 'T1_uart_J2WBw-1 : 0'
},
'T3_ram_wb_to_jtag' => {
'range' => 'T3_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'instance_name' => 'T3',
'type' => 'output'
},
'T3_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T3',
'range' => 'T3_uart_WB2Jw-1 : 0'
},
'T1_uart_wb_to_jtag' => {
'instance_name' => 'T1',
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T1_uart_WB2Jw-1 : 0'
},
'T3_ram_jtag_to_wb' => {
'range' => 'T3_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T3'
}
'range' => 'T3_uart_J2WBw-1 : 0',
'instance_name' => 'T3'
}
}
},
'plug:enable[0]' => {
'ports' => {
'processors_en' => {
'type' => 'input',
'instance_name' => 'IO',
'range' => '',
'intfc_port' => 'enable_i',
'instance_name' => 'IO',
'range' => ''
'type' => 'input'
}
}
}
},
'plug:clk[0]' => {
'ports' => {
'clk' => {
'range' => '',
'instance_name' => 'IO',
'intfc_port' => 'clk_i',
'type' => 'input'
}
}
},
'plug:reset[0]' => {
'ports' => {
'reset' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'IO',
'range' => ''
}
}
}
},
'instance_ids' => {
'T2' => {
'ports' => {
'T2_ram_wb_to_jtag' => {
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output'
},
'T2_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'range' => 'T2_ram_J2WBw-1 : 0'
},
'T2_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_WB2Jw-1 : 0'
},
'T2_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_J2WBw-1 : 0'
}
}
},
'IO' => {
'ports' => {
'reset' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
'type' => 'input',
'range' => ''
},
'processors_en' => {
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => ''
'intfc_name' => 'plug:enable[0]'
},
'clk' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i'
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]'
}
}
},
'T0' => {
'T1' => {
'ports' => {
'T0_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T0_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T0_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T0_ram_wb_to_jtag' => {
'T1_ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T0_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T0_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
}
},
'T3' => {
'ports' => {
'T3_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_ram_WB2Jw-1 : 0'
'range' => 'T1_ram_WB2Jw-1 : 0'
},
'T3_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_J2WBw-1 : 0'
},
'T3_uart_wb_to_jtag' => {
'type' => 'output',
'T1_uart_wb_to_jtag' => {
'range' => 'T1_uart_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_WB2Jw-1 : 0'
'type' => 'output'
},
'T3_ram_jtag_to_wb' => {
'type' => 'input',
'T1_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_ram_J2WBw-1 : 0'
}
'type' => 'input',
'range' => 'T1_ram_J2WBw-1 : 0'
},
'T1_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'T1_uart_J2WBw-1 : 0'
}
}
},
'T1' => {
'T0' => {
'ports' => {
'T1_ram_wb_to_jtag' => {
'T0_ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
'range' => 'T0_ram_WB2Jw-1 : 0'
},
'T1_uart_jtag_to_wb' => {
'T0_uart_jtag_to_wb' => {
'range' => 'T0_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_uart_J2WBw-1 : 0'
'type' => 'input'
},
'T1_uart_wb_to_jtag' => {
'range' => 'T1_uart_WB2Jw-1 : 0',
'T0_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output',
'intfc_port' => 'jwb_o'
'range' => 'T0_uart_WB2Jw-1 : 0'
},
'T1_ram_jtag_to_wb' => {
'T0_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_J2WBw-1 : 0'
'range' => 'T0_ram_J2WBw-1 : 0'
}
}
},
'T2' => {
'T3' => {
'ports' => {
'T2_ram_wb_to_jtag' => {
'T3_ram_wb_to_jtag' => {
'range' => 'T3_ram_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_uart_jtag_to_wb' => {
'range' => 'T2_uart_J2WBw-1 : 0',
'T3_uart_wb_to_jtag' => {
'range' => 'T3_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T2_ram_jtag_to_wb' => {
'T3_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_ram_J2WBw-1 : 0'
'range' => 'T3_ram_J2WBw-1 : 0'
},
'T2_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'T3_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_WB2Jw-1 : 0'
'range' => 'T3_uart_J2WBw-1 : 0'
}
}
}
}
}, 'ip_gen' ),
'ROM0' => {
'start' => 0,
'end' => 22937
},
'soc_param' => {
'default' => {
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Aw' => '14',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'uart_JDw' => '32',
'ram_JSTATUSw' => '8',
'ram_JINDEXw' => '8',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_Dw' => '32',
'uart_JAw' => '32',
'ram_JTAG_CHAIN' => '4',
'uart_JINDEXw' => '8',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_CHAIN' => '3'
}
},
'verilator' => {
'libs' => {
'Vtile3' => '--top-module tile_3',
'Vtile0' => '--top-module tile_0',
'Vrouter1' => '--top-module router_top_v -GP=5 ',
'Vtile1' => '--top-module tile_1',
'Vtile2' => '--top-module tile_2'
}
},
'JTAG' => {
'M_CHAIN' => 4
},
'get_config_adj' => {
'va' => '0',
'ha' => '0'
},
'MEM0' => {
'percent' => '70',
'width' => '13'
},
'RAM1' => {
'end' => 65536,
'start' => 49152
},
'MEM3' => {
'width' => '14',
'percent' => '75'
},
'ROM1' => {
'end' => 49152,
'start' => 0
},
'compile_assign_type' => {
'TOP_reset' => 'Direct',
'jtag_debug_reset_in' => 'Direct',
'processors_en' => 'Direct',
'TOP_clk' => 'Direct'
},
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'parameters_order' => {
'compile' => [
'cpu_num'
],
'SOURCE_SET_CONNECT' => [
'NoC_clk',
'T0_ss_clk_in',
'T1_ss_clk_in',
'T2_ss_clk_in',
'T3_ss_clk_in',
'NoC_reset',
'T0_ss_reset_in',
'T1_ss_reset_in',
'T2_ss_reset_in',
'T3_ss_reset_in',
'T0_cs_clk_in',
'T1_cs_clk_in',
'T2_cs_clk_in',
'T3_cs_clk_in',
'T0_cs_reset_in',
'T1_cs_reset_in',
'T2_cs_reset_in',
'T3_cs_reset_in'
],
'noc_param' => [
'TOPOLOGY',
'T1',
'T2',
'T3',
'V',
'B',
'Fpay',
'ROUTE_NAME',
'MIN_PCK_SIZE',
'BYTE_EN',
'SSA_EN',
'CONGESTION_INDEX',
'ESCAP_VC_MASK',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'SWA_ARBITER_TYPE',
'WEIGHTw',
'AVC_ATOMIC_EN',
'LB',
'PCK_TYPE',
'CAST_TYPE',
'SMART_MAX',
'SELF_LOOP_EN',
'MCAST_ENDP_LIST'
],
'SOURCE_SET' => [
'clk_number',
'clk_0_name',
'reset_number',
'reset_0_name'
],
'noc_type' => [
'ROUTER_TYPE'
]
},
'liststore' => {
'ha' => '0',
'va' => '0'
},
'fpga_param' => {},
'RAM0' => {
'end' => 32768,
'start' => 22937
}
'va' => '0',
'ha' => '0'
}
}, 'mpsoc' );
/perl/Consts.pm
1,4 → 1,4
#This file is created by /home/alireza/work/git/hca_git/ProNoC/mpsoc/intsall.sh
#This file is created by /home/alireza/work/git/pronoc/mpsoc/intsall.sh
package Consts;
 
use constant VERSION => '2.1.0';
/perl/compile.pl
358,7 → 358,7
}
 
 
my $cpu_num;
sub select_parallel_process_num {
my ($self,$name,$top,$target_dir)=@_;
my $table = def_table(2, 2, FALSE);
367,20 → 367,22
#get total number of processor in the system
my $cmd = "nproc\n";
my $cpu_num=4;
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
#nproc command has failed. set default 4 paralel processor
}else {
my ($number ) = $stdout =~ /(\d+)/;
if (defined $number ){
$cpu_num =$number if ($number > 0 );
}
if(!defined $cpu_num){
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
#nproc command has failed. set default 4 paralel processor
}else {
my ($number ) = $stdout =~ /(\d+)/;
if (defined $number ){
$cpu_num =$number if ($number > 0 );
}
}
}
($row,$col)= add_param_widget ($self,"Paralle run:" , "cpu_num", 1, 'Spin-button', "1,$cpu_num,1","specify the number of processors the Verilator can use at once to run parallel compilations/simulations", $table,$row,$col,1, 'compile', undef,undef,'vertical');
return $table;
}
 
sub select_parallel_thread_num {
my ($self,$name,$top,$target_dir)=@_;
my $table = def_table(2, 2, FALSE);
389,16 → 391,17
#get total number of processor in the system
my $cmd = "nproc\n";
my $cpu_num=4;
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
#nproc command has failed. set default 4 paralel processor
}else {
my ($number ) = $stdout =~ /(\d+)/;
if (defined $number ){
$cpu_num =$number if ($number > 0 );
}
if(!defined $cpu_num){
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
#nproc command has failed. set default 4 paralel processor
}else {
my ($number ) = $stdout =~ /(\d+)/;
if (defined $number ){
$cpu_num =$number if ($number > 0 );
}
}
}
($row,$col)= add_param_widget ($self,"Thread run:" , "thread_num", 1, 'Spin-button', "1,$cpu_num,1","specify the number of threads the Verilator can use at once in one simulation", $table,$row,$col,1, 'compile', undef,undef,'vertical');
return $table;
/perl/emulator.pl
976,7 → 976,8
noc_emulator #(
.STATISTIC_VJTAG_INDEX(STATISTIC_VJTAG_INDEX),
.PATTERN_VJTAG_INDEX(PATTERN_VJTAG_INDEX)
.PATTERN_VJTAG_INDEX(PATTERN_VJTAG_INDEX),
.NOC_ID(0)
)
noc_emulate_top
(
/perl/mpsoc_verilog_gen.pl
46,12 → 46,11
#functions
my $functions=get_functions();
$param_as_in_v = (defined $param_as_in_v)? "$param_as_in_v,\nparameter NOC_ID=0\n" : "parameter NOC_ID=0\n";
my $global_localparam=get_golal_param_v();
my $mpsoc_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule $mpsoc_name\n\t import pronoc_pkg::*;\n\t #(\n $param_as_in_v\n)(\n$io_short\n);\n": "`timescale 1ns/1ps\nmodule $mpsoc_name\n \t import pronoc_pkg::*;\n\t(\n$io_short\n);\n";
my $pdef = "`include \"pronoc_def.v\"";
my $mpsoc_v = (defined $param_as_in_v )? " $pdef\nmodule $mpsoc_name\n\t #(\n $param_as_in_v)(\n$io_short\n);\n\t`NOC_CONF": "$pdef\nmodule $mpsoc_name\n \t (\n$io_short\n);\n\t`NOC_CONF";
$mpsoc_v=$mpsoc_v. "
$functions
$global_localparam
$socs_param
$io_full
61,7 → 60,7
";
my $top_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$top_io_short\n);\n": "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top (\n $top_io_short\n);\n";
my $top_v = (defined $param_as_in_v )? "$pdef\nmodule ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$top_io_short\n);\n": "$pdef\nmodule ${mpsoc_name}_top (\n $top_io_short\n);\n";
 
$top_v=$top_v."
$global_localparam
461,18 → 460,16
wire noc_clk_in,noc_reset_in;
//NoC
noc_top the_noc
(
noc_top # (
.NOC_ID(NOC_ID)
) the_noc (
.reset(noc_reset_in),
.clk(noc_clk_in),
.chan_in_all(ni_chan_out),
.chan_out_all(ni_chan_in),
.router_event( )
);
);
clk_source src (
.clk_in($noc_clk),
.clk_out(noc_clk_in),
/perl/network_maker.pl
1573,7 → 1573,7
my %L_num;
my @all_endpoints=get_list_of_all_endpoints($self);
foreach my $r (@all_endpoints ){
$R_num{$r} =0;
#$R_num{$r} =0;
}
my @nodes=get_list_of_all_routers($self);
foreach my $p (@nodes){
1582,9 → 1582,11
foreach my $src (@all_endpoints ){
foreach my $dst (@all_endpoints ){
my $path = $self->object_get_attribute('Route',"${src}::$dst");
if (defined $path){
if (defined $path){
#router counting
my @p=@{$path};
shift @p; #remove source node from the path
pop @p; #remove the destination node from the path
foreach my $r (@p){
$R_num{$r} ++;
}
2578,9 → 2580,9
}
my @acyclic_turns = @{$pp};
my %rusage = get_router_usage ($self,\@acyclic_turns);
#step 1: calculate all minimal paths between all source and destination pairs
add_info($info,"Calculate all paths between all source and destination pairs\n");
my @all_endpoints=get_list_of_all_endpoints($self);
2613,7 → 2615,12
my ($paths_to_dst,$ports_to_dst) = get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,\@acyclic_turns);
#my @cyle_free_paths=remove_cycle_paths($self,$info,$paths_to_dst, \@forbiden_turn);
my @cyle_free_paths= @{$paths_to_dst} if (defined $paths_to_dst);
my @sort_paths=sort_paths_based_on_link_usage($self,\@cyle_free_paths);
my @sort_paths=sort_paths_based_on_router_usage($self,\@cyle_free_paths,\%rusage);
# my @sort_paths=sort_paths_based_on_link_usage($self,\@cyle_free_paths);
 
my $path;
my $n=0;
foreach my $p (@sort_paths ){
2701,6 → 2708,51
return %copy;
}
 
 
sub sort_paths_based_on_router_usage{
my ($self,$paths_to_dst,$usage)=@_;
my %scored;
my %usage_r= %{$usage};
#get list of 30% high congested ruters
my @A = sort { $usage_r{$b} <=> $usage_r{$a} } keys %usage_r;
#my $t = (scalar @A)*.3; # %30
my %congested;
foreach my $a ( @A){
$congested{$a}=$usage_r{$a};# if(scalar(keys %congested)<$t);
}
my $i=0;
foreach my $path (@{$paths_to_dst}) {
my $val = 0;
my $num=0;
for my $r (@{$path}){
if(defined $congested{$r}){
$val+=$congested{$r}**1.5;# pow of 3/2 to give higher weight to more congested routers
$num++;
}
}
$scored{$i}=($num==0)? 0 : $val/$num; #average weight of congested routers
$i++;
}
my @order = sort { $scored{$a} <=> $scored{$b} } keys %scored;
my @sorted;
$i=0;
foreach my $a ( @order){
$sorted[$i]=${$paths_to_dst}[$a];
$i++;
#print "\$max{$a}=$max{$a},"
}
#print "\n";
return @sorted;
}
 
 
sub sort_paths_based_on_link_usage{
my ($self,$paths_to_dst)=@_;
2714,6 → 2766,7
if (defined $path){
#path counting
my @p= get_adjacent_router_in_a_path($path);
foreach my $r (@p){
$L_num{$r} ++;
}
2754,6 → 2807,34
}
 
 
sub get_router_usage{
my ($self,$acycle_turn_ref)=@_;
my @all_endpoints=get_list_of_all_endpoints($self);
my %router_cnt;
#get router counts
foreach my $src (@all_endpoints ){
foreach my $dst (@all_endpoints ){
#get list of all path between a source and destination nodes
my ($paths_to_dst,$ports_to_dst)= get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,$acycle_turn_ref);
my @paths = @{$paths_to_dst};
foreach my $path (@paths){
shift @{$path}; #remove source node from the path
pop @{$path}; #remove the destination node from the path
foreach my $q ( @{$path}){
$router_cnt{"$q"} = ( defined $router_cnt{"$q"})? $router_cnt{"$q"}+1 : 1;
}
}
}
}
return %router_cnt;
}
 
 
sub check_cyclick_loop{
my ($self,$paths_to_dst)=@_;
/perl/simulator.pl
1893,7 → 1893,7
$chart = gen_multiple_charts ($simulate,\@pages,\@charts,0.4);
$ctrl = noc_sim_ctrl ($simulate,$info);
$main_table->attach ($ctrl,0, 12, 24,25,'fill','fill',2,2);
$v1 -> pack1($conf_box, TRUE, TRUE);
$v1 -> pack1($conf_box, TRUE, TRUE);
$v1 -> pack2($image, TRUE, TRUE);
$v2 -> pack2($chart, TRUE, TRUE);
/perl/soc_gen.pl
756,7 → 756,7
close(FILE) || die "Error closing file: $!";
# Write verilog file
my $h=autogen_warning().get_license_header("${name}.sv")."\n`timescale 1ns / 1ps\n";
my $h=autogen_warning().get_license_header("${name}.sv")."\n";
open(FILE, ">lib/verilog/$name.sv") || die "Can not open: $!";
print FILE $h.$file_v;
close(FILE) || die "Error closing file: $!";
/perl/topology.pl
130,7 → 130,7
for (my $i = 0; $i <$l; $i=$i+1 ) {
$tmp=int($pos/$pow);
$tmp=$tmp % $k;
$tmp=$tmp<<($i)*$kw;
$tmp=$tmp << ($i)*$kw;
$addrencode=$addrencode | $tmp;
$pow=$pow * $k;
}
143,7 → 143,7
my $mask=0;
my $pow; my $tmp;
my $pos=0;
while((0x1<<$kw) < $k){
while((0x1 << $kw) < $k){
$kw++;
$mask<<=1;
$mask|=0x1;
237,7 → 237,7
my $NXw=log2($T1);
my $NYw=log2($T2);
my $addrencode=0;
$addrencode = ($p<<($NXw+$NYw)| ($y << $NXw) | $x);
$addrencode = ($p << ($NXw+$NYw)| ($y << $NXw) | $x);
return $addrencode;
}
 
299,8 → 299,10
my $T3=$self->object_get_attribute('noc_param','T3');
if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
return fattree_addrencode($id, $T1, $T2);
}elsif ($topology eq '"RING"' || $topology eq '"LINE"' || $topology eq '"MESH"' || $topology eq '"TORUS"'){
}elsif ($topology eq '"MESH"' || $topology eq '"TORUS"'){
return mesh_tori_addrencode($id,$T1, $T2,$T3);
}elsif ($topology eq '"RING"' || $topology eq '"LINE"'){
return ring_line_addrencode($id,$T1, $T3);
}elsif ($topology eq '"FMESH"' ){
return fmesh_addrencode($id,$T1, $T2,$T3);
}else{#CUSTOM & STAR
332,7 → 334,7
my $k=shift;
my $kw=0;
my $mask=0;
while((0x1<<$kw) < $k){
while((0x1 << $kw) < $k){
$kw++;
$mask<<=1;
$mask|=0x1;
360,6 → 362,12
return mesh_tori_addr_join($x,$y,$l,$T1, $T2,$T3);
}
 
sub ring_line_addrencode {
my ($id,$T1, $T3)=@_;
my ($x,$y,$l)=mesh_tori_addrencod_sep($id,$T1,0,$T3);
return ring_line_addr_join($x,$y,$l,$T1, $T3);
}
 
sub mesh_tori_addrencod_sep{
my ($id,$T1,$T2,$T3)=@_;
my ($x,$y,$l);
375,11 → 383,20
my $NXw=log2($T1);
my $NYw=log2($T2);
my $addrencode=0;
$addrencode =($T3==1)? ($y << $NXw | $x) : ($l<<($NXw+$NYw)| ($y << $NXw) | $x);
$addrencode =($T3==1)? ($y << $NXw | $x) : ($l << ($NXw+$NYw)| ($y << $NXw) | $x);
return $addrencode;
}
 
sub ring_line_addr_join {
my ($x, $y, $l,$T1, $T3)=@_;
my $NXw=log2($T1);
my $addrencode=0;
$addrencode =($T3==1)? $x : ($l << $NXw) | $x;
return $addrencode;
}
 
 
 
sub mcast_partial_width {
my ($p,$NE)=@_;
my $m=0;
424,8 → 441,6
my $DAw = ($CAST_TYPE eq '"UNICAST"') ? $EAw: $MCASTw + $DAw_OFFSETw;
print "$DAw=$DAw\n";
 
my $custom_include="";
if($topology eq '"FATTREE"') {
my $K = $T1;
623,7 → 638,8
update_router_st(
NR${i}_PNUM,
router${i}[i]->current_r_id,
router${i}[i]->router_event
router${i}[i]->router_event,
sizeof(router${i}[i]->router_event[0])
);
return;
}
679,16 → 695,13
}
 
#define SMART_NUM ((SMART_MAX==0)? 1 : SMART_MAX)
#if SMART_NUM > 8
typedef unsigned int EVENT;
#else
typedef unsigned char EVENT;
#endif
 
 
extern void update_router_st (
unsigned int,
unsigned int,
EVENT *
void * ,
size_t
);
void single_router_st_update(int i){
/perl/topology_verilog_gen.pl
134,28 → 134,15
print $fd "
module ${name}_noc
import pronoc_pkg::*;
(
$ports
#(
parameter NOC_ID=0
)
(
$ports
);
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
 
localparam
NE = $NE,
NR = $NR,
RAw=log2(NR);
 
`NOC_CONF
input reset,clk;
$wires
209,6 → 196,7
* $instance
*******************/
router_top #(
.NOC_ID(NOC_ID),
.P($Pnum)
)
$instance
467,6 → 455,7
assign current_r_addr [RID] = RID[RAw-1: 0];
 
router_top #(
.NOC_ID(NOC_ID),
.P($i)
)
router_${i}_port
511,9 → 500,10
print $fd "
module ${name}_noc_genvar
import pronoc_pkg::*;
(
module ${name}_noc_genvar
#(
parameter NOC_ID=0
)(
 
reset,
clk,
522,21 → 512,7
router_event
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
 
localparam
NE = $NE,
NR = $NR,
RAw=log2(NR),
MAX_P=$MAX_P;
`NOC_CONF
$ports_def
 
628,6 → 604,7
my $router_v="
router_top #(
.NOC_ID(NOC_ID),
.P($Pnum)
)
router_${Pnum}_port
1446,45 → 1423,21
print $fd "
module ${name}_connection
import pronoc_pkg::*;
(
#(
parameter NOC_ID=0
)(
$ports
);
 
function integer log2;
input integer number; begin
log2=(number <=1) ? 1: 0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
`NOC_CONF
 
localparam
NE = $NE,
NR = $NR,
RAw=log2(NR),
MAX_P=$MAX_P;
localparam
P= MAX_P,
PV = V * P,
PFw = P * Fw,
CONG_ALw = CONGw * P,
PRAw = P * RAw;
 
PRAw = P * RAw;
$ports_def
 
1564,7 → 1517,7
if(TOPOLOGY == \"$name\" && ROUTE_NAME== \"$rname\" ) begin : $Vname
${Vname}_conventional_routing #(
.RAw(RAw),
.RAw(RAw),
.EAw(EAw),
.DSTPw(DSTPw)
)
1679,8 → 1632,9
//do not modify this line ===${name}===
if(TOPOLOGY == \"$name\" ) begin : T$name
${name}_connection connection
(
${name}_connection #(
.NOC_ID(NOC_ID)
) connection (
$ports
);
1725,16 → 1679,15
$ports="\t\t.reset(reset),
\t\t.clk(clk)";
$str="
//do not modify this line ===${name}===
if(TOPOLOGY == \"$name\" ) begin : T$name
${name}_noc_genvar the_noc
(
${name}_noc_genvar #(
.NOC_ID(NOC_ID)
) the_noc (
.reset(reset),
.clk(clk),
.chan_in_all(chan_in_all),
/perl/verilog_gen.pl
89,10 → 89,11
$sockets_assign_v_all="" if(!defined $sockets_assign_v_all);
 
my $has_ni =check_for_ni($soc);
my $import = ($has_ni)? "\n\timport pronoc_pkg::*;\n" : "";
my $import = ($has_ni)? "\n\t`NOC_CONF\n" : "";
my $tscale = ($has_ni)? "`include \"pronoc_def.v\"\n" : "`timescale 1ns / 1ps\n";
 
my $global_localparam=get_golal_param_v();
my $soc_v = (defined $param_as_in_v_all )? "module $soc_name $import #(\n $param_as_in_v_all\n)(\n$io_sim_v_all\n);\n": "module $soc_name (\n$io_sim_v_all\n);\n";
my $soc_v = (defined $param_as_in_v_all )? "$tscale module $soc_name #(\n $param_as_in_v_all\n)(\n$io_sim_v_all\n);\n$import\n": "$tscale module $soc_name (\n$io_sim_v_all\n);\n $import\n";
$soc_v = $soc_v."
$functions_all
$system_v_all
125,7 → 126,7
my @chains = (sort { $b <=> $a } keys %jtag_info);
$soc->object_add_attribute('JTAG','M_CHAIN',$chains[0]);
my $top_v = (defined $param_as_in_v_all )? "module ${soc_name}_top $import #(\n $param_as_in_v_all\n)(\n$top_io_short_all\n);\n": "module ${soc_name}_top (\n $top_io_short_all\n);\n";
my $top_v = (defined $param_as_in_v_all )? "module ${soc_name}_top #(\n $param_as_in_v_all\n)(\n$top_io_short_all\n);\n": "module ${soc_name}_top (\n $top_io_short_all\n);\n $import ";
#my $ins= gen_soc_instance_v($soc,$soc_name,$param_pass_v,$txview);
1294,7 → 1295,7
# $top_io_pass_all=$top_io_pass_all.",\n$clk_assigned_port";
my $has_ni =check_for_ni($soc);
my $import = ($has_ni)? "\n\timport pronoc_pkg::*;\n" : "";
my $import = ($has_ni)? "\n\t`NOC_CONF\n" : "";
my $verilator_v = "
/*********************
1301,7 → 1302,7
${name}
*********************/
module ${name} $import (\n $top_io_short_all\n);\n";
module ${name} (\n $top_io_short_all\n);\n $import \n";
my $ins= gen_soc_instance_v_no_modfy($soc,$soc_name,$param_pass_v_all);
$verilator_v.="
$functions_all
/perl/widget3.pl
2204,21 → 2204,11
my $cmd=shift;
my $exit;
my ($stdout, $stderr);
#open(OLDERR, ">&STDERR");
#open(STDERR, ">>/tmp/tmp.spderr") or die "Can't dup stdout";
#select(STDOUT); $| = 1; # make unbuffered
#print OLDERR ""; #this fixed an error about OLDERR not being used
 
## do my stuff here.
STDOUT->flush();
STDERR->flush();
capture { $exit=run_cmd_in_back_ground($cmd) } \$stdout, \$stderr;
#close(STDERR);
#open(STDERR, ">&OLDERR");
return ($stdout,$exit,$stderr);
}
/soc/mor1k_tile.SOC
1,9 → 1,9
#######################################################################
## File: mor1k_tile.SOC
##
## Copyright (C) 2014-2019 Alireza Monemi
## Copyright (C) 2014-2021 Alireza Monemi
##
## This file is part of ProNoC 1.9.1
## This file is part of ProNoC 2.1.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAVIOR.
10,118 → 10,45
################################################################################
 
$soc = bless( {
'timer0' => {
'version' => 12
},
'current_module_param_type' => undef,
'SOURCE_SET' => {
'SOC' => bless( {
'modules' => {},
'hdl_files_ticked' => undef,
'SOURCE_SET' => {
'IP' => bless( {
'parameters_order' => [],
'hdl_files' => [],
'GUI_REMOVE_SET' => 'DISABLE',
'file_name' => undef,
'hdl_files_ticked' => [],
'category' => 'TOP',
'ports' => {
'source_clk_in' => {
'range' => undef,
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'source_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => undef
}
},
'plugs' => {
'reset' => {
'1' => {},
'0' => {
'name' => 'source_reset_in'
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'value' => 1,
'0' => {
'name' => 'source_clk_in'
},
'1' => {},
'type' => 'num'
}
},
'module_name' => 'TOP',
'ip_name' => 'TOP',
'ports_order' => []
}, 'ip_gen' )
},
'soc_name' => {
'TOP' => undef
},
'TOP' => {
'version' => 0
},
'hdl_files' => undef,
'gui_status' => {
'status' => 'refresh_soc',
'timeout' => 0
},
'instances' => {
'TOP' => {
'instance_name' => 'TOP',
'plugs' => {
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_socket' => undef,
'name' => 'source_reset_in',
'connect_id' => 'IO'
}
},
'type' => 'num',
'value' => 1
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => undef,
'connect_socket_num' => undef,
'connect_id' => 'IO',
'name' => 'source_clk_in'
}
},
'type' => 'num'
}
},
'module_name' => 'TOP',
'parameters_order' => [],
'category' => 'TOP',
'description_pdf' => undef,
'module' => 'TOP'
}
},
'instance_order' => [
'TOP'
]
}, 'soc' ),
'REDEFINE_TOP' => 0
},
'device_win_adj' => {
'va' => '0',
'ha' => '0'
},
'global_param' => {
'CORE_ID' => 3,
'SW_LOC' => '/home/alireza/work/git/hca_git/mpsoc_work/SOC/mor1k_tile/sw'
},
'graph_save' => {},
'current_module_param' => undef,
'wishbone_bus0' => {
'version' => 1
},
'compile_pin_pos' => {},
'modules' => {},
'soc_name' => 'mor1k_tile',
'Unset-intfc' => {},
'tile_diagram' => {
'show_unused' => 1,
'show_clk' => 0,
'show_reset' => 0
},
'mor1kx0' => {
'version' => 26
},
'noc_param' => {},
'compile_assign_type' => {
'TOP_source_reset_in' => 'Direct',
'cpu_cpu_en' => 'Direct',
'jtag_debug_reset_in' => 'Direct',
'TOP_source_clk_in' => 'Direct',
'smartflit_chanel_t' => 'Direct',
'ni_current_e_addr' => 'Direct',
'ni_current_r_addr' => 'Direct'
},
'clk_source0' => {
'version' => 1
},
'ROM0' => {
'end' => 49152,
'start' => 0
},
'instance_order' => [
'clk_source0',
'wishbone_bus0',
131,609 → 58,249
'timer0',
'ProNoC_jtag_uart0'
],
'hdl_files_ticked' => undef,
'wishbone_bus0' => {
'version' => 1
},
'instances' => {
'timer0' => {
'sockets' => {},
'parameters' => {
'Aw' => {
'value' => '3'
},
'CNTw' => {
'value' => '32 '
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'SELw' => {
'value' => '4'
},
'PRESCALER_WIDTH' => {
'value' => '8'
}
},
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw',
'PRESCALER_WIDTH'
],
'module' => 'timer',
'category' => 'Timer',
'parameters_type' => {
'Dw' => {},
'TAGw' => {},
'CNTw' => {},
'Aw' => {},
'PRESCALER_WIDTH' => {
'value' => 'Localparam'
},
'SELw' => {}
},
'description_pdf' => '/mpsoc/rtl/src_peripheral/timer/timer.pdf',
'module_name' => 'timer',
'plugs' => {
'clk' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk',
'connect_socket_num' => '0'
}
},
'value' => 1,
'connection_num' => undef
},
'interrupt_peripheral' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'mor1kx0',
'name' => 'intrp',
'connect_socket_num' => '1',
'connect_socket' => 'interrupt_peripheral'
}
},
'connection_num' => undef
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'end' => 2516582431,
'connect_socket' => 'wb_slave',
'base' => 2516582400,
'connect_socket_num' => '2',
'connect_id' => 'wishbone_bus0',
'width' => 5,
'name' => 'wb',
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl'
}
},
'type' => 'num'
},
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'name' => 'reset'
}
},
'type' => 'num',
'value' => 1
}
},
'instance_name' => 'timer'
},
'ProNoC_jtag_uart0' => {
'sockets' => {
'jtag_to_wb' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'jtag_to_wb'
}
},
'type' => 'num'
},
'RxD_sim' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'RxD_sim'
}
},
'type' => 'num'
}
},
'parameters' => {
'SELw' => {
'value' => '4'
},
'JTAG_CONNECT' => {
'value' => '"ALTERA_JTAG_WB"'
},
'JSTATUSw' => {
'value' => '8'
},
'BUFF_Aw' => {
'value' => '4'
},
'J2WBw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'
},
'JDw' => {
'value' => '32'
},
'Dw' => {
'value' => '32'
},
'TAGw' => {
'value' => '3'
},
'INCLUDE_SIM_PRINTF' => {
'value' => 'SIMPLE_PRINTF'
},
'JAw' => {
'value' => '32'
},
'WB2Jw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'
},
'JTAG_CHAIN' => {
'value' => '3'
},
'Aw' => {
'value' => '1'
},
'JINDEXw' => {
'value' => '8'
},
'JTAG_INDEX' => {
'value' => '126-CORE_ID'
}
},
'parameters_order' => [
'Aw',
'SELw',
'TAGw',
'Dw',
'BUFF_Aw',
'JTAG_INDEX',
'JDw',
'JAw',
'JINDEXw',
'JSTATUSw',
'JTAG_CHAIN',
'JTAG_CONNECT',
'J2WBw',
'WB2Jw',
'INCLUDE_SIM_PRINTF'
],
'module_name' => 'pronoc_jtag_uart',
'plugs' => {
'clk' => {
'connection_num' => undef,
'value' => 1,
'wishbone_bus0' => {
'parameters' => {
'BTEw' => {
'value' => '2 '
},
'S' => {
'value' => '4'
},
'SELw' => {
'value' => 'Dw/8'
},
'TAGw' => {
'value' => '3'
},
'M' => {
'value' => ' 4'
},
'CTIw' => {
'value' => '3'
},
'Aw' => {
'value' => '32'
},
'Dw' => {
'value' => '32'
}
},
'sockets' => {
'snoop' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
'name' => 'snoop'
}
},
'type' => 'num'
'type' => 'num',
'value' => 1
},
'wb_slave' => {
'nums' => {
'0' => {
'width' => 4,
'name' => 'wb_slave',
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
'connect_socket' => 'wb_slave',
'end' => 2415919119,
'base' => 2415919104,
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_id' => 'clk_source0'
}
}
}
},
'instance_name' => 'uart',
'module' => 'ProNoC_jtag_uart',
'parameters_type' => {
'SELw' => {},
'BUFF_Aw' => {
'value' => 'Localparam'
},
'JSTATUSw' => {},
'J2WBw' => {},
'JTAG_CONNECT' => {
'value' => 'Localparam'
},
'Dw' => {},
'JDw' => {},
'TAGw' => {},
'WB2Jw' => {},
'JAw' => {},
'JTAG_CHAIN' => {
'value' => 'Localparam'
},
'INCLUDE_SIM_PRINTF' => {
'value' => 'Localparam'
},
'Aw' => {},
'JTAG_INDEX' => {
'value' => 'Localparam'
},
'JINDEXw' => {}
},
'description_pdf' => undef,
'category' => 'Communication'
},
'wishbone_bus0' => {
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'sockets' => {
'wb_addr_map' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
}
},
'wb_master' => {
'connection_num' => 'single connection',
'type' => 'param',
'value' => 'M',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_master'
}
}
},
'connection_num' => 'single connection'
},
'wb_addr_map' => {
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'connection_num' => 'single connection',
'type' => 'num',
'value' => 1
},
'wb_slave' => {
'value' => 'S',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
},
'connection_num' => 'single connection'
},
'snoop' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'snoop'
}
}
}
'connection_num' => 'single connection',
'value' => 'S',
'type' => 'param'
}
},
'parameters' => {
'CTIw' => {
'value' => '3'
},
'Aw' => {
'value' => '32'
},
'M' => {
'value' => ' 4'
},
'SELw' => {
'value' => 'Dw/8'
},
'BTEw' => {
'value' => '2 '
},
'S' => {
'value' => '4'
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
}
},
'category' => 'Bus',
'parameters_type' => {
'Aw' => {
'value' => 'Localparam'
},
'BTEw' => {},
'S' => {
'value' => 'Localparam'
},
'SELw' => {},
'TAGw' => {},
'M' => {
'value' => 'Localparam'
},
'CTIw' => {},
'S' => {
'value' => 'Localparam'
},
'Aw' => {
'value' => 'Localparam'
},
'Dw' => {
'value' => 'Localparam'
},
'TAGw' => {},
'SELw' => {},
'BTEw' => {}
}
},
'description_pdf' => undef,
'module' => 'wishbone_bus',
'category' => 'Bus',
'module_name' => 'wishbone_bus',
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_socket_num' => '0'
'name' => 'reset'
}
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_socket' => 'clk',
'connect_socket_num' => '0'
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef
}
}
},
'module_name' => 'wishbone_bus',
'instance_name' => 'bus'
'description_pdf' => undef,
'instance_name' => 'bus',
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'module' => 'wishbone_bus'
},
'clk_source0' => {
'parameters_order' => [
'FPGA_VENDOR'
],
'sockets' => {
'reset' => {
'connection_num' => 'multi connection',
'nums' => {
'0' => {
'name' => 'reset'
}
},
'type' => 'num',
'value' => 1
},
'clk' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk'
}
},
'connection_num' => 'multi connection'
}
},
'parameters' => {
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
}
},
'description_pdf' => undef,
'category' => 'Source',
'parameters_type' => {
'FPGA_VENDOR' => {
'value' => 'Localparam'
}
},
'module' => 'clk_source',
'module_name' => 'clk_source',
'plugs' => {
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'reset',
'connect_socket_num' => undef,
'connect_socket' => undef
}
},
'type' => 'num',
'value' => 1
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'timer0' => {
'category' => 'Timer',
'module_name' => 'timer',
'description_pdf' => '/mpsoc/rtl/src_peripheral/timer/timer.pdf',
'plugs' => {
'wb_slave' => {
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_socket' => undef,
'name' => 'clk',
'connect_id' => 'IO'
'width' => 5,
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl',
'base' => 2516582400,
'end' => 2516582431,
'connect_socket' => 'wb_slave',
'name' => 'wb',
'connect_socket_num' => '2',
'connect_id' => 'wishbone_bus0'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
}
},
'instance_name' => 'source'
},
'ni_master0' => {
'parameters' => {
'Dw' => {
'value' => '32'
},
'COMBINATION_TYPE' => {
'value' => '"COMB_NONSPEC"'
},
'SWA_ARBITER_TYPE' => {
'value' => '"RRA"'
},
'WEIGHTw' => {
'value' => '4'
},
'CONGESTION_INDEX' => {
'value' => 3
},
'MAX_TRANSACTION_WIDTH' => {
'value' => '13'
},
'PCK_TYPE' => {
'value' => '"MULTI_FLIT"'
},
'reset' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'name' => 'reset'
}
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 1
},
'SELF_LOOP_EN' => {
'value' => '"NO"'
},
'CRC_EN' => {
'value' => '"NO"'
'connection_num' => undef
},
'interrupt_peripheral' => {
'nums' => {
'0' => {
'name' => 'intrp',
'connect_socket' => 'interrupt_peripheral',
'connect_id' => 'mor1kx0',
'connect_socket_num' => '1'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
},
'clk' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'EAw' => {
'value' => '16'
},
'B' => {
'value' => '4'
},
'TOPOLOGY' => {
'value' => '"MESH"'
},
'V' => {
'value' => '2'
},
'C' => {
'value' => 0
},
'T3' => {
'value' => '1'
},
'VC_REALLOCATION_TYPE' => {
'value' => '"NONATOMIC"'
},
'ROUTE_NAME' => {
'value' => '"XY"'
},
'SMART_MAX' => {
'value' => '0'
},
'DEBUG_EN' => {
'value' => '0'
},
'SSA_EN' => {
'value' => '"NO"'
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => '1\'b0'
},
'MAX_BURST_SIZE' => {
'value' => '16'
},
'TAGw' => {
'value' => '3'
},
'AVC_ATOMIC_EN' => {
'value' => 0
},
'MIN_PCK_SIZE' => {
'value' => '2'
},
'S_Aw' => {
'value' => '8'
},
'Fpay' => {
'value' => '32'
},
'T1' => {
'value' => '2'
},
'MUX_TYPE' => {
'value' => '"BINARY"'
},
'SELw' => {
'value' => '4'
},
'BYTE_EN' => {
'value' => '1'
},
'M_Aw' => {
'value' => '32'
},
'LB' => {
'value' => '4'
},
'HDATA_PRECAPw' => {
'value' => '0'
},
'ESCAP_VC_MASK' => {
'value' => '2\'b01'
},
'T2' => {
'value' => '2'
},
'RAw' => {
'value' => '16'
},
'CAST_TYPE' => {
'value' => '"UNICAST"'
}
},
'sockets' => {
'ni' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'ni'
}
'connection_num' => undef
}
},
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw',
'PRESCALER_WIDTH'
],
'instance_name' => 'timer',
'module' => 'timer',
'parameters' => {
'PRESCALER_WIDTH' => {
'value' => '8'
},
'type' => 'num',
'value' => 1
}
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'CNTw' => {
'value' => '32 '
},
'SELw' => {
'value' => '4'
},
'Aw' => {
'value' => '3'
}
},
'parameters_type' => {
'SELw' => {},
'PRESCALER_WIDTH' => {
'value' => 'Localparam'
},
'TAGw' => {},
'Aw' => {},
'CNTw' => {},
'Dw' => {}
},
'sockets' => {}
},
'ni_master0' => {
'module' => 'ni_master',
'instance_name' => 'ni',
'parameters_order' => [
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
747,410 → 314,463
'EAw',
'HDATA_PRECAPw'
],
'instance_name' => 'ni',
'plugs' => {
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_socket_num' => '0'
}
},
'type' => 'num',
'value' => 1
},
'wb_master' => {
'type' => 'num',
'value' => 2,
'connection_num' => undef,
'value' => 2,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'wb_send',
'connect_socket_num' => '2',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '2',
'connect_socket' => 'wb_master'
'connect_socket' => 'wb_master',
'name' => 'wb_send'
},
'1' => {
'connect_socket' => 'wb_master',
'name' => 'wb_receive',
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master',
'connect_socket_num' => '3'
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0'
}
}
},
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'value' => 1,
'type' => 'num'
},
'interrupt_peripheral' => {
'type' => 'num',
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => 'interrupt_peripheral',
'name' => 'interrupt',
'connect_socket_num' => '0',
'connect_id' => 'mor1kx0'
}
}
},
'wb_slave' => {
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'width' => 10,
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1',
'name' => 'wb_slave',
'connect_socket' => 'wb_slave',
'end' => 3087008767,
'connect_socket' => 'wb_slave',
'base' => 3087007744,
'connect_id' => 'wishbone_bus0',
'width' => 10,
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'name' => 'wb_slave'
'base' => 3087007744
}
},
'value' => 1,
'connection_num' => undef
'type' => 'num'
},
'interrupt_peripheral' => {
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'interrupt',
'connect_id' => 'mor1kx0',
'connect_socket_num' => '0',
'connect_socket' => 'interrupt_peripheral'
}
},
'value' => 1
},
'clk' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0'
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'type' => 'num',
'connection_num' => undef
}
},
'description_pdf' => '/mpsoc/rtl/src_peripheral/ni/NI.pdf',
'module_name' => 'ni_master',
'module' => 'ni_master',
'description_pdf' => '/mpsoc/rtl/src_peripheral/ni/NI.pdf',
'category' => 'NoC',
'sockets' => {
'ni' => {
'type' => 'num',
'value' => 1,
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'ni'
}
}
}
},
'parameters_type' => {
'EAw' => {},
'B' => {
'value' => 'Parameter'
},
'TOPOLOGY' => {
'RAw' => {},
'DEBUG_EN' => {
'value' => 'Parameter'
},
'MAX_TRANSACTION_WIDTH' => {
'value' => 'Localparam'
},
'HDATA_PRECAPw' => {
'value' => 'Localparam'
},
'PCK_TYPE' => {
'value' => 'Parameter'
},
'CONGESTION_INDEX' => {
'value' => 'Parameter'
},
'T3' => {
'value' => 'Parameter'
},
'CRC_EN' => {
'value' => 'Localparam'
},
'MCAST_ENDP_LIST' => {
'value' => 'Parameter'
},
'Dw' => {
'value' => 'Localparam'
},
'SELF_LOOP_EN' => {
'value' => 'Parameter'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 'Parameter'
},
'CRC_EN' => {
'value' => 'Localparam'
},
'SWA_ARBITER_TYPE' => {
'value' => 'Parameter'
},
'TOPOLOGY' => {
'value' => 'Parameter'
},
'T2' => {
'value' => 'Parameter'
},
'EAw' => {},
'BYTE_EN' => {
'value' => 'Parameter'
},
'WEIGHTw' => {
'value' => 'Parameter'
},
'CONGESTION_INDEX' => {
'value' => 'Parameter'
},
'Dw' => {
'value' => 'Localparam'
},
'COMBINATION_TYPE' => {
'value' => 'Parameter'
},
'LB' => {
'value' => 'Parameter'
},
'M_Aw' => {},
'HDATA_PRECAPw' => {
'value' => 'Localparam'
},
'T2' => {
'value' => 'Parameter'
},
'ESCAP_VC_MASK' => {
'value' => 'Parameter'
},
'RAw' => {},
'CAST_TYPE' => {
'MAX_BURST_SIZE' => {
'value' => 'Localparam'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 'Parameter'
},
'SMART_MAX' => {
'value' => 'Parameter'
},
'AVC_ATOMIC_EN' => {
'value' => 'Parameter'
},
'TAGw' => {},
'LB' => {
'value' => 'Parameter'
},
'VC_REALLOCATION_TYPE' => {
'value' => 'Parameter'
},
'SSA_EN' => {
'value' => 'Parameter'
},
'ROUTE_NAME' => {
'value' => 'Parameter'
},
'MUX_TYPE' => {
'value' => 'Parameter'
},
'B' => {
'value' => 'Parameter'
},
'MIN_PCK_SIZE' => {
'value' => 'Parameter'
},
'S_Aw' => {},
'MUX_TYPE' => {
'value' => 'Parameter'
},
'Fpay' => {
'value' => 'Parameter'
},
'T1' => {
'value' => 'Parameter'
},
'SELw' => {},
'BYTE_EN' => {
'value' => 'Parameter'
},
'SMART_MAX' => {
'value' => 'Parameter'
},
'DEBUG_EN' => {
'value' => 'Parameter'
},
'SSA_EN' => {
'value' => 'Parameter'
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => 'Parameter'
},
'MAX_BURST_SIZE' => {
'value' => 'Localparam'
},
'CAST_TYPE' => {
'value' => 'Parameter'
},
'SWA_ARBITER_TYPE' => {
'value' => 'Parameter'
},
'TAGw' => {},
'MAX_TRANSACTION_WIDTH' => {
'value' => 'Localparam'
},
'M_Aw' => {},
'V' => {
'value' => 'Parameter'
},
'Fpay' => {
'value' => 'Parameter'
},
'C' => {
'value' => 'Parameter'
},
'T3' => {
'value' => 'Parameter'
'S_Aw' => {},
'AVC_ATOMIC_EN' => {
'value' => 'Parameter'
}
},
'parameters' => {
'EAw' => {
'value' => '16'
},
'T2' => {
'value' => '2'
},
'TOPOLOGY' => {
'value' => '"MESH"'
},
'SELF_LOOP_EN' => {
'value' => '"NO"'
},
'COMBINATION_TYPE' => {
'value' => '"COMB_NONSPEC"'
},
'WEIGHTw' => {
'value' => '4'
},
'VC_REALLOCATION_TYPE' => {
'value' => 'Parameter'
'BYTE_EN' => {
'value' => '1'
},
'SMART_MAX' => {
'value' => '0'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 1
},
'MAX_BURST_SIZE' => {
'value' => '16'
},
'ESCAP_VC_MASK' => {
'value' => '2\'b01'
},
'PCK_TYPE' => {
'value' => '"MULTI_FLIT"'
},
'HDATA_PRECAPw' => {
'value' => '0'
},
'DEBUG_EN' => {
'value' => '0'
},
'RAw' => {
'value' => '16'
},
'CONGESTION_INDEX' => {
'value' => 3
},
'T3' => {
'value' => '1'
},
'Dw' => {
'value' => '32'
},
'MCAST_ENDP_LIST' => {
'value' => '\'hf'
},
'CRC_EN' => {
'value' => '"NO"'
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => '1\'b0'
},
'ROUTE_NAME' => {
'value' => 'Parameter'
}
},
'category' => 'NoC'
},
'mor1kx0' => {
'description_pdf' => undef,
'parameters_type' => {
'FEATURE_MULTIPLIER' => {
'value' => 'Localparam'
},
'OPTION_DCACHE_SNOOP' => {
'value' => 'Localparam'
'MIN_PCK_SIZE' => {
'value' => '2'
},
'T1' => {
'value' => '2'
},
'SELw' => {
'value' => '4'
},
'ROUTE_NAME' => {
'value' => '"XY"'
},
'MUX_TYPE' => {
'value' => '"BINARY"'
},
'B' => {
'value' => '4'
},
'MAX_TRANSACTION_WIDTH' => {
'value' => '13'
},
'FEATURE_DMMU' => {
'value' => 'Localparam'
},
'FEATURE_IMMU' => {
'value' => 'Localparam'
},
'IRQ_NUM' => {},
'FEATURE_DIVIDER' => {
'value' => 'Localparam'
},
'OPTION_SHIFTER' => {
'value' => 'Localparam'
'TAGw' => {
'value' => '3'
},
'CAST_TYPE' => {
'value' => '"UNICAST"'
},
'SWA_ARBITER_TYPE' => {
'value' => '"RRA"'
},
'OPTION_OPERAND_WIDTH' => {},
'FEATURE_DATACACHE' => {
'value' => 'Localparam'
},
'FEATURE_INSTRUCTIONCACHE' => {
'value' => 'Localparam'
}
},
'category' => 'Processor',
'module' => 'mor1kx',
'instance_name' => 'cpu',
'plugs' => {
'wb_master' => {
'value' => 2,
'C' => {
'value' => 0
},
'Fpay' => {
'value' => '32'
},
'M_Aw' => {
'value' => '32'
},
'V' => {
'value' => '2'
},
'AVC_ATOMIC_EN' => {
'value' => 0
},
'S_Aw' => {
'value' => '8'
},
'LB' => {
'value' => '4'
},
'VC_REALLOCATION_TYPE' => {
'value' => '"NONATOMIC"'
},
'SSA_EN' => {
'value' => '"NO"'
}
}
},
'clk_source0' => {
'parameters' => {
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
}
},
'sockets' => {
'clk' => {
'value' => 1,
'type' => 'num',
'nums' => {
'1' => {
'connect_socket_num' => '1',
'connect_socket' => 'wb_master',
'name' => 'dwb',
'connect_id' => 'wishbone_bus0'
},
'0' => {
'connect_socket' => 'wb_master',
'connect_socket_num' => '0',
'name' => 'iwb',
'connect_id' => 'wishbone_bus0'
'name' => 'clk'
}
},
'type' => 'num',
'connection_num' => undef
'connection_num' => 'multi connection'
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk'
}
},
'type' => 'num'
},
'snoop' => {
'nums' => {
'0' => {
'connect_socket' => 'snoop',
'connect_socket_num' => '0',
'connect_id' => 'wishbone_bus0',
'name' => 'snoop'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'reset'
}
}
},
'enable' => {
'nums' => {
'0' => {
'name' => 'enable',
'connect_id' => 'IO',
'connect_socket' => undef,
'connect_socket_num' => undef
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'module_name' => 'mor1k',
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM',
'OPTION_DCACHE_SNOOP',
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU',
'FEATURE_MULTIPLIER',
'FEATURE_DIVIDER',
'OPTION_SHIFTER'
],
'parameters' => {
'FEATURE_INSTRUCTIONCACHE' => {
'value' => '"ENABLED"'
},
'FEATURE_DATACACHE' => {
'value' => '"ENABLED"'
},
'OPTION_SHIFTER' => {
'value' => '"BARREL"'
},
'OPTION_OPERAND_WIDTH' => {
'value' => '32'
},
'FEATURE_DIVIDER' => {
'value' => '"SERIAL"'
},
'IRQ_NUM' => {
'value' => '32'
},
'FEATURE_IMMU' => {
'value' => '"ENABLED"'
},
'OPTION_DCACHE_SNOOP' => {
'value' => '"ENABLED"'
},
'FEATURE_DMMU' => {
'value' => '"ENABLED"'
},
'FEATURE_MULTIPLIER' => {
'value' => '"THREESTAGE"'
'reset' => {
'value' => 1,
'type' => 'num',
'connection_num' => 'multi connection',
'nums' => {
'0' => {
'name' => 'reset'
}
}
},
'sockets' => {
'interrupt_peripheral' => {
'connection_num' => 'single connection',
'value' => 'IRQ_NUM',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
},
'type' => 'param'
}
}
},
}
},
'parameters_type' => {
'FPGA_VENDOR' => {
'value' => 'Localparam'
}
},
'plugs' => {
'clk' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => undef,
'name' => 'clk',
'connect_socket_num' => undef,
'connect_id' => 'IO'
}
}
},
'reset' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => undef,
'name' => 'reset',
'connect_socket_num' => undef,
'connect_id' => 'IO'
}
}
}
},
'description_pdf' => undef,
'category' => 'Source',
'module_name' => 'clk_source',
'module' => 'clk_source',
'instance_name' => 'source',
'parameters_order' => [
'FPGA_VENDOR'
]
},
'single_port_ram0' => {
'sockets' => {
'jtag_to_wb' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'jtag_to_wb'
}
},
'type' => 'num'
}
},
'parameters' => {
'BURST_MODE' => {
'value' => '"ENABLED"'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'CTIw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'INITIAL_EN' => {
'value' => '"YES"'
'WB_Byte_Aw' => {
'value' => 'WB_Aw+2'
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
},
'JDw' => {
'value' => 'Dw'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
},
'WB_Aw' => {
'value' => '20'
},
'JINDEXw' => {
'value' => '8'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'JAw' => {
'value' => '32'
},
'JSTATUSw' => {
'value' => '8'
},
'JAw' => {
'value' => '32'
},
'CTIw' => {
'value' => '3'
},
'JTAG_CHAIN' => {
'value' => '4'
'J2WBw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
},
'CORE_NUM' => {
'value' => 'CORE_ID'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'WB_Byte_Aw' => {
'value' => 'WB_Aw+2'
'JTAG_CHAIN' => {
'value' => '4'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'Aw' => {
'value' => '14'
},
'TAGw' => {
'value' => '3'
},
'JTAG_CONNECT' => {
'value' => '"ALTERA_JTAG_WB"'
},
'BTEw' => {
'value' => '2'
},
1157,565 → 777,869
'SELw' => {
'value' => 'Dw/8'
},
'TAGw' => {
'value' => '3'
},
'JDw' => {
'value' => 'Dw'
},
'J2WBw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'
},
'JTAG_CONNECT' => {
'value' => '"ALTERA_JTAG_WB"'
},
'CORE_NUM' => {
'value' => 'CORE_ID'
},
'WB2Jw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'
},
'JINDEXw' => {
'value' => '8'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'WB_Aw' => {
'value' => '20'
},
'Aw' => {
'value' => '14'
}
'INITIAL_EN' => {
'value' => '"YES"'
}
},
'parameters_order' => [
'Dw',
'Aw',
'WB_Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'CORE_NUM',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Byte_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH',
'JDw',
'JAw',
'JSTATUSw',
'JINDEXw',
'J2WBw',
'WB2Jw',
'JTAG_CHAIN'
],
'module' => 'single_port_ram',
'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf',
'category' => 'RAM',
'parameters_type' => {
'JAw' => {},
'JTAG_CHAIN' => {
'value' => 'Localparam'
},
'CTIw' => {},
'INIT_FILE_PATH' => {},
'FPGA_VENDOR' => {
'value' => 'Localparam'
},
'JTAG_INDEX' => {
'value' => 'Localparam'
},
'WB_Aw' => {
'value' => 'Localparam'
},
'JDw' => {},
'BURST_MODE' => {
'value' => 'Localparam'
},
'JINDEXw' => {},
'JAw' => {},
'MEM_CONTENT_FILE_NAME' => {
'value' => 'Localparam'
},
'CTIw' => {},
'INIT_FILE_PATH' => {},
'WB_Byte_Aw' => {},
'Dw' => {
'value' => 'Localparam'
},
'TAGw' => {},
'SELw' => {},
'BTEw' => {},
'JTAG_CONNECT' => {
'value' => 'Localparam'
},
'INITIAL_EN' => {
'value' => 'Localparam'
},
'WB2Jw' => {},
'JSTATUSw' => {},
'JTAG_INDEX' => {
'value' => 'Localparam'
},
'CORE_NUM' => {},
'WB2Jw' => {},
'JINDEXw' => {},
'MEM_CONTENT_FILE_NAME' => {
'value' => 'Localparam'
},
'WB_Aw' => {
'value' => 'Localparam'
},
'BYTE_WR_EN' => {
'value' => 'Localparam'
},
'J2WBw' => {},
'Aw' => {
'value' => 'Localparam'
},
'WB_Byte_Aw' => {},
'BTEw' => {},
'BYTE_WR_EN' => {
'JTAG_CHAIN' => {
'value' => 'Localparam'
},
'SELw' => {},
'JDw' => {},
'TAGw' => {},
'JTAG_CONNECT' => {
'value' => 'Localparam'
},
'J2WBw' => {}
}
},
'sockets' => {
'jtag_to_wb' => {
'nums' => {
'0' => {
'name' => 'jtag_to_wb'
}
},
'connection_num' => 'single connection',
'type' => 'num',
'value' => 1
}
},
'category' => 'RAM',
'module_name' => 'wb_single_port_ram',
'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf',
'plugs' => {
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'width' => 'WB_Byte_Aw',
'name' => 'wb',
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'base' => 0,
'end' => 4194303,
'connect_socket' => 'wb_slave',
'connect_socket_num' => '0',
'connect_id' => 'wishbone_bus0'
}
}
},
'clk' => {
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk'
'connect_id' => 'clk_source0'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'connection_num' => undef
'type' => 'num'
},
'reset' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket_num' => '0',
'connect_socket' => 'reset'
'connect_socket' => 'reset',
'name' => 'reset'
}
},
'connection_num' => undef
}
'connection_num' => undef,
'value' => 1,
'type' => 'num'
},
'wb_slave' => {
'connection_num' => undef,
'nums' => {
'0' => {
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'width' => 'WB_Byte_Aw',
'connect_socket_num' => '0',
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_slave',
'end' => 4194303,
'base' => 0,
'name' => 'wb'
}
},
'value' => 1,
'type' => 'num'
}
},
'module_name' => 'wb_single_port_ram',
'instance_name' => 'ram'
}
'parameters_order' => [
'Dw',
'Aw',
'WB_Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'CORE_NUM',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Byte_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH',
'JDw',
'JAw',
'JSTATUSw',
'JINDEXw',
'J2WBw',
'WB2Jw',
'JTAG_CHAIN'
],
'instance_name' => 'ram',
'module' => 'single_port_ram'
},
'mor1kx0' => {
'parameters_type' => {
'FEATURE_INSTRUCTIONCACHE' => {
'value' => 'Localparam'
},
'OPTION_SHIFTER' => {
'value' => 'Localparam'
},
'FEATURE_IMMU' => {
'value' => 'Localparam'
},
'IRQ_NUM' => {},
'FEATURE_DMMU' => {
'value' => 'Localparam'
},
'FEATURE_DIVIDER' => {
'value' => 'Localparam'
},
'OPTION_DCACHE_SNOOP' => {
'value' => 'Localparam'
},
'OPTION_OPERAND_WIDTH' => {},
'FEATURE_DATACACHE' => {
'value' => 'Localparam'
},
'FEATURE_MULTIPLIER' => {
'value' => 'Localparam'
}
},
'sockets' => {
'interrupt_peripheral' => {
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
},
'connection_num' => 'single connection',
'value' => 'IRQ_NUM',
'type' => 'param'
}
},
'parameters' => {
'FEATURE_INSTRUCTIONCACHE' => {
'value' => '"ENABLED"'
},
'IRQ_NUM' => {
'value' => '32'
},
'FEATURE_IMMU' => {
'value' => '"ENABLED"'
},
'OPTION_SHIFTER' => {
'value' => '"BARREL"'
},
'FEATURE_DIVIDER' => {
'value' => '"SERIAL"'
},
'FEATURE_DMMU' => {
'value' => '"ENABLED"'
},
'OPTION_DCACHE_SNOOP' => {
'value' => '"ENABLED"'
},
'FEATURE_DATACACHE' => {
'value' => '"ENABLED"'
},
'OPTION_OPERAND_WIDTH' => {
'value' => '32'
},
'FEATURE_MULTIPLIER' => {
'value' => '"THREESTAGE"'
}
},
'module' => 'mor1kx',
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM',
'OPTION_DCACHE_SNOOP',
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU',
'FEATURE_MULTIPLIER',
'FEATURE_DIVIDER',
'OPTION_SHIFTER'
],
'instance_name' => 'cpu',
'description_pdf' => undef,
'plugs' => {
'clk' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'value' => 1,
'type' => 'num'
},
'snoop' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0',
'name' => 'snoop',
'connect_socket' => 'snoop'
}
}
},
'enable' => {
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'enable',
'connect_socket' => undef
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
},
'reset' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'reset',
'name' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef
},
'wb_master' => {
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0',
'name' => 'iwb',
'connect_socket' => 'wb_master'
},
'1' => {
'connect_socket' => 'wb_master',
'name' => 'dwb',
'connect_socket_num' => '1',
'connect_id' => 'wishbone_bus0'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 2
}
},
'category' => 'Processor',
'module_name' => 'mor1k'
},
'ProNoC_jtag_uart0' => {
'parameters' => {
'Dw' => {
'value' => '32'
},
'JTAG_INDEX' => {
'value' => '126-CORE_ID'
},
'J2WBw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'
},
'Aw' => {
'value' => '1'
},
'INCLUDE_SIM_PRINTF' => {
'value' => 'SIMPLE_PRINTF'
},
'JTAG_CHAIN' => {
'value' => '3'
},
'JSTATUSw' => {
'value' => '8'
},
'JINDEXw' => {
'value' => '8'
},
'JAw' => {
'value' => '32'
},
'WB2Jw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'
},
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => '4'
},
'BUFF_Aw' => {
'value' => '4'
},
'JTAG_CONNECT' => {
'value' => '"ALTERA_JTAG_WB"'
},
'JDw' => {
'value' => '32'
}
},
'sockets' => {
'jtag_to_wb' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'jtag_to_wb'
}
},
'value' => 1,
'type' => 'num'
},
'RxD_sim' => {
'nums' => {
'0' => {
'name' => 'RxD_sim'
}
},
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num'
}
},
'parameters_type' => {
'JSTATUSw' => {},
'Dw' => {},
'JTAG_INDEX' => {
'value' => 'Localparam'
},
'J2WBw' => {},
'Aw' => {},
'INCLUDE_SIM_PRINTF' => {
'value' => 'Localparam'
},
'JTAG_CHAIN' => {
'value' => 'Localparam'
},
'TAGw' => {},
'SELw' => {},
'BUFF_Aw' => {
'value' => 'Localparam'
},
'JTAG_CONNECT' => {
'value' => 'Localparam'
},
'JDw' => {},
'JINDEXw' => {},
'JAw' => {},
'WB2Jw' => {}
},
'category' => 'Communication',
'module_name' => 'pronoc_jtag_uart',
'plugs' => {
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'value' => 1,
'type' => 'num'
},
'wb_slave' => {
'connection_num' => undef,
'nums' => {
'0' => {
'base' => 2415919104,
'end' => 2415919119,
'connect_socket' => 'wb_slave',
'name' => 'wb_slave',
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0',
'width' => 4,
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'
}
},
'type' => 'num',
'value' => 1
},
'clk' => {
'nums' => {
'0' => {
'connect_socket' => 'clk',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
}
},
'description_pdf' => undef,
'instance_name' => 'uart',
'parameters_order' => [
'Aw',
'SELw',
'TAGw',
'Dw',
'BUFF_Aw',
'JTAG_INDEX',
'JDw',
'JAw',
'JINDEXw',
'JSTATUSw',
'JTAG_CHAIN',
'JTAG_CONNECT',
'J2WBw',
'WB2Jw',
'INCLUDE_SIM_PRINTF'
],
'module' => 'ProNoC_jtag_uart'
}
},
'compile_pin' => {},
'RAM0' => {
'start' => 49152,
'end' => 65536
},
'MEM0' => {
'percent' => 75,
'width' => '14'
},
'single_port_ram0' => {
'version' => 39
},
'compile_pin_range_lsb' => {},
'compile' => {
'modelsim_bin' => '/home/alireza/intelFPGA_lite/questa/questasim/bin',
'type' => 'Modelsim',
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin',
'board' => 'DE5',
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim'
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim',
'type' => 'QuartusII',
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin'
},
'hdl_files' => undef,
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
'status' => 'ideal',
'timeout' => 0
},
'SOURCE_SET' => {
'clk_0_name' => 'source_clk_in',
'REDEFINE_TOP' => 0,
'SOC' => bless( {
'hdl_files' => undef,
'TOP' => {
'version' => 0
},
'instance_order' => [
'TOP'
],
'instances' => {
'TOP' => {
'plugs' => {
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => undef,
'name' => 'source_reset_in',
'connect_socket_num' => undef,
'connect_id' => 'IO'
}
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'source_clk_in',
'connect_socket' => undef
}
},
'value' => 1,
'type' => 'num'
}
},
'description_pdf' => undef,
'module_name' => 'TOP',
'category' => 'TOP',
'module' => 'TOP',
'instance_name' => 'TOP',
'parameters_order' => [],
'sockets' => {}
}
},
'modules' => {},
'soc_name' => {
'TOP' => undef
},
'device_win_adj' => {},
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'SOURCE_SET' => {
'IP' => bless( {
'plugs' => {
'reset' => {
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'source_reset_in'
},
'1' => {}
},
'clk' => {
'type' => 'num',
'value' => 1,
'0' => {
'name' => 'source_clk_in'
},
'1' => {}
}
},
'hdl_files' => [],
'file_name' => undef,
'module_name' => 'TOP',
'category' => 'TOP',
'GUI_REMOVE_SET' => 'DISABLE',
'parameters_order' => [],
'ports' => {
'source_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => undef
},
'source_reset_in' => {
'range' => undef,
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]'
}
},
'ports_order' => [],
'ip_name' => 'TOP',
'hdl_files_ticked' => []
}, 'ip_gen' )
},
'hdl_files_ticked' => undef
}, 'soc' )
},
'timer0' => {
'version' => 12
},
'ProNoC_jtag_uart0' => {
'version' => 11
},
'compile_pin_range_hsb' => {},
'current_module_param_type' => undef,
'ni_master0' => {
'version' => 84
},
'top_ip' => bless( {
'ports' => {
'ni_chan_out' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'chan_out',
'type' => 'output',
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'source_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => ''
},
'uart_wb_to_jtag' => {
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output'
},
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]'
},
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output'
},
'uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0'
},
'source_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => ''
},
'uart_RxD_din_sim' => {
'instance_name' => 'ProNoC_jtag_uart0',
'range' => '7:0 ',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
},
'ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0'
},
'ni_chan_in' => {
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0',
'intfc_port' => 'chan_in',
'type' => 'input',
'intfc_name' => 'socket:ni[0]'
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'output',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => ''
}
},
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_chan_out' => {
'instance_name' => 'ni_master0',
'range' => 'smartflit_chanel_t',
'type' => 'output',
'intfc_port' => 'chan_out'
},
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0'
'intfc_port' => 'current_r_addr'
},
'ni_chan_in' => {
'type' => 'input',
'intfc_port' => 'chan_in',
'range' => 'smartflit_chanel_t',
'intfc_port' => 'chan_in',
'instance_name' => 'ni_master0',
'type' => 'input'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_chan_out' => {
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0',
'intfc_port' => 'chan_out',
'type' => 'output'
}
'instance_name' => 'ni_master0'
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_wr_sim' => {
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'range' => ''
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0'
},
'uart_RxD_din_sim' => {
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'range' => '7:0 '
},
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => '',
'type' => 'output',
'range' => ''
}
'intfc_port' => 'RxD_ready_sim'
},
'uart_RxD_din_sim' => {
'type' => 'input',
'intfc_port' => 'RxD_din_sim',
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input',
'instance_name' => 'clk_source0'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => ''
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0'
},
'uart_wb_to_jtag' => {
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0'
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_WB2Jw-1 : 0'
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0'
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0'
},
'ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0'
'intfc_port' => 'jwb_o',
'type' => 'output'
}
}
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
}
}
},
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'instance_name' => 'clk_source0',
'intfc_port' => 'reset_i',
'range' => '',
'type' => 'input',
'range' => ''
'intfc_port' => 'reset_i'
}
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'ProNoC_jtag_uart0' => {
'instance' => 'uart',
'ports' => {
'uart_RxD_ready_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output'
},
'uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'type' => 'input',
'intfc_port' => 'RxD_din_sim'
},
'uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'uart_RxD_wr_sim' => {
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]'
}
},
'module_name' => 'pronoc_jtag_uart',
'localparam' => {
'uart_TAGw' => {
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'uart_SELw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '4',
'type' => 'Fixed'
},
'uart_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '1',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
},
'uart_BUFF_Aw' => {
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'content' => '2,16,1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '4',
'type' => 'Spin-button'
},
'uart_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
}
},
'module' => 'ProNoC_jtag_uart',
'parameters' => {
'uart_JINDEXw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '8',
'type' => 'Fixed'
},
'uart_JAw' => {
'content' => '',
'info' => 'Parameter',
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Entry',
'default' => '126-CORE_ID'
},
'uart_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '3',
'type' => 'Combo-box',
'redefine_param' => 0,
'global_param' => 'Parameter'
},
'uart_WB2Jw' => {
'content' => '',
'info' => '',
'type' => 'Fixed',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JSTATUSw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '8'
},
'uart_JTAG_CONNECT' => {
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'uart_J2WBw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'type' => 'Fixed',
'info' => undef,
'content' => ''
},
'uart_JDw' => {
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'redefine_param' => 1,
'global_param' => 'Parameter'
}
},
'category' => 'Communication'
},
'timer0' => {
'module' => 'timer',
'localparam' => {
'timer_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'content' => ''
},
'timer_CNTw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32 '
},
'timer_SELw' => {
'default' => '4',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => undef
},
'timer_TAGw' => {
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'type' => 'Fixed'
},
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'content' => '1,32,1'
},
'timer_Dw' => {
'content' => '',
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Localparam',
'redefine_param' => 1
}
},
'category' => 'Timer',
'instance' => 'timer',
'module_name' => 'timer'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'localparam' => {
'bus_Dw' => {
'info' => 'The wishbone Bus data width in bits.',
'content' => '8,512,8',
'bus_Aw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'The wishbone Bus address width',
'content' => '4,128,1',
'type' => 'Spin-button',
'default' => '32'
},
'bus_Aw' => {
'default' => '32',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '4,128,1',
'info' => 'The wishbone Bus address width'
},
'bus_BTEw' => {
'bus_SELw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '2 ',
'info' => undef,
'content' => ''
},
'bus_CTIw' => {
'default' => 'bus_Dw/8',
'content' => '',
'info' => undef,
'type' => 'Fixed',
'default' => '3',
'redefine_param' => 1,
'global_param' => 'Localparam'
'info' => undef
},
'bus_SELw' => {
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => 'bus_Dw/8',
'type' => 'Fixed'
},
'bus_S' => {
'content' => '1,256,1',
'info' => 'Number of wishbone slave interface',
'content' => '1,256,1',
'default' => '4',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '4',
'type' => 'Spin-button'
'global_param' => 'Localparam'
},
'bus_M' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'default' => ' 4',
'content' => '1,256,1',
'info' => 'Number of wishbone master interface',
'default' => ' 4',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
'info' => 'Number of wishbone master interface'
},
'bus_TAGw' => {
'content' => '',
1724,77 → 1648,145
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'bus_CTIw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'type' => 'Fixed',
'info' => undef,
'content' => ''
},
'bus_BTEw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => undef,
'content' => '',
'type' => 'Fixed',
'default' => '2 '
},
'bus_Dw' => {
'content' => '8,512,8',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'module' => 'wishbone_bus'
'category' => 'Bus',
'module_name' => 'wishbone_bus'
},
'clk_source0' => {
'category' => 'Source',
'localparam' => {
'source_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ALTERA"',
'type' => 'Combo-box',
'info' => '',
'content' => '"ALTERA","XILINX"'
}
},
'module' => 'clk_source',
'module_name' => 'clk_source',
'ports' => {
'source_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'source_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]'
}
'timer0' => {
'module_name' => 'timer',
'category' => 'Timer',
'localparam' => {
'timer_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '3',
'content' => '',
'info' => undef
},
'timer_Dw' => {
'info' => undef,
'content' => '',
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'timer_CNTw' => {
'content' => '',
'info' => undef,
'default' => '32 ',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'timer_TAGw' => {
'default' => '3',
'type' => 'Fixed',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'timer_SELw' => {
'content' => '',
'info' => undef,
'default' => '4',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'content' => '1,32,1',
'type' => 'Spin-button',
'default' => '8'
}
},
'instance' => 'source'
},
'module' => 'timer',
'instance' => 'timer'
},
'ni_master0' => {
'category' => 'NoC',
'localparam' => {
'ni_CRC_EN' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"NO"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"YES","NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'content' => '"YES","NO"'
},
'ni_TAGw' => {
'info' => 'Parameter',
'content' => '',
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_Dw' => {
'type' => 'Spin-button',
'default' => '32',
'content' => '32,256,8',
'info' => 'wishbone_bus data width in bits.',
'content' => '32,256,8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '32'
'redefine_param' => 1
},
'ni_HDATA_PRECAPw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'content' => '0,8,1',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '0',
'type' => 'Spin-button'
'type' => 'Spin-button',
'default' => '0'
},
'ni_MAX_BURST_SIZE' => {
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '16',
'type' => 'Combo-box'
},
'ni_S_Aw' => {
'default' => '8',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_M_Aw' => {
'default' => '32',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => 'Dw',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ni_MAX_TRANSACTION_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
1804,127 → 1796,241
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1'
},
'ni_M_Aw' => {
'redefine_param' => 1,
'ni_MAX_BURST_SIZE' => {
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'type' => 'Combo-box',
'default' => '16',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw'
},
'ni_S_Aw' => {
'default' => '8',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ni_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '4',
'type' => 'Fixed',
'default' => '4',
'info' => 'Parameter',
'content' => ''
},
'ni_TAGw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'type' => 'Fixed'
}
},
'parameters' => {
'ni_EAw' => {
'ni_RAw' => {
'global_param' => 'Parameter',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '16',
'content' => '',
'info' => undef
},
'ni_EAw' => {
'type' => 'Fixed',
'default' => '16',
'content' => '',
'info' => undef,
'content' => ''
},
'ni_RAw' => {
'info' => undef,
'content' => '',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '16'
'redefine_param' => 0
}
},
'module' => 'ni_master',
'instance' => 'ni',
'ports' => {
'ni_chan_out' => {
'range' => 'smartflit_chanel_t',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'chan_out',
'type' => 'output'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_e_addr'
'type' => 'input'
},
'ni_chan_in' => {
'type' => 'input',
'range' => 'smartflit_chanel_t',
'intfc_port' => 'chan_in',
'range' => 'smartflit_chanel_t',
'intfc_name' => 'socket:ni[0]'
},
'ni_chan_out' => {
'intfc_port' => 'chan_out',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_r_addr'
}
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
}
},
'category' => 'NoC',
'module_name' => 'ni_master'
},
'clk_source0' => {
'ports' => {
'source_reset_in' => {
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]'
},
'source_clk_in' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]'
}
},
'instance' => 'source',
'module' => 'clk_source',
'module_name' => 'clk_source',
'category' => 'Source',
'localparam' => {
'source_FPGA_VENDOR' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"ALTERA","XILINX"',
'info' => '',
'default' => '"ALTERA"',
'type' => 'Combo-box'
}
}
},
'single_port_ram0' => {
'category' => 'RAM',
'parameters' => {
'ram_JTAG_INDEX' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'type' => 'Entry',
'default' => 'CORE_ID'
},
'ram_JINDEXw' => {
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ram_JDw' => {
'default' => 'ram_Dw',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ram_JTAG_CHAIN' => {
'redefine_param' => 0,
'global_param' => 'Parameter',
'content' => '1,2,3,4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'type' => 'Combo-box'
},
'ram_WB2Jw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'content' => '',
'info' => undef
},
'ram_J2WBw' => {
'content' => '',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram_JAw' => {
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ram_JSTATUSw' => {
'info' => 'Parameter',
'content' => '',
'default' => '8',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram_Dw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1',
'default' => '32',
'type' => 'Spin-button'
},
'ram_JTAG_CONNECT' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ALTERA_JTAG_WB"',
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
}
},
'localparam' => {
'ram_INIT_FILE_PATH' => {
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => 'SW_LOC',
'type' => 'Fixed'
},
'ram_INITIAL_EN' => {
'content' => '"YES","NO"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'type' => 'Combo-box',
'default' => '"YES"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_WB_Aw' => {
'type' => 'Spin-button',
'default' => '20',
'content' => '4,31,1',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '4,31,1',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). '
'redefine_param' => 1
},
'ram_Aw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '4,31,1',
'info' => 'Memory address width',
'default' => '14',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
'default' => '14'
},
'ram_SELw' => {
'type' => 'Fixed',
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_FPGA_VENDOR' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"ALTERA","XILINX","GENERIC"',
'info' => '',
'default' => '"ALTERA"',
'type' => 'Combo-box'
},
'ram_BTEw' => {
'default' => '2',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_MEM_CONTENT_FILE_NAME' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Entry',
'default' => '"ram0"',
'content' => '',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
1936,412 → 2042,345
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'content' => ''
'type' => 'Entry',
'default' => '"ram0"'
},
'ram_BURST_MODE' => {
'ram_BYTE_WR_EN' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'content' => '"DISABLED","ENABLED"'
'content' => '"YES","NO"',
'info' => 'Byte enable',
'default' => '"YES"',
'type' => 'Combo-box'
},
'ram_BTEw' => {
'ram_TAGw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '2',
'default' => '3',
'type' => 'Fixed'
},
'ram_BURST_MODE' => {
'type' => 'Combo-box',
'default' => '"ENABLED"',
'content' => '"DISABLED","ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_INIT_FILE_PATH' => {
'type' => 'Fixed',
'default' => 'SW_LOC',
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_INITIAL_EN' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"YES"',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram_CTIw' => {
'content' => '',
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_SELw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => 'ram_Dw/8',
'type' => 'Fixed'
},
'ram_TAGw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'type' => 'Fixed'
'type' => 'Fixed',
'default' => '3'
},
'ram_BYTE_WR_EN' => {
'content' => '"YES","NO"',
'info' => 'Byte enable',
'default' => '"YES"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_CORE_NUM' => {
'content' => '',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'CORE_ID'
},
'ram_FPGA_VENDOR' => {
'content' => '"ALTERA","XILINX","GENERIC"',
'info' => '',
'default' => '"ALTERA"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1
}
},
'parameters' => {
'ram_JDw' => {
'default' => 'ram_Dw',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => 'Parameter'
},
'ram_JTAG_CHAIN' => {
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'content' => '1,2,3,4',
'redefine_param' => 0,
'global_param' => 'Parameter',
'default' => '4',
'type' => 'Combo-box'
},
'ram_JAw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32'
},
'ram_JTAG_CONNECT' => {
'type' => 'Combo-box',
'default' => '"ALTERA_JTAG_WB"',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
},
'ram_Dw' => {
'content' => '8,1024,1',
'info' => 'Memory data width in Bits.',
'default' => '32',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram_JTAG_INDEX' => {
'content' => '',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'type' => 'Entry',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram_JINDEXw' => {
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '8',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram_JSTATUSw' => {
'default' => 'CORE_ID',
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => '8',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
},
'ram_WB2Jw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'type' => 'Fixed',
'info' => undef,
'content' => ''
},
'ram_J2WBw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'type' => 'Fixed',
'info' => undef,
'content' => ''
}
'global_param' => 'Localparam'
}
},
'module_name' => 'wb_single_port_ram',
'category' => 'RAM',
'instance' => 'ram',
'module' => 'single_port_ram',
'module_name' => 'wb_single_port_ram',
'ports' => {
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0'
},
'ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
'range' => 'ram_J2WBw-1 : 0'
}
},
'instance' => 'ram'
}
},
'ProNoC_jtag_uart0' => {
'parameters' => {
'uart_J2WBw' => {
'type' => 'Fixed',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'content' => '',
'info' => undef,
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JTAG_CONNECT' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box'
},
'uart_JINDEXw' => {
'type' => 'Fixed',
'default' => '8',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JSTATUSw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '8',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter'
},
'uart_JTAG_INDEX' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Entry',
'default' => '126-CORE_ID',
'content' => '',
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.'
},
'uart_JAw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter'
},
'uart_JDw' => {
'type' => 'Fixed',
'default' => '32',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '3',
'type' => 'Combo-box',
'redefine_param' => 0,
'global_param' => 'Parameter'
},
'uart_WB2Jw' => {
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'type' => 'Fixed',
'content' => '',
'info' => '',
'global_param' => 'Parameter',
'redefine_param' => 1
}
},
'localparam' => {
'uart_Aw' => {
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'default' => '1',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'uart_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
},
'uart_BUFF_Aw' => {
'default' => '4',
'type' => 'Spin-button',
'content' => '2,16,1',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'uart_TAGw' => {
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'default' => '3',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'uart_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '4'
}
},
'module_name' => 'pronoc_jtag_uart',
'category' => 'Communication',
'ports' => {
'uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0'
},
'uart_RxD_wr_sim' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'intfc_name' => 'socket:RxD_sim[0]'
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'range' => '7:0 '
},
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'output',
'range' => ''
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0'
}
},
'module' => 'ProNoC_jtag_uart',
'instance' => 'uart'
},
'mor1kx0' => {
'module' => 'mor1kx',
'localparam' => {
'cpu_FEATURE_DIVIDER' => {
'default' => '"SERIAL"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"SERIAL","NONE"',
'info' => 'Specify the divider implementation'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box'
},
'cpu_IRQ_NUM' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'content' => ''
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_FEATURE_IMMU' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'type' => 'Combo-box'
},
'cpu_FEATURE_DATACACHE' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Combo-box'
},
'cpu_FEATURE_DMMU' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Combo-box',
'info' => '',
'content' => '"NONE","ENABLED"'
},
'cpu_OPTION_SHIFTER' => {
'content' => '"BARREL","SERIAL"',
'info' => 'Specify the shifter implementation',
'type' => 'Combo-box',
'default' => '"BARREL"',
'info' => 'Specify the shifter implementation',
'content' => '"BARREL","SERIAL"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_OPTION_OPERAND_WIDTH' => {
'default' => '32',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_FEATURE_MULTIPLIER' => {
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'info' => 'Specify the multiplier implementation',
'type' => 'Combo-box',
'default' => '"THREESTAGE"',
'info' => 'Specify the multiplier implementation',
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_OPTION_OPERAND_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
},
'cpu_OPTION_DCACHE_SNOOP' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'info' => '',
'content' => '"NONE","ENABLED"'
}
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_FEATURE_DMMU' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'info' => '',
'type' => 'Combo-box',
'default' => '"ENABLED"'
},
'cpu_FEATURE_DIVIDER' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'info' => 'Specify the divider implementation',
'content' => '"SERIAL","NONE"',
'default' => '"SERIAL"',
'type' => 'Combo-box'
},
'cpu_FEATURE_IMMU' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"',
'content' => '"NONE","ENABLED"',
'info' => ''
}
},
'module_name' => 'mor1k',
'category' => 'Processor',
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
'range' => ''
}
},
'instance' => 'cpu',
'module_name' => 'mor1k'
'module' => 'mor1kx',
'instance' => 'cpu'
}
},
'ports' => {
'source_clk_in' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0',
'type' => 'output',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_o'
},
'uart_RxD_din_sim' => {
'intfc_port' => 'RxD_din_sim',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 '
},
'source_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input'
},
'uart_RxD_ready_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'intfc_port' => 'RxD_ready_sim'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_chan_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'chan_in',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'ni_chan_out' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'chan_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'uart_RxD_wr_sim' => {
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'RxD_wr_sim'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'instance_name' => 'mor1kx0',
'intfc_port' => 'enable_i',
'type' => 'input'
},
'ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'instance_name' => 'single_port_ram0',
'type' => 'input',
'range' => 'ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
}
}
}, 'ip_gen' ),
'modules' => {},
'ROM0' => {
'start' => 0,
'end' => 49152
'JTAG' => {
'M_CHAIN' => '0'
},
'device_win_adj' => {
'ha' => '0',
'va' => '0'
},
'global_param' => {
'CORE_ID' => 3,
'SW_LOC' => '/home/alireza/work/git/hca_git/mpsoc_work/SOC/mor1k_tile/sw'
},
'clk_source0' => {
'version' => 1
},
'graph_save' => {},
'mor1kx0' => {
'version' => 26
},
'single_port_ram0' => {
'version' => 39
},
'soc_name' => 'mor1k_tile',
'tile_diagram' => {
'show_clk' => 0,
'show_reset' => 0,
'show_unused' => 1
},
'noc_param' => {},
'hdl_files_ticked' => undef,
'parameters_order' => {
'current_module_param' => [
'FPGA_VENDOR',
2394,22 → 2433,5
'INCLUDE_SIM_PRINTF'
]
},
'JTAG' => {
'M_CHAIN' => '0'
},
'MEM0' => {
'percent' => 75,
'width' => '14'
},
'ProNoC_jtag_uart0' => {
'version' => 11
},
'Unset-intfc' => {},
'RAM0' => {
'end' => 65536,
'start' => 49152
},
'ni_master0' => {
'version' => 84
}
'hdl_files' => undef
}, 'soc' );
/verilog/functions.v
1,12 → 1,5
 
function integer log2;
input integer number; begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
function [15:0]i2s;
input integer c; integer i; integer tmp; begin
20,6 → 13,16
endfunction //i2s
 
/*
 
function integer log2;
input integer number; begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
 
function [159:0]f2s;
input real f; reg s;reg b; integer i; integer j;integer a; real tmp; begin
s=0;

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