OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui
    from Rev 33 to Rev 34
    ↔ Reverse comparison
  •

Rev 33 → Rev 34

/ProNoC.pl
25,7 → 25,7
 
 
 
our $VERSION = '1.6.0';
our $VERSION = '1.7.0';
 
sub main{
 
/doc/ProNoC_Tutorial1.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/ProNoC_Tutorial2.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/ProNoC_intfc_gen.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/ProNoC_ip_gen.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/ProNoC_pt_gen.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/ProNoC_simulator.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/ProNoC_system_installation.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/icons/binary.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/icons/binary.png
icons/binary.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: icons/diagram.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: icons/diagram.png =================================================================== --- icons/diagram.png (nonexistent) +++ icons/diagram.png (revision 34)
icons/diagram.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: icons/enter.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: icons/enter.png =================================================================== --- icons/enter.png (nonexistent) +++ icons/enter.png (revision 34)
icons/enter.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: icons/evince-icon.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: icons/evince-icon.png =================================================================== --- icons/evince-icon.png (nonexistent) +++ icons/evince-icon.png (revision 34)
icons/evince-icon.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: icons/gate.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: icons/gate.jpg =================================================================== --- icons/gate.jpg (nonexistent) +++ icons/gate.jpg (revision 34)
icons/gate.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: icons/left.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: icons/left.png =================================================================== --- icons/left.png (nonexistent) +++ icons/left.png (revision 34)
icons/left.png Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: lib/boards/DE0_nano/De0_nano.csv =================================================================== --- lib/boards/DE0_nano/De0_nano.csv (nonexistent) +++ lib/boards/DE0_nano/De0_nano.csv (revision 34) @@ -0,0 +1,172 @@ +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# File: /home/alireza/mywork/mpsoc/perl_gui/lib/boards/DE0_nano/test/test.csv +# Generated on: Mon May 29 17:28:04 2017 + +# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software. + +To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair +CLOCK_50,Unknown,PIN_R8,3,B3_N0,3.3-V LVTTL,,,, +LED[0],Unknown,PIN_A15,7,B7_N0,3.3-V LVTTL,,,, +LED[1],Unknown,PIN_A13,7,B7_N0,3.3-V LVTTL,,,, +LED[2],Unknown,PIN_B13,7,B7_N0,3.3-V LVTTL,,,, +LED[3],Unknown,PIN_A11,7,B7_N0,3.3-V LVTTL,,,, +LED[4],Unknown,PIN_D1,1,B1_N0,3.3-V LVTTL,,,, +LED[5],Unknown,PIN_F3,1,B1_N0,3.3-V LVTTL,,,, +LED[6],Unknown,PIN_B1,1,B1_N0,3.3-V LVTTL,,,, +LED[7],Unknown,PIN_L3,2,B2_N0,3.3-V LVTTL,,,, +KEY[0],Unknown,PIN_J15,5,B5_N0,3.3-V LVTTL,,,, +KEY[1],Unknown,PIN_E1,1,B1_N0,3.3-V LVTTL,,,, +SW[0],Unknown,PIN_M1,2,B2_N0,3.3-V LVTTL,,,, +SW[1],Unknown,PIN_T8,3,B3_N0,3.3-V LVTTL,,,, +SW[2],Unknown,PIN_B9,7,B7_N0,3.3-V LVTTL,,,, +SW[3],Unknown,PIN_M15,5,B5_N0,3.3-V LVTTL,,,, +DRAM_ADDR[0],Unknown,PIN_P2,2,B2_N0,3.3-V LVTTL,,,, +DRAM_ADDR[1],Unknown,PIN_N5,3,B3_N0,3.3-V LVTTL,,,, +DRAM_ADDR[2],Unknown,PIN_N6,3,B3_N0,3.3-V LVTTL,,,, +DRAM_ADDR[3],Unknown,PIN_M8,3,B3_N0,3.3-V LVTTL,,,, +DRAM_ADDR[4],Unknown,PIN_P8,3,B3_N0,3.3-V LVTTL,,,, +DRAM_ADDR[5],Unknown,PIN_T7,3,B3_N0,3.3-V LVTTL,,,, +DRAM_ADDR[6],Unknown,PIN_N8,3,B3_N0,3.3-V LVTTL,,,, +DRAM_ADDR[7],Unknown,PIN_T6,3,B3_N0,3.3-V LVTTL,,,, +DRAM_ADDR[8],Unknown,PIN_R1,2,B2_N0,3.3-V LVTTL,,,, +DRAM_ADDR[9],Unknown,PIN_P1,2,B2_N0,3.3-V LVTTL,,,, +DRAM_ADDR[10],Unknown,PIN_N2,2,B2_N0,3.3-V LVTTL,,,, +DRAM_ADDR[11],Unknown,PIN_N1,2,B2_N0,3.3-V LVTTL,,,, +DRAM_ADDR[12],Unknown,PIN_L4,2,B2_N0,3.3-V LVTTL,,,, +DRAM_BA[0],Unknown,PIN_M7,3,B3_N0,3.3-V LVTTL,,,, +DRAM_BA[1],Unknown,PIN_M6,3,B3_N0,3.3-V LVTTL,,,, +DRAM_CKE,Unknown,PIN_L7,3,B3_N0,3.3-V LVTTL,,,, +DRAM_CLK,Unknown,PIN_R4,3,B3_N0,3.3-V LVTTL,,,, +DRAM_CS_N,Unknown,PIN_P6,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQ[0],Unknown,PIN_G2,1,B1_N0,3.3-V LVTTL,,,, +DRAM_DQ[1],Unknown,PIN_G1,1,B1_N0,3.3-V LVTTL,,,, +DRAM_DQ[2],Unknown,PIN_L8,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQ[3],Unknown,PIN_K5,2,B2_N0,3.3-V LVTTL,,,, +DRAM_DQ[4],Unknown,PIN_K2,2,B2_N0,3.3-V LVTTL,,,, +DRAM_DQ[5],Unknown,PIN_J2,2,B2_N0,3.3-V LVTTL,,,, +DRAM_DQ[6],Unknown,PIN_J1,2,B2_N0,3.3-V LVTTL,,,, +DRAM_DQ[7],Unknown,PIN_R7,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQ[8],Unknown,PIN_T4,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQ[9],Unknown,PIN_T2,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQ[10],Unknown,PIN_T3,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQ[11],Unknown,PIN_R3,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQ[12],Unknown,PIN_R5,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQ[13],Unknown,PIN_P3,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQ[14],Unknown,PIN_N3,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQ[15],Unknown,PIN_K1,2,B2_N0,3.3-V LVTTL,,,, +DRAM_DQM[0],Unknown,PIN_R6,3,B3_N0,3.3-V LVTTL,,,, +DRAM_DQM[1],Unknown,PIN_T5,3,B3_N0,3.3-V LVTTL,,,, +DRAM_CAS_N,Unknown,PIN_L1,2,B2_N0,3.3-V LVTTL,,,, +DRAM_RAS_N,Unknown,PIN_L2,2,B2_N0,3.3-V LVTTL,,,, +DRAM_WE_N,Unknown,PIN_C2,1,B1_N0,3.3-V LVTTL,,,, +I2C_SCLK,Unknown,PIN_F2,1,B1_N0,3.3-V LVTTL,,,, +I2C_SDAT,Unknown,PIN_F1,1,B1_N0,3.3-V LVTTL,,,, +G_SENSOR_CS_N,Unknown,PIN_G5,1,B1_N0,3.3-V LVTTL,,,, +G_SENSOR_INT,Unknown,PIN_M2,2,B2_N0,3.3-V LVTTL,,,, +ADC_CS_N,Unknown,PIN_A10,7,B7_N0,3.3-V LVTTL,,,, +ADC_SADDR,Unknown,PIN_B10,7,B7_N0,3.3-V LVTTL,,,, +ADC_SCLK,Unknown,PIN_B14,7,B7_N0,3.3-V LVTTL,,,, +ADC_SDAT,Unknown,PIN_A9,7,B7_N0,3.3-V LVTTL,,,, +GPIO_2[0],Unknown,PIN_A14,7,B7_N0,3.3-V LVTTL,,,, +GPIO_2[1],Unknown,PIN_B16,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2[2],Unknown,PIN_C14,7,B7_N0,3.3-V LVTTL,,,, +GPIO_2[3],Unknown,PIN_C16,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2[4],Unknown,PIN_C15,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2[5],Unknown,PIN_D16,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2[6],Unknown,PIN_D15,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2[7],Unknown,PIN_D14,7,B7_N0,3.3-V LVTTL,,,, +GPIO_2[8],Unknown,PIN_F15,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2[9],Unknown,PIN_F16,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2[10],Unknown,PIN_F14,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2[11],Unknown,PIN_G16,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2[12],Unknown,PIN_G15,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2_IN[0],Unknown,PIN_E15,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2_IN[1],Unknown,PIN_E16,6,B6_N0,3.3-V LVTTL,,,, +GPIO_2_IN[2],Unknown,PIN_M16,5,B5_N0,3.3-V LVTTL,,,, +GPIO_0_IN[0],Unknown,PIN_A8,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[0],Unknown,PIN_D3,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0_IN[1],Unknown,PIN_B8,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[1],Unknown,PIN_C3,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[2],Unknown,PIN_A2,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[3],Unknown,PIN_A3,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[4],Unknown,PIN_B3,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[5],Unknown,PIN_B4,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[6],Unknown,PIN_A4,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[7],Unknown,PIN_B5,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[8],Unknown,PIN_A5,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[9],Unknown,PIN_D5,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[10],Unknown,PIN_B6,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[11],Unknown,PIN_A6,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[12],Unknown,PIN_B7,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[13],Unknown,PIN_D6,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[14],Unknown,PIN_A7,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[15],Unknown,PIN_C6,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[16],Unknown,PIN_C8,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[17],Unknown,PIN_E6,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[18],Unknown,PIN_E7,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[19],Unknown,PIN_D8,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[20],Unknown,PIN_E8,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[21],Unknown,PIN_F8,8,B8_N0,3.3-V LVTTL,,,, +GPIO_0[22],Unknown,PIN_F9,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[23],Unknown,PIN_E9,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[24],Unknown,PIN_C9,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[25],Unknown,PIN_D9,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[26],Unknown,PIN_E11,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[27],Unknown,PIN_E10,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[28],Unknown,PIN_C11,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[29],Unknown,PIN_B11,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[30],Unknown,PIN_A12,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[31],Unknown,PIN_D11,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[32],Unknown,PIN_D12,7,B7_N0,3.3-V LVTTL,,,, +GPIO_0[33],Unknown,PIN_B12,7,B7_N0,3.3-V LVTTL,,,, +GPIO_1_IN[0],Unknown,PIN_T9,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[0],Unknown,PIN_F13,6,B6_N0,3.3-V LVTTL,,,, +GPIO_1_IN[1],Unknown,PIN_R9,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[1],Unknown,PIN_T15,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[2],Unknown,PIN_T14,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[3],Unknown,PIN_T13,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[4],Unknown,PIN_R13,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[5],Unknown,PIN_T12,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[6],Unknown,PIN_R12,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[7],Unknown,PIN_T11,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[8],Unknown,PIN_T10,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[9],Unknown,PIN_R11,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[10],Unknown,PIN_P11,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[11],Unknown,PIN_R10,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[12],Unknown,PIN_N12,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[13],Unknown,PIN_P9,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[14],Unknown,PIN_N9,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[15],Unknown,PIN_N11,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[16],Unknown,PIN_L16,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[17],Unknown,PIN_K16,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[18],Unknown,PIN_R16,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[19],Unknown,PIN_L15,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[20],Unknown,PIN_P15,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[21],Unknown,PIN_P16,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[22],Unknown,PIN_R14,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[23],Unknown,PIN_N16,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[24],Unknown,PIN_N15,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[25],Unknown,PIN_P14,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[26],Unknown,PIN_L14,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[27],Unknown,PIN_N14,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[28],Unknown,PIN_M10,4,B4_N0,3.3-V LVTTL,,,, +GPIO_1[29],Unknown,PIN_L13,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[30],Unknown,PIN_J16,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[31],Unknown,PIN_K15,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[32],Unknown,PIN_J13,5,B5_N0,3.3-V LVTTL,,,, +GPIO_1[33],Unknown,PIN_J14,5,B5_N0,3.3-V LVTTL,,,, + Index: lib/boards/DE0_nano/De0_nano.qsf =================================================================== --- lib/boards/DE0_nano/De0_nano.qsf (nonexistent) +++ lib/boards/DE0_nano/De0_nano.qsf (revision 34) @@ -0,0 +1,383 @@ +# Copyright (C) 1991-2011 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE22F17C6 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Pin & Location Assignments +# ========================== +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_R8 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_A15 -to LED[0] +set_location_assignment PIN_A13 -to LED[1] +set_location_assignment PIN_B13 -to LED[2] +set_location_assignment PIN_A11 -to LED[3] +set_location_assignment PIN_D1 -to LED[4] +set_location_assignment PIN_F3 -to LED[5] +set_location_assignment PIN_B1 -to LED[6] +set_location_assignment PIN_L3 -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_J15 -to KEY[0] +set_location_assignment PIN_E1 -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_M1 -to SW[0] +set_location_assignment PIN_T8 -to SW[1] +set_location_assignment PIN_B9 -to SW[2] +set_location_assignment PIN_M15 -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_P2 -to DRAM_ADDR[0] +set_location_assignment PIN_N5 -to DRAM_ADDR[1] +set_location_assignment PIN_N6 -to DRAM_ADDR[2] +set_location_assignment PIN_M8 -to DRAM_ADDR[3] +set_location_assignment PIN_P8 -to DRAM_ADDR[4] +set_location_assignment PIN_T7 -to DRAM_ADDR[5] +set_location_assignment PIN_N8 -to DRAM_ADDR[6] +set_location_assignment PIN_T6 -to DRAM_ADDR[7] +set_location_assignment PIN_R1 -to DRAM_ADDR[8] +set_location_assignment PIN_P1 -to DRAM_ADDR[9] +set_location_assignment PIN_N2 -to DRAM_ADDR[10] +set_location_assignment PIN_N1 -to DRAM_ADDR[11] +set_location_assignment PIN_L4 -to DRAM_ADDR[12] +set_location_assignment PIN_M7 -to DRAM_BA[0] +set_location_assignment PIN_M6 -to DRAM_BA[1] +set_location_assignment PIN_L7 -to DRAM_CKE +set_location_assignment PIN_R4 -to DRAM_CLK +set_location_assignment PIN_P6 -to DRAM_CS_N +set_location_assignment PIN_G2 -to DRAM_DQ[0] +set_location_assignment PIN_G1 -to DRAM_DQ[1] +set_location_assignment PIN_L8 -to DRAM_DQ[2] +set_location_assignment PIN_K5 -to DRAM_DQ[3] +set_location_assignment PIN_K2 -to DRAM_DQ[4] +set_location_assignment PIN_J2 -to DRAM_DQ[5] +set_location_assignment PIN_J1 -to DRAM_DQ[6] +set_location_assignment PIN_R7 -to DRAM_DQ[7] +set_location_assignment PIN_T4 -to DRAM_DQ[8] +set_location_assignment PIN_T2 -to DRAM_DQ[9] +set_location_assignment PIN_T3 -to DRAM_DQ[10] +set_location_assignment PIN_R3 -to DRAM_DQ[11] +set_location_assignment PIN_R5 -to DRAM_DQ[12] +set_location_assignment PIN_P3 -to DRAM_DQ[13] +set_location_assignment PIN_N3 -to DRAM_DQ[14] +set_location_assignment PIN_K1 -to DRAM_DQ[15] +set_location_assignment PIN_R6 -to DRAM_DQM[0] +set_location_assignment PIN_T5 -to DRAM_DQM[1] +set_location_assignment PIN_L1 -to DRAM_CAS_N +set_location_assignment PIN_L2 -to DRAM_RAS_N +set_location_assignment PIN_C2 -to DRAM_WE_N + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N + +#============================================================ +# Accelerometer and EEPROM +#============================================================ +set_location_assignment PIN_F2 -to I2C_SCLK +set_location_assignment PIN_F1 -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT + +set_location_assignment PIN_G5 -to G_SENSOR_CS_N +set_location_assignment PIN_M2 -to G_SENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_A10 -to ADC_CS_N +set_location_assignment PIN_B10 -to ADC_SADDR +set_location_assignment PIN_B14 -to ADC_SCLK +set_location_assignment PIN_A9 -to ADC_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT + +#============================================================ +# 2x13 GPIO Header +#============================================================ +set_location_assignment PIN_A14 -to GPIO_2[0] +set_location_assignment PIN_B16 -to GPIO_2[1] +set_location_assignment PIN_C14 -to GPIO_2[2] +set_location_assignment PIN_C16 -to GPIO_2[3] +set_location_assignment PIN_C15 -to GPIO_2[4] +set_location_assignment PIN_D16 -to GPIO_2[5] +set_location_assignment PIN_D15 -to GPIO_2[6] +set_location_assignment PIN_D14 -to GPIO_2[7] +set_location_assignment PIN_F15 -to GPIO_2[8] +set_location_assignment PIN_F16 -to GPIO_2[9] +set_location_assignment PIN_F14 -to GPIO_2[10] +set_location_assignment PIN_G16 -to GPIO_2[11] +set_location_assignment PIN_G15 -to GPIO_2[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12] + +set_location_assignment PIN_E15 -to GPIO_2_IN[0] +set_location_assignment PIN_E16 -to GPIO_2_IN[1] +set_location_assignment PIN_M16 -to GPIO_2_IN[2] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2] + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_A8 -to GPIO_0_IN[0] +set_location_assignment PIN_D3 -to GPIO_0[0] +set_location_assignment PIN_B8 -to GPIO_0_IN[1] +set_location_assignment PIN_C3 -to GPIO_0[1] +set_location_assignment PIN_A2 -to GPIO_0[2] +set_location_assignment PIN_A3 -to GPIO_0[3] +set_location_assignment PIN_B3 -to GPIO_0[4] +set_location_assignment PIN_B4 -to GPIO_0[5] +set_location_assignment PIN_A4 -to GPIO_0[6] +set_location_assignment PIN_B5 -to GPIO_0[7] +set_location_assignment PIN_A5 -to GPIO_0[8] +set_location_assignment PIN_D5 -to GPIO_0[9] +set_location_assignment PIN_B6 -to GPIO_0[10] +set_location_assignment PIN_A6 -to GPIO_0[11] +set_location_assignment PIN_B7 -to GPIO_0[12] +set_location_assignment PIN_D6 -to GPIO_0[13] +set_location_assignment PIN_A7 -to GPIO_0[14] +set_location_assignment PIN_C6 -to GPIO_0[15] +set_location_assignment PIN_C8 -to GPIO_0[16] +set_location_assignment PIN_E6 -to GPIO_0[17] +set_location_assignment PIN_E7 -to GPIO_0[18] +set_location_assignment PIN_D8 -to GPIO_0[19] +set_location_assignment PIN_E8 -to GPIO_0[20] +set_location_assignment PIN_F8 -to GPIO_0[21] +set_location_assignment PIN_F9 -to GPIO_0[22] +set_location_assignment PIN_E9 -to GPIO_0[23] +set_location_assignment PIN_C9 -to GPIO_0[24] +set_location_assignment PIN_D9 -to GPIO_0[25] +set_location_assignment PIN_E11 -to GPIO_0[26] +set_location_assignment PIN_E10 -to GPIO_0[27] +set_location_assignment PIN_C11 -to GPIO_0[28] +set_location_assignment PIN_B11 -to GPIO_0[29] +set_location_assignment PIN_A12 -to GPIO_0[30] +set_location_assignment PIN_D11 -to GPIO_0[31] +set_location_assignment PIN_D12 -to GPIO_0[32] +set_location_assignment PIN_B12 -to GPIO_0[33] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] + +#============================================================ +# GPIO_0, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_T9 -to GPIO_1_IN[0] +set_location_assignment PIN_F13 -to GPIO_1[0] +set_location_assignment PIN_R9 -to GPIO_1_IN[1] +set_location_assignment PIN_T15 -to GPIO_1[1] +set_location_assignment PIN_T14 -to GPIO_1[2] +set_location_assignment PIN_T13 -to GPIO_1[3] +set_location_assignment PIN_R13 -to GPIO_1[4] +set_location_assignment PIN_T12 -to GPIO_1[5] +set_location_assignment PIN_R12 -to GPIO_1[6] +set_location_assignment PIN_T11 -to GPIO_1[7] +set_location_assignment PIN_T10 -to GPIO_1[8] +set_location_assignment PIN_R11 -to GPIO_1[9] +set_location_assignment PIN_P11 -to GPIO_1[10] +set_location_assignment PIN_R10 -to GPIO_1[11] +set_location_assignment PIN_N12 -to GPIO_1[12] +set_location_assignment PIN_P9 -to GPIO_1[13] +set_location_assignment PIN_N9 -to GPIO_1[14] +set_location_assignment PIN_N11 -to GPIO_1[15] +set_location_assignment PIN_L16 -to GPIO_1[16] +set_location_assignment PIN_K16 -to GPIO_1[17] +set_location_assignment PIN_R16 -to GPIO_1[18] +set_location_assignment PIN_L15 -to GPIO_1[19] +set_location_assignment PIN_P15 -to GPIO_1[20] +set_location_assignment PIN_P16 -to GPIO_1[21] +set_location_assignment PIN_R14 -to GPIO_1[22] +set_location_assignment PIN_N16 -to GPIO_1[23] +set_location_assignment PIN_N15 -to GPIO_1[24] +set_location_assignment PIN_P14 -to GPIO_1[25] +set_location_assignment PIN_L14 -to GPIO_1[26] +set_location_assignment PIN_N14 -to GPIO_1[27] +set_location_assignment PIN_M10 -to GPIO_1[28] +set_location_assignment PIN_L13 -to GPIO_1[29] +set_location_assignment PIN_J16 -to GPIO_1[30] +set_location_assignment PIN_K15 -to GPIO_1[31] +set_location_assignment PIN_J13 -to GPIO_1[32] +set_location_assignment PIN_J14 -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] + +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" + +set_instance_assignment -name FAST_INPUT_REGISTER ON -to * +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to * +set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to * +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to * + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top Index: lib/boards/DE1_SoC/De1_SoC.csv =================================================================== --- lib/boards/DE1_SoC/De1_SoC.csv (nonexistent) +++ lib/boards/DE1_SoC/De1_SoC.csv (revision 34) @@ -0,0 +1,436 @@ +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# File: /home/alireza/mywork/develop/verilog/temp.csv +# Generated on: Mon May 29 21:59:25 2017 + +# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software. + +To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Transceiver Analog Settings Protocol,VCCR_GXB/VCCT_GXB Voltage,Transceiver I/O Pin Termination,Transceiver Dedicated Refclk Pin Termination,Transmitter Common Mode Driver Voltage,Transmitter Slew Rate Control,Transmitter Differential Output Voltage,Receiver Buffer Common Mode Voltage +CaptureDR,Input,,,,,,,,,,,,,,,, +FromCore[4],Input,,,,,,,,,,,,,,,, +FromCore[3],Input,,,,,,,,,,,,,,,, +FromCore[2],Input,,,,,,,,,,,,,,,, +FromCore[1],Input,,,,,,,,,,,,,,,, +FromCore[0],Input,,,,,,,,,,,,,,,, +FromOutputEnable,Input,,,,,,,,,,,,,,,, +FromPreviousBSCell,Input,,,,,,,,,,,,,,,, +ShiftDR,Input,,,,,,,,,,,,,,,, +TCK,Input,,,,,,,,,,,,,,,, +ToCore[4],Output,,,,,,,,,,,,,,,, +ToCore[3],Output,,,,,,,,,,,,,,,, +ToCore[2],Output,,,,,,,,,,,,,,,, +ToCore[1],Output,,,,,,,,,,,,,,,, +ToCore[0],Output,,,,,,,,,,,,,,,, +ToNextBSCell,Output,,,,,,,,,,,,,,,, +UpdateDR,Input,,,,,,,,,,,,,,,, +extest,Input,,,,,,,,,,,,,,,, +ADC_CS_N,Unknown,PIN_AJ4,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +ADC_DIN,Unknown,PIN_AK4,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +ADC_DOUT,Unknown,PIN_AK3,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +ADC_SCLK,Unknown,PIN_AK2,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +AUD_ADCDAT,Unknown,PIN_K7,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +AUD_ADCLRCK,Unknown,PIN_K8,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +AUD_BCLK,Unknown,PIN_H7,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +AUD_DACDAT,Unknown,PIN_J7,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +AUD_DACLRCK,Unknown,PIN_H8,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +AUD_XCK,Unknown,PIN_G7,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +CLOCK_50,Unknown,PIN_AF14,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +CLOCK2_50,Unknown,PIN_AA16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +CLOCK3_50,Unknown,PIN_Y26,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +CLOCK4_50,Unknown,PIN_K14,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[0],Unknown,PIN_AK14,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[1],Unknown,PIN_AH14,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[2],Unknown,PIN_AG15,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[3],Unknown,PIN_AE14,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[4],Unknown,PIN_AB15,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[5],Unknown,PIN_AC14,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[6],Unknown,PIN_AD14,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[7],Unknown,PIN_AF15,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[8],Unknown,PIN_AH15,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[9],Unknown,PIN_AG13,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[10],Unknown,PIN_AG12,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[11],Unknown,PIN_AH13,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_ADDR[12],Unknown,PIN_AJ14,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_BA[0],Unknown,PIN_AF13,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_BA[1],Unknown,PIN_AJ12,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_CAS_N,Unknown,PIN_AF11,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_CKE,Unknown,PIN_AK13,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_CLK,Unknown,PIN_AH12,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_CS_N,Unknown,PIN_AG11,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[0],Unknown,PIN_AK6,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[1],Unknown,PIN_AJ7,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[2],Unknown,PIN_AK7,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[3],Unknown,PIN_AK8,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[4],Unknown,PIN_AK9,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[5],Unknown,PIN_AG10,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[6],Unknown,PIN_AK11,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[7],Unknown,PIN_AJ11,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[8],Unknown,PIN_AH10,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[9],Unknown,PIN_AJ10,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[10],Unknown,PIN_AJ9,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[11],Unknown,PIN_AH9,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[12],Unknown,PIN_AH8,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[13],Unknown,PIN_AH7,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[14],Unknown,PIN_AJ6,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_DQ[15],Unknown,PIN_AJ5,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_LDQM,Unknown,PIN_AB13,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_RAS_N,Unknown,PIN_AE13,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_UDQM,Unknown,PIN_AK12,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +DRAM_WE_N,Unknown,PIN_AA13,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +FAN_CTRL,Unknown,PIN_AA12,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +FPGA_I2C_SCLK,Unknown,PIN_J12,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +FPGA_I2C_SDAT,Unknown,PIN_K12,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[0],Unknown,PIN_AC18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[10],Unknown,PIN_AH18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[11],Unknown,PIN_AH17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[12],Unknown,PIN_AG16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[13],Unknown,PIN_AE16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[14],Unknown,PIN_AF16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[15],Unknown,PIN_AG17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[16],Unknown,PIN_AA18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[17],Unknown,PIN_AA19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[18],Unknown,PIN_AE17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[19],Unknown,PIN_AC20,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[1],Unknown,PIN_Y17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[20],Unknown,PIN_AH19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[21],Unknown,PIN_AJ20,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[22],Unknown,PIN_AH20,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[23],Unknown,PIN_AK21,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[24],Unknown,PIN_AD19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[25],Unknown,PIN_AD20,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[26],Unknown,PIN_AE18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[27],Unknown,PIN_AE19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[28],Unknown,PIN_AF20,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[29],Unknown,PIN_AF21,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[2],Unknown,PIN_AD17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[30],Unknown,PIN_AF19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[31],Unknown,PIN_AG21,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[32],Unknown,PIN_AF18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[33],Unknown,PIN_AG20,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[34],Unknown,PIN_AG18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[35],Unknown,PIN_AJ21,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[3],Unknown,PIN_Y18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[4],Unknown,PIN_AK16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[5],Unknown,PIN_AK18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[6],Unknown,PIN_AK19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[7],Unknown,PIN_AJ19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[8],Unknown,PIN_AJ17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_0[9],Unknown,PIN_AJ16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[0],Unknown,PIN_AB17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[10],Unknown,PIN_AG26,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[11],Unknown,PIN_AH24,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[12],Unknown,PIN_AH27,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[13],Unknown,PIN_AJ27,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[14],Unknown,PIN_AK29,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[15],Unknown,PIN_AK28,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[16],Unknown,PIN_AK27,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[17],Unknown,PIN_AJ26,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[18],Unknown,PIN_AK26,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[19],Unknown,PIN_AH25,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[1],Unknown,PIN_AA21,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[20],Unknown,PIN_AJ25,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[21],Unknown,PIN_AJ24,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[22],Unknown,PIN_AK24,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[23],Unknown,PIN_AG23,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[24],Unknown,PIN_AK23,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[25],Unknown,PIN_AH23,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[26],Unknown,PIN_AK22,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[27],Unknown,PIN_AJ22,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[28],Unknown,PIN_AH22,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[29],Unknown,PIN_AG22,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[2],Unknown,PIN_AB21,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[30],Unknown,PIN_AF24,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[31],Unknown,PIN_AF23,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[32],Unknown,PIN_AE22,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[33],Unknown,PIN_AD21,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[34],Unknown,PIN_AA20,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[35],Unknown,PIN_AC22,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[3],Unknown,PIN_AC23,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[4],Unknown,PIN_AD24,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[5],Unknown,PIN_AE23,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[6],Unknown,PIN_AE24,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[7],Unknown,PIN_AF25,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[8],Unknown,PIN_AF26,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +GPIO_1[9],Unknown,PIN_AG25,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX0[0],Unknown,PIN_AE26,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX0[1],Unknown,PIN_AE27,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX0[2],Unknown,PIN_AE28,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX0[3],Unknown,PIN_AG27,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX0[4],Unknown,PIN_AF28,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX0[5],Unknown,PIN_AG28,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX0[6],Unknown,PIN_AH28,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX1[0],Unknown,PIN_AJ29,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX1[1],Unknown,PIN_AH29,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX1[2],Unknown,PIN_AH30,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX1[3],Unknown,PIN_AG30,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX1[4],Unknown,PIN_AF29,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX1[5],Unknown,PIN_AF30,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX1[6],Unknown,PIN_AD27,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX2[0],Unknown,PIN_AB23,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX2[1],Unknown,PIN_AE29,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX2[2],Unknown,PIN_AD29,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX2[3],Unknown,PIN_AC28,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX2[4],Unknown,PIN_AD30,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX2[5],Unknown,PIN_AC29,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX2[6],Unknown,PIN_AC30,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX3[0],Unknown,PIN_AD26,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX3[1],Unknown,PIN_AC27,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX3[2],Unknown,PIN_AD25,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX3[3],Unknown,PIN_AC25,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX3[4],Unknown,PIN_AB28,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX3[5],Unknown,PIN_AB25,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX3[6],Unknown,PIN_AB22,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX4[0],Unknown,PIN_AA24,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX4[1],Unknown,PIN_Y23,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX4[2],Unknown,PIN_Y24,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX4[3],Unknown,PIN_W22,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX4[4],Unknown,PIN_W24,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX4[5],Unknown,PIN_V23,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX4[6],Unknown,PIN_W25,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX5[0],Unknown,PIN_V25,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX5[1],Unknown,PIN_AA28,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX5[2],Unknown,PIN_Y27,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX5[3],Unknown,PIN_AB27,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX5[4],Unknown,PIN_AB26,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX5[5],Unknown,PIN_AA26,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +HEX5[6],Unknown,PIN_AA25,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +IRDA_RXD,Unknown,PIN_AA30,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +IRDA_TXD,Unknown,PIN_AB30,5B,B5B_N0,3.3-V LVTTL,,,,,,,,,,,, +KEY[0],Unknown,PIN_AA14,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +KEY[1],Unknown,PIN_AA15,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +KEY[2],Unknown,PIN_W15,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +KEY[3],Unknown,PIN_Y16,3B,B3B_N0,3.3-V LVTTL,,,,,,,,,,,, +LEDR[0],Unknown,PIN_V16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +LEDR[1],Unknown,PIN_W16,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +LEDR[2],Unknown,PIN_V17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +LEDR[3],Unknown,PIN_V18,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +LEDR[4],Unknown,PIN_W17,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +LEDR[5],Unknown,PIN_W19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +LEDR[6],Unknown,PIN_Y19,4A,B4A_N0,3.3-V LVTTL,,,,,,,,,,,, +LEDR[7],Unknown,PIN_W20,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +LEDR[8],Unknown,PIN_W21,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +LEDR[9],Unknown,PIN_Y21,5A,B5A_N0,3.3-V LVTTL,,,,,,,,,,,, +PS2_CLK,Unknown,PIN_AD7,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +PS2_DAT,Unknown,PIN_AE7,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +PS2_CLK2,Unknown,PIN_AD9,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +PS2_DAT2,Unknown,PIN_AE9,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +SW[0],Unknown,PIN_AB12,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +SW[1],Unknown,PIN_AC12,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +SW[2],Unknown,PIN_AF9,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +SW[3],Unknown,PIN_AF10,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +SW[4],Unknown,PIN_AD11,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +SW[5],Unknown,PIN_AD12,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +SW[6],Unknown,PIN_AE11,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +SW[7],Unknown,PIN_AC9,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +SW[8],Unknown,PIN_AD10,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +SW[9],Unknown,PIN_AE12,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_CLK27,Unknown,PIN_H15,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_DATA[0],Unknown,PIN_D2,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_DATA[1],Unknown,PIN_B1,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_DATA[2],Unknown,PIN_E2,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_DATA[3],Unknown,PIN_B2,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_DATA[4],Unknown,PIN_D1,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_DATA[5],Unknown,PIN_E1,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_DATA[6],Unknown,PIN_C2,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_DATA[7],Unknown,PIN_B3,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_HS,Unknown,PIN_A5,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_RESET_N,Unknown,PIN_F6,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +TD_VS,Unknown,PIN_A3,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_B2_CLK,Unknown,PIN_AF4,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_B2_DATA[0],Unknown,PIN_AH4,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_B2_DATA[1],Unknown,PIN_AH3,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_B2_DATA[2],Unknown,PIN_AJ2,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_B2_DATA[3],Unknown,PIN_AJ1,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_B2_DATA[4],Unknown,PIN_AH2,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_B2_DATA[5],Unknown,PIN_AG3,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_B2_DATA[6],Unknown,PIN_AG2,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_B2_DATA[7],Unknown,PIN_AG1,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_EMPTY,Unknown,PIN_AF5,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_FULL,Unknown,PIN_AG5,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_OE_N,Unknown,PIN_AF6,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_RD_N,Unknown,PIN_AG6,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_RESET_N,Unknown,PIN_AG7,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_SCL,Unknown,PIN_AG8,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_SDA,Unknown,PIN_AF8,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +USB_WR_N,Unknown,PIN_AH5,3A,B3A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_B[0],Unknown,PIN_B13,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_B[1],Unknown,PIN_G13,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_B[2],Unknown,PIN_H13,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_B[3],Unknown,PIN_F14,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_B[4],Unknown,PIN_H14,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_B[5],Unknown,PIN_F15,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_B[6],Unknown,PIN_G15,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_B[7],Unknown,PIN_J14,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_BLANK_N,Unknown,PIN_F10,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_CLK,Unknown,PIN_A11,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_G[0],Unknown,PIN_J9,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_G[1],Unknown,PIN_J10,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_G[2],Unknown,PIN_H12,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_G[3],Unknown,PIN_G10,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_G[4],Unknown,PIN_G11,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_G[5],Unknown,PIN_G12,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_G[6],Unknown,PIN_F11,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_G[7],Unknown,PIN_E11,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_HS,Unknown,PIN_B11,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_R[0],Unknown,PIN_A13,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_R[1],Unknown,PIN_C13,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_R[2],Unknown,PIN_E13,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_R[3],Unknown,PIN_B12,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_R[4],Unknown,PIN_C12,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_R[5],Unknown,PIN_D12,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_R[6],Unknown,PIN_E12,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_R[7],Unknown,PIN_F13,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_SYNC_N,Unknown,PIN_C10,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +VGA_VS,Unknown,PIN_D11,8A,B8A_N0,3.3-V LVTTL,,,,,,,,,,,, +HPS_DDR3_ADDR[0],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[10],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[11],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[12],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[13],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[14],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[1],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[2],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[3],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[4],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[5],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[6],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[7],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[8],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ADDR[9],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_BA[0],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_BA[1],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_BA[2],Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_CAS_N,Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_CKE,Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_CS_N,Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_ODT,Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_RAS_N,Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_WE_N,Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_DDR3_RESET_N,Unknown,,,,SSTL-15 Class I,,Maximum Current,,,,,,,,,, +HPS_CONV_USB_N,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_DDR3_CK_N,Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_CK_N(n),,,,,,,, +HPS_DDR3_CK_N(n),Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_CK_N,,,,,,,, +HPS_DDR3_CK_P,Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_CK_P(n),,,,,,,, +HPS_DDR3_CK_P(n),Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_CK_P,,,,,,,, +HPS_DDR3_DM[0],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DM[1],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DM[2],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DM[3],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[0],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[1],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[2],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[3],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[4],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[5],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[6],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[7],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[8],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[9],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[10],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[11],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[12],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[13],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[14],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[15],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[16],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[17],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[18],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[19],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[20],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[21],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[22],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[23],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[24],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[25],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[26],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[27],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[28],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[29],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[30],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQ[31],Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_DDR3_DQS_N[0],Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_N[0](n),,,,,,,, +HPS_DDR3_DQS_N[0](n),Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_N[0],,,,,,,, +HPS_DDR3_DQS_N[1],Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_N[1](n),,,,,,,, +HPS_DDR3_DQS_N[1](n),Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_N[1],,,,,,,, +HPS_DDR3_DQS_N[2],Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_N[2](n),,,,,,,, +HPS_DDR3_DQS_N[2](n),Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_N[2],,,,,,,, +HPS_DDR3_DQS_N[3],Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_N[3](n),,,,,,,, +HPS_DDR3_DQS_N[3](n),Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_N[3],,,,,,,, +HPS_DDR3_DQS_P[0],Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_P[0](n),,,,,,,, +HPS_DDR3_DQS_P[0](n),Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_P[0],,,,,,,, +HPS_DDR3_DQS_P[1],Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_P[1](n),,,,,,,, +HPS_DDR3_DQS_P[1](n),Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_P[1],,,,,,,, +HPS_DDR3_DQS_P[2],Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_P[2](n),,,,,,,, +HPS_DDR3_DQS_P[2](n),Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_P[2],,,,,,,, +HPS_DDR3_DQS_P[3],Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_P[3](n),,,,,,,, +HPS_DDR3_DQS_P[3](n),Unknown,,,,Differential 1.5-V SSTL Class I,,,,HPS_DDR3_DQS_P[3],,,,,,,, +HPS_DDR3_RZQ,Unknown,,,,SSTL-15 Class I,,,,,,,,,,,, +HPS_ENET_GTX_CLK,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_INT_N,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_MDC,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_MDIO,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_RX_CLK,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_RX_DATA[0],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_RX_DATA[1],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_RX_DATA[2],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_RX_DATA[3],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_RX_DV,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_TX_DATA[0],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_TX_DATA[1],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_TX_DATA[2],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_TX_DATA[3],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_ENET_TX_EN,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_FLASH_DATA[0],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_FLASH_DATA[1],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_FLASH_DATA[2],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_FLASH_DATA[3],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_FLASH_DCLK,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_FLASH_NCSO,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_GSENSOR_INT,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_I2C1_SCLK,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_I2C1_SDAT,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_I2C2_SCLK,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_I2C2_SDAT,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_I2C_CONTROL,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_KEY,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_LED,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_LTC_GPIO,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_SD_CLK,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_SD_CMD,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_SD_DATA[0],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_SD_DATA[1],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_SD_DATA[2],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_SD_DATA[3],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_SPIM_CLK,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_SPIM_MISO,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_SPIM_MOSI,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_SPIM_SS,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_UART_RX,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_UART_TX,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_CLKOUT,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_DATA[0],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_DATA[1],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_DATA[2],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_DATA[3],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_DATA[4],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_DATA[5],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_DATA[6],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_DATA[7],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_DIR,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_NXT,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_USB_STP,Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_GPIO[0],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, +HPS_GPIO[1],Unknown,,,,3.3-V LVTTL,,,,,,,,,,,, Index: lib/boards/DE1_SoC/De1_SoC.qsf =================================================================== --- lib/boards/DE1_SoC/De1_SoC.qsf (nonexistent) +++ lib/boards/DE1_SoC/De1_SoC.qsf (revision 34) @@ -0,0 +1,967 @@ +#============================================================ +# Altera DE1-SoC board settings +#============================================================ + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA5F31C6 +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" + + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_AJ4 -to ADC_CS_N +set_location_assignment PIN_AK4 -to ADC_DIN +set_location_assignment PIN_AK3 -to ADC_DOUT +set_location_assignment PIN_AK2 -to ADC_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK + +#============================================================ +# AUD +#============================================================ +set_location_assignment PIN_K7 -to AUD_ADCDAT +set_location_assignment PIN_K8 -to AUD_ADCLRCK +set_location_assignment PIN_H7 -to AUD_BCLK +set_location_assignment PIN_J7 -to AUD_DACDAT +set_location_assignment PIN_H8 -to AUD_DACLRCK +set_location_assignment PIN_G7 -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_AF14 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# CLOCK2 +#============================================================ +set_location_assignment PIN_AA16 -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 + +#============================================================ +# CLOCK3 +#============================================================ +set_location_assignment PIN_Y26 -to CLOCK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 + +#============================================================ +# CLOCK4 +#============================================================ +set_location_assignment PIN_K14 -to CLOCK4_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK4_50 + +#============================================================ +# DRAM +#============================================================ +set_location_assignment PIN_AK14 -to DRAM_ADDR[0] +set_location_assignment PIN_AH14 -to DRAM_ADDR[1] +set_location_assignment PIN_AG15 -to DRAM_ADDR[2] +set_location_assignment PIN_AE14 -to DRAM_ADDR[3] +set_location_assignment PIN_AB15 -to DRAM_ADDR[4] +set_location_assignment PIN_AC14 -to DRAM_ADDR[5] +set_location_assignment PIN_AD14 -to DRAM_ADDR[6] +set_location_assignment PIN_AF15 -to DRAM_ADDR[7] +set_location_assignment PIN_AH15 -to DRAM_ADDR[8] +set_location_assignment PIN_AG13 -to DRAM_ADDR[9] +set_location_assignment PIN_AG12 -to DRAM_ADDR[10] +set_location_assignment PIN_AH13 -to DRAM_ADDR[11] +set_location_assignment PIN_AJ14 -to DRAM_ADDR[12] +set_location_assignment PIN_AF13 -to DRAM_BA[0] +set_location_assignment PIN_AJ12 -to DRAM_BA[1] +set_location_assignment PIN_AF11 -to DRAM_CAS_N +set_location_assignment PIN_AK13 -to DRAM_CKE +set_location_assignment PIN_AH12 -to DRAM_CLK +set_location_assignment PIN_AG11 -to DRAM_CS_N +set_location_assignment PIN_AK6 -to DRAM_DQ[0] +set_location_assignment PIN_AJ7 -to DRAM_DQ[1] +set_location_assignment PIN_AK7 -to DRAM_DQ[2] +set_location_assignment PIN_AK8 -to DRAM_DQ[3] +set_location_assignment PIN_AK9 -to DRAM_DQ[4] +set_location_assignment PIN_AG10 -to DRAM_DQ[5] +set_location_assignment PIN_AK11 -to DRAM_DQ[6] +set_location_assignment PIN_AJ11 -to DRAM_DQ[7] +set_location_assignment PIN_AH10 -to DRAM_DQ[8] +set_location_assignment PIN_AJ10 -to DRAM_DQ[9] +set_location_assignment PIN_AJ9 -to DRAM_DQ[10] +set_location_assignment PIN_AH9 -to DRAM_DQ[11] +set_location_assignment PIN_AH8 -to DRAM_DQ[12] +set_location_assignment PIN_AH7 -to DRAM_DQ[13] +set_location_assignment PIN_AJ6 -to DRAM_DQ[14] +set_location_assignment PIN_AJ5 -to DRAM_DQ[15] +set_location_assignment PIN_AB13 -to DRAM_LDQM +set_location_assignment PIN_AE13 -to DRAM_RAS_N +set_location_assignment PIN_AK12 -to DRAM_UDQM +set_location_assignment PIN_AA13 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N + +#============================================================ +# FAN +#============================================================ +set_location_assignment PIN_AA12 -to FAN_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL + +#============================================================ +# FPGA +#============================================================ +set_location_assignment PIN_J12 -to FPGA_I2C_SCLK +set_location_assignment PIN_K12 -to FPGA_I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SDAT + +#============================================================ +# GPIO +#============================================================ +set_location_assignment PIN_AC18 -to GPIO_0[0] +set_location_assignment PIN_AH18 -to GPIO_0[10] +set_location_assignment PIN_AH17 -to GPIO_0[11] +set_location_assignment PIN_AG16 -to GPIO_0[12] +set_location_assignment PIN_AE16 -to GPIO_0[13] +set_location_assignment PIN_AF16 -to GPIO_0[14] +set_location_assignment PIN_AG17 -to GPIO_0[15] +set_location_assignment PIN_AA18 -to GPIO_0[16] +set_location_assignment PIN_AA19 -to GPIO_0[17] +set_location_assignment PIN_AE17 -to GPIO_0[18] +set_location_assignment PIN_AC20 -to GPIO_0[19] +set_location_assignment PIN_Y17 -to GPIO_0[1] +set_location_assignment PIN_AH19 -to GPIO_0[20] +set_location_assignment PIN_AJ20 -to GPIO_0[21] +set_location_assignment PIN_AH20 -to GPIO_0[22] +set_location_assignment PIN_AK21 -to GPIO_0[23] +set_location_assignment PIN_AD19 -to GPIO_0[24] +set_location_assignment PIN_AD20 -to GPIO_0[25] +set_location_assignment PIN_AE18 -to GPIO_0[26] +set_location_assignment PIN_AE19 -to GPIO_0[27] +set_location_assignment PIN_AF20 -to GPIO_0[28] +set_location_assignment PIN_AF21 -to GPIO_0[29] +set_location_assignment PIN_AD17 -to GPIO_0[2] +set_location_assignment PIN_AF19 -to GPIO_0[30] +set_location_assignment PIN_AG21 -to GPIO_0[31] +set_location_assignment PIN_AF18 -to GPIO_0[32] +set_location_assignment PIN_AG20 -to GPIO_0[33] +set_location_assignment PIN_AG18 -to GPIO_0[34] +set_location_assignment PIN_AJ21 -to GPIO_0[35] +set_location_assignment PIN_Y18 -to GPIO_0[3] +set_location_assignment PIN_AK16 -to GPIO_0[4] +set_location_assignment PIN_AK18 -to GPIO_0[5] +set_location_assignment PIN_AK19 -to GPIO_0[6] +set_location_assignment PIN_AJ19 -to GPIO_0[7] +set_location_assignment PIN_AJ17 -to GPIO_0[8] +set_location_assignment PIN_AJ16 -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] + +set_location_assignment PIN_AB17 -to GPIO_1[0] +set_location_assignment PIN_AG26 -to GPIO_1[10] +set_location_assignment PIN_AH24 -to GPIO_1[11] +set_location_assignment PIN_AH27 -to GPIO_1[12] +set_location_assignment PIN_AJ27 -to GPIO_1[13] +set_location_assignment PIN_AK29 -to GPIO_1[14] +set_location_assignment PIN_AK28 -to GPIO_1[15] +set_location_assignment PIN_AK27 -to GPIO_1[16] +set_location_assignment PIN_AJ26 -to GPIO_1[17] +set_location_assignment PIN_AK26 -to GPIO_1[18] +set_location_assignment PIN_AH25 -to GPIO_1[19] +set_location_assignment PIN_AA21 -to GPIO_1[1] +set_location_assignment PIN_AJ25 -to GPIO_1[20] +set_location_assignment PIN_AJ24 -to GPIO_1[21] +set_location_assignment PIN_AK24 -to GPIO_1[22] +set_location_assignment PIN_AG23 -to GPIO_1[23] +set_location_assignment PIN_AK23 -to GPIO_1[24] +set_location_assignment PIN_AH23 -to GPIO_1[25] +set_location_assignment PIN_AK22 -to GPIO_1[26] +set_location_assignment PIN_AJ22 -to GPIO_1[27] +set_location_assignment PIN_AH22 -to GPIO_1[28] +set_location_assignment PIN_AG22 -to GPIO_1[29] +set_location_assignment PIN_AB21 -to GPIO_1[2] +set_location_assignment PIN_AF24 -to GPIO_1[30] +set_location_assignment PIN_AF23 -to GPIO_1[31] +set_location_assignment PIN_AE22 -to GPIO_1[32] +set_location_assignment PIN_AD21 -to GPIO_1[33] +set_location_assignment PIN_AA20 -to GPIO_1[34] +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AC23 -to GPIO_1[3] +set_location_assignment PIN_AD24 -to GPIO_1[4] +set_location_assignment PIN_AE23 -to GPIO_1[5] +set_location_assignment PIN_AE24 -to GPIO_1[6] +set_location_assignment PIN_AF25 -to GPIO_1[7] +set_location_assignment PIN_AF26 -to GPIO_1[8] +set_location_assignment PIN_AG25 -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] + +#============================================================ +# HEX0 +#============================================================ +set_location_assignment PIN_AE26 -to HEX0[0] +set_location_assignment PIN_AE27 -to HEX0[1] +set_location_assignment PIN_AE28 -to HEX0[2] +set_location_assignment PIN_AG27 -to HEX0[3] +set_location_assignment PIN_AF28 -to HEX0[4] +set_location_assignment PIN_AG28 -to HEX0[5] +set_location_assignment PIN_AH28 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] + +#============================================================ +# HEX1 +#============================================================ +set_location_assignment PIN_AJ29 -to HEX1[0] +set_location_assignment PIN_AH29 -to HEX1[1] +set_location_assignment PIN_AH30 -to HEX1[2] +set_location_assignment PIN_AG30 -to HEX1[3] +set_location_assignment PIN_AF29 -to HEX1[4] +set_location_assignment PIN_AF30 -to HEX1[5] +set_location_assignment PIN_AD27 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] + +#============================================================ +# HEX2 +#============================================================ +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_AE29 -to HEX2[1] +set_location_assignment PIN_AD29 -to HEX2[2] +set_location_assignment PIN_AC28 -to HEX2[3] +set_location_assignment PIN_AD30 -to HEX2[4] +set_location_assignment PIN_AC29 -to HEX2[5] +set_location_assignment PIN_AC30 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] + +#============================================================ +# HEX3 +#============================================================ +set_location_assignment PIN_AD26 -to HEX3[0] +set_location_assignment PIN_AC27 -to HEX3[1] +set_location_assignment PIN_AD25 -to HEX3[2] +set_location_assignment PIN_AC25 -to HEX3[3] +set_location_assignment PIN_AB28 -to HEX3[4] +set_location_assignment PIN_AB25 -to HEX3[5] +set_location_assignment PIN_AB22 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] + +#============================================================ +# HEX4 +#============================================================ +set_location_assignment PIN_AA24 -to HEX4[0] +set_location_assignment PIN_Y23 -to HEX4[1] +set_location_assignment PIN_Y24 -to HEX4[2] +set_location_assignment PIN_W22 -to HEX4[3] +set_location_assignment PIN_W24 -to HEX4[4] +set_location_assignment PIN_V23 -to HEX4[5] +set_location_assignment PIN_W25 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] + +#============================================================ +# HEX5 +#============================================================ +set_location_assignment PIN_V25 -to HEX5[0] +set_location_assignment PIN_AA28 -to HEX5[1] +set_location_assignment PIN_Y27 -to HEX5[2] +set_location_assignment PIN_AB27 -to HEX5[3] +set_location_assignment PIN_AB26 -to HEX5[4] +set_location_assignment PIN_AA26 -to HEX5[5] +set_location_assignment PIN_AA25 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] + +#============================================================ +# IRDA +#============================================================ +set_location_assignment PIN_AA30 -to IRDA_RXD +set_location_assignment PIN_AB30 -to IRDA_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_TXD + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_AA14 -to KEY[0] +set_location_assignment PIN_AA15 -to KEY[1] +set_location_assignment PIN_W15 -to KEY[2] +set_location_assignment PIN_Y16 -to KEY[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] + +#============================================================ +# LEDR +#============================================================ +set_location_assignment PIN_V16 -to LEDR[0] +set_location_assignment PIN_W16 -to LEDR[1] +set_location_assignment PIN_V17 -to LEDR[2] +set_location_assignment PIN_V18 -to LEDR[3] +set_location_assignment PIN_W17 -to LEDR[4] +set_location_assignment PIN_W19 -to LEDR[5] +set_location_assignment PIN_Y19 -to LEDR[6] +set_location_assignment PIN_W20 -to LEDR[7] +set_location_assignment PIN_W21 -to LEDR[8] +set_location_assignment PIN_Y21 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] + +#============================================================ +# PS2 +#============================================================ +set_location_assignment PIN_AD7 -to PS2_CLK +set_location_assignment PIN_AE7 -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT + +set_location_assignment PIN_AD9 -to PS2_CLK2 +set_location_assignment PIN_AE9 -to PS2_DAT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_AB12 -to SW[0] +set_location_assignment PIN_AC12 -to SW[1] +set_location_assignment PIN_AF9 -to SW[2] +set_location_assignment PIN_AF10 -to SW[3] +set_location_assignment PIN_AD11 -to SW[4] +set_location_assignment PIN_AD12 -to SW[5] +set_location_assignment PIN_AE11 -to SW[6] +set_location_assignment PIN_AC9 -to SW[7] +set_location_assignment PIN_AD10 -to SW[8] +set_location_assignment PIN_AE12 -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] + +#============================================================ +# TD +#============================================================ +set_location_assignment PIN_H15 -to TD_CLK27 +set_location_assignment PIN_D2 -to TD_DATA[0] +set_location_assignment PIN_B1 -to TD_DATA[1] +set_location_assignment PIN_E2 -to TD_DATA[2] +set_location_assignment PIN_B2 -to TD_DATA[3] +set_location_assignment PIN_D1 -to TD_DATA[4] +set_location_assignment PIN_E1 -to TD_DATA[5] +set_location_assignment PIN_C2 -to TD_DATA[6] +set_location_assignment PIN_B3 -to TD_DATA[7] +set_location_assignment PIN_A5 -to TD_HS +set_location_assignment PIN_F6 -to TD_RESET_N +set_location_assignment PIN_A3 -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS + +#============================================================ +# USB +#============================================================ +set_location_assignment PIN_AF4 -to USB_B2_CLK +set_location_assignment PIN_AH4 -to USB_B2_DATA[0] +set_location_assignment PIN_AH3 -to USB_B2_DATA[1] +set_location_assignment PIN_AJ2 -to USB_B2_DATA[2] +set_location_assignment PIN_AJ1 -to USB_B2_DATA[3] +set_location_assignment PIN_AH2 -to USB_B2_DATA[4] +set_location_assignment PIN_AG3 -to USB_B2_DATA[5] +set_location_assignment PIN_AG2 -to USB_B2_DATA[6] +set_location_assignment PIN_AG1 -to USB_B2_DATA[7] +set_location_assignment PIN_AF5 -to USB_EMPTY +set_location_assignment PIN_AG5 -to USB_FULL +set_location_assignment PIN_AF6 -to USB_OE_N +set_location_assignment PIN_AG6 -to USB_RD_N +set_location_assignment PIN_AG7 -to USB_RESET_N +set_location_assignment PIN_AG8 -to USB_SCL +set_location_assignment PIN_AF8 -to USB_SDA +set_location_assignment PIN_AH5 -to USB_WR_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_EMPTY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FULL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RD_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_WR_N + +#============================================================ +# VGA +#============================================================ +set_location_assignment PIN_B13 -to VGA_B[0] +set_location_assignment PIN_G13 -to VGA_B[1] +set_location_assignment PIN_H13 -to VGA_B[2] +set_location_assignment PIN_F14 -to VGA_B[3] +set_location_assignment PIN_H14 -to VGA_B[4] +set_location_assignment PIN_F15 -to VGA_B[5] +set_location_assignment PIN_G15 -to VGA_B[6] +set_location_assignment PIN_J14 -to VGA_B[7] +set_location_assignment PIN_F10 -to VGA_BLANK_N +set_location_assignment PIN_A11 -to VGA_CLK +set_location_assignment PIN_J9 -to VGA_G[0] +set_location_assignment PIN_J10 -to VGA_G[1] +set_location_assignment PIN_H12 -to VGA_G[2] +set_location_assignment PIN_G10 -to VGA_G[3] +set_location_assignment PIN_G11 -to VGA_G[4] +set_location_assignment PIN_G12 -to VGA_G[5] +set_location_assignment PIN_F11 -to VGA_G[6] +set_location_assignment PIN_E11 -to VGA_G[7] +set_location_assignment PIN_B11 -to VGA_HS +set_location_assignment PIN_A13 -to VGA_R[0] +set_location_assignment PIN_C13 -to VGA_R[1] +set_location_assignment PIN_E13 -to VGA_R[2] +set_location_assignment PIN_B12 -to VGA_R[3] +set_location_assignment PIN_C12 -to VGA_R[4] +set_location_assignment PIN_D12 -to VGA_R[5] +set_location_assignment PIN_E12 -to VGA_R[6] +set_location_assignment PIN_F13 -to VGA_R[7] +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_D11 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS + +#============================================================ +# HPS +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CONTROL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP +set_instance_assignment -name io_standard "3.3-V LVTTL" -to HPS_GPIO[0] +set_instance_assignment -name io_standard "3.3-V LVTTL" -to HPS_GPIO[1] + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CAS_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CS_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ODT +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RAS_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_WE_N +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RESET_N + +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_P +set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_N + +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] + +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_P +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_N +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[3] + +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[8] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[9] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[10] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[11] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[12] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[13] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[14] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[15] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[16] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[17] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[18] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[19] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[20] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[21] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[22] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[23] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[24] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[25] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[26] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[27] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[28] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[29] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[30] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[31] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[10] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[11] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[12] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[13] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[14] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[3] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[4] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[5] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[6] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[7] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[8] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[9] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[0] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[1] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[2] +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CAS_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CKE +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CS_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ODT +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RAS_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_WE_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RESET_N +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_P +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_N + +#============================================================ +# End of pin and io_standard assignments +#============================================================ + + +set_global_assignment -name LAST_QUARTUS_VERSION 14.0 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name SDC_FILE DE1_SoC.sdc +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name STATE_MACHINE_PROCESSING "USER-ENCODED" Index: lib/boards/DE2_115/DE2_115.csv =================================================================== --- lib/boards/DE2_115/DE2_115.csv (nonexistent) +++ lib/boards/DE2_115/DE2_115.csv (revision 34) @@ -0,0 +1,801 @@ +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version +# File: E:\SVN\DE2_115\trunk\test\de2_115_golden_sopc\de2_115_golden_sopc.csv +# Generated on: Fri Jun 18 14:51:18 2010 + +# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software. + +To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved +AUD_ADCDAT,Input,PIN_D2,1,B1_N0,3.3-V LVTTL, +AUD_ADCLRCK,Bidir,PIN_C2,1,B1_N0,3.3-V LVTTL, +AUD_BCLK,Bidir,PIN_F2,1,B1_N1,3.3-V LVTTL, +AUD_DACDAT,Output,PIN_D1,1,B1_N0,3.3-V LVTTL, +AUD_DACLRCK,Bidir,PIN_E3,1,B1_N0,3.3-V LVTTL, +AUD_XCK,Output,PIN_E1,1,B1_N0,3.3-V LVTTL, +CLOCK2_50,Input,PIN_AG14,3,B3_N0,3.3-V LVTTL, +CLOCK3_50,Input,PIN_AG15,4,B4_N2,3.3-V LVTTL, +CLOCK_50,Input,PIN_Y2,2,B2_N0,3.3-V LVTTL, +DRAM_ADDR[12],Output,PIN_Y7,2,B2_N2,3.3-V LVTTL, +DRAM_ADDR[11],Output,PIN_AA5,2,B2_N2,3.3-V LVTTL, +DRAM_ADDR[10],Output,PIN_R5,2,B2_N0,3.3-V LVTTL, +DRAM_ADDR[9],Output,PIN_Y6,2,B2_N2,3.3-V LVTTL, +DRAM_ADDR[8],Output,PIN_Y5,2,B2_N2,3.3-V LVTTL, +DRAM_ADDR[7],Output,PIN_AA7,2,B2_N2,3.3-V LVTTL, +DRAM_ADDR[6],Output,PIN_W7,2,B2_N2,3.3-V LVTTL, +DRAM_ADDR[5],Output,PIN_W8,2,B2_N2,3.3-V LVTTL, +DRAM_ADDR[4],Output,PIN_V5,2,B2_N1,3.3-V LVTTL, +DRAM_ADDR[3],Output,PIN_P1,1,B1_N2,3.3-V LVTTL, +DRAM_ADDR[2],Output,PIN_U8,2,B2_N1,3.3-V LVTTL, +DRAM_ADDR[1],Output,PIN_V8,2,B2_N1,3.3-V LVTTL, +DRAM_ADDR[0],Output,PIN_R6,2,B2_N0,3.3-V LVTTL, +DRAM_BA[1],Output,PIN_R4,2,B2_N0,3.3-V LVTTL, +DRAM_BA[0],Output,PIN_U7,2,B2_N1,3.3-V LVTTL, +DRAM_CAS_N,Output,PIN_V7,2,B2_N1,3.3-V LVTTL, +DRAM_CKE,Output,PIN_AA6,2,B2_N2,3.3-V LVTTL, +DRAM_CLK,Output,PIN_AE5,3,B3_N2,3.3-V LVTTL, +DRAM_CS_N,Output,PIN_T4,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[31],Bidir,PIN_U1,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[30],Bidir,PIN_U4,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[29],Bidir,PIN_T3,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[28],Bidir,PIN_R3,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[27],Bidir,PIN_R2,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[26],Bidir,PIN_R1,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[25],Bidir,PIN_R7,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[24],Bidir,PIN_U5,2,B2_N1,3.3-V LVTTL, +DRAM_DQ[23],Bidir,PIN_L7,1,B1_N2,3.3-V LVTTL, +DRAM_DQ[22],Bidir,PIN_M7,1,B1_N2,3.3-V LVTTL, +DRAM_DQ[21],Bidir,PIN_M4,1,B1_N1,3.3-V LVTTL, +DRAM_DQ[20],Bidir,PIN_N4,1,B1_N2,3.3-V LVTTL, +DRAM_DQ[19],Bidir,PIN_N3,1,B1_N2,3.3-V LVTTL, +DRAM_DQ[18],Bidir,PIN_P2,1,B1_N2,3.3-V LVTTL, +DRAM_DQ[17],Bidir,PIN_L8,1,B1_N2,3.3-V LVTTL, +DRAM_DQ[16],Bidir,PIN_M8,1,B1_N2,3.3-V LVTTL, +DRAM_DQ[15],Bidir,PIN_AC2,2,B2_N1,3.3-V LVTTL, +DRAM_DQ[14],Bidir,PIN_AB3,2,B2_N1,3.3-V LVTTL, +DRAM_DQ[13],Bidir,PIN_AC1,2,B2_N1,3.3-V LVTTL, +DRAM_DQ[12],Bidir,PIN_AB2,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[11],Bidir,PIN_AA3,2,B2_N1,3.3-V LVTTL, +DRAM_DQ[10],Bidir,PIN_AB1,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[9],Bidir,PIN_Y4,2,B2_N1,3.3-V LVTTL, +DRAM_DQ[8],Bidir,PIN_Y3,2,B2_N1,3.3-V LVTTL, +DRAM_DQ[7],Bidir,PIN_U3,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[6],Bidir,PIN_V1,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[5],Bidir,PIN_V2,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[4],Bidir,PIN_V3,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[3],Bidir,PIN_W1,2,B2_N1,3.3-V LVTTL, +DRAM_DQ[2],Bidir,PIN_V4,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[1],Bidir,PIN_W2,2,B2_N0,3.3-V LVTTL, +DRAM_DQ[0],Bidir,PIN_W3,2,B2_N2,3.3-V LVTTL, +DRAM_DQM[3],Output,PIN_N8,1,B1_N2,3.3-V LVTTL, +DRAM_DQM[2],Output,PIN_K8,1,B1_N2,3.3-V LVTTL, +DRAM_DQM[1],Output,PIN_W4,2,B2_N2,3.3-V LVTTL, +DRAM_DQM[0],Output,PIN_U2,2,B2_N0,3.3-V LVTTL, +DRAM_RAS_N,Output,PIN_U6,2,B2_N1,3.3-V LVTTL, +DRAM_WE_N,Output,PIN_V6,2,B2_N1,3.3-V LVTTL, +EEP_I2C_SCLK,Output,PIN_D14,8,B8_N0,3.3-V LVTTL, +EEP_I2C_SDAT,Bidir,PIN_E14,8,B8_N0,3.3-V LVTTL, +ENET0_GTX_CLK,Output,PIN_A17,7,B7_N2,2.5 V, +ENET0_INT_N,Input,PIN_A21,7,B7_N1,2.5 V, +ENET0_LINK100,Input,PIN_C14,8,B8_N0,3.3-V LVTTL, +ENET0_MDC,Output,PIN_C20,7,B7_N1,2.5 V, +ENET0_MDIO,Bidir,PIN_B21,7,B7_N1,2.5 V, +ENET0_RST_N,Output,PIN_C19,7,B7_N1,2.5 V, +ENET0_RX_CLK,Input,PIN_A15,7,B7_N2,2.5 V, +ENET0_RX_COL,Input,PIN_E15,7,B7_N2,2.5 V, +ENET0_RX_CRS,Input,PIN_D15,7,B7_N2,2.5 V, +ENET0_RX_DATA[3],Input,PIN_C15,7,B7_N2,2.5 V, +ENET0_RX_DATA[2],Input,PIN_D17,7,B7_N1,2.5 V, +ENET0_RX_DATA[1],Input,PIN_D16,7,B7_N2,2.5 V, +ENET0_RX_DATA[0],Input,PIN_C16,7,B7_N2,2.5 V, +ENET0_RX_DV,Input,PIN_C17,7,B7_N1,2.5 V, +ENET0_RX_ER,Input,PIN_D18,7,B7_N1,2.5 V, +ENET0_TX_CLK,Input,PIN_B17,7,B7_N2,2.5 V, +ENET0_TX_DATA[3],Output,PIN_B19,7,B7_N1,2.5 V, +ENET0_TX_DATA[2],Output,PIN_A19,7,B7_N1,2.5 V, +ENET0_TX_DATA[1],Output,PIN_D19,7,B7_N1,2.5 V, +ENET0_TX_DATA[0],Output,PIN_C18,7,B7_N1,2.5 V, +ENET0_TX_EN,Output,PIN_A18,7,B7_N1,2.5 V, +ENET0_TX_ER,Output,PIN_B18,7,B7_N1,2.5 V, +ENET1_GTX_CLK,Output,PIN_C23,7,B7_N0,2.5 V, +ENET1_INT_N,Input,PIN_D24,7,B7_N0,2.5 V, +ENET1_LINK100,Input,PIN_D13,8,B8_N0,3.3-V LVTTL, +ENET1_MDC,Output,PIN_D23,7,B7_N0,2.5 V, +ENET1_MDIO,Bidir,PIN_D25,7,B7_N0,2.5 V, +ENET1_RST_N,Output,PIN_D22,7,B7_N0,2.5 V, +ENET1_RX_CLK,Input,PIN_B15,7,B7_N2,2.5 V, +ENET1_RX_COL,Input,PIN_B22,7,B7_N1,2.5 V, +ENET1_RX_CRS,Input,PIN_D20,7,B7_N1,2.5 V, +ENET1_RX_DATA[3],Input,PIN_D21,7,B7_N0,2.5 V, +ENET1_RX_DATA[2],Input,PIN_A23,7,B7_N0,2.5 V, +ENET1_RX_DATA[1],Input,PIN_C21,7,B7_N0,2.5 V, +ENET1_RX_DATA[0],Input,PIN_B23,7,B7_N0,2.5 V, +ENET1_RX_DV,Input,PIN_A22,7,B7_N1,2.5 V, +ENET1_RX_ER,Input,PIN_C24,7,B7_N0,2.5 V, +ENET1_TX_CLK,Input,PIN_C22,7,B7_N0,2.5 V, +ENET1_TX_DATA[3],Output,PIN_C26,7,B7_N0,2.5 V, +ENET1_TX_DATA[2],Output,PIN_B26,7,B7_N0,2.5 V, +ENET1_TX_DATA[1],Output,PIN_A26,7,B7_N0,2.5 V, +ENET1_TX_DATA[0],Output,PIN_C25,7,B7_N0,2.5 V, +ENET1_TX_EN,Output,PIN_B25,7,B7_N0,2.5 V, +ENET1_TX_ER,Output,PIN_A25,7,B7_N0,2.5 V, +ENETCLK_25,Input,PIN_A14,8,B8_N0,3.3-V LVTTL, +EX_IO[6],Bidir,PIN_D9,8,B8_N1,3.3-V LVTTL, +EX_IO[5],Bidir,PIN_E10,8,B8_N1,3.3-V LVTTL, +EX_IO[4],Bidir,PIN_F14,8,B8_N0,3.3-V LVTTL, +EX_IO[3],Bidir,PIN_H14,8,B8_N0,3.3-V LVTTL, +EX_IO[2],Bidir,PIN_H13,8,B8_N0,3.3-V LVTTL, +EX_IO[1],Bidir,PIN_J14,8,B8_N0,3.3-V LVTTL, +EX_IO[0],Bidir,PIN_J10,8,B8_N1,3.3-V LVTTL, +FL_ADDR[22],Output,PIN_AD11,3,B3_N0,3.3-V LVTTL, +FL_ADDR[21],Output,PIN_AD10,3,B3_N2,3.3-V LVTTL, +FL_ADDR[20],Output,PIN_AE10,3,B3_N1,3.3-V LVTTL, +FL_ADDR[19],Output,PIN_AD12,3,B3_N0,3.3-V LVTTL, +FL_ADDR[18],Output,PIN_AC12,3,B3_N0,3.3-V LVTTL, +FL_ADDR[17],Output,PIN_AH12,3,B3_N0,3.3-V LVTTL, +FL_ADDR[16],Output,PIN_AA8,3,B3_N1,3.3-V LVTTL, +FL_ADDR[15],Output,PIN_Y10,3,B3_N2,3.3-V LVTTL, +FL_ADDR[14],Output,PIN_AC8,3,B3_N1,3.3-V LVTTL, +FL_ADDR[13],Output,PIN_AD8,3,B3_N2,3.3-V LVTTL, +FL_ADDR[12],Output,PIN_AA10,3,B3_N1,3.3-V LVTTL, +FL_ADDR[11],Output,PIN_AF9,3,B3_N1,3.3-V LVTTL, +FL_ADDR[10],Output,PIN_AE9,3,B3_N1,3.3-V LVTTL, +FL_ADDR[9],Output,PIN_AB10,3,B3_N1,3.3-V LVTTL, +FL_ADDR[8],Output,PIN_AB12,3,B3_N0,3.3-V LVTTL, +FL_ADDR[7],Output,PIN_AB13,3,B3_N0,3.3-V LVTTL, +FL_ADDR[6],Output,PIN_AA12,3,B3_N0,3.3-V LVTTL, +FL_ADDR[5],Output,PIN_AA13,3,B3_N0,3.3-V LVTTL, +FL_ADDR[4],Output,PIN_Y12,3,B3_N0,3.3-V LVTTL, +FL_ADDR[3],Output,PIN_Y14,3,B3_N0,3.3-V LVTTL, +FL_ADDR[2],Output,PIN_Y13,3,B3_N0,3.3-V LVTTL, +FL_ADDR[1],Output,PIN_AH7,3,B3_N1,3.3-V LVTTL, +FL_ADDR[0],Output,PIN_AG12,3,B3_N0,3.3-V LVTTL, +FL_CE_N,Output,PIN_AG7,3,B3_N2,3.3-V LVTTL, +FL_DQ[7],Bidir,PIN_AF12,3,B3_N1,3.3-V LVTTL, +FL_DQ[6],Bidir,PIN_AH11,3,B3_N0,3.3-V LVTTL, +FL_DQ[5],Bidir,PIN_AG11,3,B3_N0,3.3-V LVTTL, +FL_DQ[4],Bidir,PIN_AF11,3,B3_N1,3.3-V LVTTL, +FL_DQ[3],Bidir,PIN_AH10,3,B3_N1,3.3-V LVTTL, +FL_DQ[2],Bidir,PIN_AG10,3,B3_N1,3.3-V LVTTL, +FL_DQ[1],Bidir,PIN_AF10,3,B3_N1,3.3-V LVTTL, +FL_DQ[0],Bidir,PIN_AH8,3,B3_N1,3.3-V LVTTL, +FL_OE_N,Output,PIN_AG8,3,B3_N1,3.3-V LVTTL, +FL_RST_N,Output,PIN_AE11,3,B3_N1,3.3-V LVTTL, +FL_RY,Input,PIN_Y1,2,B2_N0,3.3-V LVTTL, +FL_WE_N,Output,PIN_AC10,3,B3_N0,3.3-V LVTTL, +FL_WP_N,Output,PIN_AE12,3,B3_N1,3.3-V LVTTL, +GPIO[35],Bidir,PIN_AG26,4,B4_N0,3.3-V LVTTL, +GPIO[34],Bidir,PIN_AH23,4,B4_N1,3.3-V LVTTL, +GPIO[33],Bidir,PIN_AH26,4,B4_N0,3.3-V LVTTL, +GPIO[32],Bidir,PIN_AF20,4,B4_N1,3.3-V LVTTL, +GPIO[31],Bidir,PIN_AG23,4,B4_N1,3.3-V LVTTL, +GPIO[30],Bidir,PIN_AE20,4,B4_N1,3.3-V LVTTL, +GPIO[29],Bidir,PIN_AF26,4,B4_N1,3.3-V LVTTL, +GPIO[28],Bidir,PIN_AH22,4,B4_N1,3.3-V LVTTL, +GPIO[27],Bidir,PIN_AE24,4,B4_N0,3.3-V LVTTL, +GPIO[26],Bidir,PIN_AG22,4,B4_N1,3.3-V LVTTL, +GPIO[25],Bidir,PIN_AE25,4,B4_N1,3.3-V LVTTL, +GPIO[24],Bidir,PIN_AH25,4,B4_N1,3.3-V LVTTL, +GPIO[23],Bidir,PIN_AD25,4,B4_N0,3.3-V LVTTL, +GPIO[22],Bidir,PIN_AG25,4,B4_N1,3.3-V LVTTL, +GPIO[21],Bidir,PIN_AD22,4,B4_N0,3.3-V LVTTL, +GPIO[20],Bidir,PIN_AF22,4,B4_N0,3.3-V LVTTL, +GPIO[19],Bidir,PIN_AF21,4,B4_N1,3.3-V LVTTL, +GPIO[18],Bidir,PIN_AE22,4,B4_N0,3.3-V LVTTL, +GPIO[17],Bidir,PIN_AC22,4,B4_N0,3.3-V LVTTL, +GPIO[16],Bidir,PIN_AF25,4,B4_N1,3.3-V LVTTL, +GPIO[15],Bidir,PIN_AE21,4,B4_N1,3.3-V LVTTL, +GPIO[14],Bidir,PIN_AF24,4,B4_N1,3.3-V LVTTL, +GPIO[13],Bidir,PIN_AF15,4,B4_N2,3.3-V LVTTL, +GPIO[12],Bidir,PIN_AD19,4,B4_N0,3.3-V LVTTL, +GPIO[11],Bidir,PIN_AF16,4,B4_N2,3.3-V LVTTL, +GPIO[10],Bidir,PIN_AC19,4,B4_N0,3.3-V LVTTL, +GPIO[9],Bidir,PIN_AE15,4,B4_N2,3.3-V LVTTL, +GPIO[8],Bidir,PIN_AD15,4,B4_N2,3.3-V LVTTL, +GPIO[7],Bidir,PIN_AE16,4,B4_N2,3.3-V LVTTL, +GPIO[6],Bidir,PIN_AD21,4,B4_N0,3.3-V LVTTL, +GPIO[5],Bidir,PIN_Y16,4,B4_N0,3.3-V LVTTL, +GPIO[4],Bidir,PIN_AC21,4,B4_N0,3.3-V LVTTL, +GPIO[3],Bidir,PIN_Y17,4,B4_N0,3.3-V LVTTL, +GPIO[2],Bidir,PIN_AB21,4,B4_N0,3.3-V LVTTL, +GPIO[1],Bidir,PIN_AC15,4,B4_N2,3.3-V LVTTL, +GPIO[0],Bidir,PIN_AB22,4,B4_N0,3.3-V LVTTL, +HEX0[6],Output,PIN_H22,6,B6_N0,2.5 V, +HEX0[5],Output,PIN_J22,6,B6_N0,2.5 V, +HEX0[4],Output,PIN_L25,6,B6_N1,2.5 V, +HEX0[3],Output,PIN_L26,6,B6_N1,2.5 V, +HEX0[2],Output,PIN_E17,7,B7_N2,2.5 V, +HEX0[1],Output,PIN_F22,7,B7_N0,2.5 V, +HEX0[0],Output,PIN_G18,7,B7_N2,2.5 V, +HEX1[6],Output,PIN_U24,5,B5_N0,2.5 V, +HEX1[5],Output,PIN_U23,5,B5_N1,2.5 V, +HEX1[4],Output,PIN_W25,5,B5_N1,2.5 V, +HEX1[3],Output,PIN_W22,5,B5_N0,2.5 V, +HEX1[2],Output,PIN_W21,5,B5_N1,2.5 V, +HEX1[1],Output,PIN_Y22,5,B5_N0,2.5 V, +HEX1[0],Output,PIN_M24,6,B6_N2,2.5 V, +HEX2[6],Output,PIN_W28,5,B5_N1,2.5 V, +HEX2[5],Output,PIN_W27,5,B5_N1,2.5 V, +HEX2[4],Output,PIN_Y26,5,B5_N1,2.5 V, +HEX2[3],Output,PIN_W26,5,B5_N1,2.5 V, +HEX2[2],Output,PIN_Y25,5,B5_N1,2.5 V, +HEX2[1],Output,PIN_AA26,5,B5_N1,2.5 V, +HEX2[0],Output,PIN_AA25,5,B5_N1,2.5 V, +HEX3[6],Output,PIN_Y19,4,B4_N0,3.3-V LVTTL, +HEX3[5],Output,PIN_AF23,4,B4_N0,3.3-V LVTTL, +HEX3[4],Output,PIN_AD24,4,B4_N0,3.3-V LVTTL, +HEX3[3],Output,PIN_AA21,4,B4_N0,3.3-V LVTTL, +HEX3[2],Output,PIN_AB20,4,B4_N0,3.3-V LVTTL, +HEX3[1],Output,PIN_U21,5,B5_N0,2.5 V, +HEX3[0],Output,PIN_V21,5,B5_N1,2.5 V, +HEX4[6],Output,PIN_AE18,4,B4_N2,3.3-V LVTTL, +HEX4[5],Output,PIN_AF19,4,B4_N1,3.3-V LVTTL, +HEX4[4],Output,PIN_AE19,4,B4_N1,3.3-V LVTTL, +HEX4[3],Output,PIN_AH21,4,B4_N2,3.3-V LVTTL, +HEX4[2],Output,PIN_AG21,4,B4_N2,3.3-V LVTTL, +HEX4[1],Output,PIN_AA19,4,B4_N0,3.3-V LVTTL, +HEX4[0],Output,PIN_AB19,4,B4_N0,3.3-V LVTTL, +HEX5[6],Output,PIN_AH18,4,B4_N2,3.3-V LVTTL, +HEX5[5],Output,PIN_AF18,4,B4_N1,3.3-V LVTTL, +HEX5[4],Output,PIN_AG19,4,B4_N2,3.3-V LVTTL, +HEX5[3],Output,PIN_AH19,4,B4_N2,3.3-V LVTTL, +HEX5[2],Output,PIN_AB18,4,B4_N0,3.3-V LVTTL, +HEX5[1],Output,PIN_AC18,4,B4_N1,3.3-V LVTTL, +HEX5[0],Output,PIN_AD18,4,B4_N1,3.3-V LVTTL, +HEX6[6],Output,PIN_AC17,4,B4_N2,3.3-V LVTTL, +HEX6[5],Output,PIN_AA15,4,B4_N2,3.3-V LVTTL, +HEX6[4],Output,PIN_AB15,4,B4_N2,3.3-V LVTTL, +HEX6[3],Output,PIN_AB17,4,B4_N1,3.3-V LVTTL, +HEX6[2],Output,PIN_AA16,4,B4_N2,3.3-V LVTTL, +HEX6[1],Output,PIN_AB16,4,B4_N2,3.3-V LVTTL, +HEX6[0],Output,PIN_AA17,4,B4_N1,3.3-V LVTTL, +HEX7[6],Output,PIN_AA14,3,B3_N0,3.3-V LVTTL, +HEX7[5],Output,PIN_AG18,4,B4_N2,3.3-V LVTTL, +HEX7[4],Output,PIN_AF17,4,B4_N2,3.3-V LVTTL, +HEX7[3],Output,PIN_AH17,4,B4_N2,3.3-V LVTTL, +HEX7[2],Output,PIN_AG17,4,B4_N2,3.3-V LVTTL, +HEX7[1],Output,PIN_AE17,4,B4_N2,3.3-V LVTTL, +HEX7[0],Output,PIN_AD17,4,B4_N2,3.3-V LVTTL, +HSMC_CLKIN0,Input,PIN_AH15,4,B4_N2,3.0-V LVTTL, +HSMC_CLKIN_P1,Input,PIN_J27,6,B6_N2,LVDS, +HSMC_CLKIN_P2,Input,PIN_Y27,5,B5_N0,LVDS, +HSMC_CLKOUT0,Output,PIN_AD28,5,B5_N2,2.5 V, +HSMC_CLKOUT_P1,Output,PIN_G23,6,B6_N0,LVDS, +HSMC_CLKOUT_P2,Output,PIN_V23,5,B5_N1,LVDS, +HSMC_D[3],Bidir,PIN_AF27,5,B5_N2,2.5 V, +HSMC_D[2],Bidir,PIN_AE27,5,B5_N2,2.5 V, +HSMC_D[1],Bidir,PIN_AE28,5,B5_N2,2.5 V, +HSMC_D[0],Bidir,PIN_AE26,5,B5_N2,2.5 V, +HSMC_RX_D_P[16],Input,PIN_T21,5,B5_N0,LVDS, +HSMC_RX_D_P[15],Input,PIN_R22,5,B5_N0,LVDS, +HSMC_RX_D_P[14],Input,PIN_P21,5,B5_N0,LVDS, +HSMC_RX_D_P[13],Input,PIN_P25,6,B6_N2,LVDS, +HSMC_RX_D_P[12],Input,PIN_N25,6,B6_N2,LVDS, +HSMC_RX_D_P[11],Input,PIN_L21,6,B6_N0,LVDS, +HSMC_RX_D_P[10],Input,PIN_U25,5,B5_N0,LVDS, +HSMC_RX_D_P[9],Input,PIN_T25,5,B5_N0,LVDS, +HSMC_RX_D_P[8],Input,PIN_R25,5,B5_N0,LVDS, +HSMC_RX_D_P[7],Input,PIN_M25,6,B6_N2,LVDS, +HSMC_RX_D_P[6],Input,PIN_L23,6,B6_N1,LVDS, +HSMC_RX_D_P[5],Input,PIN_K25,6,B6_N1,LVDS, +HSMC_RX_D_P[4],Input,PIN_H25,6,B6_N1,LVDS, +HSMC_RX_D_P[3],Input,PIN_G25,6,B6_N0,LVDS, +HSMC_RX_D_P[2],Input,PIN_F26,6,B6_N1,LVDS, +HSMC_RX_D_P[1],Input,PIN_D26,6,B6_N0,LVDS, +HSMC_RX_D_P[0],Input,PIN_F24,6,B6_N0,LVDS, +HSMC_TX_D_P[16],Output,PIN_U22,5,B5_N0,LVDS, +HSMC_TX_D_P[15],Output,PIN_V27,5,B5_N1,LVDS, +HSMC_TX_D_P[14],Output,PIN_U27,5,B5_N0,LVDS, +HSMC_TX_D_P[13],Output,PIN_R27,5,B5_N0,LVDS, +HSMC_TX_D_P[12],Output,PIN_V25,5,B5_N1,LVDS, +HSMC_TX_D_P[11],Output,PIN_L27,6,B6_N2,LVDS, +HSMC_TX_D_P[10],Output,PIN_J25,6,B6_N1,LVDS, +HSMC_TX_D_P[9],Output,PIN_P27,6,B6_N2,LVDS, +HSMC_TX_D_P[8],Output,PIN_J23,6,B6_N0,LVDS, +HSMC_TX_D_P[7],Output,PIN_H23,6,B6_N0,LVDS, +HSMC_TX_D_P[6],Output,PIN_K21,6,B6_N0,LVDS, +HSMC_TX_D_P[5],Output,PIN_M27,6,B6_N2,LVDS, +HSMC_TX_D_P[4],Output,PIN_K27,6,B6_N1,LVDS, +HSMC_TX_D_P[3],Output,PIN_G27,6,B6_N1,LVDS, +HSMC_TX_D_P[2],Output,PIN_F27,6,B6_N1,LVDS, +HSMC_TX_D_P[1],Output,PIN_E27,6,B6_N1,LVDS, +HSMC_TX_D_P[0],Output,PIN_D27,6,B6_N0,LVDS, +I2C_SCLK,Output,PIN_B7,8,B8_N1,3.3-V LVTTL, +I2C_SDAT,Bidir,PIN_A8,8,B8_N1,3.3-V LVTTL, +IRDA_RXD,Input,PIN_Y15,3,B3_N0,3.3-V LVTTL, +KEY[3],Input,PIN_R24,5,B5_N0,2.5 V, +KEY[2],Input,PIN_N21,6,B6_N2,2.5 V, +KEY[1],Input,PIN_M21,6,B6_N1,2.5 V, +KEY[0],Input,PIN_M23,6,B6_N2,2.5 V, +LCD_BLON,Output,PIN_L6,1,B1_N2,3.3-V LVTTL, +LCD_DATA[7],Bidir,PIN_M5,1,B1_N2,3.3-V LVTTL, +LCD_DATA[6],Bidir,PIN_M3,1,B1_N1,3.3-V LVTTL, +LCD_DATA[5],Bidir,PIN_K2,1,B1_N1,3.3-V LVTTL, +LCD_DATA[4],Bidir,PIN_K1,1,B1_N1,3.3-V LVTTL, +LCD_DATA[3],Bidir,PIN_K7,1,B1_N1,3.3-V LVTTL, +LCD_DATA[2],Bidir,PIN_L2,1,B1_N2,3.3-V LVTTL, +LCD_DATA[1],Bidir,PIN_L1,1,B1_N2,3.3-V LVTTL, +LCD_DATA[0],Bidir,PIN_L3,1,B1_N1,3.3-V LVTTL, +LCD_EN,Output,PIN_L4,1,B1_N1,3.3-V LVTTL, +LCD_ON,Output,PIN_L5,1,B1_N1,3.3-V LVTTL, +LCD_RS,Output,PIN_M2,1,B1_N2,3.3-V LVTTL, +LCD_RW,Output,PIN_M1,1,B1_N2,3.3-V LVTTL, +LEDG[8],Output,PIN_F17,7,B7_N2,2.5 V, +LEDG[7],Output,PIN_G21,7,B7_N1,2.5 V, +LEDG[6],Output,PIN_G22,7,B7_N2,2.5 V, +LEDG[5],Output,PIN_G20,7,B7_N1,2.5 V, +LEDG[4],Output,PIN_H21,7,B7_N2,2.5 V, +LEDG[3],Output,PIN_E24,7,B7_N1,2.5 V, +LEDG[2],Output,PIN_E25,7,B7_N1,2.5 V, +LEDG[1],Output,PIN_E22,7,B7_N0,2.5 V, +LEDG[0],Output,PIN_E21,7,B7_N0,2.5 V, +LEDR[17],Output,PIN_H15,7,B7_N2,2.5 V, +LEDR[16],Output,PIN_G16,7,B7_N2,2.5 V, +LEDR[15],Output,PIN_G15,7,B7_N2,2.5 V, +LEDR[14],Output,PIN_F15,7,B7_N2,2.5 V, +LEDR[13],Output,PIN_H17,7,B7_N2,2.5 V, +LEDR[12],Output,PIN_J16,7,B7_N2,2.5 V, +LEDR[11],Output,PIN_H16,7,B7_N2,2.5 V, +LEDR[10],Output,PIN_J15,7,B7_N2,2.5 V, +LEDR[9],Output,PIN_G17,7,B7_N1,2.5 V, +LEDR[8],Output,PIN_J17,7,B7_N2,2.5 V, +LEDR[7],Output,PIN_H19,7,B7_N2,2.5 V, +LEDR[6],Output,PIN_J19,7,B7_N2,2.5 V, +LEDR[5],Output,PIN_E18,7,B7_N1,2.5 V, +LEDR[4],Output,PIN_F18,7,B7_N1,2.5 V, +LEDR[3],Output,PIN_F21,7,B7_N0,2.5 V, +LEDR[2],Output,PIN_E19,7,B7_N0,2.5 V, +LEDR[1],Output,PIN_F19,7,B7_N0,2.5 V, +LEDR[0],Output,PIN_G19,7,B7_N2,2.5 V, +OTG_ADDR[1],Output,PIN_C3,8,B8_N2,3.3-V LVTTL, +OTG_ADDR[0],Output,PIN_H7,1,B1_N0,3.3-V LVTTL, +OTG_CS_N,Output,PIN_A3,8,B8_N2,3.3-V LVTTL, +OTG_DACK_N[1],Output,PIN_D4,8,B8_N2,3.3-V LVTTL, +OTG_DACK_N[0],Output,PIN_C4,8,B8_N2,3.3-V LVTTL, +OTG_DATA[15],Bidir,PIN_G4,1,B1_N0,3.3-V LVTTL, +OTG_DATA[14],Bidir,PIN_F3,1,B1_N0,3.3-V LVTTL, +OTG_DATA[13],Bidir,PIN_F1,1,B1_N1,3.3-V LVTTL, +OTG_DATA[12],Bidir,PIN_G3,1,B1_N0,3.3-V LVTTL, +OTG_DATA[11],Bidir,PIN_G2,1,B1_N1,3.3-V LVTTL, +OTG_DATA[10],Bidir,PIN_G1,1,B1_N1,3.3-V LVTTL, +OTG_DATA[9],Bidir,PIN_H4,1,B1_N0,3.3-V LVTTL, +OTG_DATA[8],Bidir,PIN_H3,1,B1_N0,3.3-V LVTTL, +OTG_DATA[7],Bidir,PIN_H6,1,B1_N0,3.3-V LVTTL, +OTG_DATA[6],Bidir,PIN_J7,1,B1_N1,3.3-V LVTTL, +OTG_DATA[5],Bidir,PIN_J3,1,B1_N1,3.3-V LVTTL, +OTG_DATA[4],Bidir,PIN_J4,1,B1_N1,3.3-V LVTTL, +OTG_DATA[3],Bidir,PIN_K3,1,B1_N1,3.3-V LVTTL, +OTG_DATA[2],Bidir,PIN_J5,1,B1_N1,3.3-V LVTTL, +OTG_DATA[1],Bidir,PIN_K4,1,B1_N1,3.3-V LVTTL, +OTG_DATA[0],Bidir,PIN_J6,1,B1_N1,3.3-V LVTTL, +OTG_DREQ[1],Input,PIN_B4,8,B8_N2,3.3-V LVTTL, +OTG_DREQ[0],Input,PIN_J1,1,B1_N2,3.3-V LVTTL, +OTG_FSPEED,Bidir,PIN_C6,8,B8_N2,3.3-V LVTTL, +OTG_INT[1],Input,PIN_D5,8,B8_N2,3.3-V LVTTL, +OTG_INT[0],Input,PIN_A6,8,B8_N1,3.3-V LVTTL, +OTG_LSPEED,Bidir,PIN_B6,8,B8_N1,3.3-V LVTTL, +OTG_RD_N,Output,PIN_B3,8,B8_N2,3.3-V LVTTL, +OTG_RST_N,Output,PIN_C5,8,B8_N2,3.3-V LVTTL, +OTG_WR_N,Output,PIN_A4,8,B8_N2,3.3-V LVTTL, +PS2_CLK,Bidir,PIN_G6,1,B1_N0,3.3-V LVTTL, +PS2_CLK2,Bidir,PIN_G5,1,B1_N0,3.3-V LVTTL, +PS2_DAT,Bidir,PIN_H5,1,B1_N1,3.3-V LVTTL, +PS2_DAT2,Bidir,PIN_F5,1,B1_N0,3.3-V LVTTL, +SD_CLK,Output,PIN_AE13,3,B3_N0,3.3-V LVTTL, +SD_CMD,Bidir,PIN_AD14,3,B3_N0,3.3-V LVTTL, +SD_DAT[3],Bidir,PIN_AC14,3,B3_N0,3.3-V LVTTL, +SD_DAT[2],Bidir,PIN_AB14,3,B3_N0,3.3-V LVTTL, +SD_DAT[1],Bidir,PIN_AF13,3,B3_N0,3.3-V LVTTL, +SD_DAT[0],Bidir,PIN_AE14,3,B3_N0,3.3-V LVTTL, +SD_WP_N,Input,PIN_AF14,3,B3_N0,3.3-V LVTTL, +SMA_CLKIN,Input,PIN_AH14,3,B3_N0,3.3-V LVTTL, +SMA_CLKOUT,Output,PIN_AE23,4,B4_N0,3.3-V LVTTL, +SRAM_ADDR[19],Output,PIN_T8,2,B2_N1,3.3-V LVTTL, +SRAM_ADDR[18],Output,PIN_AB8,3,B3_N2,3.3-V LVTTL, +SRAM_ADDR[17],Output,PIN_AB9,3,B3_N2,3.3-V LVTTL, +SRAM_ADDR[16],Output,PIN_AC11,3,B3_N0,3.3-V LVTTL, +SRAM_ADDR[15],Output,PIN_AB11,3,B3_N1,3.3-V LVTTL, +SRAM_ADDR[14],Output,PIN_AA4,2,B2_N1,3.3-V LVTTL, +SRAM_ADDR[13],Output,PIN_AC3,2,B2_N1,3.3-V LVTTL, +SRAM_ADDR[12],Output,PIN_AB4,2,B2_N2,3.3-V LVTTL, +SRAM_ADDR[11],Output,PIN_AD3,2,B2_N1,3.3-V LVTTL, +SRAM_ADDR[10],Output,PIN_AF2,2,B2_N2,3.3-V LVTTL, +SRAM_ADDR[9],Output,PIN_T7,2,B2_N0,3.3-V LVTTL, +SRAM_ADDR[8],Output,PIN_AF5,3,B3_N2,3.3-V LVTTL, +SRAM_ADDR[7],Output,PIN_AC5,2,B2_N2,3.3-V LVTTL, +SRAM_ADDR[6],Output,PIN_AB5,2,B2_N2,3.3-V LVTTL, +SRAM_ADDR[5],Output,PIN_AE6,3,B3_N2,3.3-V LVTTL, +SRAM_ADDR[4],Output,PIN_AB6,2,B2_N2,3.3-V LVTTL, +SRAM_ADDR[3],Output,PIN_AC7,3,B3_N2,3.3-V LVTTL, +SRAM_ADDR[2],Output,PIN_AE7,3,B3_N1,3.3-V LVTTL, +SRAM_ADDR[1],Output,PIN_AD7,3,B3_N2,3.3-V LVTTL, +SRAM_ADDR[0],Output,PIN_AB7,3,B3_N1,3.3-V LVTTL, +SRAM_CE_N,Output,PIN_AF8,3,B3_N1,3.3-V LVTTL, +SRAM_DQ[15],Bidir,PIN_AG3,3,B3_N2,3.3-V LVTTL, +SRAM_DQ[14],Bidir,PIN_AF3,3,B3_N2,3.3-V LVTTL, +SRAM_DQ[13],Bidir,PIN_AE4,3,B3_N2,3.3-V LVTTL, +SRAM_DQ[12],Bidir,PIN_AE3,2,B2_N2,3.3-V LVTTL, +SRAM_DQ[11],Bidir,PIN_AE1,2,B2_N1,3.3-V LVTTL, +SRAM_DQ[10],Bidir,PIN_AE2,2,B2_N1,3.3-V LVTTL, +SRAM_DQ[9],Bidir,PIN_AD2,2,B2_N1,3.3-V LVTTL, +SRAM_DQ[8],Bidir,PIN_AD1,2,B2_N1,3.3-V LVTTL, +SRAM_DQ[7],Bidir,PIN_AF7,3,B3_N1,3.3-V LVTTL, +SRAM_DQ[6],Bidir,PIN_AH6,3,B3_N2,3.3-V LVTTL, +SRAM_DQ[5],Bidir,PIN_AG6,3,B3_N2,3.3-V LVTTL, +SRAM_DQ[4],Bidir,PIN_AF6,3,B3_N2,3.3-V LVTTL, +SRAM_DQ[3],Bidir,PIN_AH4,3,B3_N2,3.3-V LVTTL, +SRAM_DQ[2],Bidir,PIN_AG4,3,B3_N2,3.3-V LVTTL, +SRAM_DQ[1],Bidir,PIN_AF4,3,B3_N2,3.3-V LVTTL, +SRAM_DQ[0],Bidir,PIN_AH3,3,B3_N2,3.3-V LVTTL, +SRAM_LB_N,Output,PIN_AD4,3,B3_N2,3.3-V LVTTL, +SRAM_OE_N,Output,PIN_AD5,3,B3_N2,3.3-V LVTTL, +SRAM_UB_N,Output,PIN_AC4,2,B2_N2,3.3-V LVTTL, +SRAM_WE_N,Output,PIN_AE8,3,B3_N1,3.3-V LVTTL, +SW[17],Input,PIN_Y23,5,B5_N2,2.5 V, +SW[16],Input,PIN_Y24,5,B5_N2,2.5 V, +SW[15],Input,PIN_AA22,5,B5_N2,2.5 V, +SW[14],Input,PIN_AA23,5,B5_N2,2.5 V, +SW[13],Input,PIN_AA24,5,B5_N2,2.5 V, +SW[12],Input,PIN_AB23,5,B5_N2,2.5 V, +SW[11],Input,PIN_AB24,5,B5_N2,2.5 V, +SW[10],Input,PIN_AC24,5,B5_N2,2.5 V, +SW[9],Input,PIN_AB25,5,B5_N1,2.5 V, +SW[8],Input,PIN_AC25,5,B5_N2,2.5 V, +SW[7],Input,PIN_AB26,5,B5_N1,2.5 V, +SW[6],Input,PIN_AD26,5,B5_N2,2.5 V, +SW[5],Input,PIN_AC26,5,B5_N2,2.5 V, +SW[4],Input,PIN_AB27,5,B5_N1,2.5 V, +SW[3],Input,PIN_AD27,5,B5_N2,2.5 V, +SW[2],Input,PIN_AC27,5,B5_N2,2.5 V, +SW[1],Input,PIN_AC28,5,B5_N2,2.5 V, +SW[0],Input,PIN_AB28,5,B5_N1,2.5 V, +TD_CLK27,Input,PIN_B14,8,B8_N0,3.3-V LVTTL, +TD_DATA[7],Input,PIN_F7,8,B8_N2,3.3-V LVTTL, +TD_DATA[6],Input,PIN_E7,8,B8_N2,3.3-V LVTTL, +TD_DATA[5],Input,PIN_D6,8,B8_N2,3.3-V LVTTL, +TD_DATA[4],Input,PIN_D7,8,B8_N2,3.3-V LVTTL, +TD_DATA[3],Input,PIN_C7,8,B8_N2,3.3-V LVTTL, +TD_DATA[2],Input,PIN_D8,8,B8_N2,3.3-V LVTTL, +TD_DATA[1],Input,PIN_A7,8,B8_N1,3.3-V LVTTL, +TD_DATA[0],Input,PIN_E8,8,B8_N2,3.3-V LVTTL, +TD_HS,Input,PIN_E5,8,B8_N2,3.3-V LVTTL, +TD_RESET_N,Output,PIN_G7,8,B8_N2,3.3-V LVTTL, +TD_VS,Input,PIN_E4,8,B8_N2,3.3-V LVTTL, +UART_CTS,Output,PIN_G14,8,B8_N0,3.3-V LVTTL, +UART_RTS,Input,PIN_J13,8,B8_N0,3.3-V LVTTL, +UART_RXD,Input,PIN_G12,8,B8_N1,3.3-V LVTTL, +UART_TXD,Output,PIN_G9,8,B8_N2,3.3-V LVTTL, +VGA_B[7],Output,PIN_D12,8,B8_N0,3.3-V LVTTL, +VGA_B[6],Output,PIN_D11,8,B8_N1,3.3-V LVTTL, +VGA_B[5],Output,PIN_C12,8,B8_N0,3.3-V LVTTL, +VGA_B[4],Output,PIN_A11,8,B8_N0,3.3-V LVTTL, +VGA_B[3],Output,PIN_B11,8,B8_N0,3.3-V LVTTL, +VGA_B[2],Output,PIN_C11,8,B8_N1,3.3-V LVTTL, +VGA_B[1],Output,PIN_A10,8,B8_N0,3.3-V LVTTL, +VGA_B[0],Output,PIN_B10,8,B8_N0,3.3-V LVTTL, +VGA_BLANK_N,Output,PIN_F11,8,B8_N1,3.3-V LVTTL, +VGA_CLK,Output,PIN_A12,8,B8_N0,3.3-V LVTTL, +VGA_G[7],Output,PIN_C9,8,B8_N1,3.3-V LVTTL, +VGA_G[6],Output,PIN_F10,8,B8_N1,3.3-V LVTTL, +VGA_G[5],Output,PIN_B8,8,B8_N1,3.3-V LVTTL, +VGA_G[4],Output,PIN_C8,8,B8_N1,3.3-V LVTTL, +VGA_G[3],Output,PIN_H12,8,B8_N1,3.3-V LVTTL, +VGA_G[2],Output,PIN_F8,8,B8_N2,3.3-V LVTTL, +VGA_G[1],Output,PIN_G11,8,B8_N1,3.3-V LVTTL, +VGA_G[0],Output,PIN_G8,8,B8_N2,3.3-V LVTTL, +VGA_HS,Output,PIN_G13,8,B8_N0,3.3-V LVTTL, +VGA_R[7],Output,PIN_H10,8,B8_N1,3.3-V LVTTL, +VGA_R[6],Output,PIN_H8,8,B8_N2,3.3-V LVTTL, +VGA_R[5],Output,PIN_J12,8,B8_N0,3.3-V LVTTL, +VGA_R[4],Output,PIN_G10,8,B8_N1,3.3-V LVTTL, +VGA_R[3],Output,PIN_F12,8,B8_N1,3.3-V LVTTL, +VGA_R[2],Output,PIN_D10,8,B8_N1,3.3-V LVTTL, +VGA_R[1],Output,PIN_E11,8,B8_N1,3.3-V LVTTL, +VGA_R[0],Output,PIN_E12,8,B8_N1,3.3-V LVTTL, +VGA_SYNC_N,Output,PIN_C10,8,B8_N0,3.3-V LVTTL, +VGA_VS,Output,PIN_C13,8,B8_N0,3.3-V LVTTL, +HSMC_CLKIN_N1,Unknown,PIN_J28,6,B6_N2,LVDS, +HSMC_CLKIN_N2,Unknown,PIN_Y28,5,B5_N0,LVDS, +HSMC_TX_D_N[0],Unknown,PIN_D28,6,B6_N0,LVDS, +HSMC_RX_D_N[0],Unknown,PIN_F25,6,B6_N0,LVDS, +HSMC_RX_D_N[1],Unknown,PIN_C27,6,B6_N0,LVDS, +HSMC_TX_D_N[1],Unknown,PIN_E28,6,B6_N1,LVDS, +HSMC_TX_D_N[2],Unknown,PIN_F28,6,B6_N1,LVDS, +HSMC_RX_D_N[2],Unknown,PIN_E26,6,B6_N1,LVDS, +HSMC_TX_D_N[3],Unknown,PIN_G28,6,B6_N1,LVDS, +HSMC_RX_D_N[3],Unknown,PIN_G26,6,B6_N0,LVDS, +HSMC_TX_D_N[4],Unknown,PIN_K28,6,B6_N1,LVDS, +HSMC_RX_D_N[4],Unknown,PIN_H26,6,B6_N1,LVDS, +HSMC_TX_D_N[5],Unknown,PIN_M28,6,B6_N2,LVDS, +HSMC_RX_D_N[5],Unknown,PIN_K26,6,B6_N1,LVDS, +HSMC_TX_D_N[6],Unknown,PIN_K22,6,B6_N0,LVDS, +HSMC_RX_D_N[6],Unknown,PIN_L24,6,B6_N2,LVDS, +HSMC_TX_D_N[7],Unknown,PIN_H24,6,B6_N0,LVDS, +HSMC_RX_D_N[7],Unknown,PIN_M26,6,B6_N2,LVDS, +HSMC_TX_D_N[8],Unknown,PIN_J24,6,B6_N0,LVDS, +HSMC_RX_D_N[8],Unknown,PIN_R26,5,B5_N0,LVDS, +HSMC_TX_D_N[9],Unknown,PIN_P28,6,B6_N2,LVDS, +HSMC_RX_D_N[9],Unknown,PIN_T26,5,B5_N0,LVDS, +HSMC_TX_D_N[10],Unknown,PIN_J26,6,B6_N1,LVDS, +HSMC_RX_D_N[10],Unknown,PIN_U26,5,B5_N0,LVDS, +HSMC_TX_D_N[11],Unknown,PIN_L28,6,B6_N2,LVDS, +HSMC_RX_D_N[11],Unknown,PIN_L22,6,B6_N0,LVDS, +HSMC_TX_D_N[12],Unknown,PIN_V26,5,B5_N1,LVDS, +HSMC_RX_D_N[12],Unknown,PIN_N26,6,B6_N2,LVDS, +HSMC_TX_D_N[13],Unknown,PIN_R28,5,B5_N0,LVDS, +HSMC_RX_D_N[13],Unknown,PIN_P26,6,B6_N2,LVDS, +HSMC_TX_D_N[14],Unknown,PIN_U28,5,B5_N0,LVDS, +HSMC_RX_D_N[14],Unknown,PIN_R21,5,B5_N0,LVDS, +HSMC_TX_D_N[15],Unknown,PIN_V28,5,B5_N1,LVDS, +HSMC_RX_D_N[15],Unknown,PIN_R23,5,B5_N0,LVDS, +HSMC_TX_D_N[16],Unknown,PIN_V22,5,B5_N1,LVDS, +HSMC_RX_D_N[16],Unknown,PIN_T22,5,B5_N0,LVDS, +HSMC_CLKOUT_N2,Unknown,PIN_V24,5,B5_N1,LVDS, +HSMC_CLKOUT_N1,Unknown,PIN_G24,6,B6_N0,LVDS, +,Unknown,PIN_J9,,,, +,Unknown,PIN_H9,,,, +,Unknown,PIN_J8,,,, +,Unknown,PIN_F4,1,B1_N0,, +,Unknown,PIN_E2,1,B1_N0,, +,Unknown,PIN_M6,1,B1_N1,, +,Unknown,PIN_P3,1,B1_N2,, +,Unknown,PIN_N7,1,B1_N2,, +,Unknown,PIN_P4,1,B1_N2,, +,Unknown,PIN_P7,,,, +,Unknown,PIN_P5,,,, +,Unknown,PIN_P8,1,B1_N2,, +,Unknown,PIN_P6,1,B1_N2,, +,Unknown,PIN_R8,1,B1_N2,, +,Unknown,PIN_Y8,,,, +,Unknown,PIN_AA9,,,, +,Unknown,PIN_Y9,,,, +,Unknown,PIN_Y20,,,, +,Unknown,PIN_AA20,,,, +,Unknown,PIN_Y21,,,, +,Unknown,PIN_P24,,,, +,Unknown,PIN_N22,,,, +,Unknown,PIN_P23,,,, +,Unknown,PIN_M22,,,, +,Unknown,PIN_P22,,,, +,Unknown,PIN_J21,,,, +,Unknown,PIN_H20,,,, +,Unknown,PIN_J20,,,, +,Unknown,PIN_K9,,,, +,Unknown,PIN_K11,,,, +,Unknown,PIN_K13,,,, +,Unknown,PIN_K15,,,, +,Unknown,PIN_K17,,,, +,Unknown,PIN_K19,,,, +,Unknown,PIN_L10,,,, +,Unknown,PIN_L12,,,, +,Unknown,PIN_L14,,,, +,Unknown,PIN_L16,,,, +,Unknown,PIN_L18,,,, +,Unknown,PIN_L20,,,, +,Unknown,PIN_M9,,,, +,Unknown,PIN_M11,,,, +,Unknown,PIN_M13,,,, +,Unknown,PIN_M15,,,, +,Unknown,PIN_M17,,,, +,Unknown,PIN_M19,,,, +,Unknown,PIN_N10,,,, +,Unknown,PIN_N12,,,, +,Unknown,PIN_N14,,,, +,Unknown,PIN_N16,,,, +,Unknown,PIN_N18,,,, +,Unknown,PIN_N20,,,, +,Unknown,PIN_P9,,,, +,Unknown,PIN_P11,,,, +,Unknown,PIN_P13,,,, +,Unknown,PIN_P15,,,, +,Unknown,PIN_P17,,,, +,Unknown,PIN_P19,,,, +,Unknown,PIN_R10,,,, +,Unknown,PIN_R12,,,, +,Unknown,PIN_R14,,,, +,Unknown,PIN_R16,,,, +,Unknown,PIN_R18,,,, +,Unknown,PIN_R20,,,, +,Unknown,PIN_T9,,,, +,Unknown,PIN_T11,,,, +,Unknown,PIN_T13,,,, +,Unknown,PIN_T15,,,, +,Unknown,PIN_T17,,,, +,Unknown,PIN_T19,,,, +,Unknown,PIN_U10,,,, +,Unknown,PIN_U12,,,, +,Unknown,PIN_U14,,,, +,Unknown,PIN_U16,,,, +,Unknown,PIN_U18,,,, +,Unknown,PIN_U20,,,, +,Unknown,PIN_V9,,,, +,Unknown,PIN_V11,,,, +,Unknown,PIN_V13,,,, +,Unknown,PIN_V15,,,, +,Unknown,PIN_V17,,,, +,Unknown,PIN_V19,,,, +,Unknown,PIN_W10,,,, +,Unknown,PIN_W12,,,, +,Unknown,PIN_W14,,,, +,Unknown,PIN_W16,,,, +,Unknown,PIN_W18,,,, +,Unknown,PIN_W20,,,, +,Unknown,PIN_B1,,,, +,Unknown,PIN_H1,1,,, +,Unknown,PIN_K5,,,, +,Unknown,PIN_N1,1,,, +,Unknown,PIN_N5,,,, +,Unknown,PIN_AA1,2,,, +,Unknown,PIN_AG1,2,,, +,Unknown,PIN_T1,2,,, +,Unknown,PIN_T5,2,,, +,Unknown,PIN_W5,2,,, +,Unknown,PIN_AA11,3,,, +,Unknown,PIN_AD6,3,,, +,Unknown,PIN_AD9,3,,, +,Unknown,PIN_AD13,3,,, +,Unknown,PIN_AH2,3,,, +,Unknown,PIN_AH5,3,,, +,Unknown,PIN_AH9,3,,, +,Unknown,PIN_AH13,3,,, +,Unknown,PIN_AA18,4,,, +,Unknown,PIN_AD16,4,,, +,Unknown,PIN_AD20,4,,, +,Unknown,PIN_AD23,4,,, +,Unknown,PIN_AH16,4,,, +,Unknown,PIN_AH20,4,,, +,Unknown,PIN_AH24,4,,, +,Unknown,PIN_AH27,4,,, +,Unknown,PIN_AA28,5,,, +,Unknown,PIN_AG28,5,,, +,Unknown,PIN_T24,5,,, +,Unknown,PIN_T28,5,,, +,Unknown,PIN_W24,5,,, +,Unknown,PIN_B28,6,,, +,Unknown,PIN_H28,6,,, +,Unknown,PIN_K24,6,,, +,Unknown,PIN_N24,6,,, +,Unknown,PIN_N28,,,, +,Unknown,PIN_A16,7,,, +,Unknown,PIN_A20,7,,, +,Unknown,PIN_A24,,,, +,Unknown,PIN_A27,7,,, +,Unknown,PIN_E16,7,,, +,Unknown,PIN_E20,7,,, +,Unknown,PIN_E23,7,,, +,Unknown,PIN_H18,7,,, +,Unknown,PIN_A2,8,,, +,Unknown,PIN_A5,8,,, +,Unknown,PIN_A9,8,,, +,Unknown,PIN_A13,8,,, +,Unknown,PIN_E6,8,,, +,Unknown,PIN_E9,8,,, +,Unknown,PIN_E13,8,,, +,Unknown,PIN_H11,8,,, +,Unknown,PIN_K10,,,, +,Unknown,PIN_K12,,,, +,Unknown,PIN_K14,,,, +,Unknown,PIN_K16,,,, +,Unknown,PIN_K18,,,, +,Unknown,PIN_K20,,,, +,Unknown,PIN_L9,,,, +,Unknown,PIN_L11,,,, +,Unknown,PIN_L13,,,, +,Unknown,PIN_L15,,,, +,Unknown,PIN_L17,,,, +,Unknown,PIN_L19,,,, +,Unknown,PIN_M10,,,, +,Unknown,PIN_M12,,,, +,Unknown,PIN_M14,,,, +,Unknown,PIN_M16,,,, +,Unknown,PIN_M18,,,, +,Unknown,PIN_M20,,,, +,Unknown,PIN_N9,,,, +,Unknown,PIN_N11,,,, +,Unknown,PIN_N13,,,, +,Unknown,PIN_N15,,,, +,Unknown,PIN_N17,,,, +,Unknown,PIN_N19,,,, +,Unknown,PIN_P10,,,, +,Unknown,PIN_P12,,,, +,Unknown,PIN_P14,,,, +,Unknown,PIN_P16,,,, +,Unknown,PIN_P18,,,, +,Unknown,PIN_P20,,,, +,Unknown,PIN_R9,,,, +,Unknown,PIN_R11,,,, +,Unknown,PIN_R13,,,, +,Unknown,PIN_R15,,,, +,Unknown,PIN_R17,,,, +,Unknown,PIN_R19,,,, +,Unknown,PIN_T10,,,, +,Unknown,PIN_T12,,,, +,Unknown,PIN_T14,,,, +,Unknown,PIN_T16,,,, +,Unknown,PIN_T18,,,, +,Unknown,PIN_T20,,,, +,Unknown,PIN_U9,,,, +,Unknown,PIN_U11,,,, +,Unknown,PIN_U13,,,, +,Unknown,PIN_U15,,,, +,Unknown,PIN_U17,,,, +,Unknown,PIN_U19,,,, +,Unknown,PIN_V10,,,, +,Unknown,PIN_V12,,,, +,Unknown,PIN_V14,,,, +,Unknown,PIN_V16,,,, +,Unknown,PIN_V18,,,, +,Unknown,PIN_V20,,,, +,Unknown,PIN_W9,,,, +,Unknown,PIN_W11,,,, +,Unknown,PIN_W13,,,, +,Unknown,PIN_W15,,,, +,Unknown,PIN_W17,,,, +,Unknown,PIN_W19,,,, +,Unknown,PIN_AA2,,,, +,Unknown,PIN_AA27,,,, +,Unknown,PIN_AC6,,,, +,Unknown,PIN_AC9,,,, +,Unknown,PIN_AC13,,,, +,Unknown,PIN_AC16,,,, +,Unknown,PIN_AC20,,,, +,Unknown,PIN_AC23,,,, +,Unknown,PIN_AF1,,,, +,Unknown,PIN_AF28,,,, +,Unknown,PIN_AG2,,,, +,Unknown,PIN_AG5,,,, +,Unknown,PIN_AG9,,,, +,Unknown,PIN_AG13,,,, +,Unknown,PIN_AG16,,,, +,Unknown,PIN_AG20,,,, +,Unknown,PIN_AG24,,,, +,Unknown,PIN_AG27,,,, +,Unknown,PIN_B2,,,, +,Unknown,PIN_B5,,,, +,Unknown,PIN_B9,,,, +,Unknown,PIN_B13,,,, +,Unknown,PIN_B16,,,, +,Unknown,PIN_B20,,,, +,Unknown,PIN_B24,,,, +,Unknown,PIN_B27,,,, +,Unknown,PIN_C1,,,, +,Unknown,PIN_C28,,,, +,Unknown,PIN_F6,,,, +,Unknown,PIN_F9,,,, +,Unknown,PIN_F13,,,, +,Unknown,PIN_F16,,,, +,Unknown,PIN_F20,,,, +,Unknown,PIN_F23,,,, +,Unknown,PIN_H2,,,, +,Unknown,PIN_H27,,,, +,Unknown,PIN_J11,,,, +,Unknown,PIN_J18,,,, +,Unknown,PIN_K6,,,, +,Unknown,PIN_K23,,,, +,Unknown,PIN_N2,,,, +,Unknown,PIN_N6,,,, +,Unknown,PIN_N23,,,, +,Unknown,PIN_N27,,,, +,Unknown,PIN_T2,,,, +,Unknown,PIN_T6,,,, +,Unknown,PIN_T23,,,, +,Unknown,PIN_T27,,,, +,Unknown,PIN_W6,,,, +,Unknown,PIN_W23,,,, +,Unknown,PIN_Y11,,,, +,Unknown,PIN_Y18,,,, +,Unknown,PIN_J2,,,, +,Unknown,PIN_D3,,,, +,Unknown,PIN_B12,,,,
lib/boards/DE2_115/DE2_115.csv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: lib/boards/DE2_115/De2_115.qsf =================================================================== --- lib/boards/DE2_115/De2_115.qsf (nonexistent) +++ lib/boards/DE2_115/De2_115.qsf (revision 34) @@ -0,0 +1,546 @@ + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 780 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_location_assignment PIN_Y2 -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_location_assignment PIN_E21 -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_location_assignment PIN_G19 -to LEDR[0] +set_location_assignment PIN_E19 -to LEDR[2] +set_location_assignment PIN_F19 -to LEDR[1] +set_location_assignment PIN_F21 -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_location_assignment PIN_M23 -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_location_assignment PIN_AB28 -to SW[0] +set_location_assignment PIN_AC28 -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_location_assignment PIN_AB26 -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_location_assignment PIN_G18 -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_location_assignment PIN_E17 -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_location_assignment PIN_M24 -to HEX1[0] +set_location_assignment PIN_Y22 -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_location_assignment PIN_AA25 -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_location_assignment PIN_W27 -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_location_assignment PIN_V21 -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_location_assignment PIN_AB19 -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_location_assignment PIN_AG17 -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_location_assignment PIN_L6 -to LCD_BLON +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_location_assignment PIN_L4 -to LCD_EN +set_location_assignment PIN_M1 -to LCD_RW +set_location_assignment PIN_M2 -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_location_assignment PIN_G9 -to UART_TXD +set_location_assignment PIN_G12 -to UART_RXD +set_location_assignment PIN_G14 -to UART_CTS +set_location_assignment PIN_J13 -to UART_RTS +set_location_assignment PIN_G6 -to PS2_KBCLK +set_location_assignment PIN_H5 -to PS2_KBDAT +set_location_assignment PIN_G5 -to PS2_MSCLK +set_location_assignment PIN_F5 -to PS2_MSDAT +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_location_assignment PIN_AE13 -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_location_assignment PIN_AF14 -to SD_WP_N +set_location_assignment PIN_D12 -to VGA_B[7] +set_location_assignment PIN_D11 -to VGA_B[6] +set_location_assignment PIN_C12 -to VGA_B[5] +set_location_assignment PIN_A11 -to VGA_B[4] +set_location_assignment PIN_B11 -to VGA_B[3] +set_location_assignment PIN_C11 -to VGA_B[2] +set_location_assignment PIN_A10 -to VGA_B[1] +set_location_assignment PIN_B10 -to VGA_B[0] +set_location_assignment PIN_C9 -to VGA_G[7] +set_location_assignment PIN_F10 -to VGA_G[6] +set_location_assignment PIN_B8 -to VGA_G[5] +set_location_assignment PIN_C8 -to VGA_G[4] +set_location_assignment PIN_H12 -to VGA_G[3] +set_location_assignment PIN_F8 -to VGA_G[2] +set_location_assignment PIN_G11 -to VGA_G[1] +set_location_assignment PIN_G8 -to VGA_G[0] +set_location_assignment PIN_H10 -to VGA_R[7] +set_location_assignment PIN_H8 -to VGA_R[6] +set_location_assignment PIN_J12 -to VGA_R[5] +set_location_assignment PIN_G10 -to VGA_R[4] +set_location_assignment PIN_F12 -to VGA_R[3] +set_location_assignment PIN_D10 -to VGA_R[2] +set_location_assignment PIN_E11 -to VGA_R[1] +set_location_assignment PIN_E12 -to VGA_R[0] +set_location_assignment PIN_A12 -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_G13 -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_location_assignment PIN_D1 -to AUD_DACDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_location_assignment PIN_E1 -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_location_assignment PIN_B7 -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_location_assignment PIN_A21 -to ENET0_INT_N +set_location_assignment PIN_C20 -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_location_assignment PIN_C19 -to ENET0_RESET_N +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_location_assignment PIN_D24 -to ENET1_INT_N +set_location_assignment PIN_D23 -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_location_assignment PIN_D22 -to ENET1_RESET_N +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_location_assignment PIN_A14 -to ENETCLK_25 +set_location_assignment PIN_F7 -to TD_DATA[7] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_location_assignment PIN_E8 -to TD_DATA[0] +set_location_assignment PIN_B14 -to TD_CLK27 +set_location_assignment PIN_G7 -to TD_RESET_N +set_location_assignment PIN_E4 -to TD_VS +set_location_assignment PIN_E5 -to TD_HS +set_location_assignment PIN_D4 -to OTG_DACK_N[1] +set_location_assignment PIN_C4 -to OTG_DACK_N[0] +set_location_assignment PIN_A3 -to OTG_CS_N +set_location_assignment PIN_B3 -to OTG_OE_N +set_location_assignment PIN_B4 -to OTG_DREQ[1] +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_location_assignment PIN_A4 -to OTG_WE_N +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_location_assignment PIN_C6 -to OTG_FSPEED +set_location_assignment PIN_B6 -to OTG_LSPEED +set_location_assignment PIN_D5 -to OTG_INT[1] +set_location_assignment PIN_A6 -to OTG_INT[0] +set_location_assignment PIN_C5 -to OTG_RST_N +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_location_assignment PIN_Y15 -to IRDA_RXD +set_location_assignment PIN_AE5 -to DRAM_CLK +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_location_assignment PIN_V6 -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_location_assignment PIN_AG7 -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_location_assignment PIN_AC10 -to FL_WE_N +set_location_assignment PIN_AE11 -to FL_RESET_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_location_assignment PIN_Y1 -to FL_RY +set_location_assignment PIN_AB22 -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_location_assignment PIN_AD15 -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_location_assignment PIN_AC19 -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_location_assignment PIN_AH23 -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_location_assignment PIN_J10 -to EXT_IO[0] +set_location_assignment PIN_J14 -to EXT_IO[1] +set_location_assignment PIN_H13 -to EXT_IO[2] +set_location_assignment PIN_H14 -to EXT_IO[3] +set_location_assignment PIN_F14 -to EXT_IO[4] +set_location_assignment PIN_E10 -to EXT_IO[5] +set_location_assignment PIN_D9 -to EXT_IO[6] + + Index: lib/boards/Readme =================================================================== --- lib/boards/Readme (nonexistent) +++ lib/boards/Readme (revision 34) @@ -0,0 +1,14 @@ +For adding any Altera FPGA board follow these instructions: + 1- Search for your board qsf file (e.g "FPGA_Board_Name.qsf"). This file must contain the FPGA device name with other necessary global project setting including the pin assignments. + + 2- Make sure the Qsf file does not contain following assignments: + 1- "set_global_assignment -name TOP_LEVEL_ENTITY ..." : This line defines the top level module name and will be added by GUI interface + 2- "set_global_assignment -name VERILOG_FILE" or set_global_assignment -name SYSTEMVERILOG_FILE" : These assignments are used for adding source file to the project. The source file will be added by GUI automatically. + + 3- Make a new project in Quartus. + 4- Open new Project directory and replace the content of project.qsf file with the content of your FPGA board qsf file. + 5- In Quartus open file menu select open project. Then reopen the same project again to update the new qsf file setting. + 6- Now in Assignment menu open pin planner + 7- In pin planner go to file and select Export. Then save the pin assignment csv file. + 8- In ./lib/board make a folder with the name of your FPGA board. (make sure the name does not contain any space) + 9- In the newly created folder copy both qsf and csv files. Index: lib/ip/Bus/wishbone_bus.IP =================================================================== --- lib/ip/Bus/wishbone_bus.IP (revision 33) +++ lib/ip/Bus/wishbone_bus.IP (revision 34) @@ -3,7 +3,7 @@ ## ## Copyright (C) 2014-2016 Alireza Monemi ## -## This file is part of ProNoC 1.5.0 +## This file is part of ProNoC 1.6.0 ## ## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ## MAY CAUSE UNEXPECTED BEHAIVOR. @@ -10,105 +10,17 @@ ################################################################################ $wishbone_bus = bless( { - 'hdl_files' => [ - '/mpsoc/src_peripheral/bus/wishbone_bus.v', - '/mpsoc/src_noc/main_comp.v', - '/mpsoc/src_noc/arbiter.v' - ], - 'ip_name' => 'wishbone_bus', 'description' => 'wishbone bus', - 'gui_status' => { - 'status' => 'ideal', - 'timeout' => 0 - }, - 'parameters' => { - 'S' => { - 'info' => 'Number of wishbone slave interface', - 'deafult' => '4', - 'global_param' => 'Localparam', - 'content' => '1,256,1', - 'type' => 'Spin-button', - 'redefine_param' => 1 - }, - 'SELw' => { - 'info' => undef, - 'deafult' => 'Dw/8', - 'global_param' => 'Localparam', - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - }, - 'Dw' => { - 'info' => 'The wishbone Bus data width in bits.', - 'deafult' => '32', - 'global_param' => 'Localparam', - 'content' => '8,512,8', - 'type' => 'Spin-button', - 'redefine_param' => 1 - }, - 'BTEw' => { - 'info' => undef, - 'deafult' => '2 ', - 'global_param' => 'Localparam', - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - }, - 'M' => { - 'info' => 'Number of wishbone master interface', - 'deafult' => ' 4', - 'global_param' => 'Localparam', - 'content' => '1,256,1', - 'type' => 'Spin-button', - 'redefine_param' => 1 - }, - 'Aw' => { - 'info' => 'The wishbone Bus address width', - 'deafult' => '32', - 'global_param' => 'Localparam', - 'content' => '4,128,1', - 'type' => 'Spin-button', - 'redefine_param' => 1 - }, - 'TAGw' => { - 'info' => undef, - 'deafult' => '3', - 'global_param' => 'Localparam', - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - }, - 'CTIw' => { - 'info' => undef, - 'deafult' => '3', - 'global_param' => 'Localparam', - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - } - }, - 'modules' => { - 'wishbone_bus' => {}, - 'bus_arbiter' => {} - }, - 'plugs' => { - 'clk' => { - 'clk' => {}, - 'value' => 1, - '0' => { - 'name' => 'clk' - }, - 'type' => 'num' - }, - 'reset' => { - 'reset' => {}, - 'value' => 1, - '0' => { - 'name' => 'reset' - }, - 'type' => 'num' - } - }, + 'parameters_order' => [ + 'M', + 'S', + 'Dw', + 'Aw', + 'SELw', + 'TAGw', + 'CTIw', + 'BTEw' + ], 'ports_order' => [ 's_adr_o_all', 's_dat_o_all', @@ -141,229 +53,318 @@ 'clk', 'reset' ], - 'parameters_order' => [ - 'M', - 'S', - 'Dw', - 'Aw', - 'SELw', - 'TAGw', - 'CTIw', - 'BTEw' - ], + 'plugs' => { + 'clk' => { + 'clk' => {}, + '0' => { + 'name' => 'clk' + }, + 'type' => 'num', + 'value' => 1 + }, + 'reset' => { + 'value' => 1, + '0' => { + 'name' => 'reset' + }, + 'reset' => {}, + 'type' => 'num' + } + }, + 'unused' => undef, + 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/bus/wishbone_bus.v', + 'modules' => { + 'bus_arbiter' => {}, + 'wishbone_bus' => {} + }, + 'ip_name' => 'wishbone_bus', + 'category' => 'Bus', + 'version' => 0, + 'module_name' => 'wishbone_bus', + 'sockets' => { + 'wb_addr_map' => { + 'connection_num' => 'single connection', + 'value' => 1, + 'type' => 'num', + 'wb_addr_map' => {}, + '0' => { + 'name' => 'wb_addr_map' + } + }, + 'wb_slave' => { + 'connection_num' => 'single connection', + 'value' => 'S', + 'type' => 'param', + 'wb_slave' => {}, + '0' => { + 'name' => 'wb_slave' + } + }, + 'wb_master' => { + 'connection_num' => 'single connection', + 'value' => 'M', + 'wb_master' => {}, + 'type' => 'param', + '0' => { + 'name' => 'wb_master' + } + } + }, + 'parameters' => { + 'Aw' => { + 'global_param' => 'Localparam', + 'redefine_param' => 1, + 'content' => '4,128,1', + 'info' => 'The wishbone Bus address width', + 'type' => 'Spin-button', + 'deafult' => '32' + }, + 'M' => { + 'global_param' => 'Localparam', + 'content' => '1,256,1', + 'redefine_param' => 1, + 'type' => 'Spin-button', + 'info' => 'Number of wishbone master interface', + 'deafult' => ' 4' + }, + 'TAGw' => { + 'deafult' => '3', + 'type' => 'Fixed', + 'info' => undef, + 'redefine_param' => 1, + 'content' => '', + 'global_param' => 'Localparam' + }, + 'BTEw' => { + 'global_param' => 'Localparam', + 'content' => '', + 'redefine_param' => 1, + 'type' => 'Fixed', + 'info' => undef, + 'deafult' => '2 ' + }, + 'S' => { + 'content' => '1,256,1', + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'deafult' => '4', + 'info' => 'Number of wishbone slave interface', + 'type' => 'Spin-button' + }, + 'Dw' => { + 'content' => '8,512,8', + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'deafult' => '32', + 'type' => 'Spin-button', + 'info' => 'The wishbone Bus data width in bits.' + }, + 'CTIw' => { + 'type' => 'Fixed', + 'info' => undef, + 'deafult' => '3', + 'global_param' => 'Localparam', + 'content' => '', + 'redefine_param' => 1 + }, + 'SELw' => { + 'global_param' => 'Localparam', + 'redefine_param' => 1, + 'content' => '', + 'type' => 'Fixed', + 'info' => undef, + 'deafult' => 'Dw/8' + } + }, + 'hdl_files' => [ + '/mpsoc/src_peripheral/bus/wishbone_bus.v', + '/mpsoc/src_noc/main_comp.v', + '/mpsoc/src_noc/arbiter.v' + ], + 'gui_status' => { + 'timeout' => 0, + 'status' => 'ideal' + }, 'ports' => { - 's_sel_o_all' => { - 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'sel_o', - 'range' => 'SELw*S-1 : 0', - 'type' => 'output' + 's_sel_one_hot' => { + 'type' => 'input', + 'range' => 'S-1 : 0', + 'intfc_name' => 'socket:wb_addr_map[0]', + 'intfc_port' => 'sel_one_hot' + }, + 'reset' => { + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:reset[0]', + 'intfc_port' => 'reset_i' + }, + 'm_cti_i_all' => { + 'type' => 'input', + 'range' => 'CTIw*M-1 : 0', + 'intfc_name' => 'socket:wb_master[array]', + 'intfc_port' => 'cti_i' }, - 's_adr_o_all' => { + 's_dat_i_all' => { 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'adr_o', - 'range' => 'Aw*S-1 : 0', - 'type' => 'output' + 'intfc_port' => 'dat_i', + 'type' => 'input', + 'range' => 'Dw*S-1 : 0' }, - 's_dat_o_all' => { - 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'dat_o', - 'range' => 'Dw*S-1 : 0', - 'type' => 'output' - }, - 'm_cyc_i_all' => { + 'm_ack_o_all' => { + 'intfc_port' => 'ack_o', 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'cyc_i', 'range' => 'M-1 : 0', - 'type' => 'input' - }, - 'm_grant_addr' => { - 'intfc_name' => 'socket:wb_addr_map[0]', - 'intfc_port' => 'grant_addr', - 'range' => 'Aw-1 : 0', - 'type' => 'output' - }, - 's_bte_o_all' => { - 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'bte_o', - 'range' => 'BTEw*S-1 : 0', 'type' => 'output' }, 's_ack_i_all' => { - 'intfc_name' => 'socket:wb_slave[array]', + 'range' => 'S-1 : 0', + 'type' => 'input', 'intfc_port' => 'ack_i', - 'range' => 'S-1 : 0', - 'type' => 'input' + 'intfc_name' => 'socket:wb_slave[array]' }, - 's_cti_o_all' => { + 'clk' => { + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:clk[0]', + 'intfc_port' => 'clk_i' + }, + 's_cyc_o_all' => { + 'intfc_port' => 'cyc_o', 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'cti_o', - 'range' => 'CTIw*S-1 : 0', + 'range' => 'S-1 : 0', 'type' => 'output' }, - 's_tag_o_all' => { - 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'tag_o', - 'range' => 'TAGw*S-1 : 0', - 'type' => 'output' + 'm_stb_i_all' => { + 'type' => 'input', + 'range' => 'M-1 : 0', + 'intfc_name' => 'socket:wb_master[array]', + 'intfc_port' => 'stb_i' }, - 's_err_i_all' => { + 'm_dat_i_all' => { + 'range' => 'Dw*M-1 : 0', + 'type' => 'input', + 'intfc_port' => 'dat_i', + 'intfc_name' => 'socket:wb_master[array]' + }, + 's_sel_o_all' => { + 'range' => 'SELw*S-1 : 0', + 'type' => 'output', + 'intfc_port' => 'sel_o', + 'intfc_name' => 'socket:wb_slave[array]' + }, + 's_adr_o_all' => { 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'err_i', - 'range' => 'S-1 : 0', - 'type' => 'input' + 'intfc_port' => 'adr_o', + 'type' => 'output', + 'range' => 'Aw*S-1 : 0' }, - 'm_stb_i_all' => { - 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'stb_i', - 'range' => 'M-1 : 0', - 'type' => 'input' + 'm_sel_i_all' => { + 'range' => 'SELw*M-1 : 0', + 'type' => 'input', + 'intfc_port' => 'sel_i', + 'intfc_name' => 'socket:wb_master[array]' }, - 'm_ack_o_all' => { + 'm_adr_i_all' => { + 'type' => 'input', + 'range' => 'Aw*M-1 : 0', 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'ack_o', - 'range' => 'M-1 : 0', - 'type' => 'output' + 'intfc_port' => 'adr_i' }, - 'reset' => { - 'intfc_name' => 'plug:reset[0]', - 'intfc_port' => 'reset_i', - 'range' => '', - 'type' => 'input' - }, - 's_cyc_o_all' => { + 's_tag_o_all' => { + 'range' => 'TAGw*S-1 : 0', + 'type' => 'output', + 'intfc_port' => 'tag_o', + 'intfc_name' => 'socket:wb_slave[array]' + }, + 's_cti_o_all' => { + 'type' => 'output', + 'range' => 'CTIw*S-1 : 0', 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'cyc_o', - 'range' => 'S-1 : 0', - 'type' => 'output' + 'intfc_port' => 'cti_o' }, - 'm_adr_i_all' => { + 'm_bte_i_all' => { + 'intfc_port' => 'bte_i', 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'adr_i', - 'range' => 'Aw*M-1 : 0', + 'range' => 'BTEw*M-1 : 0', 'type' => 'input' }, - 'm_rty_o_all' => { - 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'rty_o', - 'range' => 'M-1 : 0', - 'type' => 'output' - }, 'm_dat_o_all' => { 'intfc_name' => 'socket:wb_master[array]', 'intfc_port' => 'dat_o', - 'range' => 'Dw*M-1 : 0', - 'type' => 'output' + 'type' => 'output', + 'range' => 'Dw*M-1 : 0' }, + 's_err_i_all' => { + 'type' => 'input', + 'range' => 'S-1 : 0', + 'intfc_name' => 'socket:wb_slave[array]', + 'intfc_port' => 'err_i' + }, 's_we_o_all' => { - 'intfc_name' => 'socket:wb_slave[array]', + 'range' => 'S-1 : 0', + 'type' => 'output', 'intfc_port' => 'we_o', - 'range' => 'S-1 : 0', - 'type' => 'output' + 'intfc_name' => 'socket:wb_slave[array]' }, - 'm_dat_i_all' => { + 'm_tag_i_all' => { 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'dat_i', - 'range' => 'Dw*M-1 : 0', - 'type' => 'input' + 'intfc_port' => 'tag_i', + 'type' => 'input', + 'range' => 'TAGw*M-1 : 0' }, - 'm_bte_i_all' => { + 'm_rty_o_all' => { + 'intfc_port' => 'rty_o', 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'bte_i', - 'range' => 'BTEw*M-1 : 0', - 'type' => 'input' + 'range' => 'M-1 : 0', + 'type' => 'output' }, - 'm_err_o_all' => { + 'm_cyc_i_all' => { + 'intfc_port' => 'cyc_i', 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'err_o', 'range' => 'M-1 : 0', - 'type' => 'output' - }, - 's_rty_i_all' => { - 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'rty_i', - 'range' => 'S-1 : 0', 'type' => 'input' }, + 'm_grant_addr' => { + 'type' => 'output', + 'range' => 'Aw-1 : 0', + 'intfc_name' => 'socket:wb_addr_map[0]', + 'intfc_port' => 'grant_addr' + }, 's_stb_o_all' => { + 'type' => 'output', + 'range' => 'S-1 : 0', 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'stb_o', + 'intfc_port' => 'stb_o' + }, + 's_rty_i_all' => { + 'type' => 'input', 'range' => 'S-1 : 0', - 'type' => 'output' - }, - 'm_tag_i_all' => { - 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'tag_i', - 'range' => 'TAGw*M-1 : 0', - 'type' => 'input' - }, - 's_dat_i_all' => { 'intfc_name' => 'socket:wb_slave[array]', - 'intfc_port' => 'dat_i', - 'range' => 'Dw*S-1 : 0', - 'type' => 'input' + 'intfc_port' => 'rty_i' }, - 'm_sel_i_all' => { - 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'sel_i', - 'range' => 'SELw*M-1 : 0', - 'type' => 'input' - }, - 'clk' => { - 'intfc_name' => 'plug:clk[0]', - 'intfc_port' => 'clk_i', - 'range' => '', - 'type' => 'input' - }, - 'm_cti_i_all' => { - 'intfc_name' => 'socket:wb_master[array]', - 'intfc_port' => 'cti_i', - 'range' => 'CTIw*M-1 : 0', - 'type' => 'input' - }, 'm_we_i_all' => { 'intfc_name' => 'socket:wb_master[array]', 'intfc_port' => 'we_i', - 'range' => 'M-1 : 0', - 'type' => 'input' + 'type' => 'input', + 'range' => 'M-1 : 0' }, - 's_sel_one_hot' => { - 'intfc_name' => 'socket:wb_addr_map[0]', - 'intfc_port' => 'sel_one_hot', - 'range' => 'S-1 : 0', - 'type' => 'input' - } - }, - 'sockets' => { - 'wb_master' => { - 'wb_master' => {}, - 'connection_num' => 'single connection', - 'value' => 'M', - '0' => { - 'name' => 'wb_master' - }, - 'type' => 'param' + 'm_err_o_all' => { + 'intfc_name' => 'socket:wb_master[array]', + 'intfc_port' => 'err_o', + 'type' => 'output', + 'range' => 'M-1 : 0' }, - 'wb_addr_map' => { - 'connection_num' => 'single connection', - 'value' => 1, - '0' => { - 'name' => 'wb_addr_map' - }, - 'wb_addr_map' => {}, - 'type' => 'num' - }, - 'wb_slave' => { - 'connection_num' => 'single connection', - 'value' => 'S', - '0' => { - 'name' => 'wb_slave' - }, - 'type' => 'param', - 'wb_slave' => {} - } - }, - 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/bus/wishbone_bus.v', - 'module_name' => 'wishbone_bus', - 'unused' => undef, - 'category' => 'Bus' + 's_bte_o_all' => { + 'intfc_name' => 'socket:wb_slave[array]', + 'intfc_port' => 'bte_o', + 'type' => 'output', + 'range' => 'BTEw*S-1 : 0' + }, + 's_dat_o_all' => { + 'range' => 'Dw*S-1 : 0', + 'type' => 'output', + 'intfc_port' => 'dat_o', + 'intfc_name' => 'socket:wb_slave[array]' + } + } }, 'ip_gen' );
/lib/ip/DMA/dma.IP
0,0 → 1,428
#######################################################################
## File: dma.IP
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.7.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$dma_multi_chan_wb = bless( {
'parameters_order' => [
'CHANNEL',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'FIFO_B',
'DEBUG_EN',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw'
],
'ports_order' => [
'reset',
'clk',
's_dat_i',
's_sel_i',
's_addr_i',
's_cti_i',
's_stb_i',
's_cyc_i',
's_we_i',
's_dat_o',
's_ack_o',
'm_rd_sel_o',
'm_rd_addr_o',
'm_rd_cti_o',
'm_rd_stb_o',
'm_rd_cyc_o',
'm_rd_we_o',
'm_rd_dat_i',
'm_rd_ack_i',
'm_wr_sel_o',
'm_wr_dat_o',
'm_wr_addr_o',
'm_wr_cti_o',
'm_wr_stb_o',
'm_wr_cyc_o',
'm_wr_we_o',
'm_wr_ack_i',
'irq'
],
'module_name' => 'dma_multi_chan_wb',
'unused' => {
'plug:wb_master[0]' => [
'dat_o',
'bte_o',
'rty_i',
'err_i',
'tag_o'
],
'plug:wb_master[1]' => [
'bte_o',
'rty_i',
'err_i',
'tag_o',
'dat_i'
],
'plug:wb_slave[0]' => [
'bte_i',
'rty_o',
'tag_i',
'err_o'
]
},
'hdl_files' => [
'/mpsoc/src_noc/main_comp.v',
'/mpsoc/src_noc/arbiter.v',
'/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',
'/mpsoc/src_noc/flit_buffer.v'
],
'modules' => {
'shared_mem_fifos' => {},
'dma_single_wb' => {},
'dma_multi_chan_wb' => {}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'ports' => {
's_cti_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cti_i',
'type' => 'input',
'range' => 'TAGw-1 : 0'
},
's_we_i' => {
'range' => '',
'intfc_port' => 'we_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
},
's_cyc_i' => {
'range' => '',
'intfc_port' => 'cyc_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
},
's_dat_o' => {
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_o',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]'
},
's_addr_i' => {
'range' => 'S_Aw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'intfc_port' => 'adr_i'
},
'm_wr_cyc_o' => {
'type' => 'output',
'intfc_port' => 'cyc_o',
'intfc_name' => 'plug:wb_master[1]',
'range' => ''
},
'm_rd_dat_i' => {
'range' => 'Dw-1 : 0',
'type' => 'input',
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_master[0]'
},
'm_rd_cti_o' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'cti_o',
'type' => 'output',
'range' => 'TAGw-1 : 0'
},
's_ack_o' => {
'range' => '',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
'type' => 'output'
},
'clk' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'm_wr_cti_o' => {
'range' => 'TAGw-1 : 0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_port' => 'cti_o'
},
's_dat_i' => {
'range' => 'Dw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'intfc_port' => 'dat_i'
},
'm_rd_stb_o' => {
'intfc_name' => 'plug:wb_master[0]',
'intfc_port' => 'stb_o',
'type' => 'output',
'range' => ''
},
's_sel_i' => {
'type' => 'input',
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'SELw-1 : 0'
},
'm_rd_we_o' => {
'type' => 'output',
'intfc_port' => 'we_o',
'intfc_name' => 'plug:wb_master[0]',
'range' => ''
},
'm_wr_dat_o' => {
'range' => 'Dw-1 : 0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_port' => 'dat_o'
},
'm_wr_stb_o' => {
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_port' => 'stb_o',
'range' => ''
},
'reset' => {
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'm_wr_addr_o' => {
'range' => 'M_Aw-1 : 0',
'intfc_port' => 'adr_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[1]'
},
'm_rd_addr_o' => {
'intfc_name' => 'plug:wb_master[0]',
'type' => 'output',
'intfc_port' => 'adr_o',
'range' => 'M_Aw-1 : 0'
},
'm_wr_sel_o' => {
'range' => 'SELw-1 : 0',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_port' => 'sel_o'
},
'm_wr_ack_i' => {
'range' => '',
'intfc_port' => 'ack_i',
'type' => 'input',
'intfc_name' => 'plug:wb_master[1]'
},
's_stb_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'stb_i',
'type' => 'input',
'range' => ''
},
'm_wr_we_o' => {
'range' => '',
'intfc_name' => 'plug:wb_master[1]',
'type' => 'output',
'intfc_port' => 'we_o'
},
'm_rd_cyc_o' => {
'range' => '',
'intfc_port' => 'cyc_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
},
'm_rd_sel_o' => {
'range' => 'SELw-1 : 0',
'intfc_port' => 'sel_o',
'type' => 'output',
'intfc_name' => 'plug:wb_master[0]'
},
'irq' => {
'type' => 'output',
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'range' => ''
},
'm_rd_ack_i' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'ack_i',
'intfc_name' => 'plug:wb_master[0]'
}
},
'parameters' => {
'DEBUG_EN' => {
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'deafult' => '1',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'MAX_BURST_SIZE' => {
'redefine_param' => 1,
'type' => 'Combo-box',
'content' => '\'2,4,8,16,32,64,128,256,512,1024,2048\'',
'info' => 'Maximum burst size in words.
The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active channels, another active channel will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ',
'global_param' => 'Parameter',
'deafult' => '256'
},
'MAX_TRANSACTION_WIDTH' => {
'global_param' => 'Parameter',
'deafult' => '10',
'content' => '2,32,1',
'info' => 'The width of maximum transaction size in words.
The maximum data that can be sent via one DMA channel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'type' => 'Spin-button',
'redefine_param' => 1
},
'FIFO_B' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'deafult' => '4',
'info' => 'Channel FIFO size in words.
All channels will share same FPGA block RAM. Hence, the total needed Block RAM words is the multiplication of channel num in channel FIFO size.
 
',
'content' => '\'2,4,8,16,32,64,128,256,512,1024,2048\'',
'type' => 'Combo-box'
},
'Dw' => {
'redefine_param' => 1,
'deafult' => '32',
'global_param' => 'Parameter',
'info' => 'Wishbone bus Data size in bit',
'content' => '8,1024,8',
'type' => 'Spin-button'
},
'TAGw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'deafult' => '3',
'global_param' => 'Parameter'
},
'M_Aw' => {
'type' => 'Fixed',
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'deafult' => '32',
'redefine_param' => 1
},
'CHANNEL' => {
'redefine_param' => 1,
'info' => 'Number of DMA channels.
In case there are multiple active DMA channels, Each time one single active DMA channel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter channel until its FIFO is not full and the number od sent data is smaller than the burst size.',
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'deafult' => '1'
},
'S_Aw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'deafult' => '8'
},
'SELw' => {
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'global_param' => 'Parameter',
'deafult' => '4',
'redefine_param' => 1
}
},
'plugs' => {
'clk' => {
'clk' => {},
'type' => 'num',
'0' => {
'name' => 'clk'
},
'value' => 1
},
'wb_master' => {
'value' => 2,
'0' => {
'name' => 'wb_rd'
},
'1' => {
'name' => 'wb_wr'
},
'wb_master' => {},
'type' => 'num'
},
'interrupt_peripheral' => {
'type' => 'num',
'interrupt_peripheral' => {},
'0' => {
'name' => 'interrupt_peripheral'
},
'value' => 1
},
'wb_slave' => {
'type' => 'num',
'value' => 1,
'wb_slave' => {},
'0' => {
'addr' => '0x9300_0000 0x93ff_ffff Memory Controller',
'name' => 'wb_slave',
'width' => 10
}
},
'reset' => {
'0' => {
'name' => 'reset'
},
'value' => 1,
'reset' => {},
'type' => 'num'
}
},
'description' => 'A round robin based multi channel DMA (no byte enable). support burst data transaction.',
'ip_name' => 'dma',
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',
'category' => 'DMA',
'system_h' => '#define ${IP}_STATUS_REG (*((volatile unsigned int *) ($BASE)))
#define ${IP}_BURST_SIZE_ADDR_REG (*((volatile unsigned int *) ($BASE+4)))
 
 
#define ${IP}_CHANNEL ${CHANNEL}
#define ${IP}_DATA_SIZE_ADDR_REG(channel) (*((volatile unsigned int *) ($BASE+8+(channel<<5))))
#define ${IP}_RD_START_ADDR_REG(channel) (*((volatile unsigned int *) ($BASE+12+(channel<<5))))
#define ${IP}_WR_START_ADDR_REG(channel) (*((volatile unsigned int *) ($BASE+16+(channel<<5))))
 
 
// assign status= {rd_enable_binarry,wr_enable_binarry,channel_rd_is_active,channel_wr_is_active};
 
#define ${IP}_channel_is_busy(channel) ( (${IP}_STATUS_REG >> channel) & 0x1)
 
 
void ${IP}_initial (unsigned int burst_size) {
${IP}_BURST_SIZE_ADDR_REG = burst_size;
}
 
 
void ${IP}_transfer (unsigned int channel, unsigned int read_start_addr, unsigned int data_size, unsigned int write_start_addr){
while ( ${IP}_channel_is_busy(channel)); // wait until DMA channel is busy
${IP}_RD_START_ADDR_REG(channel) = read_start_addr;
${IP}_DATA_SIZE_ADDR_REG(channel) = data_size;
${IP}_WR_START_ADDR_REG(channel) = write_start_addr;
}'
}, 'ip_gen' );
/lib/ip/GPIO/gpi.IP
3,7 → 3,7
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.5.0
## This file is part of ProNoC 1.6.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
10,92 → 10,6
################################################################################
 
$gpi = bless( {
'hdl_files' => [
'/mpsoc/src_peripheral/gpio/gpio.v'
],
'system_h' => '#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8)))
#define ${IP}_READ() ${IP}_READ_REG ',
'ip_name' => 'gpi',
'description' => 'General inout port',
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'plugs' => {
'clk' => {
'clk' => {},
'0' => {
'name' => 'clk'
},
'value' => 1,
'type' => 'num'
},
'reset' => {
'reset' => {},
'value' => 1,
'0' => {
'name' => 'reset'
},
'type' => 'num'
},
'wb_slave' => {
'value' => 1,
'0' => {
'width' => 5,
'name' => 'wb',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
},
'type' => 'num',
'wb_slave' => {}
}
},
'parameters' => {
'PORT_WIDTH' => {
'info' => 'Input port width ',
'deafult' => ' 1',
'global_param' => 'Parameter',
'content' => '1,32,1',
'type' => 'Spin-button',
'redefine_param' => 1
},
'Aw' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1
},
'SELw' => {
'info' => undef,
'deafult' => ' 4',
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1
},
'TAGw' => {
'info' => undef,
'deafult' => ' 3',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'Dw' => {
'info' => undef,
'deafult' => 'PORT_WIDTH',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'modules' => {
'gpi' => {},
'gpo' => {},
'gpio' => {}
},
'parameters_order' => [
'PORT_WIDTH',
'Dw',
103,96 → 17,182
'TAGw',
'SELw'
],
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
'ports' => {
'sa_tag_i' => {
'intfc_port' => 'tag_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'TAGw-1 : 0',
'type' => 'input'
},
'sa_rty_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'rty_o',
'range' => '',
'type' => 'output'
},
'sa_dat_o' => {
'range' => 'Dw-1 : 0',
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_addr_i' => {
'range' => 'Aw-1 : 0',
'intfc_port' => 'adr_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
},
'port_i' => {
'intfc_name' => 'IO',
'type' => 'input',
'intfc_port' => 'IO',
'range' => 'PORT_WIDTH-1 : 0'
},
'sa_dat_i' => {
'range' => 'Dw-1 : 0',
'type' => 'output'
'intfc_port' => 'dat_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_sel_i' => {
'intfc_port' => 'sel_i',
'sa_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'SELw-1 : 0',
'type' => 'input'
'type' => 'output',
'intfc_port' => 'ack_o',
'range' => ''
},
'sa_dat_i' => {
'intfc_port' => 'dat_i',
'sa_stb_i' => {
'intfc_port' => 'stb_i',
'range' => '',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Dw-1 : 0',
'type' => 'input'
},
'sa_we_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i',
'range' => '',
'type' => 'input'
'intfc_port' => 'we_i'
},
'sa_err_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'intfc_port' => 'err_o'
},
'sa_sel_i' => {
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'SELw-1 : 0',
'intfc_port' => 'sel_i'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => ''
},
'sa_cyc_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'intfc_port' => 'cyc_i',
'range' => '',
'type' => 'input'
'range' => ''
},
'sa_err_o' => {
'sa_rty_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'err_o',
'range' => '',
'type' => 'output'
'type' => 'output',
'intfc_port' => 'rty_o',
'range' => ''
},
'reset' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
'intfc_port' => 'reset_i'
},
'clk' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
},
'sa_ack_o' => {
'sa_tag_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
'range' => '',
'type' => 'output'
},
'port_i' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'PORT_WIDTH-1 : 0',
'type' => 'input'
},
'sa_addr_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'adr_i',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sa_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
'type' => 'input',
'intfc_port' => 'tag_i',
'range' => 'TAGw-1 : 0'
}
},
'modules' => {
'gpio' => {},
'gpo' => {},
'gpi' => {}
},
'ip_name' => 'gpi',
'category' => 'GPIO',
'sockets' => {},
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
'plugs' => {
'wb_slave' => {
'wb_slave' => {},
'type' => 'num',
'value' => 1,
'0' => {
'width' => 5,
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O',
'name' => 'wb'
}
},
'reset' => {
'value' => 1,
'type' => 'num',
'reset' => {},
'0' => {
'name' => 'reset'
}
},
'clk' => {
'value' => 1,
'type' => 'num',
'clk' => {},
'0' => {
'name' => 'clk'
}
}
},
'hdl_files' => [
'/mpsoc/src_peripheral/gpio/gpio.v'
],
'description' => 'General inout port',
'system_h' => '#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8)))
#define ${IP}_READ() ${IP}_READ_REG ',
'parameters' => {
'TAGw' => {
'deafult' => ' 3',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'content' => ''
},
'Dw' => {
'redefine_param' => 1,
'deafult' => 'PORT_WIDTH',
'global_param' => 'Localparam',
'info' => undef,
'type' => 'Fixed',
'content' => ''
},
'SELw' => {
'global_param' => 'Localparam',
'deafult' => ' 4',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'info' => undef
},
'PORT_WIDTH' => {
'info' => 'Input port width ',
'type' => 'Spin-button',
'content' => '1,32,1',
'deafult' => ' 1',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'Aw' => {
'content' => '',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'deafult' => ' 2',
'redefine_param' => 1
}
},
'module_name' => 'gpi',
'category' => 'GPIO',
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'unused' => {
'plug:wb_slave[0]' => [
'cti_i',
/lib/ip/GPIO/gpio.IP
3,7 → 3,7
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.5.0
## This file is part of ProNoC 1.6.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
10,180 → 10,180
################################################################################
 
$gpio = bless( {
'hdl_files' => [
'/mpsoc/src_peripheral/gpio/gpio.v'
],
'system_h' => '#define ${IP}_DIR_REG (*((volatile unsigned int *) ($BASE)))
#define ${IP}_WRITE _REG (*((volatile unsigned int *) ($BASE+4)))
#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8)))
#define ${IP}_DIR_SET(value) ${IP}_DIR_REG=value
#define ${IP}_WRITE(value) ${IP}_WRITE _REG=value
#define ${IP}_READ() ${IP}_READ_REG ',
'ip_name' => 'gpio',
'description' => 'General inout port',
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'parameters' => {
'PORT_WIDTH' => {
'info' => undef,
'deafult' => '1',
'global_param' => 'Parameter',
'content' => '1,32,1',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'Aw' => {
'info' => undef,
'deafult' => '2',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'SELw' => {
'info' => undef,
'deafult' => '4',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'Dw' => {
'info' => undef,
'deafult' => 'PORT_WIDTH',
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1
}
},
'plugs' => {
'reset' => {
'reset' => {},
'0' => {
'name' => 'reset'
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'clk' => {},
'0' => {
'name' => 'clk'
},
'value' => 1,
'type' => 'num'
},
'wb_slave' => {
'value' => 1,
'0' => {
'width' => 5,
'name' => 'wb',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
},
'type' => 'num',
'wb_slave' => {}
}
},
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
'module_name' => 'gpio',
'modules' => {
'gpo' => {},
'gpi' => {},
'gpio' => {},
'gpo' => {}
'gpio' => {}
},
'parameters_order' => [
'PORT_WIDTH',
'Dw',
'Aw',
'SELw',
'Dw'
],
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'sockets' => {},
'category' => 'GPIO',
'ports' => {
'sa_rty_o' => {
'intfc_port' => 'rty_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
},
'port_io' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'PORT_WIDTH-1 : 0',
'type' => 'inout'
},
'sa_dat_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Dw-1 : 0',
'type' => 'output',
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'type' => 'output'
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'SELw-1 : 0',
'type' => 'input'
},
'sa_dat_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'type' => 'input'
'type' => 'input',
'intfc_port' => 'dat_i'
},
'sa_we_i' => {
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
},
'sa_err_o' => {
'intfc_port' => 'err_o',
'sa_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
'type' => 'output',
'intfc_port' => 'ack_o'
},
'sa_sel_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'type' => 'input',
'range' => 'SELw-1 : 0',
'intfc_port' => 'sel_i'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
},
'sa_rty_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'rty_o',
'type' => 'output',
'range' => ''
},
'reset' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
'type' => 'input',
'intfc_port' => 'reset_i'
},
'sa_ack_o' => {
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[0]',
'sa_stb_i' => {
'intfc_port' => 'stb_i',
'type' => 'input',
'range' => '',
'type' => 'output'
'intfc_name' => 'plug:wb_slave[0]'
},
'port_io' => {
'intfc_port' => 'IO',
'type' => 'inout',
'range' => 'PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
},
'sa_addr_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'adr_i',
'type' => 'input',
'range' => 'Aw-1 : 0',
'type' => 'input'
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_stb_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'stb_i',
'sa_err_o' => {
'type' => 'output',
'range' => '',
'type' => 'input'
}
'intfc_port' => 'err_o',
'intfc_name' => 'plug:wb_slave[0]'
},
'sa_we_i' => {
'intfc_port' => 'we_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:wb_slave[0]'
}
},
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
'sockets' => {},
'module_name' => 'gpio',
'category' => 'GPIO',
'plugs' => {
'reset' => {
'type' => 'num',
'value' => 1,
'reset' => {},
'0' => {
'name' => 'reset'
}
},
'wb_slave' => {
'value' => 1,
'type' => 'num',
'0' => {
'width' => 5,
'name' => 'wb',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
},
'wb_slave' => {}
},
'clk' => {
'type' => 'num',
'clk' => {},
'value' => 1,
'0' => {
'name' => 'clk'
}
}
},
'description' => 'General inout port',
'parameters' => {
'Dw' => {
'global_param' => 'Localparam',
'info' => undef,
'content' => '',
'deafult' => 'PORT_WIDTH',
'type' => 'Fixed',
'redefine_param' => 1
},
'SELw' => {
'global_param' => 'Localparam',
'info' => undef,
'deafult' => '4',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'PORT_WIDTH' => {
'info' => undef,
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '1,32,1',
'deafult' => '1'
},
'Aw' => {
'deafult' => '2',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => undef,
'global_param' => 'Localparam'
}
},
'system_h' => '#define ${IP}_DIR_REG (*((volatile unsigned int *) ($BASE)))
#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4)))
#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8)))
#define ${IP}_DIR_SET(value) ${IP}_DIR_REG=value
#define ${IP}_WRITE(value) ${IP}_WRITE _REG=value
#define ${IP}_READ() ${IP}_READ_REG ',
'hdl_files' => [
'/mpsoc/src_peripheral/gpio/gpio.v'
],
'ip_name' => 'gpio',
'unused' => {
'plug:wb_slave[0]' => [
'tag_i',
'cyc_i',
'tag_i',
'cti_i',
'bte_i'
'bte_i',
'cti_i'
]
}
},
'parameters_order' => [
'PORT_WIDTH',
'Dw',
'Aw',
'SELw',
'Dw'
]
}, 'ip_gen' );
/lib/ip/GPIO/gpo.IP
3,7 → 3,7
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.5.0
## This file is part of ProNoC 1.6.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
10,101 → 10,64
################################################################################
 
$gpo = bless( {
'version' => 1,
'description' => 'General output port',
'hdl_files' => [
'/mpsoc/src_peripheral/gpio/gpio.v'
],
'system_h' => '#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4)))
#define ${IP}_WRITE(value) ${IP}_WRITE_REG=value
 
',
'description' => 'General output port',
'ip_name' => 'gpo',
'plugs' => {
'clk' => {
'clk' => {},
'value' => 1,
'0' => {
'name' => 'clk'
},
'type' => 'num'
},
'reset' => {
'reset' => {},
'0' => {
'name' => 'reset'
},
'value' => 1,
'type' => 'num'
},
'wb_slave' => {
'value' => 1,
'0' => {
'width' => 5,
'name' => 'wb',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
},
'type' => 'num',
'wb_slave' => {}
}
},
'modules' => {
'gpi' => {},
'gpio' => {},
'gpo' => {}
},
'parameters' => {
'PORT_WIDTH' => {
'info' => 'output port width',
'deafult' => ' 1',
'global_param' => 'Parameter',
'content' => '1,32,1',
'type' => 'Spin-button',
'redefine_param' => 1
},
'SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'redefine_param' => 1,
'deafult' => ' 4',
'content' => ''
},
'Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'deafult' => ' 2',
'content' => '',
'info' => undef,
'deafult' => ' 2',
'redefine_param' => 1
},
'Dw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'deafult' => 'PORT_WIDTH',
'redefine_param' => 1,
'type' => 'Fixed'
'info' => undef
},
'TAGw' => {
'info' => undef,
'redefine_param' => 1,
'deafult' => ' 3',
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1
},
'SELw' => {
'info' => undef,
'deafult' => ' 4',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'Dw' => {
'info' => undef,
'deafult' => 'PORT_WIDTH',
'global_param' => 'Localparam',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1
}
'PORT_WIDTH' => {
'deafult' => ' 1',
'content' => '1,32,1',
'info' => 'output port width',
'redefine_param' => 1,
'type' => 'Spin-button',
'global_param' => 'Parameter'
}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'unused' => {
'plug:wb_slave[0]' => [
'bte_i',
'cti_i'
]
},
'modules' => {
'gpo' => {},
'gpi' => {},
'gpio' => {}
},
'ports' => {
'sa_tag_i' => {
'intfc_port' => 'tag_i',
112,93 → 75,131
'range' => 'TAGw-1 : 0',
'type' => 'input'
},
'sa_rty_o' => {
'intfc_port' => 'rty_o',
'reset' => {
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i'
},
'sa_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
'type' => 'output',
'intfc_port' => 'ack_o'
},
'sa_dat_o' => {
'sa_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_o',
'range' => 'Dw-1 : 0',
'type' => 'output'
'range' => '',
'type' => 'input'
},
'sa_sel_i' => {
'type' => 'input',
'range' => 'SELw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'sel_i',
'range' => 'SELw-1 : 0',
'type' => 'input'
'intfc_port' => 'sel_i'
},
'clk' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]'
},
'sa_cyc_i' => {
'intfc_port' => 'cyc_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'range' => ''
},
'sa_dat_i' => {
'intfc_port' => 'dat_i',
'type' => 'input',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_i',
'range' => 'Dw-1 : 0',
'type' => 'input'
'range' => 'Dw-1 : 0'
},
'port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'intfc_name' => 'IO',
'range' => 'PORT_WIDTH-1 : 0',
'type' => 'output'
'range' => 'PORT_WIDTH-1 : 0'
},
'sa_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sa_we_i' => {
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
'type' => 'input',
'intfc_port' => 'we_i'
},
'sa_cyc_i' => {
'sa_dat_o' => {
'range' => 'Dw-1 : 0',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cyc_i',
'range' => '',
'type' => 'input'
'type' => 'output',
'intfc_port' => 'dat_o'
},
'sa_err_o' => {
'sa_rty_o' => {
'type' => 'output',
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'err_o',
'range' => '',
'type' => 'output'
'intfc_port' => 'rty_o'
},
'reset' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'range' => '',
'type' => 'input'
},
'sa_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
'sa_err_o' => {
'type' => 'output',
'range' => '',
'type' => 'output'
},
'sa_addr_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'adr_i',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sa_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
'intfc_port' => 'err_o'
}
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'category' => 'GPIO',
'ip_name' => 'gpo',
'system_h' => '#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4)))
#define ${IP}_WRITE(value) ${IP}_WRITE_REG=value
 
',
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'plugs' => {
'reset' => {
'reset' => {},
'type' => 'num',
'0' => {
'name' => 'reset'
},
'value' => 1
},
'wb_slave' => {
'value' => 1,
'wb_slave' => {},
'0' => {
'width' => 5,
'name' => 'wb',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
},
'type' => 'num'
},
'clk' => {
'value' => 1,
'clk' => {},
'0' => {
'name' => 'clk'
},
'type' => 'num'
}
},
'sockets' => {},
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v',
'sockets' => {},
'module_name' => 'gpo',
'category' => 'GPIO',
'unused' => {
'plug:wb_slave[0]' => [
'cti_i',
'bte_i'
]
}
'module_name' => 'gpo'
}, 'ip_gen' );
/lib/ip/NoC/ni.IP File deleted
lib/ip/NoC/ni.IP Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: lib/ip/NoC/ni_sep.IP =================================================================== --- lib/ip/NoC/ni_sep.IP (revision 33) +++ lib/ip/NoC/ni_sep.IP (nonexistent) @@ -1,680 +0,0 @@ -####################################################################### -## File: ni_sep.IP -## -## Copyright (C) 2014-2016 Alireza Monemi -## -## This file is part of ProNoC 1.5.1 -## -## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT -## MAY CAUSE UNEXPECTED BEHAIVOR. -################################################################################ - -$ni_sep = bless( { - 'hdl_files' => [ - '/mpsoc/src_peripheral/ni/ni_sep.v', - '/mpsoc/src_peripheral/ni/sub_ni_rd.v', - '/mpsoc/src_peripheral/ni/sub_ni_wr.v', - '/mpsoc/src_noc/arbiter.v', - '/mpsoc/src_noc/flit_buffer.v', - '/mpsoc/src_noc/inout_ports.v', - '/mpsoc/src_noc/main_comp.v', - '/mpsoc/src_noc/route_mesh.v', - '/mpsoc/src_noc/route_torus.v', - '/mpsoc/src_noc/routing.v' - ], - 'system_h' => '#define ${IP}_BASE_ADDR ${BASE} - #define ${IP}_STATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR ))) - #define ${IP}_MEM_PCKSIZ (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 ))) - #define ${IP}_PCKSIZE (*((volatile unsigned int *) (${IP}_BASE_ADDR+8))) - #define ${IP}_MEM (*((volatile unsigned int *) (${IP}_BASE_ADDR+12))) - - #define ${IP}_VC_WR_ADDR(v) (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 + (1<<5)+ (v<<6) ))) - #define ${IP}_VC_RD_ADDR(v) (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 + (v<<6) ))) - - - #define ${IP}_VC_NUM ${V} - #define ${IP}_VC_MASK ((1<<${V})-1) - #define ${IP}_CLASS_IN_HDR_WIDTH 8 - #define ${IP}_DEST_IN_HDR_WIDTH 8 - #define ${IP}_X_Y_IN_HDR_WIDTH 4 - -/* - [14+V : 14+2V-1]rd_vc_not_empty - [14 : 14+V-1] wr_vc_not_empty - 13 rsv_pck_isr - 12 rd_done_isr - 11 wr_done_isr - 10 rsv_pck_int_en - 9 rd_done_int_en - 8 wr_done_int_en - 7 all_wr_vcs_full - 6 any_rd_vc_has_data - 5 rd_no_pck_err - 4 rd_ovr_size_err - 3 rd_done - 2 wr_done - 1 rd_busy - 0 wr_busy -*/ - #define ${IP}_WR_BUSY (1<<0) - #define ${IP}_RD_BUSY (1<<1) - #define ${IP}_WR_DONE (1<<2) - #define ${IP}_RD_DONE (1<<3) - #define ${IP}_RD_OVR_ERR (1<<4) - #define ${IP}_RD_NPCK_ERR (1<<5) - #define ${IP}_HAS_PCK (1<<6) - #define ${IP}_ALL_VCS_FULL (1<<7) - #define ${IP}_WR_DONE_INT_EN (1<<8) - #define ${IP}_RD_DONE_INT_EN (1<<9) - #define ${IP}_RSV_PCK_INT_EN (1<<10) - #define ${IP}_WR_DONE_ISR (1<<11) - #define ${IP}_RD_DONE_ISR (1<<12) - #define ${IP}_RSV_PCK_ISR (1<<13) - #define ${IP}WR_VCS_NO_EMPTY (${IP}_VC_MASK <<14) - #define ${IP}RD_VCS_NO_EMPTY (${IP}_VC_MASK << (14+${V})) - - #define ${IP}_PTR_WIDTH 20 - #define ${IP}_PCK_SIZE_WIDTH 12 - - - - - #define ${IP}_HDR_DEST_CORE_ADDR(DES_X, DES_Y) ((DES_X << ${IP}_X_Y_IN_HDR_WIDTH) | DES_Y)<<(2*${IP}_X_Y_IN_HDR_WIDTH) - #define ${IP}_HDR_CLASS(pck_class) (pck_class << ( ${IP}_DEST_IN_HDR_WIDTH+ (4* ${IP}_X_Y_IN_HDR_WIDTH))) - - - #define ${IP}_wait_for_sending_pck() while (!(${IP}_STATUS & ${IP}_WR_DONE)) - #define ${IP}_wait_for_reading_pck() while (!(${IP}_STATUS & ${IP}_RD_DONE)) - #define ${IP}_wait_for_getting_pck() while (!(${IP}_STATUS & ${IP}_HAS_PCK)) - -/***************************************** -void send_pck (unsigned int * pck_buffer, unsigned int data_size, unsigned int vc_num); -sending a packet through NoC network; -(unsigned int des_x,unsigned int des_y : destination core address; -unsigned int * pck_buffer : the buffer which hold the packet; The data must start from buff[1]; -unsigned int data_size : the size of data which wanted to be sent out in word = packet_size-1; -unsigned int class - -****************************************/ - inline void ${IP}_send_pck (unsigned int des_x, unsigned int des_y, volatile unsigned int * pck_buffer, unsigned int data_size, unsigned int pck_class, unsigned int vc_num){ - pck_buffer [0] = ${IP}_HDR_DEST_CORE_ADDR(des_x, des_y) | ${IP}_HDR_CLASS(pck_class); - ${IP}_VC_WR_ADDR(vc_num) = (unsigned int) (& pck_buffer [0]) + (data_size<<${IP}_PTR_WIDTH); - ${IP}_wait_for_sending_pck(); - } - -/******************************************* -void save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size); -save a received packet on pck_buffer -unsigned int * pck_buffer: the buffer for storing the packet; The read data start from buff[1]; -********************************************/ - inline void ${IP}_save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size,unsigned int vc_num){ - ${IP}_VC_RD_ADDR(vc_num) = (unsigned int) (& pck_buffer [0]) + (buffer_size<<${IP}_PTR_WIDTH); - ${IP}_wait_for_reading_pck(); - }', - 'ip_name' => 'ni_sep', - 'parameters_order' => [ - 'V', - 'B', - 'NX', - 'NY', - 'Fpay', - 'TOPOLOGY', - 'ROUTE_NAME', - 'DEBUG_EN', - 'COMB_MEM_PTR_W', - 'COMB_PCK_SIZE_W', - 'Dw', - 'S_Aw', - 'M_Aw', - 'TAGw', - 'SELw', - 'Yw', - 'Fw', - 'Xw' - ], - 'ports_order' => [ - 'reset', - 'clk', - 'current_x', - 'current_y', - 'flit_out', - 'flit_out_wr', - 'credit_in', - 'flit_in', - 'flit_in_wr', - 'credit_out', - 's_dat_i', - 's_sel_i', - 's_addr_i', - 's_cti_i', - 's_stb_i', - 's_cyc_i', - 's_we_i', - 's_dat_o', - 's_ack_o', - 'm_rd_sel_o', - 'm_rd_dat_o', - 'm_rd_addr_o', - 'm_rd_cti_o', - 'm_rd_stb_o', - 'm_rd_cyc_o', - 'm_rd_we_o', - 'm_rd_ack_i', - 'm_wr_sel_o', - 'm_wr_addr_o', - 'm_wr_cti_o', - 'm_wr_stb_o', - 'm_wr_cyc_o', - 'm_wr_we_o', - 'm_wr_dat_i', - 'm_wr_ack_i', - 'irq' - ], - 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ni/ni_sep.v', - 'sockets' => { - 'ni' => { - 'connection_num' => 'single connection', - '0' => { - 'name' => 'ni' - }, - 'value' => 1, - 'type' => 'num', - 'ni' => {} - } - }, - 'module_name' => 'ni_sep', - 'unused' => { - 'plug:wb_master[1]' => [ - 'tag_o', - 'bte_o', - 'dat_o', - 'err_i', - 'rty_i' - ], - 'plug:wb_slave[0]' => [ - 'err_o', - 'rty_o', - 'tag_i', - 'bte_i' - ], - 'plug:wb_master[0]' => [ - 'tag_o', - 'dat_i', - 'bte_o', - 'err_i', - 'rty_i' - ] - }, - 'category' => 'NoC', - 'plugs' => { - 'wb_master' => { - 'wb_master' => {}, - '1' => { - 'name' => 'wb_wr' - }, - '0' => { - 'name' => 'wb_rd' - }, - 'value' => 2, - 'type' => 'num' - }, - 'reset' => { - 'reset' => {}, - '0' => { - 'name' => 'reset' - }, - 'value' => 1, - 'type' => 'num' - }, - 'clk' => { - 'clk' => {}, - '0' => { - 'name' => 'clk' - }, - 'value' => 1, - 'type' => 'num' - }, - 'interrupt_peripheral' => { - 'interrupt_peripheral' => {}, - 'value' => 1, - '0' => { - 'name' => 'intrpt_prhl' - }, - 'type' => 'num' - }, - 'wb_slave' => { - '1' => { - 'width' => 1, - 'name' => 'wb_slave_1', - 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' - }, - '0' => { - 'width' => 9, - 'name' => 'wb_slave', - 'addr' => '0xb800_0000 0xbfff_ffff custom devices' - }, - 'value' => 1, - 'type' => 'num', - 'wb_slave' => {} - } - }, - 'modules' => { - 'ni_sep' => {} - }, - 'parameters' => { - 'Dw' => { - 'info' => undef, - 'deafult' => ' 32', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'DEBUG_EN' => { - 'info' => undef, - 'deafult' => '0', - 'global_param' => 'Parameter', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'NY' => { - 'info' => undef, - 'deafult' => ' 2', - 'global_param' => 'Parameter', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'NX' => { - 'info' => undef, - 'deafult' => ' 2', - 'global_param' => 'Parameter', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'V' => { - 'info' => '', - 'deafult' => ' 4', - 'global_param' => 'Parameter', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'CONGESTION_INDEX' => { - 'info' => undef, - 'deafult' => '3', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'Fw' => { - 'info' => undef, - 'deafult' => '2+V+Fpay', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 0, - 'type' => 'Fixed' - }, - 'COMB_PCK_SIZE_W' => { - 'info' => undef, - 'deafult' => '12', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'TAGw' => { - 'info' => undef, - 'deafult' => '3', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'M_Aw' => { - 'info' => undef, - 'deafult' => '32', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'COMB_MEM_PTR_W' => { - 'info' => undef, - 'deafult' => '20', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ROUTE_NAME' => { - 'info' => undef, - 'deafult' => '"XY"', - 'global_param' => 'Parameter', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'Xw ' => { - 'info' => undef, - 'deafult' => 'log2(NX)', - 'global_param' => 0, - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 0 - }, - 'Fpay' => { - 'info' => undef, - 'deafult' => ' 32', - 'global_param' => 'Parameter', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'ROUTE_TYPE' => { - 'info' => undef, - 'deafult' => '"DETERMINISTIC"', - 'global_param' => 1, - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - }, - 'SELw' => { - 'info' => undef, - 'deafult' => '4 ', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'P' => { - 'info' => undef, - 'deafult' => ' 5', - 'global_param' => 1, - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - }, - 'B' => { - 'info' => '', - 'deafult' => ' 4', - 'global_param' => 'Parameter', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'S_Aw' => { - 'info' => undef, - 'deafult' => '7', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'TOPOLOGY' => { - 'info' => undef, - 'deafult' => '"MESH"', - 'global_param' => 'Parameter', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'Xw' => { - 'info' => undef, - 'deafult' => 'log2(NX)', - 'global_param' => 'Localparam', - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 0 - }, - 'Yw' => { - 'info' => undef, - 'deafult' => 'log2(NY)', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 0, - 'type' => 'Fixed' - }, - 'SSA_EN' => { - 'info' => undef, - 'deafult' => '"NO"', - 'global_param' => 1, - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'Xwj' => { - 'info' => undef, - 'deafult' => 'fvf', - 'global_param' => 0, - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - } - }, - 'gui_status' => { - 'timeout' => 0, - 'status' => 'ideal' - }, - 'ports' => { - 'm_rd_cyc_o' => { - 'intfc_port' => 'cyc_o', - 'intfc_name' => 'plug:wb_master[0]', - 'range' => '', - 'type' => 'output' - }, - 's_dat_i' => { - 'intfc_port' => 'dat_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'Dw-1 : 0', - 'type' => 'input' - }, - 's_cyc_i' => { - 'intfc_port' => 'cyc_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '', - 'type' => 'input' - }, - 'm_wr_sel_o' => { - 'intfc_port' => 'sel_o', - 'intfc_name' => 'plug:wb_master[1]', - 'range' => 'SELw-1 : 0', - 'type' => 'output' - }, - 'm_wr_dat_i' => { - 'intfc_port' => 'dat_i', - 'intfc_name' => 'plug:wb_master[1]', - 'range' => 'Dw-1 : 0', - 'type' => 'input' - }, - 'm_wr_addr_o' => { - 'intfc_port' => 'adr_o', - 'intfc_name' => 'plug:wb_master[1]', - 'range' => 'M_Aw-1 : 0', - 'type' => 'output' - }, - 'credit_out' => { - 'intfc_port' => 'credit_out', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'V-1 : 0', - 'type' => 'output' - }, - 'flit_in_wr' => { - 'intfc_port' => 'flit_in_wr', - 'intfc_name' => 'socket:ni[0]', - 'range' => '', - 'type' => 'input' - }, - 's_dat_o' => { - 'intfc_port' => 'dat_o', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'Dw-1 : 0', - 'type' => 'output' - }, - 's_addr_i' => { - 'intfc_port' => 'adr_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'S_Aw-1 : 0', - 'type' => 'input' - }, - 's_cti_i' => { - 'intfc_port' => 'cti_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'TAGw-1 : 0', - 'type' => 'input' - }, - 'current_y' => { - 'intfc_port' => 'current_y', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'Yw-1 : 0', - 'type' => 'input' - }, - 'm_wr_cti_o' => { - 'intfc_port' => 'cti_o', - 'intfc_name' => 'plug:wb_master[1]', - 'range' => 'TAGw-1 : 0', - 'type' => 'output' - }, - 'm_rd_ack_i' => { - 'intfc_port' => 'ack_i', - 'intfc_name' => 'plug:wb_master[0]', - 'range' => '', - 'type' => 'input' - }, - 's_sel_i' => { - 'intfc_port' => 'sel_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'SELw-1 : 0', - 'type' => 'input' - }, - 's_we_i' => { - 'intfc_port' => 'we_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '', - 'type' => 'input' - }, - 'm_rd_dat_o' => { - 'intfc_port' => 'dat_o', - 'intfc_name' => 'plug:wb_master[0]', - 'range' => 'Dw-1 : 0', - 'type' => 'output' - }, - 's_stb_i' => { - 'intfc_port' => 'stb_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '', - 'type' => 'input' - }, - 'm_wr_stb_o' => { - 'intfc_port' => 'stb_o', - 'intfc_name' => 'plug:wb_master[1]', - 'range' => '', - 'type' => 'output' - }, - 'flit_out_wr' => { - 'intfc_port' => 'flit_out_wr', - 'intfc_name' => 'socket:ni[0]', - 'range' => '', - 'type' => 'output' - }, - 'm_rd_sel_o' => { - 'intfc_port' => 'sel_o', - 'intfc_name' => 'plug:wb_master[0]', - 'range' => 'SELw-1 : 0', - 'type' => 'output' - }, - 'm_rd_addr_o' => { - 'intfc_port' => 'adr_o', - 'intfc_name' => 'plug:wb_master[0]', - 'range' => 'M_Aw-1 : 0', - 'type' => 'output' - }, - 's_ack_o' => { - 'intfc_port' => 'ack_o', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '', - 'type' => 'output' - }, - 'm_wr_ack_i' => { - 'intfc_port' => 'ack_i', - 'intfc_name' => 'plug:wb_master[1]', - 'range' => '', - 'type' => 'input' - }, - 'm_rd_we_o' => { - 'intfc_port' => 'we_o', - 'intfc_name' => 'plug:wb_master[0]', - 'range' => '', - 'type' => 'output' - }, - 'flit_out' => { - 'intfc_port' => 'flit_out', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'Fw-1 : 0', - 'type' => 'output' - }, - 'credit_in' => { - 'intfc_port' => 'credit_in', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'V-1 : 0', - 'type' => 'input' - }, - 'reset' => { - 'intfc_port' => 'reset_i', - 'intfc_name' => 'plug:reset[0]', - 'range' => '', - 'type' => 'input' - }, - 'm_rd_stb_o' => { - 'intfc_port' => 'stb_o', - 'intfc_name' => 'plug:wb_master[0]', - 'range' => '', - 'type' => 'output' - }, - 'flit_in' => { - 'intfc_port' => 'flit_in', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'Fw-1 : 0', - 'type' => 'input' - }, - 'm_rd_cti_o' => { - 'intfc_port' => 'cti_o', - 'intfc_name' => 'plug:wb_master[0]', - 'range' => 'TAGw-1 : 0', - 'type' => 'output' - }, - 'm_wr_we_o' => { - 'intfc_port' => 'we_o', - 'intfc_name' => 'plug:wb_master[1]', - 'range' => '', - 'type' => 'output' - }, - 'current_x' => { - 'intfc_port' => 'current_x', - 'intfc_name' => 'socket:ni[0]', - 'range' => 'Xw-1 : 0', - 'type' => 'input' - }, - 'irq' => { - 'intfc_port' => 'int_o', - 'intfc_name' => 'plug:interrupt_peripheral[0]', - 'range' => '', - 'type' => 'output' - }, - 'clk' => { - 'intfc_port' => 'clk_i', - 'intfc_name' => 'plug:clk[0]', - 'range' => '', - 'type' => 'input' - }, - 'm_wr_cyc_o' => { - 'intfc_port' => 'cyc_o', - 'intfc_name' => 'plug:wb_master[1]', - 'range' => '', - 'type' => 'output' - } - } - }, 'ip_gen' );
lib/ip/NoC/ni_sep.IP Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: lib/ip/NoC/ni_master.IP =================================================================== --- lib/ip/NoC/ni_master.IP (nonexistent) +++ lib/ip/NoC/ni_master.IP (revision 34) @@ -0,0 +1,693 @@ +####################################################################### +## File: ni_master.IP +## +## Copyright (C) 2014-2016 Alireza Monemi +## +## This file is part of ProNoC 1.6.0 +## +## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT +## MAY CAUSE UNEXPECTED BEHAIVOR. +################################################################################ + +$ni_master = bless( { + 'plugs' => { + 'interrupt_peripheral' => { + 'type' => 'num', + 'value' => 1, + '0' => { + 'name' => 'interrupt' + }, + 'interrupt_peripheral' => {} + }, + 'wb_slave' => { + 'wb_slave' => {}, + 'type' => 'num', + 'value' => 1, + '0' => { + 'addr' => '0xb800_0000 0xbfff_ffff custom devices', + 'name' => 'wb_slave', + 'width' => 10 + } + }, + 'reset' => { + 'reset' => {}, + '0' => { + 'name' => 'reset' + }, + 'type' => 'num', + 'value' => 1 + }, + 'clk' => { + 'clk' => {}, + '0' => { + 'name' => 'clk' + }, + 'value' => 1, + 'type' => 'num' + }, + 'wb_master' => { + '1' => { + 'name' => 'wb_receive' + }, + 'type' => 'num', + 'wb_master' => {}, + 'value' => 2, + '0' => { + 'name' => 'wb_send' + } + } + }, + 'sockets' => { + 'ni' => { + 'connection_num' => 'single connection', + 'value' => 1, + 'type' => 'num', + 'ni' => {}, + '0' => { + 'name' => 'ni' + } + } + }, + 'unused' => { + 'plug:wb_master[1]' => [ + 'bte_o', + 'dat_i', + 'err_i', + 'tag_o', + 'rty_i' + ], + 'plug:wb_slave[0]' => [ + 'tag_i', + 'err_o', + 'rty_o', + 'bte_i' + ], + 'plug:wb_master[0]' => [ + 'bte_o', + 'err_i', + 'tag_o', + 'dat_o', + 'rty_i' + ] + }, + 'ip_name' => 'ni_master', + 'description' => '', + 'hdl_files' => [ + '/mpsoc/src_noc/arbiter.v', + '/mpsoc/src_noc/flit_buffer.v', + '/mpsoc/src_noc/input_ports.v', + '/mpsoc/src_noc/main_comp.v', + '/mpsoc/src_noc/route_mesh.v', + '/mpsoc/src_noc/route_torus.v', + '/mpsoc/src_noc/routing.v', + '/mpsoc/src_peripheral/ni/ni_vc_dma.v', + '/mpsoc/src_peripheral/ni/ni_vc_wb_slave_regs.v', + '/mpsoc/src_peripheral/ni/ni_master.v', + '/mpsoc/src_peripheral/ni/ni_crc32.v' + ], + 'parameters' => { + 'B' => { + 'global_param' => 'Parameter', + 'type' => 'Fixed', + 'content' => '', + 'deafult' => ' 4', + 'redefine_param' => 1, + 'info' => 'Parameter' + }, + 'CRC_EN' => { + 'redefine_param' => 1, + 'deafult' => '"NO"', + 'content' => '"YES","NO"', + 'info' => 'The parameter can be selected as "YES" or "NO". +If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ', + 'global_param' => 'Localparam', + 'type' => 'Combo-box' + }, + 'DEBUG_EN' => { + 'type' => 'Fixed', + 'global_param' => 'Parameter', + 'info' => 'Parameter', + 'deafult' => ' 1', + 'content' => '', + 'redefine_param' => 1 + }, + 'Yw' => { + 'info' => undef, + 'redefine_param' => 0, + 'content' => '', + 'deafult' => 'log2(NY)', + 'type' => 'Fixed', + 'global_param' => 'Localparam' + }, + 'NY' => { + 'info' => 'Parameter', + 'redefine_param' => 1, + 'deafult' => ' 4', + 'content' => '', + 'type' => 'Fixed', + 'global_param' => 'Parameter' + }, + 'C' => { + 'type' => 'Fixed', + 'global_param' => 'Parameter', + 'info' => 'Parameter', + 'content' => '', + 'deafult' => ' 4', + 'redefine_param' => 1 + }, + 'SELw' => { + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'redefine_param' => 1, + 'content' => '', + 'deafult' => '4', + 'info' => 'Parameter' + }, + 'Fpay' => { + 'redefine_param' => 1, + 'deafult' => ' 32', + 'content' => '', + 'info' => 'Parameter', + 'global_param' => 'Parameter', + 'type' => 'Fixed' + }, + 'MAX_TRANSACTION_WIDTH' => { + 'info' => 'maximum packet size width in words. +The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.', + 'content' => '4,32,1', + 'deafult' => '13', + 'redefine_param' => 1, + 'type' => 'Spin-button', + 'global_param' => 'Localparam' + }, + 'SRC_ADR_HDR_WIDTH' => { + 'redefine_param' => 1, + 'content' => '', + 'deafult' => '8', + 'info' => 'Parameter', + 'global_param' => 'Localparam', + 'type' => 'Fixed' + }, + 'ROUTING_HDR_WIDTH' => { + 'type' => 'Fixed', + 'global_param' => 'Localparam', + 'info' => 'Parameter', + 'content' => '', + 'deafult' => '8', + 'redefine_param' => 1 + }, + 'Fw' => { + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'redefine_param' => 0, + 'deafult' => '2+V+Fpay', + 'content' => '', + 'info' => undef + }, + 'DST_ADR_HDR_WIDTH' => { + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'redefine_param' => 1, + 'deafult' => '8', + 'content' => '', + 'info' => 'Parameter' + }, + 'Xw' => { + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'deafult' => 'log2(NX)', + 'content' => '', + 'redefine_param' => 0, + 'info' => undef + }, + 'M_Aw' => { + 'redefine_param' => 1, + 'deafult' => '32', + 'content' => 'Dw', + 'info' => 'Parameter', + 'global_param' => 'Localparam', + 'type' => 'Fixed' + }, + 'P' => { + 'global_param' => 'Parameter', + 'type' => 'Fixed', + 'redefine_param' => 1, + 'deafult' => '5', + 'content' => '', + 'info' => 'Parameter' + }, + 'ROUTE_TYPE' => { + 'info' => 'Parameter', + 'redefine_param' => 1, + 'deafult' => ' ', + 'content' => '', + 'type' => 'Fixed', + 'global_param' => 'Parameter' + }, + 'MAX_BURST_SIZE' => { + 'type' => 'Combo-box', + 'global_param' => 'Localparam', + 'info' => 'Maximum burst size in words. +The NI release wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ', + 'redefine_param' => 1, + 'content' => '2,4,8,16,32,64,128,256,512,1024,2048', + 'deafult' => '16' + }, + 'Dw' => { + 'type' => 'Spin-button', + 'global_param' => 'Localparam', + 'info' => 'wishbone_bus data width in bits.', + 'redefine_param' => 1, + 'content' => '32,256,8', + 'deafult' => '32' + }, + 'ROUTE_NAME' => { + 'deafult' => '"XY" ', + 'content' => '', + 'redefine_param' => 1, + 'info' => 'Parameter', + 'global_param' => 'Parameter', + 'type' => 'Fixed' + }, + 'NX' => { + 'content' => '', + 'deafult' => ' 4', + 'redefine_param' => 1, + 'info' => 'Parameter', + 'global_param' => 'Parameter', + 'type' => 'Fixed' + }, + 'CLASS_HDR_WIDTH' => { + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'redefine_param' => 1, + 'deafult' => '8', + 'content' => '', + 'info' => 'Parameter' + }, + 'TOPOLOGY' => { + 'info' => 'Parameter', + 'redefine_param' => 1, + 'content' => '', + 'deafult' => '"MESH"', + 'type' => 'Fixed', + 'global_param' => 'Parameter' + }, + 'S_Aw' => { + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'redefine_param' => 1, + 'content' => '', + 'deafult' => '8', + 'info' => 'Parameter' + }, + 'V' => { + 'global_param' => 'Parameter', + 'type' => 'Fixed', + 'content' => '', + 'deafult' => '4', + 'redefine_param' => 1, + 'info' => 'Parameter' + }, + 'TAGw' => { + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'deafult' => '3', + 'content' => '', + 'redefine_param' => 1, + 'info' => 'Parameter' + } + }, + 'version' => 37, + 'category' => 'NoC', + 'description_pdf' => '/mpsoc/src_peripheral/ni/NI_master.pdf', + 'ports' => { + 's_addr_i' => { + 'range' => 'S_Aw-1 : 0', + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'adr_i' + }, + 'm_send_cti_o' => { + 'intfc_port' => 'cti_o', + 'intfc_name' => 'plug:wb_master[0]', + 'type' => 'output', + 'range' => 'TAGw-1 : 0' + }, + 'm_send_sel_o' => { + 'type' => 'output', + 'intfc_port' => 'sel_o', + 'intfc_name' => 'plug:wb_master[0]', + 'range' => 'SELw-1 : 0' + }, + 'm_receive_ack_i' => { + 'range' => '', + 'type' => 'input', + 'intfc_name' => 'plug:wb_master[1]', + 'intfc_port' => 'ack_i' + }, + 'm_send_cyc_o' => { + 'range' => '', + 'type' => 'output', + 'intfc_port' => 'cyc_o', + 'intfc_name' => 'plug:wb_master[0]' + }, + 'm_receive_sel_o' => { + 'range' => 'SELw-1 : 0', + 'type' => 'output', + 'intfc_port' => 'sel_o', + 'intfc_name' => 'plug:wb_master[1]' + }, + 's_dat_i' => { + 'type' => 'input', + 'intfc_port' => 'dat_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => 'Dw-1 : 0' + }, + 'flit_out' => { + 'range' => 'Fw-1 : 0', + 'type' => 'output', + 'intfc_name' => 'socket:ni[0]', + 'intfc_port' => 'flit_out' + }, + 'm_receive_cyc_o' => { + 'intfc_name' => 'plug:wb_master[1]', + 'intfc_port' => 'cyc_o', + 'type' => 'output', + 'range' => '' + }, + 'current_x' => { + 'range' => 'Xw-1 : 0', + 'type' => 'input', + 'intfc_port' => 'current_x', + 'intfc_name' => 'socket:ni[0]' + }, + 'm_receive_we_o' => { + 'intfc_port' => 'we_o', + 'intfc_name' => 'plug:wb_master[1]', + 'type' => 'output', + 'range' => '' + }, + 'flit_out_wr' => { + 'range' => '', + 'intfc_name' => 'socket:ni[0]', + 'intfc_port' => 'flit_out_wr', + 'type' => 'output' + }, + 's_cyc_i' => { + 'intfc_port' => 'cyc_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input', + 'range' => '' + }, + 'm_receive_addr_o' => { + 'range' => 'M_Aw-1 : 0', + 'type' => 'output', + 'intfc_name' => 'plug:wb_master[1]', + 'intfc_port' => 'adr_o' + }, + 's_sel_i' => { + 'range' => 'SELw-1 : 0', + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'sel_i' + }, + 'm_send_ack_i' => { + 'type' => 'input', + 'intfc_port' => 'ack_i', + 'intfc_name' => 'plug:wb_master[0]', + 'range' => '' + }, + 'reset' => { + 'type' => 'input', + 'intfc_name' => 'plug:reset[0]', + 'intfc_port' => 'reset_i', + 'range' => '' + }, + 'm_send_stb_o' => { + 'range' => '', + 'intfc_name' => 'plug:wb_master[0]', + 'intfc_port' => 'stb_o', + 'type' => 'output' + }, + 'm_send_dat_i' => { + 'intfc_port' => 'dat_i', + 'intfc_name' => 'plug:wb_master[0]', + 'type' => 'input', + 'range' => 'Dw-1 : 0' + }, + 'credit_in' => { + 'type' => 'input', + 'intfc_name' => 'socket:ni[0]', + 'intfc_port' => 'credit_in', + 'range' => 'V-1 : 0' + }, + 'irq' => { + 'range' => '', + 'type' => 'output', + 'intfc_port' => 'int_o', + 'intfc_name' => 'plug:interrupt_peripheral[0]' + }, + 's_stb_i' => { + 'range' => '', + 'type' => 'input', + 'intfc_port' => 'stb_i', + 'intfc_name' => 'plug:wb_slave[0]' + }, + 'm_send_we_o' => { + 'range' => '', + 'intfc_name' => 'plug:wb_master[0]', + 'intfc_port' => 'we_o', + 'type' => 'output' + }, + 'flit_in' => { + 'range' => 'Fw-1 : 0', + 'type' => 'input', + 'intfc_name' => 'socket:ni[0]', + 'intfc_port' => 'flit_in' + }, + 'm_send_addr_o' => { + 'intfc_port' => 'adr_o', + 'intfc_name' => 'plug:wb_master[0]', + 'type' => 'output', + 'range' => 'M_Aw-1 : 0' + }, + 'credit_out' => { + 'range' => 'V-1 : 0', + 'type' => 'output', + 'intfc_port' => 'credit_out', + 'intfc_name' => 'socket:ni[0]' + }, + 'm_receive_stb_o' => { + 'intfc_name' => 'plug:wb_master[1]', + 'intfc_port' => 'stb_o', + 'type' => 'output', + 'range' => '' + }, + 'clk' => { + 'range' => '', + 'intfc_name' => 'plug:clk[0]', + 'intfc_port' => 'clk_i', + 'type' => 'input' + }, + 's_we_i' => { + 'intfc_port' => 'we_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input', + 'range' => '' + }, + 's_ack_o' => { + 'intfc_port' => 'ack_o', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'output', + 'range' => '' + }, + 'm_receive_cti_o' => { + 'range' => 'TAGw-1 : 0', + 'type' => 'output', + 'intfc_port' => 'cti_o', + 'intfc_name' => 'plug:wb_master[1]' + }, + 's_cti_i' => { + 'range' => 'TAGw-1 : 0', + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'cti_i' + }, + 'current_y' => { + 'range' => 'Yw-1 : 0', + 'type' => 'input', + 'intfc_port' => 'current_y', + 'intfc_name' => 'socket:ni[0]' + }, + 's_dat_o' => { + 'range' => 'Dw-1 : 0', + 'intfc_port' => 'dat_o', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'output' + }, + 'flit_in_wr' => { + 'type' => 'input', + 'intfc_name' => 'socket:ni[0]', + 'intfc_port' => 'flit_in_wr', + 'range' => '' + }, + 'm_receive_dat_o' => { + 'range' => 'Dw-1 : 0', + 'intfc_port' => 'dat_o', + 'intfc_name' => 'plug:wb_master[1]', + 'type' => 'output' + } + }, + 'modules' => { + 'ni_vc_dma' => {}, + 'header_flit_generator' => {}, + 'ni_master' => {}, + 'ovc_status' => {}, + 'vc_wb_slave_registers' => {} + }, + 'gui_status' => { + 'timeout' => 0, + 'status' => 'ideal' + }, + 'system_h' => ' /* NI wb registers addresses + 0 : STATUS1_WB_ADDR // status1: {send_enable_binarry,receive_enable_binarry,send_vc_is_busy,receive_vc_is_busy,receive_vc_got_packet} + 1 : STATUS2_WB_ADDR // status2: + 2 : BURST_SIZE_WB_ADDR // The busrt size in words + + 3 : SEND_DATA_SIZE_WB_ADDR, // The size of data to be sent in byte + 4 : SEND_STRT_WB_ADDR, // The address of data to be sent in byte + 5 : SEND_DEST_WB_ADDR // The destination router address + 6 : SEND_CTRL_WB_ADDR + + 7 : RECEIVE_DATA_SIZE_WB_ADDR // The size of recieved data in byte + 8 : RECEIVE_STRT_WB_ADDR // The address pointer of reciever memory in byte + 9 : RECEIVE_SRC_WB_ADDR // The source router (the router which is sent this packet). + 10 : RECEIVE_CTRL_WB_ADDR // The NI reciever control register + 11 : RECEIVE_MAX_BUFF_SIZ // The receiver\'s allocated buffer size in words. If the packet size is bigger tha the buffer size the rest of will be discarred + +*/ + + + +#define ${IP}_STATUS1_REG (*((volatile unsigned int *) ($BASE))) //0 +#define ${IP}_STATUS2_REG (*((volatile unsigned int *) ($BASE+4))) //1 +#define ${IP}_BURST_SIZE_REG (*((volatile unsigned int *) ($BASE+8))) //2 + + +#define ${IP}_NUM_VCs ${V} + +#define ${IP}_SEND_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+12+(v<<6)))) //3 +#define ${IP}_SEND_START_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+16+(v<<6)))) //4 +#define ${IP}_SEND_DEST_REG(v) (*((volatile unsigned int *) ($BASE+20+(v<<6)))) //5 +#define ${IP}_SEND_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+24+(v<<6)))) //6 + +#define ${IP}_RECEIVE_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+28+(v<<6)))) //7 +#define ${IP}_RECEIVE_STRT_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+32+(v<<6)))) //8 +#define ${IP}_RECEIVE_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+36+(v<<6)))) //9 +#define ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) (*((volatile unsigned int *) ($BASE+40+(v<<6)))) //10 +#define ${IP}_RECEIVE_CRC_MATCH_REG(v) (*((volatile unsigned int *) ($BASE+44+(v<<6)))) //11 + + + +// assign status1= {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet}; +// assign status2= {send_enable_binarry,receive_enable_binarry,crc_miss_match,got_pck_isr, save_done_isr,send_done_isr,got_pck_int_en, save_done_int_en,send_done_int_en}; + + +#define ${IP}_got_packet(v) ((${IP}_STATUS1_REG >> (v)) & 0x1) +#define ${IP}_packet_is_saved(v) ((${IP}_STATUS1_REG >> (${V}+v)) & 0x1) +#define ${IP}_receive_is_busy(v) ((${IP}_STATUS1_REG >> (2*${V}+v)) & 0x1) +#define ${IP}_send_is_busy(v) ((${IP}_STATUS1_REG >> (3*${V}+v)) & 0x1) + + + +void ${IP}_initial (unsigned int burst_size) { + ${IP}_BURST_SIZE_REG = burst_size; +} + + +void ${IP}_transfer (unsigned int v, unsigned int class_num, unsigned int data_start_addr, unsigned int data_size, unsigned int dest_x,unsigned int dest_y){ + while (${IP}_send_is_busy(v)); // wait until VC is busy sending previous packet + + ${IP}_SEND_DATA_SIZE_REG(v) = data_size; + ${IP}_SEND_START_ADDR_REG(v) = data_start_addr; + ${IP}_SEND_DEST_REG(v) = dest_x | (dest_y<<4)| (class_num<<8) ; + +} + +void ${IP}_receive (unsigned int v, unsigned int data_start_addr, unsigned int max_buffer_size){ + while (${IP}_receive_is_busy(v)); // wait until VC is busy saving previous packet + + ${IP}_RECEIVE_STRT_ADDR_REG(v) = data_start_addr; + ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) = max_buffer_size; + ${IP}_RECEIVE_CTRL_REG(v) = 1; + + +}', + 'ports_order' => [ + 'reset', + 'clk', + 'current_x', + 'current_y', + 'flit_out', + 'flit_out_wr', + 'credit_in', + 'flit_in', + 'flit_in_wr', + 'credit_out', + 's_dat_i', + 's_sel_i', + 's_addr_i', + 's_cti_i', + 's_stb_i', + 's_cyc_i', + 's_we_i', + 's_dat_o', + 's_ack_o', + 'm_send_sel_o', + 'm_send_addr_o', + 'm_send_cti_o', + 'm_send_stb_o', + 'm_send_cyc_o', + 'm_send_we_o', + 'm_send_dat_i', + 'm_send_ack_i', + 'm_receive_sel_o', + 'm_receive_dat_o', + 'm_receive_addr_o', + 'm_receive_cti_o', + 'm_receive_stb_o', + 'm_receive_cyc_o', + 'm_receive_we_o', + 'm_receive_ack_i', + 'irq' + ], + 'module_name' => 'ni_master', + 'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_master.v', + 'parameters_order' => [ + 'CLASS_HDR_WIDTH', + 'ROUTING_HDR_WIDTH', + 'DST_ADR_HDR_WIDTH', + 'SRC_ADR_HDR_WIDTH', + 'TOPOLOGY', + 'ROUTE_NAME', + 'NX', + 'NY', + 'C', + 'V', + 'B', + 'Fpay', + 'MAX_TRANSACTION_WIDTH', + 'MAX_BURST_SIZE', + 'DEBUG_EN', + 'Dw', + 'S_Aw', + 'M_Aw', + 'TAGw', + 'SELw', + 'Xw', + 'Yw', + 'Fw', + 'CRC_EN' + ] + }, 'ip_gen' ); Index: lib/ip/Other/dummy_module.IP =================================================================== --- lib/ip/Other/dummy_module.IP (nonexistent) +++ lib/ip/Other/dummy_module.IP (revision 34) @@ -0,0 +1,205 @@ +####################################################################### +## File: dummy_module.IP +## +## Copyright (C) 2014-2016 Alireza Monemi +## +## This file is part of ProNoC 1.6.0 +## +## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT +## MAY CAUSE UNEXPECTED BEHAIVOR. +################################################################################ + +$wb_master_dummy_request = bless( { + 'version' => 1, + 'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/wb_master_dummy_request.v', + 'ip_name' => 'dummy_module', + 'ports' => { + 'clk' => { + 'intfc_name' => 'plug:clk[0]', + 'type' => 'input', + 'range' => '', + 'intfc_port' => 'clk_i' + }, + 'm_rd_addr_o' => { + 'intfc_port' => 'adr_o', + 'type' => 'output', + 'intfc_name' => 'plug:wb_master[0]', + 'range' => 'M_Aw-1 : 0' + }, + 'm_rd_sel_o' => { + 'intfc_port' => 'sel_o', + 'range' => 'SELw-1 : 0', + 'intfc_name' => 'plug:wb_master[0]', + 'type' => 'output' + }, + 'm_rd_we_o' => { + 'range' => '', + 'type' => 'output', + 'intfc_name' => 'plug:wb_master[0]', + 'intfc_port' => 'we_o' + }, + 'reset' => { + 'range' => '', + 'intfc_name' => 'plug:reset[0]', + 'type' => 'input', + 'intfc_port' => 'reset_i' + }, + 'm_rd_cyc_o' => { + 'range' => '', + 'type' => 'output', + 'intfc_name' => 'plug:wb_master[0]', + 'intfc_port' => 'cyc_o' + }, + 'm_rd_cti_o' => { + 'type' => 'output', + 'intfc_name' => 'plug:wb_master[0]', + 'range' => 'TAGw-1 : 0', + 'intfc_port' => 'cti_o' + }, + 'm_rd_ack_i' => { + 'intfc_name' => 'plug:wb_master[0]', + 'type' => 'input', + 'range' => '', + 'intfc_port' => 'ack_i' + }, + 'm_rd_stb_o' => { + 'type' => 'output', + 'intfc_name' => 'plug:wb_master[0]', + 'range' => '', + 'intfc_port' => 'stb_o' + }, + 'm_rd_dat_i' => { + 'type' => 'input', + 'intfc_name' => 'plug:wb_master[0]', + 'range' => 'Dw-1 : 0', + 'intfc_port' => 'dat_i' + } + }, + 'ports_order' => [ + 'clk', + 'reset', + 'm_rd_sel_o', + 'm_rd_addr_o', + 'm_rd_cti_o', + 'm_rd_stb_o', + 'm_rd_cyc_o', + 'm_rd_we_o', + 'm_rd_dat_i', + 'm_rd_ack_i' + ], + 'module_name' => 'wb_master_dummy_request', + 'parameters_order' => [ + 'Dw', + 'S_Aw', + 'M_Aw', + 'TAGw', + 'SELw', + 'REQ_LEN_CLK_NUM', + 'REQ_WAIT_CLK_NUM' + ], + 'description' => 'This module have one wishbone bus master port which is used for readding wishbone address zero for predefined clock cycle num that can be set using "REQ_LEN_CLK_NUM" parameter. Then it will remain deactivate for another predefined clock cycle num that can be set using "REQ_WAIT_CLK_NUM". I wrote this module just for testing a processing tile. ', + 'plugs' => { + 'wb_master' => { + 'wb_master' => {}, + '0' => { + 'name' => 'wb_master' + }, + 'value' => 1, + 'type' => 'num' + }, + 'clk' => { + '0' => { + 'name' => 'clk' + }, + 'value' => 1, + 'clk' => {}, + 'type' => 'num' + }, + 'reset' => { + 'value' => 1, + '0' => { + 'name' => 'reset' + }, + 'reset' => {}, + 'type' => 'num' + } + }, + 'parameters' => { + 'S_Aw' => { + 'deafult' => ' 7', + 'type' => 'Fixed', + 'info' => 'Parameter', + 'redefine_param' => 1, + 'global_param' => 'Parameter', + 'content' => '' + }, + 'REQ_LEN_CLK_NUM' => { + 'type' => 'Spin-button', + 'deafult' => ' 10', + 'info' => 'Parameter', + 'content' => '1,100000,1', + 'global_param' => 'Parameter', + 'redefine_param' => 1 + }, + 'TAGw' => { + 'info' => 'Parameter', + 'type' => 'Fixed', + 'deafult' => ' 3', + 'global_param' => 'Parameter', + 'redefine_param' => 1, + 'content' => '' + }, + 'M_Aw' => { + 'global_param' => 'Parameter', + 'redefine_param' => 1, + 'content' => '', + 'deafult' => ' 32', + 'type' => 'Fixed', + 'info' => 'Parameter' + }, + 'REQ_WAIT_CLK_NUM' => { + 'info' => 'Parameter', + 'type' => 'Spin-button', + 'deafult' => ' 20', + 'global_param' => 'Parameter', + 'redefine_param' => 1, + 'content' => '1,100000,1' + }, + 'SELw' => { + 'info' => 'Parameter', + 'type' => 'Fixed', + 'deafult' => ' 4', + 'redefine_param' => 1, + 'global_param' => 'Parameter', + 'content' => '' + }, + 'Dw' => { + 'global_param' => 'Parameter', + 'redefine_param' => 1, + 'content' => '', + 'type' => 'Fixed', + 'deafult' => ' 32', + 'info' => 'Parameter' + } + }, + 'modules' => { + 'wb_master_dummy_request' => {} + }, + 'gui_status' => { + 'timeout' => 0, + 'status' => 'ideal' + }, + 'hdl_files' => [ + '/mpsoc/src_peripheral/Other/wb_master_dummy_request.v' + ], + 'category' => 'Other', + 'unused' => { + 'plug:wb_master[0]' => [ + 'dat_o', + 'tag_o', + 'rty_i', + 'bte_o', + 'err_i' + ] + } + }, 'ip_gen' ); Index: lib/ip/Other/sim_uart.IP =================================================================== --- lib/ip/Other/sim_uart.IP (nonexistent) +++ lib/ip/Other/sim_uart.IP (revision 34) @@ -0,0 +1,229 @@ +####################################################################### +## File: sim_uart.IP +## +## Copyright (C) 2014-2016 Alireza Monemi +## +## This file is part of ProNoC 1.7.0 +## +## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT +## MAY CAUSE UNEXPECTED BEHAIVOR. +################################################################################ + +$simulator_UART = bless( { + 'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/Other/simulator_UART.v', + 'gui_status' => { + 'status' => 'ideal', + 'timeout' => 0 + }, + 'version' => 6, + 'modules' => { + 'simulator_UART' => {} + }, + 'ports' => { + 's_stb_i' => { + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'stb_i', + 'range' => '', + 'type' => 'input' + }, + 's_cyc_i' => { + 'type' => 'input', + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'cyc_i' + }, + 's_sel_i' => { + 'intfc_port' => 'sel_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input', + 'range' => 'SELw-1 : 0' + }, + 'reset' => { + 'range' => '', + 'type' => 'input', + 'intfc_name' => 'plug:reset[0]', + 'intfc_port' => 'reset_i' + }, + 's_cti_i' => { + 'intfc_port' => 'cti_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input', + 'range' => 'TAGw-1 : 0' + }, + 's_dat_i' => { + 'intfc_port' => 'dat_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input', + 'range' => 'Dw-1 : 0' + }, + 's_ack_o' => { + 'intfc_port' => 'ack_o', + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '', + 'type' => 'output' + }, + 's_addr_i' => { + 'intfc_port' => 'adr_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input', + 'range' => 'S_Aw-1 : 0' + }, + 's_dat_o' => { + 'range' => 'Dw-1 : 0', + 'type' => 'output', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'dat_o' + }, + 's_we_i' => { + 'intfc_port' => 'we_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'range' => '', + 'type' => 'input' + }, + 'clk' => { + 'intfc_port' => 'clk_i', + 'intfc_name' => 'plug:clk[0]', + 'range' => '', + 'type' => 'input' + } + }, + 'unused' => { + 'plug:wb_slave[0]' => [ + 'tag_i', + 'bte_i', + 'rty_o', + 'err_o' + ] + }, + 'description' => 'A simple uart that display input characters on simulator terminal using $write command. +', + 'parameters_order' => [ + 'Dw', + 'S_Aw', + 'M_Aw', + 'TAGw', + 'SELw', + 'BUFFER_SIZE', + 'WAIT_COUNT' + ], + 'plugs' => { + 'reset' => { + 'value' => 1, + 'reset' => {}, + '0' => { + 'name' => 'reset' + }, + 'type' => 'num' + }, + 'clk' => { + 'type' => 'num', + 'clk' => {}, + '0' => { + 'name' => 'clk' + }, + 'value' => 1 + }, + 'wb_slave' => { + 'wb_slave' => {}, + 'type' => 'num', + '0' => { + 'width' => 1, + 'name' => 'wb_slave', + 'addr' => '0xa500_0000 0xa5ff_ffff Debug' + }, + 'value' => 1 + } + }, + 'ip_name' => 'sim_uart', + 'ports_order' => [ + 'reset', + 'clk', + 's_dat_i', + 's_sel_i', + 's_addr_i', + 's_cti_i', + 's_stb_i', + 's_cyc_i', + 's_we_i', + 's_dat_o', + 's_ack_o' + ], + 'hdl_files' => [ + '/mpsoc/src_peripheral/Other/simulator_UART.v' + ], + 'system_h' => '#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE))) + +void ${IP}_putchar(char ch){ //print one char from jtag_uart + ${IP}_DATA_REG=ch; +} + + +void ${IP}_putstring (char * buffer, char sz){ + while (sz){ + ${IP}_putchar(*buffer); + *buffer++; + sz--; + } +} +', + 'category' => 'Other', + 'parameters' => { + 'SELw' => { + 'content' => '', + 'type' => 'Fixed', + 'global_param' => 'Localparam', + 'info' => 'Parameter', + 'redefine_param' => 1, + 'deafult' => ' 4' + }, + 'S_Aw' => { + 'deafult' => ' 7', + 'redefine_param' => 1, + 'info' => 'Parameter', + 'content' => '', + 'type' => 'Fixed', + 'global_param' => 'Localparam' + }, + 'M_Aw' => { + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'content' => '', + 'info' => 'Parameter', + 'deafult' => ' 32' + }, + 'WAIT_COUNT' => { + 'deafult' => '1000', + 'info' => 'If internal buffer has a data, the internal module timer starts counting up in each clock cycle. If Timer reach the WAIT_COUNT value, it writes the buffer vakue on simulator terminal.', + 'global_param' => 'Localparam', + 'type' => 'Spin-button', + 'content' => '2,100000,1', + 'redefine_param' => 1 + }, + 'Dw' => { + 'redefine_param' => 1, + 'content' => '', + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'info' => 'Parameter', + 'deafult' => ' 32' + }, + 'BUFFER_SIZE' => { + 'info' => 'Internal buffer size ', + 'content' => '2,1000,1', + 'global_param' => 'Localparam', + 'type' => 'Spin-button', + 'redefine_param' => 1, + 'deafult' => '100' + }, + 'TAGw' => { + 'deafult' => ' 3', + 'redefine_param' => 1, + 'content' => '', + 'type' => 'Fixed', + 'global_param' => 'Localparam', + 'info' => 'Parameter' + } + }, + 'module_name' => 'simulator_UART' + }, 'ip_gen' ); Index: lib/ip/RAM/dual_port_ram.IP =================================================================== --- lib/ip/RAM/dual_port_ram.IP (revision 33) +++ lib/ip/RAM/dual_port_ram.IP (revision 34) @@ -3,7 +3,7 @@ ## ## Copyright (C) 2014-2016 Alireza Monemi ## -## This file is part of ProNoC 1.5.0 +## This file is part of ProNoC 1.6.0 ## ## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ## MAY CAUSE UNEXPECTED BEHAIVOR. @@ -16,332 +16,345 @@ '/mpsoc/src_peripheral/ram/wb_dual_port_ram.v', '/mpsoc/src_peripheral/ram/wb_bram_ctrl.v' ], - 'description' => 'Dual port ram.', - 'ip_name' => 'dual_port_ram', - 'parameters' => { - 'SELw' => { - 'info' => 'Parameter', - 'deafult' => 'Dw/8', - 'global_param' => 'Localparam', - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - }, - 'PORT_B_BURST_MODE' => { - 'info' => 'wisbone bus burst mode ebable/disable on port B', - 'deafult' => '"DISABLED"', - 'global_param' => 'Don\'t include', - 'content' => '"DISABLED","ENABLED" ', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'Dw' => { - 'info' => 'Ram data width in Bits', - 'deafult' => '32', - 'global_param' => 'Localparam', - 'content' => '4,1024,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - }, - 'BTEw' => { - 'info' => 'Parameter', - 'deafult' => '2', - 'global_param' => 'Localparam', - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - }, - 'WB_Aw' => { - 'info' => 'Wishbone bus address width in byte', - 'deafult' => 'Aw+2', - 'global_param' => 'Don\'t include', - 'content' => '', - 'redefine_param' => 0, - 'type' => 'Fixed' - }, - 'RAM_INDEX' => { - 'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only. - -', - 'deafult' => 'CORE_ID', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Entry' - }, - 'Aw' => { - 'info' => 'Ram address width', - 'deafult' => '12', - 'global_param' => 'Localparam', - 'content' => '2,31,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - }, - 'TAGw' => { - 'info' => 'Parameter', - 'deafult' => '3', - 'global_param' => 'Localparam', - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - }, - 'PORT_A_BURST_MODE' => { - 'info' => ' wisbone bus burst mode enable/disable on port A', - 'deafult' => '"DISABLED"', - 'global_param' => 'Localparam', - 'content' => '"DISABLED","ENABLED"', - 'redefine_param' => 1, - 'type' => 'Combo-box' - }, - 'BYTE_WR_EN' => { - 'info' => 'Parameter', - 'deafult' => '"YES"', - 'global_param' => 'Localparam', - 'content' => '"YES","NO"', - 'redefine_param' => 1, - 'type' => 'Combo-box' - }, - 'CTIw' => { - 'info' => 'Parameter', - 'deafult' => '3', - 'global_param' => 'Localparam', - 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 - }, - 'FPGA_VENDOR' => { - 'info' => 'Parameter', - 'deafult' => '"ALTERA"', - 'global_param' => 'Localparam', - 'content' => '"ALTERA","GENERIC"', - 'redefine_param' => 1, - 'type' => 'Combo-box' - } - }, - 'gui_status' => { - 'status' => 'ideal', - 'timeout' => 0 - }, + 'module_name' => 'wb_dual_port_ram', + 'category' => 'RAM', 'plugs' => { 'clk' => { 'clk' => {}, 'value' => 1, + 'type' => 'num', '0' => { 'name' => 'clk' - }, - 'type' => 'num' + } }, 'reset' => { - 'reset' => {}, - 'value' => 1, '0' => { 'name' => 'reset' }, - 'type' => 'num' + 'type' => 'num', + 'value' => 1, + 'reset' => {} }, 'wb_slave' => { + 'value' => 2, '1' => { + 'addr' => '0x0000_0000 0x3fff_ffff RAM', 'width' => 'WB_Aw', - 'name' => 'wb_b', - 'addr' => '0x0000_0000 0x3fff_ffff RAM' + 'name' => 'wb_b' }, - 'value' => 2, + 'type' => 'num', + 'wb_slave' => {}, '0' => { + 'addr' => '0x0000_0000 0x3fff_ffff RAM', 'width' => 'WB_Aw', - 'name' => 'wb_a', - 'addr' => '0x0000_0000 0x3fff_ffff RAM' - }, - 'type' => 'num', - 'wb_slave' => {} + 'name' => 'wb_a' + } } }, - 'modules' => { - 'wb_dual_port_ram' => {} - }, 'ports' => { + 'sb_err_o' => { + 'range' => '', + 'intfc_port' => 'err_o', + 'intfc_name' => 'plug:wb_slave[1]', + 'type' => 'output' + }, + 'sa_stb_i' => { + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'stb_i', + 'range' => '' + }, 'sb_addr_i' => { + 'intfc_name' => 'plug:wb_slave[1]', + 'type' => 'input', 'intfc_port' => 'adr_i', - 'intfc_name' => 'plug:wb_slave[1]', - 'range' => 'Aw-1 : 0', - 'type' => 'input' + 'range' => 'Aw-1 : 0' }, - 'sa_tag_i' => { - 'intfc_port' => 'tag_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'TAGw-1 : 0', - 'type' => 'input' + 'sb_rty_o' => { + 'type' => 'output', + 'intfc_name' => 'plug:wb_slave[1]', + 'intfc_port' => 'rty_o', + 'range' => '' }, - 'sa_rty_o' => { - 'intfc_port' => 'rty_o', + 'sb_cyc_i' => { + 'intfc_port' => 'cyc_i', + 'range' => '', + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[1]' + }, + 'sa_we_i' => { + 'intfc_port' => 'we_i', + 'range' => '', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input' + }, + 'sb_we_i' => { + 'intfc_port' => 'we_i', + 'range' => '', + 'intfc_name' => 'plug:wb_slave[1]', + 'type' => 'input' + }, + 'sb_dat_i' => { + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[1]', + 'range' => 'Dw-1 : 0', + 'intfc_port' => 'dat_i' + }, + 'sa_err_o' => { + 'type' => 'output', 'intfc_name' => 'plug:wb_slave[0]', 'range' => '', - 'type' => 'output' + 'intfc_port' => 'err_o' }, - 'sa_sel_i' => { - 'intfc_port' => 'sel_i', - 'intfc_name' => 'plug:wb_slave[0]', + 'sb_sel_i' => { + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[1]', 'range' => 'SELw-1 : 0', - 'type' => 'input' + 'intfc_port' => 'sel_i' }, - 'sa_cti_i' => { + 'sb_ack_o' => { + 'type' => 'output', + 'intfc_name' => 'plug:wb_slave[1]', + 'range' => '', + 'intfc_port' => 'ack_o' + }, + 'sb_cti_i' => { 'intfc_port' => 'cti_i', - 'intfc_name' => 'plug:wb_slave[0]', 'range' => 'CTIw-1 : 0', + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[1]' + }, + 'sb_stb_i' => { + 'intfc_port' => 'stb_i', + 'range' => '', + 'intfc_name' => 'plug:wb_slave[1]', 'type' => 'input' }, - 'sa_bte_i' => { - 'intfc_port' => 'bte_i', + 'sa_cti_i' => { + 'type' => 'input', 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'cti_i', + 'range' => 'CTIw-1 : 0' + }, + 'sb_bte_i' => { + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[1]', 'range' => 'BTEw-1 : 0', - 'type' => 'input' + 'intfc_port' => 'bte_i' }, - 'sa_err_o' => { - 'intfc_port' => 'err_o', + 'sa_rty_o' => { 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'output', 'range' => '', - 'type' => 'output' + 'intfc_port' => 'rty_o' }, - 'sa_cyc_i' => { - 'intfc_port' => 'cyc_i', + 'clk' => { + 'intfc_port' => 'clk_i', + 'range' => '', + 'type' => 'input', + 'intfc_name' => 'plug:clk[0]' + }, + 'sa_dat_o' => { + 'type' => 'output', 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '', - 'type' => 'input' + 'range' => 'Dw-1 : 0', + 'intfc_port' => 'dat_o' }, - 'sb_err_o' => { - 'intfc_port' => 'err_o', - 'intfc_name' => 'plug:wb_slave[1]', + 'sa_dat_i' => { + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'dat_i', + 'range' => 'Dw-1 : 0' + }, + 'sa_bte_i' => { + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input', + 'intfc_port' => 'bte_i', + 'range' => 'BTEw-1 : 0' + }, + 'sa_ack_o' => { 'range' => '', - 'type' => 'output' + 'intfc_port' => 'ack_o', + 'type' => 'output', + 'intfc_name' => 'plug:wb_slave[0]' }, - 'sb_dat_o' => { - 'intfc_port' => 'dat_o', - 'intfc_name' => 'plug:wb_slave[1]', - 'range' => 'Dw-1 : 0', - 'type' => 'output' + 'sa_sel_i' => { + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'sel_i', + 'range' => 'SELw-1 : 0' }, 'reset' => { - 'intfc_port' => 'reset_i', 'intfc_name' => 'plug:reset[0]', + 'type' => 'input', 'range' => '', - 'type' => 'input' + 'intfc_port' => 'reset_i' }, - 'sa_ack_o' => { - 'intfc_port' => 'ack_o', - 'intfc_name' => 'plug:wb_slave[0]', + 'sa_cyc_i' => { 'range' => '', - 'type' => 'output' + 'intfc_port' => 'cyc_i', + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]' }, - 'sb_cti_i' => { - 'intfc_port' => 'cti_i', - 'intfc_name' => 'plug:wb_slave[1]', - 'range' => 'CTIw-1 : 0', - 'type' => 'input' + 'sa_tag_i' => { + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]', + 'intfc_port' => 'tag_i', + 'range' => 'TAGw-1 : 0' }, - 'sb_bte_i' => { - 'intfc_port' => 'bte_i', + 'sb_dat_o' => { + 'type' => 'output', 'intfc_name' => 'plug:wb_slave[1]', - 'range' => 'BTEw-1 : 0', - 'type' => 'input' + 'range' => 'Dw-1 : 0', + 'intfc_port' => 'dat_o' }, - 'sb_cyc_i' => { - 'intfc_port' => 'cyc_i', - 'intfc_name' => 'plug:wb_slave[1]', - 'range' => '', - 'type' => 'input' - }, - 'sb_ack_o' => { - 'intfc_port' => 'ack_o', - 'intfc_name' => 'plug:wb_slave[1]', - 'range' => '', - 'type' => 'output' - }, 'sa_addr_i' => { 'intfc_port' => 'adr_i', - 'intfc_name' => 'plug:wb_slave[0]', 'range' => 'Aw-1 : 0', - 'type' => 'input' + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[0]' }, - 'sb_rty_o' => { - 'intfc_port' => 'rty_o', - 'intfc_name' => 'plug:wb_slave[1]', - 'range' => '', - 'type' => 'output' - }, - 'sb_dat_i' => { - 'intfc_port' => 'dat_i', - 'intfc_name' => 'plug:wb_slave[1]', - 'range' => 'Dw-1 : 0', - 'type' => 'input' - }, - 'sb_we_i' => { - 'intfc_port' => 'we_i', - 'intfc_name' => 'plug:wb_slave[1]', - 'range' => '', - 'type' => 'input' - }, - 'sa_dat_o' => { - 'intfc_port' => 'dat_o', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'Dw-1 : 0', - 'type' => 'output' - }, - 'sb_sel_i' => { - 'intfc_port' => 'sel_i', - 'intfc_name' => 'plug:wb_slave[1]', - 'range' => 'SELw-1 : 0', - 'type' => 'input' - }, - 'sa_dat_i' => { - 'intfc_port' => 'dat_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'Dw-1 : 0', - 'type' => 'input' - }, - 'sa_we_i' => { - 'intfc_port' => 'we_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '', - 'type' => 'input' - }, - 'clk' => { - 'intfc_port' => 'clk_i', - 'intfc_name' => 'plug:clk[0]', - 'range' => '', - 'type' => 'input' - }, 'sb_tag_i' => { 'intfc_port' => 'tag_i', - 'intfc_name' => 'plug:wb_slave[1]', 'range' => 'TAGw-1 : 0', - 'type' => 'input' - }, - 'sb_stb_i' => { - 'intfc_port' => 'stb_i', - 'intfc_name' => 'plug:wb_slave[1]', - 'range' => '', - 'type' => 'input' - }, - 'sa_stb_i' => { - 'intfc_port' => 'stb_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '', - 'type' => 'input' + 'type' => 'input', + 'intfc_name' => 'plug:wb_slave[1]' } }, - 'parameters_order' => [ - 'Dw', - 'Aw', - 'BYTE_WR_EN', - 'FPGA_VENDOR', - 'TAGw', - 'SELw', - 'CTIw', - 'BTEw', - 'WB_Aw', - 'RAM_INDEX', - 'PORT_A_BURST_MODE', - 'PORT_B_BURST_MODE' - ], + 'description' => 'Dual port ram.', + 'parameters' => { + 'WB_Aw' => { + 'type' => 'Fixed', + 'redefine_param' => 0, + 'info' => 'Wishbone bus address width in byte', + 'content' => '', + 'deafult' => 'Aw+2', + 'global_param' => 'Don\'t include' + }, + 'BTEw' => { + 'info' => 'Parameter', + 'content' => '', + 'type' => 'Fixed', + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'deafult' => '2' + }, + 'MEM_CONTENT_FILE_NAME' => { + 'type' => 'Entry', + 'redefine_param' => 1, + 'content' => '', + 'info' => 'MEM_FILE_NAME: +The memory file name (without file type extension ) that is used for writting the memory content at initialization time. + +File Path: +For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}. +For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME} + +file_type: +memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command. +mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ', + 'deafult' => '"ram0"', + 'global_param' => 'Localparam' + }, + 'TAGw' => { + 'info' => 'Parameter', + 'content' => '', + 'type' => 'Fixed', + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'deafult' => '3' + }, + 'CTIw' => { + 'redefine_param' => 1, + 'type' => 'Fixed', + 'content' => '', + 'info' => 'Parameter', + 'deafult' => '3', + 'global_param' => 'Localparam' + }, + 'INIT_FILE_PATH' => { + 'redefine_param' => 1, + 'type' => 'Fixed', + 'info' => undef, + 'content' => '', + 'deafult' => 'SW_LOC', + 'global_param' => 'Don\'t include' + }, + 'Aw' => { + 'deafult' => '12', + 'global_param' => 'Localparam', + 'type' => 'Spin-button', + 'redefine_param' => 1, + 'info' => 'Ram address width', + 'content' => '2,31,1' + }, + 'INITIAL_EN' => { + 'type' => 'Combo-box', + 'redefine_param' => 1, + 'info' => 'If selected as "YES", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', + 'content' => '"YES","NO"', + 'deafult' => '"NO"', + 'global_param' => 'Localparam' + }, + 'RAM_INDEX' => { + 'deafult' => 'CORE_ID', + 'global_param' => 'Localparam', + 'redefine_param' => 1, + 'type' => 'Entry', + 'content' => '', + 'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only. + +' + }, + 'SELw' => { + 'deafult' => 'Dw/8', + 'global_param' => 'Localparam', + 'redefine_param' => 1, + 'type' => 'Fixed', + 'info' => 'Parameter', + 'content' => '' + }, + 'Dw' => { + 'redefine_param' => 1, + 'type' => 'Spin-button', + 'content' => '4,1024,1', + 'info' => 'Ram data width in Bits', + 'deafult' => '32', + 'global_param' => 'Localparam' + }, + 'PORT_B_BURST_MODE' => { + 'info' => 'wisbone bus burst mode ebable/disable on port B', + 'content' => '"DISABLED","ENABLED" ', + 'redefine_param' => 1, + 'type' => 'Fixed', + 'global_param' => 'Localparam', + 'deafult' => '"ENABLED"' + }, + 'BYTE_WR_EN' => { + 'content' => '"YES","NO"', + 'info' => 'Parameter', + 'type' => 'Combo-box', + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'deafult' => '"YES"' + }, + 'PORT_A_BURST_MODE' => { + 'deafult' => '"ENABLED"', + 'global_param' => 'Localparam', + 'redefine_param' => 1, + 'type' => 'Combo-box', + 'content' => '"DISABLED","ENABLED"', + 'info' => ' wisbone bus burst mode enable/disable on port A' + }, + 'FPGA_VENDOR' => { + 'redefine_param' => 1, + 'type' => 'Combo-box', + 'content' => '"ALTERA","GENERIC"', + 'info' => 'Parameter', + 'deafult' => '"GENERIC"', + 'global_param' => 'Localparam' + } + }, 'ports_order' => [ 'clk', 'reset', @@ -372,8 +385,32 @@ 'sb_err_o', 'sb_rty_o' ], - 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_dual_port_ram.v', - 'module_name' => 'wb_dual_port_ram', + 'version' => 6, + 'gui_status' => { + 'timeout' => 0, + 'status' => 'ideal' + }, + 'parameters_order' => [ + 'Dw', + 'Aw', + 'BYTE_WR_EN', + 'FPGA_VENDOR', + 'TAGw', + 'SELw', + 'CTIw', + 'BTEw', + 'WB_Aw', + 'RAM_INDEX', + 'PORT_A_BURST_MODE', + 'PORT_B_BURST_MODE', + 'INITIAL_EN', + 'MEM_CONTENT_FILE_NAME', + 'INIT_FILE_PATH' + ], 'unused' => undef, - 'category' => 'RAM' + 'ip_name' => 'dual_port_ram', + 'modules' => { + 'wb_dual_port_ram' => {} + }, + 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_dual_port_ram.v' }, 'ip_gen' ); Index: lib/ip/RAM/single_port_ram.IP =================================================================== --- lib/ip/RAM/single_port_ram.IP (revision 33) +++ lib/ip/RAM/single_port_ram.IP (revision 34) @@ -3,7 +3,7 @@ ## ## Copyright (C) 2014-2016 Alireza Monemi ## -## This file is part of ProNoC 1.5.0 +## This file is part of ProNoC 1.6.0 ## ## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ## MAY CAUSE UNEXPECTED BEHAIVOR. @@ -10,187 +10,240 @@ ################################################################################ $wb_single_port_ram = bless( { - 'hdl_files' => [ - '/mpsoc/src_peripheral/ram/wb_single_port_ram.v', - '/mpsoc/src_peripheral/ram/generic_ram.v', - '/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv', - '/mpsoc/src_peripheral/ram/wb_bram_ctrl.v' - ], - 'ip_name' => 'single_port_ram', - 'description' => 'Single port ram with wishbone bus interface.', 'modules' => { 'wb_single_port_ram' => {} }, - 'gui_status' => { - 'timeout' => 0, - 'status' => 'ideal' - }, + 'module_name' => 'wb_single_port_ram', + 'version' => 19, + 'category' => 'RAM', + 'description' => 'Single port ram with wishbone bus interface.', 'plugs' => { 'reset' => { + 'value' => 1, 'reset' => {}, - 'value' => 1, + 'type' => 'num', '0' => { 'name' => 'reset' - }, - 'type' => 'num' + } }, - 'clk' => { - 'clk' => {}, - 'value' => 1, - '0' => { - 'name' => 'clk' - }, - 'type' => 'num' - }, 'wb_slave' => { + 'value' => 1, + 'type' => 'num', '0' => { + 'name' => 'wb', 'width' => 'WB_Aw', - 'name' => 'wb', 'addr' => '0x0000_0000 0x3fff_ffff RAM' }, - 'value' => 1, - 'type' => 'num', 'wb_slave' => {} - } + }, + 'clk' => { + 'type' => 'num', + '0' => { + 'name' => 'clk' + }, + 'value' => 1, + 'clk' => {} + } }, + 'unused' => undef, + 'ip_name' => 'single_port_ram', + 'hdl_files' => [ + '/mpsoc/src_peripheral/ram/wb_single_port_ram.v', + '/mpsoc/src_peripheral/ram/generic_ram.v', + '/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv', + '/mpsoc/src_peripheral/ram/wb_bram_ctrl.v' + ], + 'parameters_order' => [ + 'Dw', + 'Aw', + 'BYTE_WR_EN', + 'FPGA_VENDOR', + 'JTAG_CONNECT', + 'JTAG_INDEX', + 'TAGw', + 'SELw', + 'CTIw', + 'BTEw', + 'WB_Aw', + 'BURST_MODE', + 'MEM_CONTENT_FILE_NAME', + 'INITIAL_EN', + 'INIT_FILE_PATH' + ], + 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v', + 'gui_status' => { + 'timeout' => 0, + 'status' => 'ideal' + }, 'parameters' => { 'SELw' => { - 'info' => 'Parameter', - 'deafult' => 'Dw/8', 'global_param' => 'Localparam', - 'content' => '', 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'Dw' => { - 'info' => 'Memory data width in Bits.', - 'deafult' => '32', - 'global_param' => 'Parameter', - 'content' => '8,1024,1', - 'redefine_param' => 1, - 'type' => 'Spin-button' - }, - 'BTEw' => { - 'info' => 'Parameter', - 'deafult' => '2', - 'global_param' => 'Localparam', + 'type' => 'Fixed', 'content' => '', - 'type' => 'Fixed', - 'redefine_param' => 1 + 'deafult' => 'Dw/8', + 'info' => 'Parameter' }, + + 'MEM_CONTENT_FILE_NAME' => { + 'type' => 'Entry', + 'content' => '', + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'info' => 'MEM_FILE_NAME: +The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time. + +File Path: +For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}. +For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME} + +file_type: +bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime. +memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command. +mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ', + 'deafult' => '"ram0"' + }, + 'JTAG_CONNECT' => { + 'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"', + 'type' => 'Combo-box', + 'global_param' => 'Localparam', + 'redefine_param' => 1, + 'deafult' => '"DISABLED"', + 'info' => 'JTAG_CONNECT: +if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ' + }, 'WB_Aw' => { + 'deafult' => 'Aw+2', 'info' => undef, - 'deafult' => 'Aw+2', 'global_param' => 'Don\'t include', - 'content' => '', 'redefine_param' => 1, - 'type' => 'Fixed' + 'type' => 'Fixed', + 'content' => '' }, + + 'JTAG_INDEX' => { + 'global_param' => 'Localparam', + 'redefine_param' => 1, + 'content' => '', + 'type' => 'Entry', + 'deafult' => 'CORE_ID', + 'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory. + + In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1). + + You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units). + +' + }, 'Aw' => { 'info' => 'Memory address width', 'deafult' => '12', - 'global_param' => 'Parameter', 'content' => '4,31,1', 'type' => 'Spin-button', - 'redefine_param' => 1 + 'redefine_param' => 1, + 'global_param' => 'Parameter' }, - 'BURST_MODE' => { - 'info' => 'Wishbone bus burst read/write mode enable/disable. ', - 'deafult' => '"DISABLED"', - 'global_param' => 'Localparam', - 'content' => '"DISABLED","ENABLED"', - 'type' => 'Combo-box', - 'redefine_param' => 1 - }, 'TAGw' => { - 'info' => 'Parameter', - 'deafult' => '3', + 'redefine_param' => 1, 'global_param' => 'Localparam', 'content' => '', 'type' => 'Fixed', + 'info' => 'Parameter', + 'deafult' => '3' + }, + 'BTEw' => { + 'deafult' => '2', + 'info' => 'Parameter', + 'type' => 'Fixed', + 'content' => '', + 'global_param' => 'Localparam', 'redefine_param' => 1 }, - 'JTAG_INDEX' => { - 'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory. - - In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1). - - You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units). - -', - 'deafult' => 'CORE_ID', + 'FPGA_VENDOR' => { + 'type' => 'Combo-box', + 'content' => '"ALTERA","GENERIC"', + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'info' => '', + 'deafult' => '"GENERIC"' + }, + 'CTIw' => { + 'type' => 'Fixed', + 'content' => '', + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'info' => 'Parameter', + 'deafult' => '3' + }, + 'Dw' => { + 'type' => 'Spin-button', + 'content' => '8,1024,1', + 'redefine_param' => 1, + 'global_param' => 'Parameter', + 'info' => 'Memory data width in Bits.', + 'deafult' => '32' + }, + 'INIT_FILE_PATH' => { + 'info' => undef, + 'deafult' => 'SW_LOC', + 'redefine_param' => 1, + 'global_param' => 'Localparam', + 'type' => 'Fixed', + 'content' => '' + }, + + 'INITIAL_EN' => { + 'deafult' => '"NO"', + 'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.', 'global_param' => 'Localparam', - 'content' => '', 'redefine_param' => 1, - 'type' => 'Entry' + 'content' => '"YES","NO"', + 'type' => 'Combo-box' }, - 'JTAG_CONNECT' => { - 'info' => 'JTAG_CONNECT: -if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ', - 'deafult' => '"DISABLED"', - 'global_param' => 'Localparam', - 'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"', - 'type' => 'Combo-box', - 'redefine_param' => 1 - }, + 'BURST_MODE' => { + 'deafult' => '"ENABLED"', + 'info' => 'Wishbone bus burst read/write mode enable/disable. ', + 'type' => 'Combo-box', + 'content' => '"DISABLED","ENABLED"', + 'global_param' => 'Localparam', + 'redefine_param' => 1 + }, 'BYTE_WR_EN' => { 'info' => '', 'deafult' => '"YES"', - 'global_param' => 'Localparam', + 'type' => 'Combo-box', 'content' => '"YES","NO"', 'redefine_param' => 1, - 'type' => 'Combo-box' - }, - 'INIT_FILE_NAME' => { - 'info' => 'The name of RAM content memory file (without extention). The file will be used by the JTAG programer to programe the memory at run time.', - 'deafult' => '"ram0"', - 'global_param' => 'Don\'t include', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Entry' - }, - 'CTIw' => { - 'info' => 'Parameter', - 'deafult' => '3', - 'global_param' => 'Localparam', - 'content' => '', - 'redefine_param' => 1, - 'type' => 'Fixed' - }, - 'FPGA_VENDOR' => { - 'info' => '', - 'deafult' => '"ALTERA"', - 'global_param' => 'Localparam', - 'content' => '"ALTERA","GENERIC"', - 'redefine_param' => 1, - 'type' => 'Combo-box' - } + 'global_param' => 'Localparam' + } }, - 'parameters_order' => [ - 'Dw', - 'Aw', - 'BYTE_WR_EN', - 'FPGA_VENDOR', - 'JTAG_CONNECT', - 'JTAG_INDEX', - 'TAGw', - 'SELw', - 'CTIw', - 'BTEw', - 'WB_Aw', - 'BURST_MODE', - 'INIT_FILE_NAME' - ], + 'ports_order' => [ + 'clk', + 'reset', + 'sa_dat_i', + 'sa_sel_i', + 'sa_addr_i', + 'sa_tag_i', + 'sa_cti_i', + 'sa_bte_i', + 'sa_stb_i', + 'sa_cyc_i', + 'sa_we_i', + 'sa_dat_o', + 'sa_ack_o', + 'sa_err_o', + 'sa_rty_o' + ], 'ports' => { - 'sa_tag_i' => { + 'sa_cyc_i' => { + 'intfc_port' => 'cyc_i', 'intfc_name' => 'plug:wb_slave[0]', - 'intfc_port' => 'tag_i', - 'range' => 'TAGw-1 : 0', - 'type' => 'input' + 'type' => 'input', + 'range' => '' }, - 'sa_rty_o' => { + 'sa_ack_o' => { 'intfc_name' => 'plug:wb_slave[0]', - 'intfc_port' => 'rty_o', + 'intfc_port' => 'ack_o', 'range' => '', 'type' => 'output' }, @@ -200,29 +253,35 @@ 'range' => 'Dw-1 : 0', 'type' => 'output' }, - 'sa_cti_i' => { + 'sa_addr_i' => { + 'intfc_port' => 'adr_i', + 'intfc_name' => 'plug:wb_slave[0]', + 'type' => 'input', + 'range' => 'Aw-1 : 0' + }, + 'sa_tag_i' => { 'intfc_name' => 'plug:wb_slave[0]', - 'intfc_port' => 'cti_i', - 'range' => 'CTIw-1 : 0', - 'type' => 'input' + 'intfc_port' => 'tag_i', + 'type' => 'input', + 'range' => 'TAGw-1 : 0' }, - 'sa_sel_i' => { + 'sa_dat_i' => { 'intfc_name' => 'plug:wb_slave[0]', - 'intfc_port' => 'sel_i', - 'range' => 'SELw-1 : 0', + 'intfc_port' => 'dat_i', + 'range' => 'Dw-1 : 0', 'type' => 'input' }, - 'sa_bte_i' => { - 'intfc_port' => 'bte_i', + 'sa_stb_i' => { + 'type' => 'input', + 'range' => '', 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'BTEw-1 : 0', - 'type' => 'input' + 'intfc_port' => 'stb_i' }, - 'sa_dat_i' => { - 'intfc_port' => 'dat_i', + 'sa_rty_o' => { 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'Dw-1 : 0', - 'type' => 'input' + 'intfc_port' => 'rty_o', + 'range' => '', + 'type' => 'output' }, 'sa_we_i' => { 'intfc_port' => 'we_i', @@ -230,68 +289,41 @@ 'range' => '', 'type' => 'input' }, - 'sa_err_o' => { - 'intfc_port' => 'err_o', + 'sa_sel_i' => { + 'type' => 'input', + 'range' => 'SELw-1 : 0', 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '', - 'type' => 'output' + 'intfc_port' => 'sel_i' }, - 'sa_cyc_i' => { - 'intfc_port' => 'cyc_i', + 'sa_cti_i' => { + 'range' => 'CTIw-1 : 0', + 'type' => 'input', + 'intfc_port' => 'cti_i', + 'intfc_name' => 'plug:wb_slave[0]' + }, + 'clk' => { + 'intfc_name' => 'plug:clk[0]', + 'intfc_port' => 'clk_i', + 'type' => 'input', + 'range' => '' + }, + 'sa_bte_i' => { + 'intfc_port' => 'bte_i', 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '', + 'range' => 'BTEw-1 : 0', 'type' => 'input' }, 'reset' => { - 'intfc_name' => 'plug:reset[0]', + 'range' => '', + 'type' => 'input', 'intfc_port' => 'reset_i', - 'range' => '', - 'type' => 'input' + 'intfc_name' => 'plug:reset[0]' }, - 'sa_ack_o' => { - 'intfc_port' => 'ack_o', + 'sa_err_o' => { + 'intfc_port' => 'err_o', 'intfc_name' => 'plug:wb_slave[0]', 'range' => '', 'type' => 'output' - }, - 'clk' => { - 'intfc_port' => 'clk_i', - 'intfc_name' => 'plug:clk[0]', - 'range' => '', - 'type' => 'input' - }, - 'sa_addr_i' => { - 'intfc_port' => 'adr_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => 'Aw-1 : 0', - 'type' => 'input' - }, - 'sa_stb_i' => { - 'intfc_port' => 'stb_i', - 'intfc_name' => 'plug:wb_slave[0]', - 'range' => '', - 'type' => 'input' } - }, - 'ports_order' => [ - 'clk', - 'reset', - 'sa_dat_i', - 'sa_sel_i', - 'sa_addr_i', - 'sa_tag_i', - 'sa_cti_i', - 'sa_bte_i', - 'sa_stb_i', - 'sa_cyc_i', - 'sa_we_i', - 'sa_dat_o', - 'sa_ack_o', - 'sa_err_o', - 'sa_rty_o' - ], - 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v', - 'module_name' => 'wb_single_port_ram', - 'unused' => undef, - 'category' => 'RAM' + } }, 'ip_gen' );
/lib/mpsoc/aeMB_noc.MPSOC
0,0 → 1,2972
#######################################################################
## File: aeMB_noc.MPSOC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.7.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$aeMB_noc = bless( {
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
},
'tile' => {
'1' => {},
'3' => {},
'2' => {},
'0' => {}
},
'mpsoc_name' => 'aeMB_noc',
'noc_indept_param' => {},
'compile' => {
'quartus_bin' => '/home/alireza/altera/13.0sp1/quartus/bin',
'type' => 'Modelsim',
'board' => 'DE2_115',
'modelsim_bin' => '/home/alireza/altera/modeltech/bin'
},
'noc_param' => {
'SSA_EN' => '"NO"',
'C' => 0,
'ESCAP_VC_MASK' => '2\'b01',
'CONGESTION_INDEX' => 3,
'ROUTE_SUBFUNC' => '"XY"',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'AVC_ATOMIC_EN' => 0,
'V' => '2',
'MUX_TYPE' => '"BINARY"',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'TOPOLOGY' => '"MESH"',
'Fpay' => '32',
'NY' => ' 2',
'NX' => ' 2',
'B' => '4',
'FIRST_ARBITER_EXT_P_EN' => 0,
'DEBUG_EN' => '0',
'ROUTE_NAME' => '"XY"'
},
'top_ip' => bless( {
'ports' => {
'clk' => {
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'IO',
'intfc_port' => 'clk_i'
},
'processors_en' => {
'instance_name' => 'IO',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input',
'intfc_port' => 'enable_i'
},
'aeMB_tile_1_led_port_o' => {
'type' => 'output',
'range' => 'aeMB_tile_1_led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'instance_name' => 'aeMB_tile_1',
'intfc_port' => 'IO'
},
'aeMB_tile_0_led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'aeMB_tile_0_led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'instance_name' => 'aeMB_tile_0'
},
'aeMB_tile_3_led_port_o' => {
'instance_name' => 'aeMB_tile_3',
'range' => 'aeMB_tile_3_led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO'
},
'aeMB_tile_2_led_port_o' => {
'intfc_name' => 'IO',
'range' => 'aeMB_tile_2_led_PORT_WIDTH-1 : 0',
'instance_name' => 'aeMB_tile_2',
'type' => 'output',
'intfc_port' => 'IO'
},
'reset' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'IO'
}
},
'instance_ids' => {
'aeMB_tile_3' => {
'ports' => {
'aeMB_tile_3_led_port_o' => {
'intfc_port' => 'IO',
'range' => 'aeMB_tile_3_led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output'
}
}
},
'IO' => {
'ports' => {
'reset' => {
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
},
'processors_en' => {
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'intfc_port' => 'enable_i'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
}
}
},
'aeMB_tile_0' => {
'ports' => {
'aeMB_tile_0_led_port_o' => {
'range' => 'aeMB_tile_0_led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO'
}
}
},
'aeMB_tile_1' => {
'ports' => {
'aeMB_tile_1_led_port_o' => {
'intfc_name' => 'IO',
'range' => 'aeMB_tile_1_led_PORT_WIDTH-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
}
},
'aeMB_tile_2' => {
'ports' => {
'aeMB_tile_2_led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'aeMB_tile_2_led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
}
}
}
},
'interface' => {
'plug:clk[0]' => {
'ports' => {
'clk' => {
'instance_name' => 'IO',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
}
}
},
'plug:reset[0]' => {
'ports' => {
'reset' => {
'range' => '',
'instance_name' => 'IO',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'plug:enable[0]' => {
'ports' => {
'processors_en' => {
'instance_name' => 'IO',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'IO' => {
'ports' => {
'aeMB_tile_2_led_port_o' => {
'type' => 'output',
'range' => 'aeMB_tile_2_led_PORT_WIDTH-1 : 0',
'instance_name' => 'aeMB_tile_2',
'intfc_port' => 'IO'
},
'aeMB_tile_3_led_port_o' => {
'range' => 'aeMB_tile_3_led_PORT_WIDTH-1 : 0',
'instance_name' => 'aeMB_tile_3',
'type' => 'output',
'intfc_port' => 'IO'
},
'aeMB_tile_0_led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'aeMB_tile_0_led_PORT_WIDTH-1 : 0',
'instance_name' => 'aeMB_tile_0'
},
'aeMB_tile_1_led_port_o' => {
'intfc_port' => 'IO',
'range' => 'aeMB_tile_1_led_PORT_WIDTH-1 : 0',
'instance_name' => 'aeMB_tile_1',
'type' => 'output'
}
}
}
}
}, 'ip_gen' ),
'file_name' => undef,
'parameters_order' => {
'noc_type' => [
'ROUTER_TYPE'
],
'noc_param' => [
'NX',
'NY',
'V',
'B',
'Fpay',
'TOPOLOGY',
'ROUTE_NAME',
'SSA_EN',
'CONGESTION_INDEX',
'ESCAP_VC_MASK',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'AVC_ATOMIC_EN',
'ROUTE_SUBFUNC'
]
},
'setting' => {
'show_noc_setting' => 1,
'show_tile_setting' => 1,
'show_adv_setting' => 0,
'soc_path' => 'lib/soc'
},
'socs' => {
'sep' => {
'top' => bless( {
'interface' => {
'socket:ni[0]' => {
'ports' => {
'nis_credit_in' => {
'instance_name' => 'ni_sep0',
'range' => 'nis_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'nis_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'nis_Xw-1 : 0',
'instance_name' => 'ni_sep0'
},
'nis_flit_in_wr' => {
'type' => 'input',
'instance_name' => 'ni_sep0',
'range' => '',
'intfc_port' => 'flit_in_wr'
},
'nis_current_y' => {
'instance_name' => 'ni_sep0',
'range' => 'nis_Yw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_y'
},
'nis_flit_out' => {
'type' => 'output',
'range' => 'nis_Fw-1 : 0',
'instance_name' => 'ni_sep0',
'intfc_port' => 'flit_out'
},
'nis_flit_in' => {
'type' => 'input',
'range' => 'nis_Fw-1 : 0',
'instance_name' => 'ni_sep0',
'intfc_port' => 'flit_in'
},
'nis_credit_out' => {
'type' => 'output',
'instance_name' => 'ni_sep0',
'range' => 'nis_V-1 : 0',
'intfc_port' => 'credit_out'
},
'nis_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_sep0',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
}
},
'instance_ids' => {
'clk_source0' => {
'module_name' => 'clk_source',
'module' => 'clk_source',
'instance' => 'ss',
'ports' => {
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
}
},
'category' => 'Source'
},
'ni_sep0' => {
'module' => 'ni_sep',
'module_name' => 'ni_sep',
'ports' => {
'nis_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'nis_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'nis_flit_in' => {
'type' => 'input',
'range' => 'nis_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in'
},
'nis_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'nis_credit_out' => {
'intfc_port' => 'credit_out',
'range' => 'nis_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output'
},
'nis_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'nis_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'nis_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'nis_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'nis_current_y' => {
'intfc_port' => 'current_y',
'range' => 'nis_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'nis_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
}
},
'instance' => 'nis',
'parameters' => {
'nis_NY' => {
'content' => '',
'deafult' => 4,
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'nis_TOPOLOGY' => {
'redefine_param' => 1,
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '"MESH"'
},
'nis_B' => {
'deafult' => '4',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => '',
'redefine_param' => 1
},
'nis_NX' => {
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Parameter',
'deafult' => 4,
'content' => ''
},
'nis_V' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => '',
'type' => 'Fixed',
'content' => '',
'deafult' => '2'
},
'nis_ROUTE_NAME' => {
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '"XY"'
},
'nis_DEBUG_EN' => {
'deafult' => '0',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => undef,
'global_param' => 'Parameter'
},
'nis_Fpay' => {
'content' => '',
'deafult' => '32',
'global_param' => 'Parameter',
'info' => undef,
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'category' => 'NoC'
},
'wishbone_bus0' => {
'instance' => 'bus',
'category' => 'Bus',
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus'
}
},
'ports' => {
'nis_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_sep0'
},
'nis_current_y' => {
'range' => 'nis_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_sep0',
'type' => 'input',
'intfc_port' => 'current_y'
},
'nis_current_x' => {
'type' => 'input',
'instance_name' => 'ni_sep0',
'range' => 'nis_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_x'
},
'nis_credit_in' => {
'type' => 'input',
'range' => 'nis_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_sep0',
'intfc_port' => 'credit_in'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'type' => 'input'
},
'nis_credit_out' => {
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'nis_V-1 : 0',
'instance_name' => 'ni_sep0',
'intfc_port' => 'credit_out'
},
'nis_flit_out_wr' => {
'type' => 'output',
'instance_name' => 'ni_sep0',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr'
},
'nis_flit_in' => {
'instance_name' => 'ni_sep0',
'intfc_name' => 'socket:ni[0]',
'range' => 'nis_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ss_clk_in' => {
'type' => 'input',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i'
},
'nis_flit_out' => {
'type' => 'output',
'instance_name' => 'ni_sep0',
'intfc_name' => 'socket:ni[0]',
'range' => 'nis_Fw-1 : 0',
'intfc_port' => 'flit_out'
}
}
}, 'ip_gen' )
},
'lm32_tile$' => {
'top' => bless( {
'interface' => {
'IO' => {
'ports' => {
'gpo_port_o' => {
'intfc_port' => 'IO',
'instance_name' => 'gpo0',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_en_i' => {
'range' => '',
'instance_name' => 'lm320',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_out' => {
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni0',
'intfc_port' => 'flit_out'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0'
},
'ni_flit_out_wr' => {
'range' => '',
'instance_name' => 'ni0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_in' => {
'type' => 'input',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'range' => 'ni_Xw-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_flit_in' => {
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_y' => {
'type' => 'input',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'intfc_port' => 'current_y'
},
'ni_flit_in_wr' => {
'type' => 'input',
'range' => '',
'instance_name' => 'ni0',
'intfc_port' => 'flit_in_wr'
}
}
}
},
'instance_ids' => {
'ni0' => {
'instance' => 'ni',
'ports' => {
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_x' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_x'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_flit_in_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_flit_out' => {
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_credit_out' => {
'type' => 'output',
'range' => 'ni_V-1: 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out'
}
},
'category' => 'NoC',
'parameters' => {
'ni_V' => {
'content' => '',
'deafult' => '2',
'global_param' => 'Parameter',
'info' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_TOPOLOGY' => {
'content' => '',
'deafult' => '"MESH"',
'global_param' => 'Parameter',
'info' => undef,
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Parameter',
'deafult' => '"XY"',
'content' => ''
},
'ni_NX' => {
'content' => '',
'deafult' => ' 2',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed'
},
'ni_B' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => '',
'redefine_param' => 1,
'deafult' => '4',
'content' => ''
},
'ni_NY' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => undef,
'deafult' => ' 2',
'content' => ''
},
'ni_Fpay' => {
'redefine_param' => 1,
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '32'
},
'ni_DEBUG_EN' => {
'redefine_param' => 1,
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '0'
}
},
'module_name' => 'ni',
'module' => 'ni'
},
'jtag_wb0' => {
'category' => 'JTAG',
'instance' => 'jtag_wb0',
'module_name' => 'vjtag_wb',
'module' => 'jtag_wb'
},
'single_port_ram0' => {
'parameters' => {
'ram_Aw' => {
'content' => '4,31,1',
'deafult' => '12',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Memory address width',
'type' => 'Spin-button'
},
'ram_Dw' => {
'deafult' => '32',
'content' => '8,1024,1',
'type' => 'Spin-button',
'redefine_param' => 1,
'info' => 'Memory data width in Bits.',
'global_param' => 'Parameter'
}
},
'category' => 'RAM',
'instance' => 'ram',
'module_name' => 'wb_single_port_ram',
'module' => 'single_port_ram'
},
'clk_source0' => {
'instance' => 'ss',
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'category' => 'Source',
'module_name' => 'clk_source',
'module' => 'clk_source'
},
'lm320' => {
'category' => 'Processor',
'instance' => 'cpu',
'ports' => {
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'type' => 'input'
}
},
'module' => 'lm32',
'module_name' => 'lm32'
},
'gpo0' => {
'module' => 'gpo',
'module_name' => 'gpo',
'ports' => {
'gpo_port_o' => {
'intfc_port' => 'IO',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output'
}
},
'instance' => 'gpo',
'parameters' => {
'gpo_PORT_WIDTH' => {
'content' => '1,32,1',
'deafult' => ' 1',
'redefine_param' => 1,
'info' => 'output port width',
'global_param' => 'Parameter',
'type' => 'Spin-button'
}
},
'category' => 'GPIO'
},
'wishbone_bus0' => {
'instance' => 'bus',
'category' => 'Bus',
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus'
}
},
'ports' => {
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'instance_name' => 'ni0'
},
'ni_flit_out_wr' => {
'type' => 'output',
'instance_name' => 'ni0',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_in' => {
'type' => 'input',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'intfc_port' => 'credit_in'
},
'ni_flit_out' => {
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'intfc_port' => 'flit_out'
},
'ss_reset_in' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'intfc_port' => 'reset_i'
},
'gpo_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_in' => {
'instance_name' => 'ni0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'type' => 'input'
},
'ss_clk_in' => {
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'clk_source0',
'intfc_port' => 'clk_i'
},
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'instance_name' => 'lm320'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
}
},
'parameters' => {
'gpo_PORT_WIDTH' => ' 1',
'ram_Aw' => '12',
'ram_Dw' => '32'
}
}, 'ip_gen' )
},
'sim_uart_test' => {
'top' => bless( {
'interface' => {
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'flit_in_wr'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Yw-1 : 0'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Xw-1 : 0'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_out_wr' => {
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_out' => {
'type' => 'output',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_out'
}
}
},
'plug:enable[0]' => {
'ports' => {
'aeMB0_sys_ena_i' => {
'type' => 'input',
'range' => '',
'instance_name' => 'aeMB0',
'intfc_port' => 'enable_i'
}
}
}
},
'parameters' => {
'ram_Aw' => '12',
'ram_Dw' => '32'
},
'instance_ids' => {
'clk_source0' => {
'module' => 'clk_source',
'module_name' => 'clk_source',
'instance' => 'ss',
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
}
},
'category' => 'Source'
},
'ni_master0' => {
'module_name' => 'ni_master',
'module' => 'ni_master',
'instance' => 'ni',
'ports' => {
'ni_flit_out' => {
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out'
},
'ni_credit_in' => {
'type' => 'input',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out_wr' => {
'type' => 'output',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_current_y' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'intfc_port' => 'current_y'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_current_x' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'intfc_port' => 'current_x'
}
},
'category' => 'NoC',
'parameters' => {
'ni_ROUTE_NAME' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '"XY" '
},
'ni_TOPOLOGY' => {
'content' => '',
'deafult' => '"MESH"',
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_V' => {
'content' => '',
'deafult' => '4',
'global_param' => 'Parameter',
'info' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => ' 4'
},
'ni_B' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => ' 4'
},
'ni_C' => {
'content' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'type' => 'Fixed'
},
'ni_NY' => {
'global_param' => 'Parameter',
'info' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'content' => '',
'deafult' => ' 4'
},
'ni_Fpay' => {
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => ' 32'
},
'ni_DEBUG_EN' => {
'content' => '',
'deafult' => ' 1',
'global_param' => 'Parameter',
'info' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
}
}
},
'single_port_ram0' => {
'module_name' => 'wb_single_port_ram',
'module' => 'single_port_ram',
'instance' => 'ram',
'category' => 'RAM',
'parameters' => {
'ram_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Memory data width in Bits.',
'deafult' => '32',
'content' => '8,1024,1'
},
'ram_Aw' => {
'info' => 'Memory address width',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button',
'content' => '4,31,1',
'deafult' => '12'
}
}
},
'sim_uart0' => {
'module' => 'sim_uart',
'module_name' => 'simulator_UART',
'category' => 'Other',
'instance' => 'sim_uart'
},
'wishbone_bus0' => {
'category' => 'Bus',
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'module' => 'wishbone_bus'
},
'aeMB0' => {
'instance' => 'aeMB0',
'ports' => {
'aeMB0_sys_ena_i' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'category' => 'Processor',
'module' => 'aeMB',
'module_name' => 'aeMB_top'
}
},
'ports' => {
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
},
'ni_current_y' => {
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_y'
},
'ni_current_x' => {
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_x'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:clk[0]'
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'aeMB0_sys_ena_i' => {
'type' => 'input',
'instance_name' => 'aeMB0',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'intfc_port' => 'enable_i'
}
}
}, 'ip_gen' )
},
'aeMB_tile' => {
'top' => bless( {
'interface' => {
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_current_y' => {
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_y'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni_master0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out'
}
}
},
'plug:enable[0]' => {
'ports' => {
'aeMB_sys_ena_i' => {
'range' => '',
'instance_name' => 'aeMB0',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
}
}
},
'parameters' => {
'ram_Aw' => 13,
'led_PORT_WIDTH' => ' 1',
'ram_Dw' => '32'
},
'ports' => {
'ni_credit_out' => {
'type' => 'output',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_out'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'aeMB_sys_ena_i' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'instance_name' => 'aeMB0',
'type' => 'input',
'intfc_port' => 'enable_i'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_x' => {
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_x'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ss_clk_in' => {
'type' => 'input',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i'
},
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'type' => 'output',
'intfc_port' => 'IO'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
}
},
'instance_ids' => {
'ni_master0' => {
'module' => 'ni_master',
'module_name' => 'ni_master',
'category' => 'NoC',
'parameters' => {
'ni_B' => {
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '4'
},
'ni_NX' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'redefine_param' => 1,
'deafult' => ' 2',
'content' => ''
},
'ni_ROUTE_NAME' => {
'deafult' => '"XY"',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter'
},
'ni_V' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '2'
},
'ni_TOPOLOGY' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '"MESH"'
},
'ni_DEBUG_EN' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'deafult' => '0',
'content' => ''
},
'ni_Fpay' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '32'
},
'ni_NY' => {
'content' => '',
'deafult' => ' 2',
'global_param' => 'Parameter',
'info' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_C' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => 0
}
},
'ports' => {
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0'
}
},
'instance' => 'ni'
},
'single_port_ram0' => {
'instance' => 'ram',
'parameters' => {
'ram_Dw' => {
'deafult' => '32',
'content' => '8,1024,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Memory data width in Bits.'
},
'ram_Aw' => {
'content' => '4,31,1',
'deafult' => 13,
'redefine_param' => 1,
'info' => 'Memory address width',
'global_param' => 'Parameter',
'type' => 'Spin-button'
}
},
'category' => 'RAM',
'module' => 'single_port_ram',
'module_name' => 'wb_single_port_ram'
},
'clk_source0' => {
'module_name' => 'clk_source',
'module' => 'clk_source',
'ports' => {
'ss_clk_in' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
}
},
'instance' => 'ss',
'category' => 'Source'
},
'gpo0' => {
'ports' => {
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO'
}
},
'instance' => 'led',
'parameters' => {
'led_PORT_WIDTH' => {
'global_param' => 'Parameter',
'info' => 'output port width',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '1,32,1',
'deafult' => ' 1'
}
},
'category' => 'GPIO',
'module_name' => 'gpo',
'module' => 'gpo'
},
'aeMB0' => {
'module_name' => 'aeMB_top',
'module' => 'aeMB',
'instance' => 'aeMB',
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:enable[0]'
}
},
'category' => 'Processor'
},
'sim_uart0' => {
'category' => 'Other',
'instance' => 'sim_uart',
'module_name' => 'simulator_UART',
'module' => 'sim_uart'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'instance' => 'bus'
}
}
}, 'ip_gen' ),
'tile_nums' => [
0,
1,
2,
3
]
},
'lm32_tile' => {
'top' => bless( {
'instance_ids' => {
'gpo0' => {
'module' => 'gpo',
'module_name' => 'gpo',
'parameters' => {
'gpo_PORT_WIDTH' => {
'type' => 'Spin-button',
'info' => 'output port width',
'redefine_param' => 1,
'global_param' => 'Parameter',
'deafult' => ' 1',
'content' => '1,32,1'
}
},
'category' => 'GPIO',
'instance' => 'gpo',
'ports' => {
'gpo_port_o' => {
'range' => 'gpo_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO'
}
}
},
'lm320' => {
'module_name' => 'lm32',
'module' => 'lm32',
'category' => 'Processor',
'ports' => {
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => ''
}
},
'instance' => 'cpu'
},
'wishbone_bus0' => {
'category' => 'Bus',
'instance' => 'bus',
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus'
},
'jtag_wb0' => {
'category' => 'JTAG',
'instance' => 'jtag_wb0',
'module' => 'jtag_wb',
'module_name' => 'vjtag_wb'
},
'single_port_ram0' => {
'instance' => 'ram',
'category' => 'RAM',
'parameters' => {
'ram_Dw' => {
'global_param' => 'Parameter',
'info' => 'Memory data width in Bits.',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '8,1024,1',
'deafult' => '32'
},
'ram_Aw' => {
'redefine_param' => 1,
'info' => 'Memory address width',
'global_param' => 'Parameter',
'type' => 'Spin-button',
'content' => '4,31,1',
'deafult' => '12'
}
},
'module_name' => 'wb_single_port_ram',
'module' => 'single_port_ram'
},
'ni0' => {
'category' => 'NoC',
'parameters' => {
'ni_Fpay' => {
'content' => '',
'deafult' => '32',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'deafult' => '0',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => undef,
'redefine_param' => 1
},
'ni_NY' => {
'content' => '',
'deafult' => ' 2',
'redefine_param' => 1,
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_V' => {
'content' => '',
'deafult' => 2,
'info' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Parameter',
'deafult' => '"XY"',
'content' => ''
},
'ni_TOPOLOGY' => {
'redefine_param' => 1,
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '"MESH"'
},
'ni_NX' => {
'content' => '',
'deafult' => ' 2',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_B' => {
'redefine_param' => 1,
'info' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '4'
}
},
'ports' => {
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'intfc_port' => 'credit_out'
},
'ni_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_current_x' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'intfc_port' => 'current_x'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
}
},
'instance' => 'ni',
'module_name' => 'ni',
'module' => 'ni'
},
'clk_source0' => {
'category' => 'Source',
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
},
'instance' => 'ss',
'module' => 'clk_source',
'module_name' => 'clk_source'
}
},
'ports' => {
'ni_flit_out' => {
'type' => 'output',
'instance_name' => 'ni0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out'
},
'ni_credit_out' => {
'type' => 'output',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni0'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'gpo_port_o' => {
'instance_name' => 'gpo0',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO'
},
'ss_reset_in' => {
'range' => '',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input'
},
'cpu_en_i' => {
'instance_name' => 'lm320',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
},
'ni_flit_in' => {
'type' => 'input',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'intfc_port' => 'flit_in'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'instance_name' => 'ni0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_y'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni0',
'intfc_name' => 'socket:ni[0]',
'range' => ''
}
},
'parameters' => {
'ram_Dw' => '32',
'gpo_PORT_WIDTH' => ' 1',
'ram_Aw' => '12'
},
'interface' => {
'IO' => {
'ports' => {
'gpo_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'instance_name' => 'gpo0',
'range' => 'gpo_PORT_WIDTH-1 : 0'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'lm320',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'range' => '',
'instance_name' => 'ni0',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_x' => {
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_x'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'instance_name' => 'ni0'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_flit_out' => {
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni0',
'intfc_port' => 'flit_out'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input'
}
}
}
}
}, 'ip_gen' )
},
'new_ni_test' => {
'top' => bless( {
'interface' => {
'plug:enable[0]' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'aeMB0',
'range' => ''
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'output'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'input'
},
'ni_flit_in' => {
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_in'
},
'ni_current_x' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_x'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'instance_name' => 'ni_master0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'intfc_port' => 'IO'
}
}
}
},
'ports' => {
'ss_reset_in' => {
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0',
'intfc_port' => 'reset_i'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'type' => 'output'
},
'ni_credit_in' => {
'type' => 'input',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in'
},
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'aeMB0',
'range' => '',
'intfc_name' => 'plug:enable[0]'
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'type' => 'output',
'intfc_port' => 'IO'
},
'ss_clk_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ni_current_x' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_x'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_y' => {
'type' => 'input',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'intfc_port' => 'current_y'
}
},
'instance_ids' => {
'ni_master0' => {
'module' => 'ni_master',
'module_name' => 'ni_master',
'instance' => 'ni',
'ports' => {
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'type' => 'output'
},
'ni_flit_out' => {
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_x' => {
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_x'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
}
},
'category' => 'NoC',
'parameters' => {
'ni_NY' => {
'content' => '',
'deafult' => ' 2',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_C' => {
'content' => '',
'deafult' => 4,
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'content' => '',
'deafult' => '0',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_Fpay' => {
'content' => '',
'deafult' => 32,
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_NX' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => ' 2'
},
'ni_V' => {
'deafult' => 4,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter'
},
'ni_TOPOLOGY' => {
'deafult' => '"MESH"',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter'
},
'ni_ROUTE_NAME' => {
'deafult' => '"XY"',
'content' => '',
'type' => 'Fixed',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ni_B' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '4'
}
}
},
'single_port_ram0' => {
'module_name' => 'wb_single_port_ram',
'module' => 'single_port_ram',
'parameters' => {
'ram_Aw' => {
'info' => 'Memory address width',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button',
'content' => '4,31,1',
'deafult' => 13
},
'ram_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'info' => 'Memory data width in Bits.',
'redefine_param' => 1,
'deafult' => '32',
'content' => '8,1024,1'
}
},
'category' => 'RAM',
'instance' => 'ram'
},
'clk_source0' => {
'category' => 'Source',
'instance' => 'ss',
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]'
}
},
'module' => 'clk_source',
'module_name' => 'clk_source'
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'deafult' => ' 1',
'content' => '1,32,1',
'type' => 'Spin-button',
'redefine_param' => 1,
'info' => 'output port width',
'global_param' => 'Parameter'
}
},
'category' => 'GPIO',
'instance' => 'led',
'ports' => {
'led_port_o' => {
'type' => 'output',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
}
},
'module' => 'gpo',
'module_name' => 'gpo'
},
'wishbone_bus0' => {
'instance' => 'bus',
'category' => 'Bus',
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus'
},
'sim_uart0' => {
'module_name' => 'simulator_UART',
'module' => 'sim_uart',
'instance' => 'sim_uart',
'category' => 'Other'
},
'aeMB0' => {
'module' => 'aeMB',
'module_name' => 'aeMB_top',
'instance' => 'aeMB',
'ports' => {
'aeMB_sys_ena_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i'
}
},
'category' => 'Processor'
}
},
'parameters' => {
'ram_Aw' => 13,
'led_PORT_WIDTH' => ' 1',
'ram_Dw' => '32'
}
}, 'ip_gen' )
},
'ni_sep_test' => {
'top' => bless( {
'interface' => {
'plug:enable[0]' => {
'ports' => {
'aeMB_sys_ena_i' => {
'type' => 'input',
'instance_name' => 'aeMB0',
'range' => '',
'intfc_port' => 'enable_i'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'instance_name' => 'ni_sep0'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_sep0',
'type' => 'output'
},
'ni_credit_in' => {
'type' => 'input',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_sep0',
'intfc_port' => 'credit_in'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_sep0',
'range' => 'ni_Fw-1 : 0'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'range' => '',
'instance_name' => 'ni_sep0'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'range' => 'ni_Xw-1 : 0',
'instance_name' => 'ni_sep0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni_sep0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'instance_name' => 'ni_sep0',
'intfc_port' => 'current_y'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input'
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'ni_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'instance_name' => 'ni_sep0'
}
}
}
},
'instance_ids' => {
'aeMB0' => {
'module' => 'aeMB',
'module_name' => 'aeMB_top',
'instance' => 'aeMB',
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'category' => 'Processor'
},
'ni_sep0' => {
'module' => 'ni_sep',
'module_name' => 'ni_sep',
'parameters' => {
'ni_NY' => {
'content' => '',
'deafult' => ' 2',
'global_param' => 'Parameter',
'info' => undef,
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => undef,
'deafult' => '32',
'content' => ''
},
'ni_DEBUG_EN' => {
'content' => '',
'deafult' => '0',
'global_param' => 'Parameter',
'info' => undef,
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_TOPOLOGY' => {
'type' => 'Fixed',
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Parameter',
'deafult' => '"MESH"',
'content' => ''
},
'ni_ROUTE_NAME' => {
'deafult' => '"XY"',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => undef
},
'ni_V' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => '',
'deafult' => '2',
'content' => ''
},
'ni_NX' => {
'content' => '',
'deafult' => ' 2',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed'
},
'ni_B' => {
'deafult' => '4',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => ''
}
},
'category' => 'NoC',
'instance' => 'ni',
'ports' => {
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'range' => ''
},
'ni_current_x' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'intfc_port' => 'current_x'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_y' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'intfc_port' => 'current_y'
},
'ni_credit_out' => {
'type' => 'output',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'flit_out'
}
}
},
'wishbone_bus0' => {
'category' => 'Bus',
'instance' => 'bus',
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus'
},
'single_port_ram0' => {
'module_name' => 'wb_single_port_ram',
'module' => 'single_port_ram',
'instance' => 'ram',
'parameters' => {
'ram_Dw' => {
'content' => '8,1024,1',
'deafult' => '32',
'global_param' => 'Parameter',
'info' => 'Memory data width in Bits.',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Aw' => {
'deafult' => '12',
'content' => '4,31,1',
'type' => 'Spin-button',
'info' => 'Memory address width',
'redefine_param' => 1,
'global_param' => 'Parameter'
}
},
'category' => 'RAM'
},
'clk_source0' => {
'module' => 'clk_source',
'module_name' => 'clk_source',
'ports' => {
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ss_clk_in' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i'
}
},
'instance' => 'ss',
'category' => 'Source'
}
},
'ports' => {
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_sep0'
},
'aeMB_sys_ena_i' => {
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'instance_name' => 'aeMB0',
'intfc_port' => 'enable_i'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_sep0',
'intfc_port' => 'credit_in'
},
'ni_credit_out' => {
'type' => 'output',
'instance_name' => 'ni_sep0',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_sep0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'intfc_port' => 'clk_i'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni_sep0',
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_flit_in' => {
'instance_name' => 'ni_sep0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'instance_name' => 'ni_sep0'
},
'ni_irq' => {
'type' => 'output',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'instance_name' => 'ni_sep0',
'intfc_port' => 'int_o'
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_sep0',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
}
},
'parameters' => {
'ram_Dw' => '32',
'ram_Aw' => '12'
}
}, 'ip_gen' )
}
}
}, 'mpsoc' );
/lib/mpsoc/lm32_noc.MPSOC
3,7 → 3,7
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.5.1
## This file is part of ProNoC 1.6.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
10,2561 → 10,237
################################################################################
 
$lm32_noc = bless( {
'class_param' => {
'Cn_1' => '2\'b11',
'Cn_0' => '2\'b11'
},
'socs' => {
'test' => {
'top' => bless( {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_cti_i' => {
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]',
'instance_name' => 'ni0',
'range' => 'ni_TAGw-1 : 0',
'type' => 'input'
},
'ni_s_cyc_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'cyc_i',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_s_stb_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'stb_i',
'range' => '',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_s_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'instance_name' => 'ni0',
'range' => 'ni_SELw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_s_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'ack_o',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_s_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'ni_S_Aw-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_s_we_i' => {
'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_s_rty_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'rty_o',
'range' => '',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_dat_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_o',
'range' => 'ni_Dw-1 : 0',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_dat_i' => {
'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[0]',
'instance_name' => 'ni0',
'range' => 'ni_Dw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_s_err_o' => {
'intfc_port' => 'err_o',
'intfc_name' => 'plug:wb_slave[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'instance_name' => 'ni0',
'type' => 'output'
}
},
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'range' => '',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'range' => 'ni_Xw-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'range' => '',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
}
},
'plug:wb_slave[0]' => {
'ports' => {
'ni_s_rty_o' => {
'intfc_port' => 'rty_o',
'range' => '',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_cti_i' => {
'intfc_port' => 'cti_i',
'instance_name' => 'ni0',
'range' => 'ni_TAGw-1 : 0',
'type' => 'input'
},
'ni_s_cyc_i' => {
'intfc_port' => 'cyc_i',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_s_dat_o' => {
'intfc_port' => 'dat_o',
'range' => 'ni_Dw-1 : 0',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_dat_i' => {
'intfc_port' => 'dat_i',
'range' => 'ni_Dw-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_s_stb_i' => {
'intfc_port' => 'stb_i',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_s_err_o' => {
'intfc_port' => 'err_o',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_s_sel_i' => {
'intfc_port' => 'sel_i',
'range' => 'ni_SELw-1 : 0',
'instance_name' => 'ni0',
'type' => 'input'
},
'ni_s_ack_o' => {
'intfc_port' => 'ack_o',
'range' => '',
'instance_name' => 'ni0',
'type' => 'output'
},
'ni_s_addr_i' => {
'intfc_port' => 'adr_i',
'instance_name' => 'ni0',
'range' => 'ni_S_Aw-1 : 0',
'type' => 'input'
},
'ni_s_we_i' => {
'intfc_port' => 'we_i',
'range' => '',
'instance_name' => 'ni0',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'gpi0' => {
'module_name' => 'gpi',
'category' => 'GPI',
'instance' => 'gpi0',
'module' => 'gpi'
},
'clk_source0' => {
'module_name' => 'clk_source',
'category' => 'source',
'instance' => 'ss',
'module' => 'clk_source'
},
'ext_int0' => {
'module_name' => 'ext_int',
'category' => 'interrupt',
'instance' => 'ext_int',
'module' => 'ext_int'
},
'ni0' => {
'parameters' => {
'ni_SSA_EN' => {
'info' => undef,
'deafult' => '"NO"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1
},
'ni_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1
},
'ni_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_CONGESTION_INDEX' => {
'info' => undef,
'deafult' => '3',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr',
'range' => '',
'type' => 'output'
},
'ni_s_cti_i' => {
'intfc_port' => 'cti_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'ni_TAGw-1 : 0',
'type' => 'input'
},
'ni_s_cyc_i' => {
'intfc_port' => 'cyc_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
},
'ni_s_stb_i' => {
'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
},
'ni_s_sel_i' => {
'intfc_port' => 'sel_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'ni_SELw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_y',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_s_ack_o' => {
'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_s_addr_i' => {
'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'ni_S_Aw-1 : 0',
'type' => 'input'
},
'ni_s_we_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i',
'range' => '',
'type' => 'input'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_s_rty_o' => {
'intfc_port' => 'rty_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
},
'ni_s_dat_o' => {
'intfc_port' => 'dat_o',
'intfc_name' => 'plug:wb_slave[0]',
'range' => 'ni_Dw-1 : 0',
'type' => 'output'
},
'ni_s_dat_i' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_i',
'range' => 'ni_Dw-1 : 0',
'type' => 'input'
},
'ni_s_err_o' => {
'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'err_o',
'range' => '',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'type' => 'output'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni',
'module' => 'ni'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'Altera_single_port_ram0' => {
'module_name' => 'Altera_single_port_ram',
'category' => 'RAM',
'instance' => 'Altera_single_port_ram0',
'module' => 'Altera_single_port_ram'
}
}
}, 'ip_gen' )
},
'lm32_tile' => {
'top' => bless( {
'parameters' => {
'gpo_PORT_WIDTH' => ' 1',
'ram_Dw' => '32',
'ram_Aw' => '12'
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'lm320',
'range' => '',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'gpo_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
'noc_param' => {
'V' => 2,
'MUX_TYPE' => '"BINARY"',
'NY' => ' 2',
'ROUTE_SUBFUNC' => '"XY"',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'AVC_ATOMIC_EN' => 0,
'FIRST_ARBITER_EXT_P_EN' => 0,
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'Fpay' => '32',
'SSA_EN' => '"NO"',
'C' => 2,
'DEBUG_EN' => '0',
'ROUTE_NAME' => '"XY"',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'NX' => ' 2',
'ESCAP_VC_MASK' => '2\'b01',
'CONGESTION_INDEX' => 3,
'B' => '4',
'TOPOLOGY' => '"MESH"'
},
'file_name' => undef,
'top_ip' => bless( {
'interface' => {
'plug:enable[0]' => {
'ports' => {
'processors_en' => {
'type' => 'input',
'instance_name' => 'IO',
'range' => '',
'intfc_port' => 'enable_i'
}
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'lm320',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
}
},
'IO' => {
'ports' => {
'gpo_port_o' => {
'intfc_port' => 'IO',
'instance_name' => 'gpo0',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
}
},
'tiles' => {
'0' => {
'parameters' => {
'gpo_PORT_WIDTH' => 3,
'ram_Dw' => '32',
'ram_Aw' => '12'
}
}
},
'instance_ids' => {
'single_port_ram0' => {
'parameters' => {
'ram_Dw' => {
'info' => 'Memory data width in Bits.',
'deafult' => '32',
'global_param' => 'Parameter',
'content' => '8,1024,1',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Aw' => {
'info' => 'Memory address width',
'deafult' => '12',
'global_param' => 'Parameter',
'content' => '4,31,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module_name' => 'wb_single_port_ram',
'category' => 'RAM',
'instance' => 'ram',
'module' => 'single_port_ram'
'IO' => {
'ports' => {
'lm32_tile_1_gpo_port_o' => {
'intfc_port' => 'IO',
'range' => 'lm32_tile_1_gpo_PORT_WIDTH-1 : 0',
'instance_name' => 'lm32_tile_1',
'type' => 'output'
},
'lm320' => {
'ports' => {
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'lm32',
'category' => 'Processor',
'instance' => 'cpu',
'module' => 'lm32'
},
'clk_source0' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'clk_source',
'category' => 'Source',
'instance' => 'ss',
'module' => 'clk_source'
},
'gpo0' => {
'parameters' => {
'gpo_PORT_WIDTH' => {
'info' => 'output port width',
'deafult' => ' 1',
'global_param' => 'Parameter',
'content' => '1,32,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'ports' => {
'gpo_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
}
},
'module_name' => 'gpo',
'category' => 'GPIO',
'instance' => 'gpo',
'module' => 'gpo'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'ni0' => {
'parameters' => {
'ni_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
'lm32_tile_2_gpo_port_o' => {
'type' => 'output',
'instance_name' => 'lm32_tile_2',
'range' => 'lm32_tile_2_gpo_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni',
'module' => 'ni'
}
}
}, 'ip_gen' ),
'tile_nums' => [
0,
1,
2,
3
]
},
'int_ni' => {
'top' => bless( {
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'aeMB0_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'aeMB0_sys_ena_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
}
}
'lm32_tile_0_gpo_port_o' => {
'intfc_port' => 'IO',
'range' => 'lm32_tile_0_gpo_PORT_WIDTH-1 : 0',
'type' => 'output',
'instance_name' => 'lm32_tile_0'
},
'lm32_tile_3_gpo_port_o' => {
'type' => 'output',
'instance_name' => 'lm32_tile_3',
'range' => 'lm32_tile_3_gpo_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
}
}
},
'plug:reset[0]' => {
'ports' => {
'reset' => {
'range' => '',
'intfc_port' => 'reset_i',
'instance_name' => 'IO',
'type' => 'input'
}
}
},
'plug:clk[0]' => {
'ports' => {
'clk' => {
'type' => 'input',
'instance_name' => 'IO',
'intfc_port' => 'clk_i',
'range' => ''
}
},
'instance_ids' => {
'aeMB0' => {
'ports' => {
'aeMB0_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'aeMB_top',
'category' => 'Processor',
'instance' => 'aeMB0',
'module' => 'aeMB'
},
'ext_int0' => {
'module_name' => 'ext_int',
'category' => 'interrupt',
'instance' => 'ext_int0',
'module' => 'ext_int'
},
'clk_source0' => {
'module_name' => 'clk_source',
'category' => 'source',
'instance' => 'clk_source0',
'module' => 'clk_source'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'ni0' => {
'parameters' => {
'ni0_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_CONGESTION_INDEX' => {
'info' => undef,
'deafult' => '3',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_SSA_EN' => {
'info' => undef,
'deafult' => '"NO"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni0',
'module' => 'ni'
},
'int_ctrl0' => {
'module_name' => 'int_ctrl',
'category' => 'interrupt',
'instance' => 'int_ctrl0',
'module' => 'int_ctrl'
},
'Altera_single_port_ram0' => {
'module_name' => 'Altera_single_port_ram',
'category' => 'RAM',
'instance' => 'Altera_single_port_ram0',
'module' => 'Altera_single_port_ram'
}
}
}
},
'ports' => {
'lm32_tile_2_gpo_port_o' => {
'intfc_name' => 'IO',
'range' => 'lm32_tile_2_gpo_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'type' => 'output',
'instance_name' => 'lm32_tile_2'
},
'lm32_tile_1_gpo_port_o' => {
'instance_name' => 'lm32_tile_1',
'type' => 'output',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'range' => 'lm32_tile_1_gpo_PORT_WIDTH-1 : 0'
},
'clk' => {
'range' => '',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'IO',
'type' => 'input'
},
'lm32_tile_3_gpo_port_o' => {
'range' => 'lm32_tile_3_gpo_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'type' => 'output',
'instance_name' => 'lm32_tile_3'
},
'reset' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i',
'instance_name' => 'IO',
'type' => 'input'
},
'processors_en' => {
'type' => 'input',
'instance_name' => 'IO',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'intfc_port' => 'enable_i'
},
'lm32_tile_0_gpo_port_o' => {
'instance_name' => 'lm32_tile_0',
'type' => 'output',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'range' => 'lm32_tile_0_gpo_PORT_WIDTH-1 : 0'
}
}, 'ip_gen' )
},
'ni_test' => {
'top' => bless( {
'parameters' => {
'ram_Dw' => '32',
'ram_Aw' => 12,
'led_PORT_WIDTH' => ' 1'
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
},
'instance_ids' => {
'IO' => {
'ports' => {
'clk' => {
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input'
},
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
},
'led_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ss_reset_in' => {
'processors_en' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]'
},
'reset' => {
'type' => 'input',
'range' => '',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'intfc_name' => 'plug:reset[0]'
}
}
},
'lm32_tile_3' => {
'ports' => {
'lm32_tile_3_gpo_port_o' => {
'range' => 'lm32_tile_3_gpo_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'aeMB0' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'aeMB_top',
'category' => 'Processor',
'instance' => 'aeMB',
'module' => 'aeMB'
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'info' => 'output port width',
'deafult' => ' 1',
'global_param' => 1,
'content' => '1,32,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
}
},
'module_name' => 'gpo',
'category' => 'GPI',
'instance' => 'led',
'module' => 'gpo'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'int_ctrl0' => {
'module_name' => 'int_ctrl',
'category' => 'interrupt',
'instance' => 'int_ctrl',
'module' => 'int_ctrl'
},
'Altera_single_port_ram0' => {
'parameters' => {
'ram_Dw' => {
'info' => undef,
'deafult' => '32',
'global_param' => 1,
'content' => '8,1024,1',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Aw' => {
'info' => undef,
'deafult' => 12,
'global_param' => 1,
'content' => '4,31,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module_name' => 'Altera_single_port_ram',
'category' => 'RAM',
'instance' => 'ram',
'module' => 'Altera_single_port_ram'
},
'clk_source0' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'clk_source',
'category' => 'source',
'instance' => 'ss',
'module' => 'clk_source'
},
'ni0' => {
'parameters' => {
'ni_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni',
'module' => 'ni'
},
'timer0' => {
'module_name' => 'timer',
'category' => 'TIM',
'instance' => 'timer',
'module' => 'timer'
}
}
}, 'ip_gen' )
},
'tang' => {
'top' => bless( {
'parameters' => {
'ram_Dw' => '32',
'ram_Aw' => 13,
'led_PORT_WIDTH' => ' 1'
}
},
'ports' => {
'uart_readyfordata' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'altera_jtag_uart0',
'range' => '',
'type' => 'output'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
},
'led_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'uart_dataavailable' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'altera_jtag_uart0',
'range' => '',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
'lm32_tile_2' => {
'ports' => {
'lm32_tile_2_gpo_port_o' => {
'intfc_port' => 'IO',
'range' => 'lm32_tile_2_gpo_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output'
}
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'uart_readyfordata' => {
'intfc_port' => 'IO',
'instance_name' => 'altera_jtag_uart0',
'range' => '',
'type' => 'output'
},
'uart_dataavailable' => {
'intfc_port' => 'IO',
'instance_name' => 'altera_jtag_uart0',
'range' => '',
'type' => 'output'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'aeMB0' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'aeMB_top',
'category' => 'Processor',
'instance' => 'aeMB',
'module' => 'aeMB'
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'info' => 'output port width',
'deafult' => ' 1',
'global_param' => 1,
'content' => '1,32,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output'
}
},
'module_name' => 'gpo',
'category' => 'GPI',
'instance' => 'led',
'module' => 'gpo'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'int_ctrl0' => {
'module_name' => 'int_ctrl',
'category' => 'interrupt',
'instance' => 'int_ctrl',
'module' => 'int_ctrl'
},
'altera_jtag_uart0' => {
'ports' => {
'uart_readyfordata' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => '',
'type' => 'output'
},
'uart_dataavailable' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => '',
'type' => 'output'
}
},
'module_name' => 'altera_jtag_uart_wb',
'category' => 'Jtag',
'instance' => 'uart',
'module' => 'altera_jtag_uart'
},
'Altera_single_port_ram0' => {
'parameters' => {
'ram_Dw' => {
'info' => undef,
'deafult' => '32',
'global_param' => 1,
'content' => '8,1024,1',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Aw' => {
'info' => undef,
'deafult' => 13,
'global_param' => 1,
'content' => '4,31,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module_name' => 'Altera_single_port_ram',
'category' => 'RAM',
'instance' => 'ram',
'module' => 'Altera_single_port_ram'
},
'clk_source0' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'clk_source',
'category' => 'source',
'instance' => 'ss',
'module' => 'clk_source'
},
'ni0' => {
'parameters' => {
'ni_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni',
'module' => 'ni'
},
'timer0' => {
'module_name' => 'timer',
'category' => 'TIM',
'instance' => 'timer',
'module' => 'timer'
}
}
}, 'ip_gen' )
},
'test_ni_p' => {
'top' => bless( {
'parameters' => {
'ram_Dw' => '32',
'ram_Aw' => '10'
},
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'aeMB_sys_int_i' => {
'intfc_port' => 'int_i',
'intfc_name' => 'plug:interrupt_cpu[0]',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni0_irq' => {
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
},
'plug:interrupt_cpu[0]' => {
'ports' => {
'aeMB_sys_int_i' => {
'intfc_port' => 'int_i',
'instance_name' => 'aeMB0',
'range' => '',
'type' => 'input'
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'ni0_irq' => {
'intfc_port' => 'int_o',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'aeMB0' => {
'ports' => {
'aeMB_sys_int_i' => {
'intfc_port' => 'int_i',
'intfc_name' => 'plug:interrupt_cpu[0]',
'range' => '',
'type' => 'input'
},
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'aeMB_top',
'category' => 'Processor',
'instance' => 'aeMB',
'module' => 'aeMB'
},
'clk_source0' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'clk_source',
'category' => 'source',
'instance' => 'ss',
'module' => 'clk_source'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'ni0' => {
'parameters' => {
'ni0_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_CONGESTION_INDEX' => {
'info' => undef,
'deafult' => '3',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_SSA_EN' => {
'info' => undef,
'deafult' => '"NO"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni0_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 1,
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni0_irq' => {
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'range' => '',
'type' => 'output'
},
'ni0_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_V-1: 0',
'type' => 'output'
},
'ni0_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Xw-1 : 0',
'type' => 'input'
},
'ni0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni0_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Yw-1 : 0',
'type' => 'input'
},
'ni0_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Fw-1 : 0',
'type' => 'input'
},
'ni0_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_V-1 : 0',
'type' => 'input'
},
'ni0_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni0_Fw-1 : 0',
'type' => 'output'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni0',
'module' => 'ni'
},
'Altera_single_port_ram0' => {
'parameters' => {
'ram_Dw' => {
'info' => undef,
'deafult' => '32',
'global_param' => 1,
'content' => '8,1024,1',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Aw' => {
'info' => undef,
'deafult' => '10',
'global_param' => 1,
'content' => '4,31,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module_name' => 'Altera_single_port_ram',
'category' => 'RAM',
'instance' => 'ram',
'module' => 'Altera_single_port_ram'
}
}
}, 'ip_gen' )
}
},
'setting' => {
'show_adv_setting' => 1,
'soc_path' => 'lib/soc',
'show_noc_setting' => 1,
'show_tile_setting' => 1
'lm32_tile_1' => {
'ports' => {
'lm32_tile_1_gpo_port_o' => {
'intfc_port' => 'IO',
'range' => 'lm32_tile_1_gpo_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output'
}
}
},
'lm32_tile_0' => {
'ports' => {
'lm32_tile_0_gpo_port_o' => {
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'range' => 'lm32_tile_0_gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
}
}
}
}
}, 'ip_gen' ),
'compile' => {
'board' => 'DE2_115',
'quartus_bin' => '/home/alireza/altera/13.0sp1/quartus/bin',
'type' => 'Verilator',
'modelsim_bin' => '/home/alireza/altera/modeltech/bin'
},
'tile' => {
'1' => {},
'0' => {
'param_setting' => 'Custom'
},
'3' => {},
'2' => {}
'socs' => {
'sep' => {},
'new_ni_test' => {},
'lm32_tile' => {
'tile_nums' => [
0,
1,
2,
3
]
},
'ni_sep_test' => {},
'lm32_tile$' => {}
},
'class_param' => {
'Cn_0' => '2\'b11',
'Cn_1' => '2\'b11'
},
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'mpsoc_name' => 'lm32_noc',
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'parameters_order' => {
'class_param' => [
'Cn_0',
'Cn_1'
],
'noc_type' => [
'ROUTER_TYPE'
],
'noc_param' => [
'NX',
'NY',
2582,34 → 258,32
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'AVC_ATOMIC_EN',
'ROUTE_SUBFUNC'
'ROUTE_SUBFUNC',
'CONGESTION_INDEX',
'ESCAP_VC_MASK'
],
'noc_type' => [
'ROUTER_TYPE'
]
'class_param' => [
'Cn_0',
'Cn_1'
]
},
'file_name' => undef,
'noc_param' => {
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'NY' => ' 2',
'DEBUG_EN' => '0',
'NX' => ' 2',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'V' => 2,
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'ROUTE_SUBFUNC' => '"XY"',
'C' => 2,
'ROUTE_NAME' => '"XY"',
'Fpay' => '32',
'MUX_TYPE' => '"BINARY"',
'B' => '4',
'TOPOLOGY' => '"MESH"',
'AVC_ATOMIC_EN' => 0,
'SSA_EN' => '"NO"',
'FIRST_ARBITER_EXT_P_EN' => 0
},
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'noc_indept_param' => {}
'noc_indept_param' => {},
'tile' => {
'0' => {
'param_setting' => 'Custom'
},
'2' => {},
'1' => {},
'3' => {}
},
'setting' => {
'show_adv_setting' => 1,
'soc_path' => 'lib/soc',
'show_noc_setting' => 1,
'show_tile_setting' => 1
},
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
}
}, 'mpsoc' );
/lib/perl/compile.pl
0,0 → 1,1180
#! /usr/bin/perl -w
use Glib qw/TRUE FALSE/;
use strict;
use warnings;
use soc;
#use ip;
#use interface;
#use POSIX 'strtol';
 
use File::Path;
use File::Find::Rule;
use File::Copy;
use File::Copy::Recursive qw(dircopy);
use Cwd 'abs_path';
use Verilog::EditFiles;
 
use Gtk2;
#use Gtk2::Pango;
 
use List::MoreUtils qw( minmax );
 
 
 
################
# Comile
#################
 
 
 
sub is_capital_sensitive()
{
my ($cell_layout, $cell, $tree_model, $iter, $data) = @_;
my $sensitive = !$tree_model->iter_has_child($iter);
$cell->set('sensitive', $sensitive);
}
 
sub gen_combo_model{
my $ref=shift;
my %inputs=%{$ref};
my $store = Gtk2::TreeStore->new('Glib::String');
for my $i (sort { $a cmp $b} keys %inputs ) {
my $iter = $store->append(undef);
$store->set($iter, 0, $i);
for my $capital (sort { $a cmp $b} keys %{$inputs{$i}}) {
my $iter2 = $store->append($iter);
$store->set($iter2, 0, $capital);
}
}
return $store;
 
}
 
sub gen_tree_combo{
my $model=shift;
my $combo = Gtk2::ComboBox->new_with_model($model);
my $renderer = Gtk2::CellRendererText->new();
$combo->pack_start($renderer, TRUE);
$combo->set_attributes($renderer, "text", 0);
$combo->set_cell_data_func($renderer, \&is_capital_sensitive);
return $combo;
 
}
 
sub get_range {
my ($board,$self,$porttype,$assignname,$portrange,$portname) =@_;
my $box= def_hbox(FALSE,0);
my @range=$board->board_get_pin_range($porttype,$assignname);
if ($range[0] ne '*undefine*'){
my $content = join(",", @range);
my ($min, $max) = minmax @range;
if (length($portrange)!=0){
my $range_hsb=gen_combobox_object($self,'compile_pin_range_hsb',$portname,$content,$max,undef,undef);
$box->pack_start( $range_hsb, FALSE, FALSE, 0);
$box->pack_start(gen_label_in_center(':'),, FALSE, FALSE, 0);
}
 
my $range_lsb=gen_combobox_object($self,'compile_pin_range_lsb',$portname,$content,$min,undef,undef);
$box->pack_start( $range_lsb, FALSE, FALSE, 0);
}
return $box;
 
}
 
 
sub read_csv_file{
my $file=shift;
open(my $fh, "<$file") || die "Cannot open:$file; $!";
 
my $board = soc->board_new();
#read header format
my $header;
while (my $line= <$fh>){
chomp $line;
$line=remove_all_white_spaces($line);
#print "l:$line\n";
if(length ( $line)!=0){
if ($line !~ /\#/) {
$header= $line;
last;
}
}
}
 
my @headers = split (',',$header);
my $pin_name_col = get_scolar_pos('To',@headers);
if(!defined $pin_name_col){
message_dialog("Error: $file file has an unsupported format!");
return $board;
}
my $direction_col = get_scolar_pos('Direction',@headers);
close $fh;
 
#save pins
open( $fh, "<$file") || die "Cannot open:$file; $!";
 
while (my $line= <$fh>){
chomp $line;
my @fileds = split (',',$line);
my $to = $fileds[$pin_name_col];
my $direction = (defined $direction_col )? $fileds[$direction_col] : 'Unknown';
if(defined $direction && length($to)!=0){
if ($direction eq 'Input' || $direction eq 'Output' || $direction eq 'Bidir'){
$board->board_add_pin ($fileds[1],$to);
}elsif($direction eq 'Unknown'){
$board->board_add_pin ('Input',$to);
$board->board_add_pin ('Output',$to);
$board->board_add_pin ('Bidir',$to);
 
}
}
 
}
close $fh;
return $board;
}
 
 
 
 
sub gen_top_v{
my ($self,$board,$name,$top)=@_;
 
my $top_v=get_license_header("Top.v");
#read port list
my $vdb=read_verilog_file($top);
my %port_type=get_ports_type($vdb,"${name}_top");
my %port_range=get_ports_rang($vdb,"${name}_top");
my $io='';
my $io_def='';
my $io_assign='';
my %board_io;
my $first=1;
foreach my $p (sort keys %port_type){
my $porttype=$port_type{$p};
my $portrange=$port_range{$p};
my $assign_type = $self->object_get_attribute('compile_assign_type',$p);
my $assign_name = $self->object_get_attribute('compile_pin',$p);
my $range_hsb = $self->object_get_attribute('compile_pin_range_hsb',$p);
my $range_lsb = $self->object_get_attribute('compile_pin_range_lsb',$p);
my $assign="\t";
if (defined $assign_name){
if($assign_name eq '*VCC'){
$assign= (length($portrange)!=0)? '{32{1\'b1}}' : '1\'b1';
} elsif ($assign_name eq '*GND'){
$assign= (length($portrange)!=0)? '{32{1\'b0}}' : '1\'b0';
}elsif ($assign_name eq '*NOCONNECT'){
$assign="\t";
 
}else{
$board_io{$assign_name}=$porttype;
my $range = (defined $range_hsb) ? "[$range_hsb : $range_lsb]" :
(defined $range_lsb) ? "[ $range_lsb]" : " ";
my $l=(defined $assign_type)?
($assign_type eq 'Direct') ? '' : '~' : '';
$assign="$l $assign_name $range";
}
}
$io_assign= ($first)? "$io_assign \t .$p($assign)":"$io_assign,\n \t .$p($assign)";
$first=0;
}
$first=1;
foreach my $p (sort keys %board_io){
$io=($first)? "\t$p" : "$io,\n\t$p";
my $dir=$board_io{$p};
my $range;
my $type= ($dir eq 'input') ? 'Input' :
($dir eq 'output')? 'Output' : 'Bidir';
my @r= $board->board_get_pin_range($type,$p);
if ($r[0] eq '*undefine*'){
$range="\t\t\t";
} else {
my ($min, $max) = minmax @r;
$range="\t[$max : $min]\t";
}
$io_def = "$io_def \t $dir $range $p;\n";
$first=0;
}
$top_v="$top_v
module Top (
$io
);
$io_def
 
${name}_top uut(
$io_assign
);
 
 
endmodule
";
my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
my $board_top_file= "$fpath/Top.v";
save_file($board_top_file,$top_v);
}
 
 
 
 
 
 
 
 
 
 
sub select_compiler {
my ($self,$name,$top,$target_dir)=@_;
my $window = def_popwin_size(40,40,"Step 1: Select Compiler",'percent');
#get the list of boards located in "boards/*" folder
my @dirs = grep {-d} glob("./lib/boards/*");
my ($fpgas,$init);
foreach my $dir (@dirs) {
my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
$init=$name;
$fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";
}
my $table = def_table(2, 2, FALSE);
my $col=0;
my $row=0;
 
my $compiler=gen_combobox_object ($self,'compile','type',"QuartusII,Verilator,Modelsim","QuartusII",undef,undef);
$table->attach(gen_label_in_center("Compiler tool"),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
$table->attach($compiler,$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
$row++;$col=0;
my $old_board_name=$self->object_get_attribute('compile','board');
my $old_compiler=$self->object_get_attribute('compile','type');
my $compiler_options = ($old_compiler eq "QuartusII")? select_board ($self,$name,$top,$target_dir):
($old_compiler eq "Modelsim")? select_model_path ($self,$name,$top,$target_dir):
gen_label_in_center(" ");
$table->attach($compiler_options,$col,$col+2,$row,$row+1,'fill','shrink',2,2); $row++;
 
$col=1;
my $i;
for ($i=$row; $i<5; $i++){
my $temp=gen_label_in_center(" ");
$table->attach_defaults ($temp, 0, 1 , $i, $i+1);
}
$row=$i;
 
$window->add ($table);
$window->show_all();
my $next=def_image_button('icons/right.png','Next');
$table->attach($next,$col,$col+1,$row,$row+1,'shrink','shrink',2,2);$col++;
$next-> signal_connect("clicked" => sub{
my $compiler_type=$self->object_get_attribute('compile','type');
if($compiler_type eq "QuartusII"){
my $new_board_name=$self->object_get_attribute('compile','board');
if(defined $old_board_name) {
remove_pin_assignment($self) if ($old_board_name ne $new_board_name);
my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
my $board_top_file= "$fpath/Top.v";
unlink $board_top_file if ($old_board_name ne $new_board_name);
 
 
}
get_pin_assignment($self,$name,$top,$target_dir);
}elsif($compiler_type eq "Modelsim"){
modelsim_compilation($self,$name,$top,$target_dir);
 
}else{#verilator
verilator_compilation($self,$name,$top,$target_dir);
 
}
 
$window->destroy;
});
 
$compiler->signal_connect("changed" => sub{
$compiler_options->destroy;
my $new_board_name=$self->object_get_attribute('compile','type');
$compiler_options = ($new_board_name eq "QuartusII")? select_board ($self,$name,$top,$target_dir):
($new_board_name eq "Modelsim")? select_model_path ($self,$name,$top,$target_dir):
gen_label_in_center(" ");
$table->attach($compiler_options,0,2,1,2,'fill','shrink',2,2);
$table->show_all;
 
});
 
}
 
 
 
 
 
sub select_board {
my ($self,$name,$top,$target_dir)=@_;
#get the list of boards located in "boards/*" folder
my @dirs = grep {-d} glob("./lib/boards/*");
my ($fpgas,$init);
foreach my $dir (@dirs) {
my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
$init=$name;
$fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";
}
my $table = def_table(2, 2, FALSE);
my $col=0;
my $row=0;
 
my $old_board_name=$self->object_get_attribute('compile','board');
$table->attach(gen_label_help("The list of supported boards are obtained from \"perl_gui/lib/boards/\" path. You can add your boards by adding its required files in aformentioned path. Note that currently only Altera FPGAs are supported. For boards from other vendors, you need to directly use their own compiler and call $name.v file in your top level module.",'Targeted Board:'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
$table->attach(gen_combobox_object ($self,'compile','board',$fpgas,$init,undef,undef),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
my $bin = $self->object_get_attribute('compile','quartus_bin');
my $Quartus_bin= $ENV{QUARTUS_BIN};
$col=0;
$self->object_add_attribute('compile','quartus_bin',$ENV{QUARTUS_BIN}) if (!defined $bin && defined $Quartus_bin);
$table->attach(gen_label_help("Path to quartus/bin directory. You can set a default path as QUARTUS_BIN envirement variable in ~/.bashrc file.
e.g: export QUARTUS_BIN=/home/alireza/altera/13.0sp1/quartus/bin",'Quartus bin:'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
$table->attach(get_dir_in_object ($self,'compile','quartus_bin',undef,undef,undef),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
return $table;
}
 
sub select_model_path {
my ($self,$name,$top,$target_dir)=@_;
my $table = def_table(2, 2, FALSE);
my $col=0;
my $row=0;
 
my $bin = $self->object_get_attribute('compile','modelsim_bin');
my $modelsim_bin= $ENV{MODELSIM_BIN};
$col=0;
$self->object_add_attribute('compile','modelsim_bin',$modelsim_bin) if (!defined $bin && defined $modelsim_bin);
$table->attach(gen_label_help("Path to modelsim/bin directory. You can set a default path as MODELSIM_BIN envirement variable in ~/.bashrc file.
e.g. export MODELSIM_BIN=/home/alireza/altera/modeltech/bin",'Modelsim bin:'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
$table->attach(get_dir_in_object ($self,'compile','modelsim_bin',undef,undef,undef),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
return $table;
}
 
 
sub remove_pin_assignment{
my $self=shift;
$self->object_remove_attribute('compile_pin_pos');
$self->object_remove_attribute('compile_pin');
$self->object_remove_attribute('compile_assign_type');
$self->object_remove_attribute('compile_pin_range_hsb');
$self->object_remove_attribute('compile_pin_range_lsb');
}
 
 
sub get_pin_assignment{
my ($self,$name,$top,$target_dir)=@_;
my $window = def_popwin_size(80,80,"Step 2: Pin Assignment",'percent');
 
my $table = def_table(2, 2, FALSE);
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$scrolled_win->add_with_viewport($table);
 
 
my $mtable = def_table(10, 10, FALSE);
my $next=def_image_button('icons/right.png','Next');
my $back=def_image_button('icons/left.png','Previous');
 
 
$mtable->attach_defaults($scrolled_win,0,10,0,9);
$mtable->attach($back,2,3,9,10,'shrink','shrink',2,2);
$mtable->attach($next,8,9,9,10,'shrink','shrink',2,2);
 
 
 
 
#get boards pin list
my $board_name=$self->object_get_attribute('compile','board');
my @csv_file = glob("./lib/boards/$board_name/*.csv");
if(!defined $csv_file[0]){
message_dialog("Error: ./lib/boards/$board_name folder does not contain the csv file.!");
$window->destroy;
}
my $board=read_csv_file($csv_file[0]);
 
# Write object file
#open(FILE, ">lib/soc/tttttttt") || die "Can not open: $!";
#print FILE Data::Dumper->Dump([\%$board],['board']);
#close(FILE) || die "Error closing file: $!";
 
my @dirs = ('Input', 'Bidir', 'Output');
my %models;
foreach my $p (@dirs){
my %pins=$board->board_get_pin($p);
$models{$p}=gen_combo_model(\%pins);
}
my $row=0;
my $col=0;
my @lables= ('Port Direction','Port Range ','Port name ','Assigment Type','Board Port name ','Board Port Range');
foreach my $p (@lables){
my $l=gen_label_in_left($p);
$l->set_markup("<b> $p </b>");
$table->attach ($l, $col,$col+1, $row, $row+1,'fill','shrink',2,2);
$col++
}
$row++;
 
 
#read port list
my $vdb=read_verilog_file($top);
my %port_type=get_ports_type($vdb,"${name}_top");
my %port_range=get_ports_rang($vdb,"${name}_top");
my %param = $vdb->get_modules_parameters("${name}_top");
foreach my $p (sort keys %port_type){
my $porttype=$port_type{$p};
my $portrange=$port_range{$p};
 
if (length($portrange)!=0){
#replace parameter with their values
my @a= split (/\b/,$portrange);
foreach my $l (@a){
my $value=$param{$l};
if(defined $value){
chomp $value;
($portrange=$portrange)=~ s/\b$l\b/$value/g if(defined $param{$l});
}
}
$portrange = "[ $portrange ]" ;
}
my $label1= gen_label_in_left(" $porttype");
my $label2= gen_label_in_left(" $portrange");
my $label3= gen_label_in_left(" $p");
 
$table->attach($label1, 0,1, $row, $row+1,'fill','shrink',2,2);
$table->attach($label2, 1,2, $row, $row+1,'fill','shrink',2,2);
$table->attach($label3, 2,3, $row, $row+1,'fill','shrink',2,2);
my $assign_type= "Direct,Negate(~)";
if ($porttype eq 'input') {
my $assign_combo=gen_combobox_object($self,'compile_assign_type',$p,$assign_type,'Direct',undef,undef);
$table->attach( $assign_combo, 3,4, $row, $row+1,'fill','shrink',2,2);
}
 
my $type= ($porttype eq 'input') ? 'Input' :
($porttype eq 'output')? 'Output' : 'Bidir';
 
my $combo= gen_tree_combo($models{$type});
my $saved=$self->object_get_attribute('compile_pin_pos',$p);
my $box;
my $loc=$row;
if(defined $saved) {
my @indices=@{$saved};
my $path = Gtk2::TreePath->new_from_indices(@indices);
my $iter = $models{$type}->get_iter($path);
undef $path;
$combo->set_active_iter($iter);
$box->destroy if(defined $box);
my $text=$self->object_get_attribute('compile_pin',$p);
$box=get_range ($board,$self,$type,$text,$portrange,$p);
$table->attach($box, 5,6, $loc, $loc+1,'fill','shrink',2,2);
}
$combo->signal_connect("changed" => sub{
#get and saved new value
my $treeiter= $combo->get_active_iter();
my $text = $models{$type}->get_value($treeiter, 0);
$self->object_add_attribute('compile_pin',$p,$text);
#get and saved value position in model
my $treepath = $models{$type}->get_path ($treeiter);
my @indices= $treepath->get_indices();
$self->object_add_attribute('compile_pin_pos',$p,\@indices);
#update borad port range
$box->destroy if(defined $box);
$box=get_range ($board,$self,$type,$text,$portrange,$p);
$table->attach($box, 5,6, $loc, $loc+1,'fill','shrink',2,2);
$table->show_all;
 
});
$table->attach($combo, 4,5, $row, $row+1,'fill','shrink',2,2);
 
 
 
 
 
 
$row++;
 
}
$next-> signal_connect("clicked" => sub{
$window->destroy;
quartus_compilation($self,$board,$name,$top,$target_dir);
});
$back-> signal_connect("clicked" => sub{
$window->destroy;
select_compiler($self,$name,$top,$target_dir);
});
 
 
$window->add ($mtable);
$window->show_all();
}
 
 
 
 
 
sub quartus_compilation{
my ($self,$board,$name,$top,$target_dir)=@_;
my $run=def_image_button('icons/run.png','run');
my $back=def_image_button('icons/left.png','Previous');
my $regen=def_image_button('icons/refresh.png','Regenerate Top.v');
 
 
my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
my $board_top_file ="${fpath}Top.v";
unless (-e $board_top_file ){
gen_top_v($self,$board,$name,$top) ;
}
 
my ($app,$table,$tview,$window) = software_main($fpath,'Top.v');
$table->attach($back,1,2,1,2,'shrink','shrink',2,2);
$table->attach($regen,4,5,1,2,'shrink','shrink',2,2);
$table->attach ($run,9, 10, 1,2,'shrink','shrink',0,0);
 
$regen-> signal_connect("clicked" => sub{
my $dialog = Gtk2::MessageDialog->new (my $window,
'destroy-with-parent',
'question', # message type
'yes-no', # which set of buttons?
"Are you sure you want to regenaret the Top.v file? Note that any changes you have made will be lost");
my $response = $dialog->run;
if ($response eq 'yes') {
gen_top_v($self,$board,$name,$top);
$app->load_source("$board_top_file");
}
$dialog->destroy;
});
$back-> signal_connect("clicked" => sub{
$window->destroy;
get_pin_assignment($self,$name,$top,$target_dir);
});
 
 
#compile
$run-> signal_connect("clicked" => sub{
set_gui_status($self,'save_project',1);
$app->do_save();
my $error = 0;
add_info(\$tview,"CREATE: start creating Quartus project in $target_dir\n");
 
#get list of source file
add_info(\$tview," Read the list of all source files $target_dir/src_verilog\n");
my @files = File::Find::Rule->file()
->name( '*.v','*.V','*.sv' )
->in( "$target_dir/src_verilog" );
 
#make sure source files have key word 'module'
my @sources;
foreach my $p (@files){
push (@sources,$p) if(check_file_has_string($p,'module'));
}
my $files = join ("\n",@sources);
add_info(\$tview,"$files\n");
 
#creat project qsf file
my $qsf_file="$target_dir/${name}.qsf";
save_file ($qsf_file,"# Generated using ProNoC\n");
 
#append global assignets to qsf file
my $board_name=$self->object_get_attribute('compile','board');
my @qsfs = glob("./lib/boards/$board_name/*.qsf");
if(!defined $qsfs[0]){
message_dialog("Error: ./lib/boards/$board_name folder does not contain the qsf file.!");
$window->destroy;
}
 
 
my $assignment_file = $qsfs[0];
if(-f $assignment_file){
merg_files ($assignment_file,$qsf_file);
}
 
#add the list of source fils to qsf file
my $s="\n\n\n set_global_assignment -name TOP_LEVEL_ENTITY Top\n";
foreach my $p (@sources){
my ($name,$path,$suffix) = fileparse("$p",qr"\..[^.]*$");
$s="$s set_global_assignment -name VERILOG_FILE $p\n" if ($suffix eq ".v");
$s="$s set_global_assignment -name SYSTEMVERILOG_FILE $p\n" if ($suffix eq ".sv");
}
append_text_to_file($qsf_file,$s);
add_info(\$tview,"\n Qsf file has been created\n");
 
#start compilation
my $Quartus_bin= $self->object_get_attribute('compile','quartus_bin');;
add_info(\$tview, "Start Quartus compilation.....\n");
my @compilation_command =(
"cd \"$target_dir/\" \n xterm -e sh -c '$Quartus_bin/quartus_map --64bit $name --read_settings_files=on; echo \$? > status' ",
"cd \"$target_dir/\" \n xterm -e sh -c '$Quartus_bin/quartus_fit --64bit $name --read_settings_files=on; echo \$? > status' ",
"cd \"$target_dir/\" \n xterm -e sh -c '$Quartus_bin/quartus_asm --64bit $name --read_settings_files=on; echo \$? > status' ",
"cd \"$target_dir/\" \n xterm -e sh -c '$Quartus_bin/quartus_sta --64bit $name;echo \$? > status' ");
foreach my $cmd (@compilation_command){
add_info(\$tview,"$cmd\n");
unlink "$target_dir/status";
my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout( $cmd);
open(my $fh, "<$target_dir/status") || die "Can not open: $!";
read($fh,my $status,1);
close($fh);
if("$status" != "0"){
($stdout,$exit)=run_cmd_in_back_ground_get_stdout("cd \"$target_dir/output_files/\" \n grep -h \"Error (\" *");
add_colored_info(\$tview,"$stdout\n Quartus compilation failed !\n",'red');
$error=1;
last;
}
}
add_colored_info(\$tview,"Quartus compilation is done successfully in $target_dir!\n", 'blue') if($error==0);
 
});
 
 
 
 
 
 
 
}
 
 
 
 
 
 
sub modelsim_compilation{
my ($self,$name,$top,$target_dir)=@_;
#my $window = def_popwin_size(80,80,"Step 2: Compile",'percent');
my $run=def_image_button('icons/run.png','run');
my $back=def_image_button('icons/left.png','Previous');
my $regen=def_image_button('icons/refresh.png','Regenerate testbench.v');
#create testbench.v
gen_modelsim_soc_testbench ($self,$name,$top,$target_dir) if ((-f "$target_dir/src_verilog/testbench.v")==0);
 
 
 
my ($app,$table,$tview,$window) = software_main("$target_dir/src_verilog",'testbench.v');
$table->attach($back,1,2,1,2,'shrink','shrink',2,2);
$table->attach($regen,4,5,1,2,'shrink','shrink',2,2);
$table->attach ($run,9, 10, 1,2,'shrink','shrink',0,0);
$regen-> signal_connect("clicked" => sub{
my $dialog = Gtk2::MessageDialog->new (my $window,
'destroy-with-parent',
'question', # message type
'yes-no', # which set of buttons?
"Are you sure you want to regenaret the testbench.v file? Note that any changes you have made will be lost");
my $response = $dialog->run;
if ($response eq 'yes') {
gen_modelsim_soc_testbench ($self,$name,$top,$target_dir);
$app->load_source("$target_dir/src_verilog/testbench.v");
}
$dialog->destroy;
});
 
 
$back-> signal_connect("clicked" => sub{
$window->destroy;
select_compiler($self,$name,$top,$target_dir);
});
 
#creat modelsim dir
add_info(\$tview,"creat Modelsim dir in $target_dir\n");
my $model="$target_dir/Modelsim";
rmtree("$model");
mkpath("$model/rtl_work",1,01777);
#create modelsim.tcl file
my $tcl="#!/usr/bin/tclsh
 
 
transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
";
 
#Get the list of all verilog files in src_verilog folder
add_info(\$tview,"Get the list of all verilog files in src_verilog folder\n");
my @files = File::Find::Rule->file()
->name( '*.v','*.V','*.sv' )
->in( "$target_dir/src_verilog" );
#make sure source files have key word 'module'
my @sources;
foreach my $p (@files){
my ($name,$path,$suffix) = fileparse("$p",qr"\..[^.]*$");
if(check_file_has_string($p,'module')){
if ($suffix eq ".sv"){$tcl=$tcl."vlog -sv -work work +incdir+$path \{$p\}\n";}
else {$tcl=$tcl."vlog -vlog01compat -work work +incdir+$path \{$p\}\n";}
}
}
 
$tcl="$tcl
vsim -t 1ps -L rtl_work -L work -voptargs=\"+acc\" testbench
 
add wave *
view structure
view signals
run -all
";
 
save_file ("$model/run.tcl",$tcl);
$run -> signal_connect("clicked" => sub{
set_gui_status($self,'save_project',1);
$app->do_save();
my $modelsim_bin= $self->object_get_attribute('compile','modelsim_bin');
my $cmd="cd $target_dir; $modelsim_bin/vsim -do $model/run.tcl";
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
add_info(\$tview,"$stderr\n");
}else {
add_info(\$tview,"$stdout\n");
}
 
});
#$window->show_all();
}
 
 
 
 
sub verilator_compilation {
my ($self,$name,$top,$target_dir)=@_;
my $window = def_popwin_size(80,80,"Step 2: Compile",'percent');
my $mtable = def_table(10, 10, FALSE);
my ($outbox,$outtext)= create_text();
add_colored_tag($outtext,'red');
add_colored_tag($outtext,'blue');
my $next=def_image_button('icons/run.png','Next');
my $back=def_image_button('icons/left.png','Previous');
 
$mtable->attach_defaults ($outbox ,0, 10, 4,9);
$mtable->attach($back,2,3,9,10,'shrink','shrink',2,2);
$mtable->attach($next,8,9,9,10,'shrink','shrink',2,2);
 
 
$back-> signal_connect("clicked" => sub{
$window->destroy;
select_compiler($self,$name,$top,$target_dir);
});
$next-> signal_connect("clicked" => sub{
$window->destroy;
verilator_testbench($self,$name,$top,$target_dir);
});
 
#creat verilator dir
add_info(\$outtext,"creat verilator dir in $target_dir\n");
my $verilator="$target_dir/verilator";
rmtree("$verilator/rtl_work");
rmtree("$verilator/processed_rtl");
mkpath("$verilator/rtl_work/",1,01777);
mkpath("$verilator/processed_rtl/",1,01777);
 
#copy all verilog files in rtl_work folder
add_info(\$outtext,"Copy all verilog files in rtl_work folder\n");
my @files = File::Find::Rule->file()
->name( '*.v','*.V','*.sv' )
->in( "$target_dir/src_verilog" );
foreach my $file (@files) {
copy($file,"$verilator/rtl_work/");
}
 
#"split all verilog modules in separate files"
add_info(\$outtext,"split all verilog modules in separate files\n");
my $split = Verilog::EditFiles->new
(outdir => "$verilator/processed_rtl",
translate_synthesis => 0,
celldefine => 0,
);
$split->read_and_split(glob("$verilator/rtl_work/*.v"));
$split->read_and_split(glob("$verilator/rtl_work/*.sv"));
$split->write_files();
#run verilator
#my $cmd= "cd \"$verilator/processed_rtl\" \n xterm -e sh -c ' verilator --cc $name.v --profile-cfuncs --prefix \"Vtop\" -O3 -CFLAGS -O3'";
my $cmd= "cd \"$verilator/processed_rtl\" \n verilator --cc $name.v --profile-cfuncs --prefix \"Vtop\" -O3 -CFLAGS -O3";
add_info(\$outtext,"$cmd\n");
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
add_info(\$outtext,"$stderr\n");
}else {
add_info(\$outtext,"$stdout\n");
}
 
#check if verilator model has been generated
if (-f "$verilator/processed_rtl/obj_dir/Vtop.cpp"){
add_colored_info(\$outtext,"Veriator model has been generated successfully!",'blue');
}else {
add_colored_info(\$outtext,"Verilator compilation failed!\n","red");
$next->destroy();
}
 
 
 
$window->add ($mtable);
$window->show_all();
 
 
 
}
 
sub gen_verilator_soc_testbench {
my ($self,$name,$top,$target_dir)=@_;
my $verilator="$target_dir/verilator";
my $dir="$verilator/";
my $soc_top= $self->soc_get_top ();
my @intfcs=$soc_top->top_get_intfc_list();
my %PP;
my $top_port_info="IO type\t port_size\t port_name\n";
foreach my $intfc (@intfcs){
my $key= ( $intfc eq 'plug:clk[0]')? 'clk' :
( $intfc eq 'plug:reset[0]')? 'reset':
( $intfc eq 'plug:enable[0]')? 'en' : 'other';
my $key1="${key}1";
my $key0="${key}0";
 
my @ports=$soc_top->top_get_intfc_ports_list($intfc);
foreach my $p (@ports){
my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
$PP{$key1}= (defined $PP{$key1})? "$PP{$key1} top->$p=1;\n" : "top->$p=1;\n";
$PP{$key0}= (defined $PP{$key0})? "$PP{$key0} top->$p=0;\n" : "top->$p=0;\n";
$top_port_info="$top_port_info $type $range top->$p \n";
}
 
}
my $main_c=get_license_header("testbench.cpp");
$main_c="$main_c
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#include <verilated.h> // Defines common routines
#include \"Vtop.h\" // From Verilating \"$name.v\" file
 
Vtop *top;
/*
$top_port_info
*/
 
int reset,clk;
unsigned int main_time = 0; // Current simulation time
 
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv); // Remember args
top = new Vtop;
 
/********************
* initialize input
*********************/
 
$PP{reset1}
$PP{en1}
main_time=0;
printf(\"Start Simulation\\n\");
while (!Verilated::gotFinish()) {
if (main_time >= 10 ) {
$PP{reset0}
}
 
 
if ((main_time & 1) == 0) {
$PP{clk1} // Toggle clock
// you can change the inputs and read the outputs here in case they are captured at posedge of clock
 
 
 
}//if
else
{
$PP{clk0}
 
}//else
main_time ++;
top->eval();
}
top->final();
}
 
double sc_time_stamp () { // Called by \$time in Verilog
return main_time;
}
";
save_file("$dir/testbench.cpp",$main_c);
 
 
}
 
 
sub gen_modelsim_soc_testbench {
my ($self,$name,$top,$target_dir)=@_;
my $dir="$target_dir/src_verilog";
my $soc_top= $self->object_get_attribute('top_ip',undef);
my @intfcs=$soc_top->top_get_intfc_list();
my %PP;
my $top_port_def="// ${name}.v IO definition \n";
my $pin_assign;
my $rst_inputs='';
 
#read port list
my $vdb=read_verilog_file($top);
my %param = $vdb->get_modules_parameters("${name}_top");
 
 
 
 
foreach my $intfc (@intfcs){
my $key= ( $intfc eq 'plug:clk[0]')? 'clk' :
( $intfc eq 'plug:reset[0]')? 'reset':
( $intfc eq 'plug:enable[0]')? 'en' : 'other';
my $key1="${key}1";
my $key0="${key}0";
 
my @ports=$soc_top->top_get_intfc_ports_list($intfc);
my $f=1;
foreach my $p (@ports){
my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
$PP{$key1}= (defined $PP{$key1})? "$PP{$key1} $p=1;\n" : "$p=1;\n";
$PP{$key0}= (defined $PP{$key0})? "$PP{$key0} $p=0;\n" : "$p=0;\n";
 
 
if (length($range)!=0){
#replace parameter with their values
my @a= split (/\b/,$range);
foreach my $l (@a){
my $value=$param{$l};
if(defined $value){
chomp $value;
($range=$range)=~ s/\b$l\b/$value/g if(defined $param{$l});
}
}
$range = "[ $range ]" ;
}
 
 
 
if($type eq 'input'){
$top_port_def="$top_port_def reg $range $p;\n"
}else{
$top_port_def="$top_port_def wire $range $p;\n"
}
$pin_assign=(defined $pin_assign)? "$pin_assign,\n\t\t.$p($p)": "\t\t.$p($p)";
$rst_inputs= "$rst_inputs $p=0;\n" if ($key eq 'other' && $type eq 'input' );
}
 
}
 
my $test_v= get_license_header("testbench.v");
 
$test_v ="$test_v
 
`timescale 1ns/1ps
 
module testbench;
 
$top_port_def
 
 
$name uut (
$pin_assign
);
 
//clock defination
initial begin
forever begin
#5 $PP{clk0}
#5 $PP{clk1}
end
end
 
 
 
initial begin
// reset $name module at the start up
$PP{reset1}
$PP{en1}
$rst_inputs
// deasert the reset after 200 ns
#200
$PP{reset0}
 
// write your testbench here
 
 
 
 
end
 
endmodule
";
save_file("$dir/testbench.v",$test_v);
 
 
}
 
sub verilator_testbench{
my ($self,$name,$top,$target_dir)=@_;
my $verilator="$target_dir/verilator";
my $dir="$verilator";
gen_verilator_soc_testbench (@_) if((-f "$dir/testbench.cpp")==0);
#copy makefile
copy("../script/verilator_soc_make", "$verilator/processed_rtl/obj_dir/Makefile");
 
my ($app,$table,$tview,$window) = software_main($dir,'testbench.cpp');
 
 
my $make = def_image_button('icons/gen.png','Compile');
my $regen=def_image_button('icons/refresh.png','Regenerate Testbench.cpp');
my $run = def_image_button('icons/run.png','Run');
my $back=def_image_button('icons/left.png','Previous');
$table->attach ($back,1,2,1,2,'shrink','shrink',0,0);
$table->attach ($regen,3,4,1,2,'shrink','shrink',0,0);
$table->attach ($make,7, 8, 1,2,'shrink','shrink',0,0);
$table->attach ($run,9, 10, 1,2,'shrink','shrink',0,0);
 
$back-> signal_connect("clicked" => sub{
$window->destroy;
verilator_compilation($self,$name,$top,$target_dir);
});
 
$regen-> signal_connect("clicked" => sub{
my $dialog = Gtk2::MessageDialog->new (my $window,
'destroy-with-parent',
'question', # message type
'yes-no', # which set of buttons?
"Are you sure you want to regenaret the testbench.cpp file? Note that any changes you have made will be lost");
my $response = $dialog->run;
if ($response eq 'yes') {
gen_verilator_soc_testbench ($self,$name,$top,$target_dir);
$app->load_source("$dir/testbench.cpp");
}
$dialog->destroy;
});
$make -> signal_connect("clicked" => sub{
$app->do_save();
copy("$dir/testbench.cpp", "$verilator/processed_rtl/obj_dir/testbench.cpp");
run_make_file("$verilator/processed_rtl/obj_dir/",$tview);
 
});
 
$run -> signal_connect("clicked" => sub{
my $bin="$verilator/processed_rtl/obj_dir/testbench";
if (-f $bin){
my $cmd= "cd \"$verilator/processed_rtl/obj_dir/\" \n xterm -e sh -c $bin";
add_info(\$tview,"$cmd\n");
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
if(length $stderr>1){
add_colored_info(\$tview,"$stderr\n",'red');
}else {
add_info(\$tview,"$stdout\n");
}
 
}else{
add_colored_info(\$tview,"Cannot find $bin executable binary file! make sure you have compiled the testbench successfully\n", 'red')
}
});
 
 
}
 
 
1;
/lib/perl/diagram.pl
0,0 → 1,334
#!/usr/bin/perl -w
use strict;
use warnings;
use soc;
require "widget.pl";
require "emulator.pl";
use File::Copy;
 
#use GraphViz;
 
 
sub get_dot_file{
my $soc= shift;
my $soc_name=$soc->object_get_attribute('soc_name');
my $remove_clk = $soc->object_get_attribute("diagrame","show_clk");
my $remove_reset = $soc->object_get_attribute("diagrame","show_reset");
my $remove_unused = $soc->object_get_attribute("diagrame","show_unused");
 
my $dotfile=
"digraph G {
graph [rankdir = LR , splines=polyline, overlap = false];
node[shape=record];
";
 
my @all_instances=$soc->soc_get_all_instances();
#print "@all_instances\n";
my $graph_connect= '';
my $n=0;
#my %socket_color;
foreach my $instance_id (@all_instances){
my $first=1;
my $instance_name=$soc->soc_get_instance_name($instance_id);
$dotfile="$dotfile \n\t$instance_id \[label=\"{ ";
my @sockets= $soc->soc_get_all_sockets_of_an_instance($instance_id);
@sockets = remove_scolar_from_array(\@sockets,'clk') if ($remove_clk);
@sockets = remove_scolar_from_array(\@sockets,'reset') if ($remove_reset);
 
foreach my $socket (@sockets){
 
my @nums=$soc->soc_list_socket_nums($instance_id,$socket);
foreach my $num (@nums){
my $name= $soc->soc_get_socket_name ($instance_id,$socket,$num);
my ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($instance_id,$socket);
my $v=$soc->soc_get_module_param_value($instance_id,$s_value);
$v=1 if ( length( $v || '' ) ==0);
#for(my $i=$v-1; $i>=0; $i--) {
for(my $i=0; $i<$v; $i++) {
#$socket_color{socket_${socket}\_$i}=$n;
#$n = ($n<30)? $n+1 : 0;
my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($instance_id,$socket,$i);
my %connected_plugs=%$ref1;
my %connected_plug_nums=%$ref2;
if(%connected_plugs || $remove_unused==0){
$dotfile= ($first)? "$dotfile\{<socket_${socket}\_$i>$name\_$i" : "$dotfile |<socket_${socket}_${i}>$name\_${i}";
$first=0;
}
}
}
}
$dotfile=($first)? "$dotfile $instance_name" : "$dotfile}|$instance_name";
$first=1;
my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
@plugs = remove_scolar_from_array(\@plugs,'clk') if ($remove_clk);
@plugs = remove_scolar_from_array(\@plugs,'reset') if ($remove_reset);
 
my %plug_order;
my @noconnect;
foreach my $plug (@plugs){
my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
foreach my $num (@nums){
my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
if(defined $connect_socket || $remove_unused==0){
#$dotfile= ($first)? "$dotfile |{<plug_${plug}_${num}>$name" : "$dotfile|<plug_${plug}_${num}>$name";
if(defined $connect_id && defined $connect_socket){
my @sockets= $soc->soc_get_all_sockets_of_an_instance($connect_id);
my $order_val=0;
my $s1=get_pos($connect_id, @all_instances);
my $s2=get_pos($connect_socket, @sockets);
$order_val=$s1*1000000+$s2*10000+$connect_socket_num;
$plug_order{$order_val}= "<plug_${plug}_${num}>$name";
}else {push (@noconnect,"<plug_${plug}_${num}>$name");}
}
 
#my $connect_name=$soc->soc_get_instance_name($connect_id);
#my $color = get_color_hex_string($n);
#$n = ($n<30)? $n+1 : 0;
$graph_connect="$graph_connect $instance_id:plug_${plug}_${num} -> $connect_id:socket_${connect_socket}_${connect_socket_num} [ dir=none]\n" if(defined $connect_socket);
}
}
foreach my $p (sort {$a<=>$b} keys %plug_order){
my $k=$plug_order{$p};
#print "$instance_name : $k=\$plug_order{$p}\n";
$dotfile= ($first) ? "$dotfile |{ ${k}": "$dotfile |${k}";
$first=0;
 
}
 
foreach my $k (@noconnect){
$dotfile= ($first) ? "$dotfile |{ ${k}": "$dotfile |${k}";
$first=0;
}
 
$dotfile= "$dotfile} }\"];";
 
}
$dotfile="$dotfile\n\n$graph_connect";
$dotfile="$dotfile\n\n}\n";
 
 
return $dotfile;
 
 
}
 
 
 
 
 
sub show_tile_diagram {
my $soc= shift;
 
my $table=def_table(20,20,FALSE);
my $window=def_popwin_size(80,80,"Processing Tile functional block diagram",'percent');
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$window->add ($table);
my $plus = def_image_button('icons/plus.png',undef,TRUE);
my $minues = def_image_button('icons/minus.png',undef,TRUE);
my $unused = gen_check_box_object ($soc,"diagrame","show_unused",0,undef,undef);
my $save = def_image_button('icons/save.png',undef,TRUE);
my $clk = gen_check_box_object ($soc,"diagrame","show_clk",0,undef,undef);
my $reset = gen_check_box_object ($soc,"diagrame","show_reset",0,undef,undef);
#my $save = def_image_button('icons/save.png',undef,TRUE);
 
my $scale=$soc->object_get_attribute("diagrame","scale");
$scale= 1 if (!defined $scale);
my $col=0;
$table->attach ($plus , $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
$table->attach ($minues, $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
$table->attach ($save, $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
$table->attach (gen_label_in_left(" Remove unconnected Interfaces"), $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
$table->attach ($unused, $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
$table->attach (gen_label_in_left(" Remove Clk Interfaces"), $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
$table->attach ($clk, $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
$table->attach (gen_label_in_left(" Remove Reset Interfaces"), $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
$table->attach ($reset, $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
while ($col<20){
my $tmp=gen_label_in_left('');
$table->attach_defaults ($tmp, $col, $col+1,0,1);$col++;
}
$plus -> signal_connect("clicked" => sub{
$scale*=1.1 if ($scale <10);
$soc->object_add_attribute("diagrame","scale", $scale );
show_diagram ($soc,$scrolled_win,$table);
});
$minues -> signal_connect("clicked" => sub{
$scale*=.9 if ($scale >0.1); ;
$soc->object_add_attribute("diagrame","scale", $scale );
show_diagram ($soc,$scrolled_win,$table);
});
$save-> signal_connect("clicked" => sub{
save_diagram_as ($soc);
});
$unused-> signal_connect("toggled" => sub{
if(gen_diagram($soc)){
show_diagram ($soc,$scrolled_win,$table);
}
 
});
$clk-> signal_connect("toggled" => sub{
if(gen_diagram($soc)){
show_diagram ($soc,$scrolled_win,$table);
}
 
});
$reset-> signal_connect("toggled" => sub{
if(gen_diagram($soc)){
show_diagram ($soc,$scrolled_win,$table);
}
 
});
 
 
 
if(gen_diagram($soc)){
show_diagram ($soc,$scrolled_win,$table);
}
$window->show_all();
 
 
 
 
}
 
 
 
sub gen_diagram {
my ($soc)=@_;
 
 
my $dotfile= get_dot_file($soc);
my $tmp_dir = "$ENV{'PRONOC_WORK'}/tmp";
mkpath("$tmp_dir/",1,01777);
open(FILE, ">$tmp_dir/diagram.txt") || die "Can not open: $!";
print FILE $dotfile;
close(FILE) || die "Error closing file: $!";
 
my $cmd = "dot $tmp_dir/diagram.txt | neato -n -Tpng -o $tmp_dir/diagram.png";
 
my ($stdout,$exit,$stderr)= run_cmd_in_back_ground_get_stdout ($cmd);
 
if ( length( $stderr || '' ) !=0) {
message_dialog("$stderr\nHave you installed graphviz? If not run \n \t \"sudo apt-get install graphviz\" \n in terminal");
return 0;
}
else {
#my $diagram=show_gif("$tmp_dir/diagram.png");
return 1;
}
 
 
}
 
 
 
sub show_diagram {
my ($soc,$scrolled_win,$table)=@_;
 
$scrolled_win->destroy;
$scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$table->attach_defaults ($scrolled_win, 0, 20, 1, 20); #,'fill','shrink',2,2);
my $scale=$soc->object_get_attribute("diagrame","scale");
$scale= 1 if (!defined $scale);
my $tmp_dir = "$ENV{'PRONOC_WORK'}/tmp";
my $diagram=open_image("$tmp_dir/diagram.png",70*$scale,70*$scale,'percent');
$scrolled_win->add_with_viewport($diagram);
$scrolled_win->show_all();
 
 
}
 
 
sub save_diagram_as {
my $soc= shift;
my $file;
my $title ='Save as';
 
 
 
my @extensions=('png');
my $open_in=undef;
my $dialog = Gtk2::FileChooserDialog->new(
'Save file', undef,
'save',
'gtk-cancel' => 'cancel',
'gtk-ok' => 'ok',
);
# if(defined $extension){
foreach my $ext (@extensions){
my $filter = Gtk2::FileFilter->new();
$filter->set_name($ext);
$filter->add_pattern("*.$ext");
$dialog->add_filter ($filter);
}
# }
if(defined $open_in){
$dialog->set_current_folder ($open_in);
# print "$open_in\n";
}
if ( "ok" eq $dialog->run ) {
$file = $dialog->get_filename;
my $ext = $dialog->get_filter;
$ext=$ext->get_name;
my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
$file = ($suffix eq ".$ext" )? $file : "$file.$ext";
$soc->object_add_attribute("graph_save","name",$file);
$soc->object_add_attribute("graph_save","extension",$ext);
my $tmp = "$ENV{'PRONOC_WORK'}/tmp/diagram.png";
copy ($tmp,$file);
 
 
}
$dialog->destroy;
 
 
 
 
}
 
 
 
return 1;
/lib/perl/emulator.pl
62,17 → 62,23
$results[1]= [0];
my $legend_info="This attribute controls placement of the legend within the graph image. The value is supplied as a two-letter string, where the first letter is placement (a B or an R for bottom or right, respectively) and the second is alignment (L, R, C, T, or B for left, right, center, top, or bottom, respectively). ";
my $fontsize="Tiny,Small,MediumBold,Large,Giant";
 
 
 
my @ginfo = (
{ label=>"Graph Title", param_name=>"G_Title", type=>"Entry", default_val=>undef, content=>undef, info=>undef, param_parent=>'graph_param', ref_delay=>undef },
#{ label=>"Graph Title", param_name=>"G_Title", type=>"Entry", default_val=>undef, content=>undef, info=>undef, param_parent=>'graph_param', ref_delay=>undef },
{ label=>"Y Axix Title", param_name=>"Y_Title", type=>"Entry", default_val=>'Latency (clock)', content=>undef, info=>undef, param_parent=>'graph_param', ref_delay=>undef },
{ label=>"X Axix Title", param_name=>"X_Title", type=>"Entry", default_val=>'Load per router (flits/clock (%))', content=>undef, info=>undef, param_parent=>'graph_param',ref_delay=>undef },
{ label=>"legend placement", param_name=>"legend_placement", type=>'Combo-box', default_val=>'BL', content=>"BL,BC,BR,RT,RC,RB", info=>$legend_info, param_parent=>'graph_param', ref_delay=>undef},
{ label=>"legend placement", param_name=>"legend_placement", type=>'Combo-box', default_val=>'BL', content=>"BL,BC,BR,RT,RC,RB", info=>$legend_info, param_parent=>'graph_param', ref_delay=>1},
{ label=>"Y min", param_name=>"Y_MIN", type=>'Spin-button', default_val=>0, content=>"0,1024,1", info=>"Y axix minimum value", param_parent=>'graph_param', ref_delay=> 5},
{ label=>"X min", param_name=>"X_MIN", type=>'Spin-button', default_val=>0, content=>"0,1024,1", info=>"X axix minimum value", param_parent=>'graph_param', ref_delay=> 5},
{ label=>"X max", param_name=>"X_MAX", type=>'Spin-button', default_val=>100, content=>"0,1024,1", info=>"X axix maximum value", param_parent=>'graph_param', ref_delay=> 5},
{ label=>"Line Width", param_name=>"LINEw", type=>'Spin-button', default_val=>3, content=>"1,20,1", info=>undef, param_parent=>'graph_param', ref_delay=> 5},
 
{ label=>"legend font size", param_name=>"legend_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>'graph_param', ref_delay=>1},
{ label=>"label font size", param_name=>"label_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>'graph_param', ref_delay=>1},
{ label=>"label font size", param_name=>"x_axis_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>'graph_param', ref_delay=>1},
);
 
 
147,10 → 153,13
my $graphs_info;
foreach my $d ( @ginfo){
$graphs_info->{$d->{param_name}}=$emulate->object_get_attribute( 'graph_param',$d->{param_name});
$graphs_info->{$d->{param_name}}= $d->{default_val} if(!defined $graphs_info->{$d->{param_name}});
if(!defined $graphs_info->{$d->{param_name}}){
$graphs_info->{$d->{param_name}}= $d->{default_val};
$emulate->object_add_attribute( 'graph_param',$d->{param_name},$d->{default_val} );
}
}
 
$graph->set (
x_label => $graphs_info->{X_Title},
165,11 → 174,25
box_axis => 0,
skip_undef=> 1,
transparent => 1,
line_width => $graphs_info->{LINEw},
cycle_clrs => 'blue',
legend_placement => $graphs_info->{legend_placement},
dclrs=>\@color,
# transparent => 1,
 
transparent => '0',
bgclr => 'white',
boxclr => 'white',
fgclr => 'black',
textclr => 'black',
labelclr => 'black',
axislabelclr => 'black',
legendclr => 'black',
cycle_clrs => '1',
 
line_width => $graphs_info->{LINEw},
# cycle_clrs => 'black',
legend_placement => $graphs_info->{legend_placement},
dclrs=>\@color,
y_number_format=>"%.1f",
BACKGROUND=>'black',
);
}#if
$graph->set_legend(@legend_keys);
317,6 → 340,19
my ($emulate,$self, $data) = @_;
$self->{graphdata} = $data;
my $graph = $self->{graph};
my $font;
$font= $emulate->object_get_attribute( 'graph_param','label_font');
$graph->set_x_label_font(GD::Font->$font);
$graph->set_y_label_font(GD::Font->$font);
$font= $emulate->object_get_attribute( 'graph_param','legend_font');
$graph->set_legend_font(GD::Font->$font);
 
$font= $emulate->object_get_attribute( 'graph_param','x_axis_font');
#$graph->set_values_font(GD::gdGiantFont);
$graph->set_x_axis_font(GD::Font->$font);
$graph->set_y_axis_font(GD::Font->$font);
 
my $gd2=$graph->plot($data) or warn $graph->error;
my $loader = Gtk2::Gdk::PixbufLoader->new;
438,8 → 474,7
 
sub get_graph_setting {
my ($emulate,$ref)=@_;
my($width,$hight)=max_win_size();
my $window=def_popwin_size($width/3,$hight/3,'Graph Setting');
my $window=def_popwin_size(33,33,'Graph Setting','percent');
my $table = def_table(10, 2, FALSE);
my $row=0;
 
490,7 → 525,7
sub get_color_window{
my ($emulate,$atrebute1,$atrebute2)=@_;
my $window=def_popwin_size(800,600,"Select line color");
my $window=def_popwin_size(40,40,"Select line color",'percent');
my ($r,$c)=(4,8);
my $table= def_table(5,6,TRUE);
for (my $col=0;$col<$c;$col++){
746,8 → 781,7
my ($emulate,$mode, $row_num,$info)=@_;
my $table=def_table($row_num,10,FALSE);
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
my($width,$hight)=max_win_size();
my $set_win=def_popwin_size($width/2.5,$hight*.8,"NoC configuration setting");
my $set_win=def_popwin_size(40,80,"NoC configuration setting",'percent');
$scrolled_win->set_policy( "automatic", "automatic" );
$scrolled_win->add_with_viewport($table);
1062,8 → 1096,8
my $image;
my $vbox = Gtk2::HBox->new (TRUE,1);
$image = Gtk2::Image->new_from_file ("icons/load.gif") if($status eq "run");
$image = def_image("icons/button_ok.png") if($status eq "done");
$image = def_image("icons/cancel.png") if($status eq "failed");
$image = def_icon("icons/button_ok.png") if($status eq "done");
$image = def_icon("icons/cancel.png") if($status eq "failed");
#$image_file = "icons/load.gif" if($status eq "run");
if (defined $image) {
1631,7 → 1665,10
$simulate->object_add_attribute('status',undef,'run');
set_gui_status($simulate,"ref",1);
show_info($info, "Start Simulation\n");
 
my $name=$simulate->object_get_attribute ("simulate_name",undef);
my $log= (defined $name)? "$ENV{PRONOC_WORK}/simulate/$name.log": "$ENV{PRONOC_WORK}/simulate/sim.log";
#unlink $log; # remove old log file
my $sample_num=$simulate->object_get_attribute("emulate_num",undef);
for (my $i=1; $i<=$sample_num; $i++){
my $status=$simulate->object_get_attribute ("sample$i","status");
1676,11 → 1713,17
add_info($info, "Run $bin with injection ratio of $ratio_in \% \n");
my $cmd="$bin -t \"$patern\" -s $PCK_SIZE -n $PCK_NUM_LIMIT -c $SIM_CLOCK_LIMIT -i $ratio_in -p \"100,0,0,0,0\" -h \"$HOTSPOT_PERCENTAGE,$HOTSPOT_NUM,$HOTSPOT_CORE_1,$HOTSPOT_CORE_2,$HOTSPOT_CORE_3,$HOTSPOT_CORE_4,$HOTSPOT_CORE_5\"";
add_info($info, "$cmd \n");
my $time_strg = localtime;
append_text_to_file($log,"started at:$time_strg\n"); #save simulation output
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout("$cmd");
if($exit){
add_info($info, "Error in running simulation: $stderr \n");
return;
}
append_text_to_file($log,$stdout); #save simulation output
$time_strg = localtime;
append_text_to_file($log,"Ended at:$time_strg\n"); #save simulation output
my @q =split (/average latency =/,$stdout);
my $d=$q[1];
@q =split (/\n/,$d);
/lib/perl/interface_gen.pl
17,7 → 17,7
if (!defined $file) {return; }
if (-e $file) {
my $vdb = read_file($file);
my $vdb = read_verilog_file($file);
my @modules=sort $vdb->get_modules($file);
#foreach my $p(@module_list) {print "$p\n"}
$intfc_gen->intfc_set_interface_file($file);
177,13 → 177,13
 
sub get_interface_ports {
my ($intfc_gen,$info)=@_;
my $window=def_popwin_size(800,600,"Import Ports");
my $window=def_popwin_size(60,60,"Import Ports",'percent');
 
my $file=$intfc_gen->intfc_get_interface_file();
if (!defined $file){show_info(\$info,"File name has not been defined yet!"); return;}
my $module=$intfc_gen->intfc_get_module_name();
if (!defined $module){ show_info(\$info,"Module name has not been selected yet!"); return;}
my $vdb=read_file($file);
my $vdb=read_verilog_file($file);
my %port_type=get_ports_type($vdb,$module);
my %port_range=get_ports_rang($vdb,$module);
331,8 → 331,8
my $combo=gen_combobox_object($intfc_gen,'connection_num',undef,"single connection,multi connection","single connection",'refresh',1);
my $combo_box=labele_widget_info(" Select soket type:",$combo,'Define the soket as multi connection if only all interfaces ports all output and they can feed more than one plug connection');
$table->attach_defaults ($entrybox, 0, 2 , $row, $row+1);
$table->attach_defaults ($combo_box, 3, 5 , $row, $row+1);
$table->attach ($entrybox, 0, 2 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($combo_box, 3, 6 , $row, $row+1,'expand','shrink',2,2);
}
 
349,7 → 349,7
my $size = keys %types;
if($size >0){
my $sep = Gtk2::HSeparator->new;
$table->attach_defaults ($sep, 0, 10 , $row, $row+1); $row++;
$table->attach ($sep, 0, 10 , $row, $row+1,'fill','fill',2,2); $row++;
my $swap= def_image_button("icons/swap.png","swap");
388,26 → 388,26
my $sep2 = Gtk2::HSeparator->new;
$table->attach ($lab1, 1, 2 , $row, $row+1,'shrink','shrink',2,2);
$table->attach ($swap, 3, 4 , $row, $row+1,'shrink','shrink',2,2);
$table->attach ($lab2, 5, 6 , $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach_defaults ($sep2, 0, 9 , $row, $row+1); $row++;
$table->attach ($lab1, 1, 2 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($swap, 3, 4 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($lab2, 5, 6 , $row, $row+1,'expand','shrink',2,2); $row++;
$table->attach ($sep2, 0, 9 , $row, $row+1,'fill','fill',2,2); $row++;
my $lab3= gen_label_in_center("Type");
my $lab4= gen_label_in_center("Range");
my $lab5= gen_label_in_center("Name");
$table->attach_defaults ($lab3, 0, 1 , $row, $row+1);
$table->attach_defaults ($lab4, 1, 2 , $row, $row+1);
$table->attach_defaults ($lab5, 2, 3 , $row, $row+1);
$table->attach ($lab3, 0, 1 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($lab4, 1, 2 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($lab5, 2, 3 , $row, $row+1,'expand','shrink',2,2);
my $lab6= gen_label_in_center("Type");
my $lab7= gen_label_in_center("Range");
my $lab8= gen_label_in_center("Name");
$table->attach_defaults ($lab6, 4, 5 , $row, $row+1);
$table->attach_defaults ($lab7, 5, 6 , $row, $row+1);
$table->attach_defaults ($lab8, 6, 7 , $row, $row+1);
$table->attach ($lab6, 4, 5 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($lab7, 5, 6 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($lab8, 6, 7 , $row, $row+1,'expand','shrink',2,2);
my $lab9= gen_label_help ("When an IP core does not have any of interface output port, the default value will be send to the IP core's input port which is supposed to be connected to that port","Output port Default ");
$table->attach_defaults ($lab9, 8, 9 , $row, $row+1);
$table->attach ($lab9, 8, 9 , $row, $row+1,'expand','shrink',2,2);
$row++;
foreach my $id (sort keys %ranges){
456,15 → 456,15
#$box->pack_start($entry3,TRUE,FALSE,3);
#$box->pack_start($separator,TRUE,FALSE,3);
$table->attach_defaults ($combo1, 0, 1 , $row, $row+1);
$table->attach_defaults ($entry2, 1, 2 , $row, $row+1);
$table->attach_defaults ($entry3, 2, 3 , $row, $row+1);
$table->attach ($combo1, 0, 1 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($entry2, 1, 2 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($entry3, 2, 3 , $row, $row+1,'expand','shrink',2,2);
$table->attach_defaults ($connect_type_lable, 4, 5 , $row, $row+1);
$table->attach_defaults ($entry4, 5, 6 , $row, $row+1);
$table->attach_defaults ($entry5, 6, 7 , $row, $row+1);
$table->attach_defaults ($combentry, 8, 9 , $row, $row+1);
$table->attach ($connect_type_lable, 4, 5 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($entry4, 5, 6 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($entry5, 6, 7 , $row, $row+1,'expand','shrink',2,2);
$table->attach ($combentry, 8, 9 , $row, $row+1,'expand','shrink',2,2);
$combo1->signal_connect("changed"=>sub{
my $new_type=$combo1->get_active_text();
546,7 → 546,7
my $row=port_select($intfc_gen,$info,$table,1);
for (my $i=$row; $i<20; $i++){
my $temp=gen_label_in_center(" ");
$table->attach_defaults ($temp, 0, 1 , $i, $i+1);
#$table->attach_defaults ($temp, 0, 1 , $i, $i+1);
}
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
595,10 → 595,21
print FILE Data::Dumper->Dump([\%$intfc_gen],["HashRef"]);
close(FILE) || die "Error closing file: $!";
#store \%$intfc_gen, "lib/$name.ITC";
my $message="Interface $name has been generated successfully" ;
message_dialog($message);
exec($^X, $0, @ARGV);# reset ProNoC to apply changes
#$hashref = retrieve('file');
my $message="Interface $name has been generated successfully. In order to see this interface in IP generator you need to reset the ProNoC. Do you want to reset the ProNoC now?" ;
my $dialog = Gtk2::MessageDialog->new (my $window,
'destroy-with-parent',
'question', # message type
'yes-no', # which set of buttons?
"$message");
my $response = $dialog->run;
if ($response eq 'yes') {
exec($^X, $0, @ARGV);# reset ProNoC to apply changes
}
$dialog->destroy;
 
}else{
my $message="Category must be defined!";
message_dialog($message);
619,7 → 630,7
my ($intfc_gen,$info)=@_;
my $description = $intfc_gen->intfc_get_description();
my $table = Gtk2::Table->new (15, 15, TRUE);
my $window=def_popwin_size(500,500,"Add description");
my $window=def_popwin_size(50,50,"Add description",'percent');
my ($scrwin,$text_view)=create_text();
#my $buffer = $textbox->get_buffer();
my $ok=def_image_button("icons/select.png",' Ok ');
704,10 → 715,17
my $devbox=dev_box_show($intfc_gen,$info);
$main_table->attach_defaults ($fbox , 0, 12, 0,1);
$main_table->attach_defaults ($sbox , 0, 12, 1,2);
$main_table->attach_defaults ($devbox , 0, 12, 2,12);
$main_table->attach_defaults ($infobox , 0, 12, 12,14);
#$main_table->attach_defaults ($fbox , 0, 12, 0,1);
#$main_table->attach_defaults ($sbox , 0, 12, 1,2);
#$main_table->attach_defaults ($devbox , 0, 12, 2,12);
#$main_table->attach_defaults ($infobox , 0, 12, 12,14);
 
my $v1=def_pack_vbox(TRUE,0,$fbox,$sbox);
my $v2=gen_vpaned($v1,.1,$devbox);
my $v3=gen_vpaned($v2,.6,$infobox);
$main_table->attach_defaults ($v3 , 0, 12, 0,14);
 
 
$main_table->attach ($generate , 6, 8, 14,15,'shrink','shrink',2,2);
 
 
721,17 → 739,19
$devbox->destroy();
$fbox->destroy();
$sbox->destroy();
$v1->destroy();
select(undef, undef, undef, 0.1); #wait 10 ms
$devbox=dev_box_show($intfc_gen,$info);
$fbox=file_box($intfc_gen,$info);
$sbox=module_select($intfc_gen,$info);
$main_table->attach_defaults ($fbox , 0, 12, 0,1);
$main_table->attach_defaults ($sbox , 0, 12, 1,2);
$main_table->attach_defaults ($devbox , 0, 12, 3,12);
$sbox=module_select($intfc_gen,$info);
$v1=def_pack_vbox(TRUE,0,$fbox,$sbox);
$v2->pack1($v1,TRUE, TRUE);
$v2->pack2($devbox,TRUE, TRUE);
$v3-> pack1($v2, TRUE, TRUE);
#$main_table->attach_defaults ($v3 , 0, 12, 0,14);
$v3->show_all();
$devbox->show_all();
$sbox->show_all();
$fbox->show_all();
});
 
 
/lib/perl/ip.pm
436,7 → 436,7
ip_add_port($self,$category,$module,$port,$type,$range,$intfc_name,$intfc_port);
}
my @fileds =("system_h","hdl_files","sw_files","gen_sw_files","sw_params_list","unused","parameters_order","description");
my @fileds =("system_h","hdl_files","sw_files","gen_sw_files","sw_params_list","unused","parameters_order","description","version",'description_pdf');
foreach my $p (@fileds){
my $val=$ipgen->ipgen_get($p);
$self->{categories}{$category}{names}{$module}{$p}=$ipgen->ipgen_get($p) if(defined $val );
448,10 → 448,20
 
 
sub object_add_attribute{
my ($self,$attribute1,$attribute2,$value)=@_;
if(!defined $attribute2){$self->{$attribute1}=$value;}
else {$self->{$attribute1}{$attribute2}=$value;}
 
}
 
sub object_get_attribute{
my ($self,$attribute1,$attribute2)=@_;
if(!defined $attribute2) {return $self->{$attribute1};}
return $self->{$attribute1}{$attribute2};
 
 
}
 
 
 
475,4 → 485,7
 
 
 
 
 
 
1
/lib/perl/ip_gen.pl
72,7 → 72,7
if (!defined $file) {return; }
if (-e $file) {
my $vdb = read_file($file);
my $vdb = read_verilog_file($file);
my @modules=sort $vdb->get_modules($file);
#foreach my $p(@module_list) {print "$p\n"}
$ipgen->ipgen_add("file_name",$file);
438,7 → 438,7
my ($ipgen,$module)=@_;
my $file= $ipgen->ipgen_get("file_name");
$ipgen->ipgen_add("module_name",$module);
my $vdb =read_file($file);
my $vdb =read_verilog_file($file);
my %parameters = $vdb->get_modules_parameters_not_local($module);
my @parameters_order= $vdb->get_modules_parameters_not_local_order($module);
my @ports_order=$vdb->get_module_ports_order($module);
586,12 → 586,12
}
my $module = $ipgen->ipgen_get("module_name");
my($width,$hight)=max_win_size();
my $window = def_popwin_size(.85*$width,.5*$hight,"Define parameters detail");
my $window = def_popwin_size(85,50,"Define parameters detail",'percent');
my @widget_type_list=("Fixed","Entry","Combo-box","Spin-button");
my @param_type_list=("Parameter","Localparam","Don't include");
my $type_info="Define the parameter type:
656,7 → 656,7
my @allowed;
my $row=1;
my $error;
push(@parameters,"#new#");
foreach my $p (@parameters) {
my ($saved_deafult,$saved_widget_type,$saved_content,$saved_info,$vfile_param_type,$redefine_param)= $ipgen->ipgen_get_parameter_detail($p);
725,6 → 725,16
my $check_result=$check_redefine->get_active();
my $redefine_param=($check_result eq 1)? 1:0;
$ipgen->ipgen_add_parameter($p,$deafult,$type,$content,$saved_info,$vfile_param_type,$redefine_param);
if ($type eq "Spin-button"){
my @d=split(",",$content);
if( scalar @d != 3){
$error=$error."wrong content setting for parameter $p\n" ;
print "$error";
}
}
 
 
}
});
$add_remove->signal_connect (clicked => sub{
749,6 → 759,7
} else { #remove the parameter
$ipgen->ipgen_remove_parameter($p);
$ipgen->ipgen_remove_parameters_order($p);
$p = "#new#";
set_gui_status($ipgen,"change_parameter",0);
$ok->clicked;
#$window->destroy();
797,8 → 808,18
});
$ok->signal_connect (clicked => sub{
 
 
 
$window->destroy();
if (defined $error){
message_dialog("$error");
$error=undef;
}else {
$window->destroy();
}
 
});
823,8 → 844,7
my ($ipgen,$info)=@_;
my $table = Gtk2::Table->new (15, 15, TRUE);
my $table2 = Gtk2::Table->new (15, 15, TRUE);
my($width,$hight)=max_win_size();
my $window = def_popwin_size(.7*$width,.7*$hight,"Add definition file");
my $window = def_popwin_size(70,70,"Add definition file",'percent');
my $ok=def_image_button("icons/select.png",' Ok ');
my $scrwin= new Gtk2::ScrolledWindow (undef, undef);
$scrwin->set_policy( "automatic", "automatic" );
852,13 → 872,14
my ($ipgen,$info)=@_;
my $description = $ipgen->ipgen_get("description");
my $table = Gtk2::Table->new (15, 15, FALSE);
my($width,$hight)=max_win_size();
my $window = def_popwin_size(.4*$width,.4*$hight, "Add description");
my $window = def_popwin_size(40,40, "Add description",'percent');
my ($scrwin,$text_view)=create_text();
#my $buffer = $textbox->get_buffer();
my $ok=def_image_button("icons/select.png",' Ok ');
$table->attach_defaults($scrwin,0,15,0,14);
$table->attach_defaults(gen_label_help("User can open the PDF file when oppening IP parameter setting","IP Documentation file in PDF"),0,7,0,1);
$table->attach_defaults(gen_label_help("Description will be shown on IP generator text view when selecting this IP","Short Description"),5,10,1,2);
$table->attach_defaults(get_file_name_object ( $ipgen, 'description_pdf',undef,"pdf",undef),7,15,0,1);
$table->attach_defaults($scrwin,0,15,2,14);
$table->attach($ok,6,9,14,15,'expand','shrink',2,2);
my $text_buffer = $text_view->get_buffer;
if(defined $description) {$text_buffer->set_text($description)};
964,8 → 985,7
sub get_param_info{
my ($ipgen,$saved_info)=@_;
my $table = Gtk2::Table->new (15, 15, FALSE);
my($width,$hight)=max_win_size();
my $window = def_popwin_size(.5*$width,.5*$hight,"Add description");
my $window = def_popwin_size(50,50,"Add description",'percent');
my ($scrwin,$text_view)=create_text();
my $ok=def_image_button("icons/select.png",' Ok ');
1175,9 → 1195,7
sub get_intfc_setting{
my ($ipgen,$intfc_name, $intfc_type)=@_;
my($width,$hight)=max_win_size();
my $window = def_popwin_size(.7*$width,.7*$hight,"Interface parameter setting");
my $window = def_popwin_size(70,70,"Interface parameter setting",'percent');
my $table=def_table(7,6,FALSE);
my $ok = def_image_button('icons/select.png','OK');
1564,10 → 1582,43
}
 
 
sub write_ip{
my $ipgen=shift;
my $name=$ipgen->ipgen_get("module_name");
my $category=$ipgen->ipgen_get("category");
my $ip_name= $ipgen->ipgen_get("ip_name");
my $dir = Cwd::getcwd();
 
#Increase IP version
my $v=$ipgen->object_get_attribute("version",undef);
$v = 0 if(!defined $v);
$v++;
$ipgen->object_add_attribute("version",undef,$v);
#print "$v\n";
 
# Write
mkpath("$dir/lib/ip/$category/",1,01777);
open(FILE, ">lib/ip/$category/$ip_name.IP") || die "Can not open: $!";
print FILE perl_file_header("$ip_name.IP");
print FILE Data::Dumper->Dump([\%$ipgen],[$name]);
close(FILE) || die "Error closing file: $!";
my $message="IP $ip_name has been generated successfully. In order to see the generated IP in processing tile generator you need to reset the ProNoC. Do you want to reset the ProNoC now?" ;
my $dialog = Gtk2::MessageDialog->new (my $window,
'destroy-with-parent',
'question', # message type
'yes-no', # which set of buttons?
"$message");
my $response = $dialog->run;
if ($response eq 'yes') {
exec($^X, $0, @ARGV);# reset ProNoC to apply changes
}
$dialog->destroy;
 
}
 
 
 
sub generate_ip{
my $ipgen=shift;
my $name=$ipgen->ipgen_get("module_name");
1575,10 → 1626,19
my $ip_name= $ipgen->ipgen_get("ip_name");
my $dir = Cwd::getcwd();
 
#check if name has been set
if(defined ($name) && defined ($category)){
if (!defined $ip_name) {$ip_name= $name}
my $error = check_verilog_identifier_syntax($ip_name);
if ( defined $error ){
message_dialog("The IP name \"$ip_name\" is given with an unacceptable formatting. This name will be used as a verilog module name so it must follow Verilog identifier declaration formatting:\n $error");
return ;
}
 
 
 
#check if any source file has been added for this ip
my @l=$ipgen->ipgen_get_list("hdl_files");
if( scalar @l ==0){
1590,15 → 1650,9
"No hdl library file has been set for this IP. Do you want to generate this IP?");
my $response = $dialog->run;
if ($response eq 'yes') {
# Write
mkpath("$dir/lib/ip/$category/",1,01777);
open(FILE, ">lib/ip/$category/$ip_name.IP") || die "Can not open: \">lib/ip/$category/$ip_name.IP\" $!";
print FILE perl_file_header("$ip_name.IP");
print FILE Data::Dumper->Dump([\%$ipgen],[$name]);
close(FILE) || die "Error closing file: $!";
my $message="IP $ip_name has been generated successfully" ;
message_dialog($message);
exec($^X, $0, @ARGV);# reset ProNoC to apply changes
write_ip($ipgen);
}
$dialog->destroy;
 
1606,15 → 1660,8
#$dialog->show_all;
}else{
# Write
mkpath("$dir/lib/ip/$category/",1,01777);
open(FILE, ">lib/ip/$category/$ip_name.IP") || die "Can not open: $!";
print FILE perl_file_header("$ip_name.IP");
print FILE Data::Dumper->Dump([\%$ipgen],[$name]);
close(FILE) || die "Error closing file: $!";
my $message="IP $ip_name has been generated successfully" ;
message_dialog($message);
exec($^X, $0, @ARGV);# reset ProNoC to apply changes
 
write_ip($ipgen);
}
}else{
my $message;
1697,9 → 1744,9
;
my $var_help=gen_button_message($var_list,"icons/info.png","Global variables");
my($width,$hight)=max_win_size();
my $window = def_popwin_size($width*2/3,$hight*2/3,$title);
my $window = def_popwin_size(75,75,$title,'percent');
my $notebook=source_notebook($ipgen,$info,$window,$page,$dest,$page_info_ref);
my $table=def_table (15, 15, FALSE);
1862,7 → 1909,6
#my $hdr = $ipgen->ipgen_get_hdr();
my $hdr = $ipgen-> ipgen_get($page_info{filed_name});
my $table = Gtk2::Table->new (14, 15, FALSE);
#my $window=def_popwin_size(600,600,"Add header file");
my ($scrwin,$text_view)=create_text();
 
my $help=gen_label_help($page_info{help});
1981,7 → 2027,33
# The main table containg the lib tree, selected modules and info section
my $main_table = def_table (15, 12, FALSE);
 
 
 
 
#my $vpaned = Gtk2::VPaned -> new;
#$table->attach_defaults ($vpaned,0, 10, 0,1);
#my $make = def_image_button('icons/run.png','Compile');
#$table->attach ($make,9, 10, 1,2,'shrink','shrink',0,0);
#$make -> signal_connect("clicked" => sub{
#$self->do_save();
#run_make_file($sw,$tview);
 
#});
 
#$window -> add ( $table);
 
#my($width,$hight)=max_win_size();
#my $scwin_dirs = Gtk2::ScrolledWindow -> new;
#$scwin_dirs -> set_policy ('automatic', 'automatic');
 
 
 
 
# The box which holds the info, warning, error ... mesages
my ($infobox,$info)= create_text();
2009,12 → 2081,20
#$table->attach_defaults ($event_box, $col, $col+1, $row, $row+1);
$main_table->attach_defaults ($tree_box , 0, 2, 0, 13);
$main_table->attach_defaults ($file_info , 2, 12, 0, 2);
$main_table->attach_defaults ($intfc_info , 2, 12, 2, 6);
 
my $v1=gen_vpaned($file_info,.2,$intfc_info);
my $v2=gen_vpaned($v1,.4,$port_info);
my $h1=gen_hpaned($tree_box,.15,$v2);
my $v3=gen_vpaned($h1,.6,$infobox);
 
 
#$main_table->attach_defaults ($tree_box , 0, 2, 0, 13);
#$main_table->attach_defaults ($file_info , 2, 12, 0, 2);
#$main_table->attach_defaults ($intfc_info , 2, 12, 2, 6);
$main_table->attach_defaults ($port_info , 2, 12, 6,13);
$main_table->attach_defaults ($infobox , 0, 12, 13,14);
#$main_table->attach_defaults ($port_info , 2, 12, 6,13);
#$main_table->attach_defaults ($infobox , 0, 12, 13,14);
$main_table->attach_defaults ($v3, 0, 12, 0,14);
$main_table->attach ($generate, 6, 8, 14,15,'expand','shrink',2,2);
$main_table->attach ($open,0, 1, 14,15,'expand','shrink',2,2);
 
/lib/perl/mpsoc.pm
90,6 → 90,20
delete $self->{socs}{$name};
}
 
sub mpsoc_remove_soc_top{
my ($self,$name)=@_;
delete $self->{socs}{$name}{top};
}
 
 
sub mpsoc_remove_all_soc_tops{
my $self=shift;
foreach my $name (sort keys %{$self->{socs}}){
delete $self->{socs}{$name}{top};
}
}
 
 
sub mpsoc_remove_all_soc{
my ($self)=@_;
delete $self->{socs};
118,7 → 132,7
@nums = @{$self->{socs}{$name}{tile_nums}};
}
return @ nums;
return @nums;
}
 
sub mpsoc_get_scolar_pos{
239,7 → 253,17
return @{$self->{parameters_order}{$attribute}};
}
 
sub object_remove_attribute{
my ($self,$attribute1,$attribute2)=@_;
if(!defined $attribute2){
delete $self->{$attribute1} if ( exists( $self->{$attribute1}));
}
else {
delete $self->{$attribute1}{$attribute2} if ( exists( $self->{$attribute1}{$attribute2})); ;
 
}
 
}
 
1
 
/lib/perl/mpsoc_gen.pl
285,7 → 285,7
my ($mpsoc,$name,$inserted,$conflicts,$msg)=@_;
$msg="\tThe inserted tile number(s) have been mapped previously to \n\t\t\"$msg\".\n\tDo you want to remove the conflicted tiles number(s) in newly \n\tinsterd range or remove them from the previous ones? ";
my $wind=def_popwin_size(100,300,"warning");
my $wind=def_popwin_size(10,30,"warning",'percent');
my $label= gen_label_in_left($msg);
my $table=def_table(2,6,FALSE);
$table->attach_defaults ($label , 0, 6, 0,1);
419,7 → 419,7
sub get_soc_parameter_setting{
my ($mpsoc,$soc_name,$tile)=@_;
my $window = (defined $tile)? def_popwin_size(600,400,"Parameter setting for $soc_name located in tile($tile) "):def_popwin_size(600,400,"Default Parameter setting for $soc_name ");
my $window = (defined $tile)? def_popwin_size(40,40,"Parameter setting for $soc_name located in tile($tile) ",'percent'):def_popwin_size(40,40,"Default Parameter setting for $soc_name ",'percent');
my $table = def_table(10, 7, TRUE);
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
1101,9 → 1101,9
sub get_config{
my ($mpsoc,$info)=@_;
my $table=def_table(20,10,FALSE);# my ($row,$col,$homogeneous)=@_;
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$scrolled_win->add_with_viewport($table);
#my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
#$scrolled_win->set_policy( "automatic", "automatic" );
#$scrolled_win->add_with_viewport($table);
 
#noc_setting
my $row=noc_config ($mpsoc,$table);
1159,7 → 1159,7
 
 
 
return $scrolled_win;
return $table;
 
}
 
1237,7 → 1237,17
my ($mpsoc,$soc,$info)=@_;
my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
my $soc_name=$soc->object_get_attribute('soc_name');
my ($file_v,$tmp)=soc_generate_verilog($soc);
# copy all files in project work directory
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../");
#make target dir
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
mkpath("$target_dir/src_verilog/lib/",1,0755);
mkpath("$target_dir/src_verilog/tiles/",1,0755);
mkpath("$target_dir/sw",1,0755);
 
my ($file_v,$tmp)=soc_generate_verilog($soc,"$target_dir/sw");
# Write object file
open(FILE, ">lib/soc/$soc_name.SOC") || die "Can not open: $!";
1253,14 → 1263,7
# copy all files in project work directory
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../");
#make target dir
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
mkpath("$target_dir/src_verilog/lib/",1,0755);
mkpath("$target_dir/src_verilog/tiles/",1,0755);
mkpath("$target_dir/sw",1,0755);
#copy hdl codes in src_verilog
1316,6 → 1319,19
}
 
 
sub generate_mpsoc_lib_file {
my ($mpsoc,$info) = @_;
my $name=$mpsoc->object_get_attribute('mpsoc_name');
$mpsoc->mpsoc_remove_all_soc_tops();
open(FILE, ">lib/mpsoc/$name.MPSOC") || die "Can not open: $!";
print FILE perl_file_header("$name.MPSOC");
print FILE Data::Dumper->Dump([\%$mpsoc],[$name]);
close(FILE) || die "Error closing file: $!";
get_soc_list($mpsoc,$info);
}
 
 
################
# generate_mpsoc
#################
1323,8 → 1339,9
sub generate_mpsoc{
my ($mpsoc,$info)=@_;
my $name=$mpsoc->object_get_attribute('mpsoc_name');
if ( $name =~ /\W+/ ){
message_dialog('The mpsoc name must not contain any non-word character:("./\()\':,.;<>~!@#$%^&*|+=[]{}`~?-")!")');
my $error = check_verilog_identifier_syntax($name);
if ( defined $error ){
message_dialog("The \"$name\" is given with an unacceptable formatting. The mpsoc name will be used as top level verilog module name so it must follow Verilog identifier declaration formatting:\n $error");
return 0;
}
my $size= (defined $name)? length($name) :0;
1354,15 → 1371,12
my ($file_v,$top_v)=mpsoc_generate_verilog($mpsoc);
my ($file_v,$top_v)=mpsoc_generate_verilog($mpsoc,$sw_dir);
# Write object file
open(FILE, ">lib/mpsoc/$name.MPSOC") || die "Can not open: $!";
print FILE perl_file_header("$name.MPSOC");
print FILE Data::Dumper->Dump([\%$mpsoc],[$name]);
close(FILE) || die "Error closing file: $!";
generate_mpsoc_lib_file($mpsoc,$info);
# Write verilog file
open(FILE, ">lib/verilog/$name.v") || die "Can not open: $!";
1581,7 → 1595,7
}
$button->signal_connect("clicked" => sub{
my $window = def_popwin_size(400,400,"Parameter setting for Tile $tile ");
my $window = def_popwin_size(40,40,"Parameter setting for Tile $tile ",'percent');
my $table = def_table(6, 2, TRUE);
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
1717,14 → 1731,40
 
 
 
sub software_edit_mpsoc {
my $self=shift;
my $name=$self->object_get_attribute('mpsoc_name');
if (length($name)==0){
message_dialog("Please define the MPSoC name!");
return ;
}
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name/sw";
my $sw = "$target_dir";
my ($app,$table,$tview) = software_main($sw);
 
 
 
my $make = def_image_button('icons/gen.png','Compile');
$table->attach ($make,9, 10, 1,2,'shrink','shrink',0,0);
 
$make -> signal_connect("clicked" => sub{
$app->do_save();
run_make_file($sw,$tview);
 
});
 
}
 
 
 
 
 
 
 
############
# main
############
1753,8 → 1793,10
my $noc_conf_box=get_config ($mpsoc,$info);
my $noc_tiles=gen_tiles($mpsoc);
 
my $scr_conf = new Gtk2::ScrolledWindow (undef, undef);
$scr_conf->set_policy( "automatic", "automatic" );
$scr_conf->add_with_viewport($noc_conf_box);
 
 
$main_table->set_row_spacings (4);
$main_table->set_col_spacings (1);
1767,8 → 1809,8
my $open = def_image_button('icons/browse.png','Load MPSoC');
my $compile = def_image_button('icons/run.png','Compile');
my $software = def_image_button('icons/binary.png','Software');
my $entry=gen_entry_object($mpsoc,'mpsoc_name',undef,undef,undef,undef);
my $entrybox=labele_widget_info(" MPSoC name:",$entry);
1775,27 → 1817,45
#$table->attach_defaults ($event_box, $col, $col+1, $row, $row+1);
$main_table->attach_defaults ($noc_conf_box , 0, 4, 0, 22);
$main_table->attach_defaults ($noc_tiles , 4, 12, 0, 22);
$main_table->attach_defaults ($infobox , 0, 12, 22,24);
#$main_table->attach_defaults ($noc_conf_box , 0, 4, 0, 22);
#$main_table->attach_defaults ($noc_tiles , 4, 12, 0, 22);
#$main_table->attach_defaults ($infobox , 0, 12, 22,24);
 
my $h1=gen_hpaned($scr_conf,.3,$noc_tiles);
my $v2=gen_vpaned($h1,.55,$infobox);
$main_table->attach_defaults ($v2 , 0, 12, 0,24);
 
 
 
 
 
$main_table->attach ($open,0, 3, 24,25,'expand','shrink',2,2);
$main_table->attach_defaults ($entrybox,3, 7, 24,25);
$main_table->attach ($generate, 10, 12, 24,25,'expand','shrink',2,2);
$main_table->attach ($generate, 8, 9, 24,25,'expand','shrink',2,2);
$main_table->attach ($software, 9, 10, 24,25,'expand','shrink',2,2);
$main_table->attach ($compile, 10, 12, 24,25,'expand','shrink',2,2);
 
#referesh the mpsoc generator
$refresh-> signal_connect("clicked" => sub{
$noc_conf_box->destroy();
$noc_conf_box=get_config ($mpsoc,$info);
$main_table->attach_defaults ($noc_conf_box , 0, 4, 0, 22);
$noc_conf_box->show_all();
$scr_conf->add_with_viewport($noc_conf_box);
#$main_table->attach_defaults ($noc_conf_box , 0, 4, 0, 22);
#$noc_conf_box->show_all();
 
 
$noc_tiles->destroy();
$noc_tiles=gen_tiles($mpsoc);
$main_table->attach_defaults ($noc_tiles , 4, 12, 0, 22);
#$h1->destroy();
#$h1=gen_hpaned($noc_conf_box,.3,$noc_tiles);
$h1 -> pack1($scr_conf, TRUE, TRUE);
$h1 -> pack2($noc_tiles, TRUE, TRUE);
$v2-> pack1($h1, TRUE, TRUE);
$h1->show_all;
#$main_table->attach_defaults ($noc_tiles , 4, 12, 0, 22);
 
$main_table->show_all();
 
1812,6 → 1872,14
if ($timeout>0){
$timeout--;
set_gui_status($mpsoc,$state,$timeout);
}elsif ($state eq 'save_project'){
# Write object file
my $name=$mpsoc->object_get_attribute('mpsoc_name');
open(FILE, ">lib/mpsoc/$name.MPSOC") || die "Can not open: $!";
print FILE perl_file_header("$name.MPSOC");
print FILE Data::Dumper->Dump([\%$mpsoc],[$name]);
close(FILE) || die "Error closing file: $!";
set_gui_status($mpsoc,"ideal",0);
}
elsif( $state ne "ideal" ){
$refresh->clicked;
1841,8 → 1909,30
set_gui_status($mpsoc,"ref",5);
load_mpsoc($mpsoc,$info);
});
 
 
$compile -> signal_connect("clicked" => sub{
my $name=$mpsoc->object_get_attribute('mpsoc_name');
if (length($name)==0){
message_dialog("Please define the MPSoC name!");
return ;
}
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
my $top_file = "$target_dir/src_verilog/${name}_top.v";
if (-f $top_file){
select_compiler($mpsoc,$name,$top_file,$target_dir);
} else {
message_dialog("Cannot find $top_file file. Please run RTL Generator first!");
return;
}
});
$software -> signal_connect("clicked" => sub{
software_edit_mpsoc($mpsoc);
 
});
 
my $sc_win = new Gtk2::ScrolledWindow (undef, undef);
$sc_win->set_policy( "automatic", "automatic" );
1882,8 → 1972,8
$dialog->add_filter ($filter);
my $dir = Cwd::getcwd();
$dialog->set_current_folder ("$dir/lib/mpsoc") ;
 
 
my @newsocs=$mpsoc->mpsoc_get_soc_list();
add_info(\$info,'');
if ( "ok" eq $dialog->run ) {
$file = $dialog->get_filename;
my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
1890,13 → 1980,33
if($suffix eq '.MPSOC'){
my $pp= eval { do $file };
if ($@ || !defined $pp){
show_info(\$info,"**Error reading $file file: $@\n");
add_info(\$info,"**Error: cannot open $file file: $@\n");
$dialog->destroy;
return;
}
 
clone_obj($mpsoc,$pp);
#read save mpsoc socs
my @oldsocs=$mpsoc->mpsoc_get_soc_list();
#add exsiting SoCs and add them to mpsoc
my $error;
#print "old: @oldsocs\n new @newsocs \n";
foreach my $p (@oldsocs) {
#print "$p\n";
my @num= $mpsoc->mpsoc_get_soc_tiles_num($p);
if (scalar @num && ( grep (/^$p$/,@newsocs)==0)){
my $m="Processing tile $p that has been used for ties @num but is not located in librray anymore\n";
$error = (defined $error ) ? "$error $m" : $m;
}
$mpsoc->mpsoc_remove_soc ($p) if (grep (/^$p$/,@newsocs)==0);
 
clone_obj($mpsoc,$pp);
}
@newsocs=get_soc_list($mpsoc,$info); # add all existing socs
add_info(\$info,"**Error: \n $error\n") if(defined $error);
 
set_gui_status($mpsoc,"load_file",0);
}
/lib/perl/mpsoc_verilog_gen.pl
12,9 → 12,17
 
 
sub mpsoc_generate_verilog{
my $mpsoc=shift;
my ($mpsoc,$sw_dir)=@_;
my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
my $top_ip=ip_gen->top_gen_new();
my $io_v="\tclk,\n\treset";
 
#$top_ip->top_add_port($inst,$port,$range,$type,$intfc_name,$intfc_port);
$top_ip->top_add_port('IO','reset','', 'input' ,'plug:reset[0]','reset_i');
$top_ip->top_add_port('IO','clk','', 'input' ,'plug:clk[0]','clk_i');
my $io_def_v="
//IO
\tinput\tclk,reset;\n";
33,15 → 41,16
my $noc_v=gen_noc_v($pass_param);
#generate socs
my $socs_v=gen_socs_v($mpsoc,\$io_v,\$io_def_v,\$top_io);
my $socs_v=gen_socs_v($mpsoc,\$io_v,\$io_def_v,\$top_io,$top_ip,$sw_dir);
#functions
my $functions=get_functions();
my $mpsoc_v = (defined $param_as_in_v )? "module $mpsoc_name #(\n $param_as_in_v\n)(\n$io_v\n);\n": "module $mpsoc_name (\n$io_v\n);\n";
add_text_to_string (\$mpsoc_v,$noc_param);
add_text_to_string (\$mpsoc_v,$functions);
add_text_to_string (\$mpsoc_v,$socs_param);
add_text_to_string (\$mpsoc_v,$noc_param);
add_text_to_string (\$mpsoc_v,$io_def_v);
add_text_to_string (\$mpsoc_v,$noc_v);
add_text_to_string (\$mpsoc_v,$socs_v);
80,6 → 89,7
 
#add_text_to_string(\$top_v,$local_param_v_all."\n".$io_full_v_all);
#add_text_to_string(\$top_v,$ins);
$mpsoc->object_add_attribute('top_ip',undef,$top_ip);
return ($mpsoc_v,$top_v);
}
 
262,7 → 272,7
sub gen_noc_v{
my $pass_param = shift;
my $noc = read_file("../src_noc/noc.v");
my $noc = read_verilog_file("../src_noc/noc.v");
my @noc_param=$noc->get_modules_parameters_not_local_order('noc');
380,7 → 390,7
 
 
sub gen_socs_v{
my ($mpsoc,$io_v_ref,$io_def_v,$top_io_ref)=@_;
my ($mpsoc,$io_v_ref,$io_def_v,$top_io_ref,$top_ip,$sw_dir)=@_;
#generate loop
427,7 → 437,7
my $socs_v;
my $nx= $mpsoc->object_get_attribute('noc_param',"NX");
my $ny= $mpsoc->object_get_attribute('noc_param',"NY");
my $processors_en=0;
440,7 → 450,7
my ($soc_v,$en)= gen_soc_v($mpsoc,$soc_name,$tile_num,$x,$y,$soc_num,$io_v_ref,$io_def_v,$top_io_ref);
my ($soc_v,$en)= gen_soc_v($mpsoc,$soc_name,$tile_num,$x,$y,$soc_num,$io_v_ref,$io_def_v,$top_io_ref,$top_ip,$sw_dir);
add_text_to_string(\$socs_v,$soc_v);
$processors_en|=$en;
463,6 → 473,7
add_text_to_string($io_v_ref,",\n\tprocessors_en");
add_text_to_string($io_def_v,"\t input processors_en;");
add_text_to_string($top_io_ref,",\n\t\t.processors_en(processors_en_anded_jtag)");
$top_ip->top_add_port('IO','processors_en','' ,'input','plug:enable[0]','enable_i');
}
478,7 → 489,7
 
 
sub gen_soc_v{
my ($mpsoc,$soc_name,$tile_num,$x,$y,$soc_num,$io_v_ref,$io_def_v,$top_io_ref)=@_;
my ($mpsoc,$soc_name,$tile_num,$x,$y,$soc_num,$io_v_ref,$io_def_v,$top_io_ref,$top_ip,$sw_path)=@_;
my $soc_v;
my $processor_en=0;
my $xw= log2($mpsoc->object_get_attribute('noc_param',"NX"));
485,8 → 496,8
my $yw= log2($mpsoc->object_get_attribute('noc_param',"NY"));
$soc_v="\n\n // Tile:$tile_num (x=$x,y=$y)\n \t$soc_name #(\n";
# core id
add_text_to_string(\$soc_v,"\t\t.CORE_ID($tile_num)");
# Global parameter
add_text_to_string(\$soc_v,"\t\t.CORE_ID($tile_num),\n\t\t.SW_LOC(\"$sw_path/tile$tile_num\")");
# ni parameter
my $top=$mpsoc->mpsoc_get_soc($soc_name);
521,7 → 532,7
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
my $soc_file="$target_dir/src_verilog/tiles/$soc_name.v";
my $vdb =read_file($soc_file);
my $vdb =read_verilog_file($soc_file);
my %soc_localparam = $vdb->get_modules_parameters($soc_name);
607,8 → 618,8
my $new_range = add_instantc_name_to_parameters(\%params,"${soc_name}_$soc_num",$range);
#my $new_range=$range;
my $port_def=(length ($range)>1 )? "\t$type\t [ $new_range ] $io_port;\n": "\t$type\t\t\t$io_port;\n";
$top_ip->top_add_port("${soc_name}_$tile_num" ,$io_port, $new_range ,$type,$intfc_name,$intfc_port);
add_text_to_string($io_def_v,"$port_def");
add_text_to_string(\$soc_v,',') if ($i);
add_text_to_string(\$soc_v,"\n\t\t.$p($io_port)");
/lib/perl/readme_gen.pl
1,15 → 1,16
#! /usr/bin/perl -w
 
use Time::Piece;
 
 
sub get_license_header {
my $file_name=shift;
 
my $t = Time::Piece->new();
my $year=$t->year;
my $head="
/**********************************************************************
** File: $file_name
**
** Copyright (C) 2014-2016 Alireza Monemi
** Copyright (C) 2014-$year Alireza Monemi
**
** This file is part of ProNoC $ProNOC::VERSION
**
16,7 → 17,7
** ProNoC ( stands for Prototype Network-on-chip) is free software:
** you can redistribute it and/or modify it under the terms of the GNU
** Lesser General Public License as published by the Free Software Foundation,
** either version 3 of the License, or (at your option) any later version.
** either version 2 of the License, or (at your option) any later version.
**
** ProNoC is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24,7 → 25,7
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
******************************************************************************/
";
 
/lib/perl/simulator.pl
54,7 → 54,7
#verilate the noc
my $start = localtime;
add_info($info_text, "verilate the NoC and make the library files");
my $command = "cd \"$script_dir/\" \n xterm -l -lf logfile1.txt -e sh verilator_compile_hw.sh";
my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout( $command);
92,7 → 92,7
add_info($info_text, "Verilator compilation failed !\n$command\n $stdout\n");
return;
}
my $end = localtime;
 
101,17 → 101,19
my $path=$simulate->object_get_attribute ('sim_param',"BIN_DIR");
my $name=$simulate->object_get_attribute ('sim_param',"SAVE_NAME");
#create project didrectory if its not exist
#create project directory if its not exist
($stdout,$exit)=run_cmd_in_back_ground_get_stdout("mkdir -p $path" );
if($exit != 0 ){ print "$stdout\n"; message_dialog($stdout); return;}
if($exit != 0 ){ print "$stdout\n"; message_dialog($stdout,'error'); return;}
#move the log file
move("$script_dir/logfile1.txt" , "$path/$name.log1");
move("$script_dir/logfile2.txt" , "$path/$name.log2");
unlink "$path/$name.log";
append_text_to_file("$path/$name.log","start:$start\n");
merg_files("$script_dir/logfile1.txt" , "$path/$name.log");
merg_files("$script_dir/logfile2.txt" , "$path/$name.log");
append_text_to_file("$path/$name.log","end:$end\n");
#check if the verilation was successful
if ((-e $bin)==0) {#something goes wrong
message_dialog("Verilator compilation was unsuccessful please check the $path/$name.log files for more information");
message_dialog("Verilator compilation was unsuccessful please check the $path/$name.log files for more information",'error');
return;
}
118,7 → 120,7
#copy ($bin,"$path/$name") or die "Can not copy: $!";
($stdout,$exit)=run_cmd_in_back_ground_get_stdout("cp -f $bin $path/$name");
if($exit != 0 ){ print "$stdout\n"; message_dialog($stdout); return;}
if($exit != 0 ){ print "$stdout\n"; message_dialog($stdout,'error'); return;}
#save noc info
open(FILE, ">$path/$name.inf") || die "Can not open: $!";
147,7 → 149,7
 
 
##########
# save_emulation
# save_simulation
##########
sub save_simulation {
my ($simulate)=@_;
/lib/perl/soc.pm
64,6 → 64,9
}
}
}
 
 
$self->{instances}{$instance_id}{description_pdf}=$ip->ip_get($category,$module,'description_pdf');
return 1;
}
150,6 → 153,11
}
 
 
sub soc_get_description_pdf{
my ($self,$instance_id)=@_;
return $self->{instances}{$instance_id}{description_pdf};
}
 
sub soc_get_plug_name {
my ($self,$instance_id,$plug,$num)=@_;
my $name;
278,9 → 286,23
}
return @list;
}
}
 
sub soc_get_all_sockets_of_an_instance{
my ($self,$instance_id)=@_;
my @list;
if(exists ($self->{instances}{$instance_id}{sockets})){
foreach my $p (sort keys %{$self->{instances}{$instance_id}{sockets}}){
push (@list,$p);
}
}
return @list;
}
 
 
##############################################
sub soc_get_modules_plug_connected_to_socket{
my ($self,$id,$socket,$socket_num)=@_;
536,7 → 558,19
}
}
return @list;
}
 
sub soc_list_socket_nums{
my ($self,$instance_id,$socket)=@_;
my @list;
if(exists($self->{instances}{$instance_id}{sockets}{$socket})){
foreach my $num (sort keys %{$self->{instances}{$instance_id}{sockets}{$socket}{nums}}){
push (@list,$num);
}
}
return @list;
}
 
 
sub soc_get_plug{
668,13 → 702,88
}
 
 
sub object_remove_attribute{
my ($self,$attribute1,$attribute2)=@_;
if(!defined $attribute2){
delete $self->{$attribute1} if ( exists( $self->{$attribute1}));
}
else {
delete $self->{$attribute1}{$attribute2} if ( exists( $self->{$attribute1}{$attribute2})); ;
 
}
 
}
 
 
sub board_new {
# be backwards compatible with non-OO call
my $class = ("ARRAY" eq ref $_[0]) ? "soc" : shift;
my $self;
$self->{'Input'}{'*VCC'}{'*VCC'} = ['*undefine*'];
$self->{'Input'}{'*GND'}{'*GND'} = ['*undefine*'];
$self->{'Input'}{'*NOCONNECT'}{'*NOCONNECT'} = ['*undefine*'];
$self->{'Output'}{'*NOCONNECT'}{'*NOCONNECT'} = ['*undefine*'];
$self->{'Bidir'}{'*NOCONNECT'}{'*NOCONNECT'} = ['*undefine*'];
bless($self,$class);
return $self;
}
 
 
 
sub board_add_pin {
my ($self,$direction,$name)=@_;
my ($intfc,$pin_name,$pin_num);
my @f= split('_',$name);
if(!defined $f[1]){ # There is no '_' in pin name
my @p= split(/\[/,$name);
$intfc=$p[0];
$pin_name=$p[0];
if(defined $p[1]){ #it is an array
my @q= split(/\]/,$p[1]);
$pin_num=$q[0]; #save pin num
}else{
$pin_num='*undefine*';
}
}
else{ # take the word before '_' as interface
$intfc=$f[0];
my @p= split(/\[/,$name);
$pin_name=$p[0];
if(defined $p[1]){
my @q= split(/\]/,$p[1]);
$pin_num=$q[0];
}else{
$pin_num='*undefine*';
}
}
my @a;
@a= @{$self->{$direction}{$intfc}{$pin_name}} if(exists $self->{$direction}{$intfc}{$pin_name});
push (@a,$pin_num);
@{$self->{$direction}{$intfc}{$pin_name}}=@a;
 
}
 
sub board_get_pin {
my ($self,$direction)=@_;
my %p=%{$self->{$direction}};
return %p;
 
}
 
sub board_get_pin_range {
my ($self,$direction,$pin_name)=@_;
my @f= split('_',$pin_name);
my $intfc = $f[0];
my $ref =$self->{$direction}{$intfc}{$pin_name};
my @range;
@range= @{$ref} if(defined $ref);
return @range;
}
 
 
1
/lib/perl/soc_gen.pl
19,6 → 19,7
 
 
 
 
# clean names for column numbers.
use constant DISPLAY_COLUMN => 0;
use constant CATRGORY_COLUMN => 1;
31,9 → 32,10
require "verilog_gen.pl";
require "readme_gen.pl";
require "hdr_file_gen.pl";
require "diagram.pl";
require "compile.pl";
require "software_editor.pl";
 
 
 
 
sub is_hex {
77,7 → 79,11
return;
}
$soc->soc_add_instance_order($instance_id);
# Add IP version
my $v=$ip->ip_get($category,$module,"version");
$v = 0 if(!defined $v);
#print "$v\n";
$soc->object_add_attribute($instance_id,"version",$v);
# Read default parameter from lib and add them to soc
my %param_default= $ip->get_param_default($category,$module);
125,8 → 131,7
my %new_param_value=%param_value;
#gui
my $table_size = ($param_num<10) ? 10 : $param_num;
my($width,$hight)=max_win_size();
my $window = def_popwin_size(.6*$width,.6*$hight, "Parameter setting for $module ");
my $window = def_popwin_size(60,60, "Parameter setting for $module ",'percent');
my $table = def_table($table_size, 7, FALSE);
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
136,19 → 141,30
my $ok = def_image_button('icons/select.png','OK');
my $at0= 'expand';
my $at1= 'shrink';
$table->attach (gen_label_in_center("Parameter name"),0, 3, $row, $row+1,'expand','shrink',2,2);
$table->attach (gen_label_in_center("Value"),3, 6, $row, $row+1,'expand','shrink',2,2);
$table->attach (gen_label_in_center("Description"),6, 7, $row, $row+1,'expand','shrink',2,2);
$table->attach (gen_label_in_left("Parameter name"),0, 3, $row, $row+1,$at0,$at1,2,2);
$table->attach (gen_label_in_left("Value"),3, 6, $row, $row+1,$at0,$at1,2,2);
$table->attach (gen_label_in_left("Description"),6, 7, $row, $row+1,$at0,$at1,2,2);
$row++;
foreach my $p (@parameters){
my ($default,$type,$content,$info)= $ip->ip_get_parameter($category,$module,$p);
my $value=$param_value{$p};
if ($type eq "File_Entry"){
my $entry=gen_entry($value);
my $brows=get_file_name(undef,undef,$entry,undef,undef,undef,undef,undef);
my $box=def_hbox(TRUE,0);
$box->pack_start($entry,FALSE,FALSE,3);
$box->pack_start($brows,FALSE,FALSE,3);
$table->attach ($box, 3, 6, $row, $row+1,$at0,$at1,2,2);
$entry-> signal_connect("changed" => sub{$new_param_value{$p}=$entry->get_text();});
}
if ($type eq "Entry"){
elsif ($type eq "Entry"){
my $entry=gen_entry($value);
$table->attach ($entry, 3, 6, $row, $row+1,'expand','shrink',2,2);
$table->attach ($entry, 3, 6, $row, $row+1,$at0,$at1,2,2);
$entry-> signal_connect("changed" => sub{$new_param_value{$p}=$entry->get_text();});
}
elsif ($type eq "Combo-box"){
155,7 → 171,7
my @combo_list=split(",",$content);
my $pos=get_item_pos($value, @combo_list);
my $combo=gen_combo(\@combo_list, $pos);
$table->attach ($combo, 3, 6, $row, $row+1,'expand','shrink',2,2);
$table->attach ($combo, 3, 6, $row, $row+1,$at0,$at1,2,2);
$combo-> signal_connect("changed" => sub{$new_param_value{$p}=$combo->get_active_text();});
}
168,7 → 184,7
my $spin=gen_spin($min,$max,$step);
if(defined $value) {$spin->set_value($value);}
else {$spin->set_value($min);}
$table->attach ($spin, 3, 4, $row, $row+1,'expand','shrink',2,2);
$table->attach ($spin, 3, 4, $row, $row+1,$at0,$at1,2,2);
$spin-> signal_connect("value_changed" => sub{ $new_param_value{$p}=$spin->get_value_as_int(); });
# $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
175,7 → 191,7
}
if (defined $info && $type ne "Fixed"){
my $info_button=def_image_button('icons/help.png');
$table->attach ($info_button, 6, 7, $row, $row+1,'expand','shrink',2,2);
$table->attach ($info_button, 6, 7, $row, $row+1,$at0,$at1,2,2);
$info_button->signal_connect('clicked'=>sub{
message_dialog($info);
184,8 → 200,8
}
if ($type ne "Fixed"){
#print "$p:val:$value\n";
my $label =gen_label_in_center($p);
$table->attach ($label, 0, 3, $row, $row+1,'expand','shrink',2,2);
my $label =gen_label_in_left($p);
$table->attach ($label, 0, 3, $row, $row+1,$at0,$at1,2,2);
$row++;
}
193,14 → 209,16
}
#if ($row== 0){
#my $label =gen_label_in_left("The $module IP does not have any adjatable parameter");
# $table->attach ($label, 0, 7, $row, $row+1,'expand','shrink',2,2);
# $table->attach ($label, 0, 7, $row, $row+1,$at0,'shrink',2,2);
 
#}
my $mtable = def_table(10, 1, FALSE);
 
$mtable->attach_defaults($scrolled_win,0,1,0,9);
$mtable->attach($ok,0,1,9,10,'expand','shrink',2,2);
$mtable->attach($ok,0,1,9,10,'expand','fill',2,2);
$window->add ($mtable);
$window->show_all();
340,8 → 358,31
my $module=$soc->soc_get_module($instance_id);
my $category=$soc->soc_get_category($instance_id);
my $module_name_label=box_label(FALSE,0,$module);
$table->attach_defaults ($module_name_label,0,1,$offset+0,$offset+1);
my $box0=def_hbox(FALSE,5);
$box0->pack_start( $module_name_label, FALSE, FALSE, 3);
 
#module pdf
my $pdf=$soc->soc_get_description_pdf($instance_id);
if(defined $pdf){
my $b=def_image_button('icons/evince-icon.png');
$box0->pack_start( $b, FALSE, FALSE, 3);
$b->signal_connect ("clicked" => sub{
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../"); #mpsoc directory address
#print "path ${project_dir}$pdf\n";
if (-f "${project_dir}$pdf"){
system qq (xdg-open ${project_dir}$pdf);
}elsif (-f "$pdf"){
system qq (xdg-open $pdf);
}else{
message_dialog("Error! $pdf or ${project_dir}$pdf did not find!\n");
}
 
});
 
}
$table->attach ($box0,0,1,$offset+0,$offset+1,'expand','shrink',2,2);
 
#parameter setting button
my $param_button = def_image_button('icons/setting.png','Setting');
my $box1=def_hbox(FALSE,5);
348,7 → 389,7
my $up=def_image_button("icons/up_sim.png");
$box1->pack_start( $up, FALSE, FALSE, 3);
$box1->pack_start($param_button, FALSE, FALSE,3);
$table->attach_defaults ($box1 ,0,1,$offset+1,$offset+2);
$table->attach ($box1 ,0,1,$offset+1,$offset+2,'expand','shrink',2,2);
$param_button->signal_connect (clicked => sub{
get_module_parameter($soc,$ip,$instance_id);
367,7 → 408,7
my $dwn=def_image_button("icons/down_sim.png");
$box2->pack_start( $dwn, FALSE, FALSE, 3);
$box2->pack_start($cancel_button, FALSE, FALSE,3);
$table->attach_defaults ($box2,0,1,$offset+2,$offset+3);
$table->attach ($box2,0,1,$offset+2,$offset+3,'expand','shrink',2,2);
$cancel_button->signal_connect (clicked => sub{
remove_instance_from_soc($soc,$instance_id);
377,37 → 418,86
set_gui_status($soc,"refresh_soc",0);
});
 
#instance name
my $instance_name=$soc->soc_get_instance_name($instance_id);
my $instance_label=gen_label_in_left("Instance name");
my $instance_label=gen_label_in_left(" Instance name");
my $instance_entry = gen_entry($instance_name);
$table->attach_defaults ($instance_label,1,2,$offset+0,$offset+1);
$table->attach_defaults ($instance_entry,1,2,$offset+1,$offset+2);
$table->attach ($instance_label,1,2,$offset+0,$offset+1,'expand','shrink',2,2);
#$table->attach_defaults ($instance_entry,1,2,$offset+1,$offset+2);
 
 
my $enter= def_image_button("icons/enter.png");
$instance_entry->signal_connect (changed => sub{
my $box=def_pack_hbox(FALSE,0,$instance_entry );
$table->attach ($box,1,2,$offset+1,$offset+2,'expand','shrink',2,2);
 
my ($old_v,$new_v)= get_old_new_ip_version ($soc,$ip,$instance_id);
if($old_v != $new_v){
my $warn=def_image_button("icons/warnning.png");
$table->attach ($warn,1,2,$offset+2,$offset+3,'expand','shrink',2,2); #$box2->pack_start($warn, FALSE, FALSE, 3);
$warn->signal_connect (clicked => sub{
message_dialog("Warning: ${module}'s version (V.$old_v) missmatches with the one exsiting in librray (V.$new_v). The generated system may not work correctly. Please remove and then add $module again to update it with current version")
});
 
 
}
 
$instance_entry->signal_connect ("activate" => sub{
#print "changed\n";
$instance_name=$instance_entry->get_text();
my $new_name=$instance_entry->get_text();
#check if instance name exist in soc
set_gui_status($soc,"refresh_soc",1) if($instance_name eq $new_name );
my @instance_names= $soc->soc_get_all_instance_name();
if( grep {$_ eq $instance_name} @instance_names){
print "$instance_name exist\n";
if( grep {$_ eq $new_name} @instance_names){
print "$new_name exist\n";
}
else {
#add instance name to soc
$soc->soc_set_instance_name($instance_id,$instance_name);
$soc->soc_set_instance_name($instance_id,$new_name);
set_gui_status($soc,"refresh_soc",25);
set_gui_status($soc,"refresh_soc",1);
}
});
my $change=0;
$instance_entry->signal_connect ("changed" => sub{
if($change ==0){
$box->pack_start( $enter, FALSE, FALSE, 0);
$box->show_all;
$change=1;
}
 
});
$enter->signal_connect ("clicked" => sub{
my $new_name=$instance_entry->get_text();
#check if instance name exist in soc
set_gui_status($soc,"refresh_soc",1) if($instance_name eq $new_name );
my @instance_names= $soc->soc_get_all_instance_name();
if( grep {$_ eq $new_name} @instance_names){
print "$new_name exist\n";
}
else {
#add instance name to soc
$soc->soc_set_instance_name($instance_id,$new_name);
set_gui_status($soc,"refresh_soc",1);
}
 
 
});
 
 
#interface_pluges
my %plugs = $ip->get_module_plugs_value($category,$module);
484,11 → 574,11
#plug name
my $plug_name= $soc->soc_get_plug_name($instance_id,$plug,$k);
if(! defined $plug_name ){$plug_name=($plug_num>1)?"$plug\[$k\]":$plug}
$plug_name=" $plug_name";
$plug_name=" $plug_name ";
my($plug_box, $plug_combo)= def_h_labeled_combo_scaled($plug_name,\@connettions_name,$pos,1,2);
#if($row>2){$table->resize ($row, 2);}
$table->attach_defaults ($plug_box,2,5,$row+$offset,$row+$offset+1);$row=$row+1;
$table->attach ($plug_box,2,5,$row+$offset,$row+$offset+1,'fill','fill',2,2); $row++;
my $plug_num=$k;
my @ll=($soc,$instance_id,$plug,$info,$plug_num);
577,7 → 667,7
my $separator = Gtk2::HSeparator->new;
#$box->pack_start($separator, FALSE, FALSE, 3);
if($row<3) {$row=3;}
$table->attach_defaults ($separator,0,5,$row+$offset,$row+$offset+1);$row=$row+1;
$table->attach ($separator,0,5,$row+$offset,$row+$offset+1,'fill','fill',2,2); $row++;
return ($offset+$row);
}
 
619,8 → 709,8
}
if($row<20){for ($i=$row; $i<20; $i++){
my $temp=gen_label_in_center(" ");
$table->attach_defaults ($temp, 0, 1 , $i, $i+1);
#my $temp=gen_label_in_center(" ");
#$table->attach_defaults ($temp, 0, 1 , $i, $i+1);
}}
858,7 → 948,7
my $name=$soc->object_get_attribute('soc_name');
my ($file_v,$top_v,$readme,$prog)=soc_generate_verilog($soc);
my ($file_v,$top_v,$readme,$prog)=soc_generate_verilog($soc,$sw_path);
# Write object file
open(FILE, ">lib/soc/$name.SOC") || die "Can not open: $!";
867,13 → 957,14
close(FILE) || die "Error closing file: $!";
# Write verilog file
my $h=autogen_warning().get_license_header("${name}.v")."\n`timescale 1ns / 1ps\n";
open(FILE, ">lib/verilog/$name.v") || die "Can not open: $!";
print FILE $file_v;
print FILE $h.$file_v;
close(FILE) || die "Error closing file: $!";
# Write Top module file
if($gen_top){
my $l=autogen_warning().get_license_header("${name}_top.v");
my $l=autogen_warning().get_license_header("${name}_top.v")."\n`timescale 1ns / 1ps\n";
open(FILE, ">lib/verilog/${name}_top.v") || die "Can not open: $!";
print FILE "$l\n$top_v";
close(FILE) || die "Error closing file: $!";
1034,7 → 1125,7
my $soc=shift;
my $window = def_popwin_size(1200,500,"Wishbone slave port address setting");
my $window = def_popwin_size(80,50,"Wishbone slave port address setting",'percent');
my $table = def_table(10, 6, FALSE);
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
1335,7 → 1426,7
#############
 
sub load_soc{
my ($soc,$info)=@_;
my ($soc,$info,$ip)=@_;
my $file;
my $dialog = Gtk2::FileChooserDialog->new(
'Select a File', undef,
1363,38 → 1454,133
return;
}
clone_obj($soc,$pp);
check_instances_version($soc,$ip);
set_gui_status($soc,"load_file",0);
}
}
$dialog->destroy;
 
 
 
 
}
 
 
sub check_instances_version{
my ($soc,$ip)=@_;
 
#check if the IP's version didnt increases
my @all_instances=$soc->soc_get_all_instances();
foreach my $instance_id (@all_instances){
my ($old_v,$new_v)= get_old_new_ip_version ($soc,$ip,$instance_id);
my $differences='';
$differences="$differences \t The $instance_id version (V.$old_v) missmatches with the one exsiting in the library (V.$new_v).\n " if($old_v != $new_v);
message_dialog("Warning: The generated system may not work correctly: \n $differences Please remove and then add the aforementioned instance(s) to update them with current version(s)") if(length($differences)>1);
 
}
 
 
}
 
sub get_old_new_ip_version{
my ($soc,$ip,$instance_id)=@_;
my $old_v=$soc->object_get_attribute($instance_id,"version",undef);
$old_v=0 if(!defined $old_v);
my $module=$soc->soc_get_module($instance_id);
my $category=$soc->soc_get_category($instance_id);
my $new_v=$ip->ip_get($category,$module,"version");
$new_v=0 if(!defined $new_v);
return ($old_v,$new_v);
}
 
 
 
 
sub get_ram_init{
my $soc=shift;
my $window = def_popwin_size(80,50,"Memory initial file setting setting",'percent');
my $table = def_table(10, 6, FALSE);
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$scrolled_win->add_with_viewport($table);
my $row=0;
my $col=0;
my @instances=$soc->soc_get_all_instances();
foreach my $id (@instances){
my $category = $soc->soc_get_category($id);
if ($category eq 'RAM') {
my $ram_name= $soc->soc_get_instance_name($id);
$table->attach (gen_label_in_left("$ram_name"),$col,$col+1, $row, $row+1,'fill','shrink',2,2);$col++;
my $init_type=gen_combobox_object ($soc,'RAM_INIT','type',"Dont_Care,Fill_0,Fill_1,Search_in_sw,Fixed_file","Search_in_sw",undef);
my $init_inf= "Define how the memory must be initialized :
Dont_Care: The memory wont be initialized
Fill_0: All memory bits will fill with value zero
Fill_1: All memory bits will fill with value one
Search_in_sw: Each instance of this processing core
use different initial file that is
located in its SW folder.
Fixed_file: All instance of this processing core
use the same initial file";
$row++;
}
}
$window->add($scrolled_win);
$window->show_all;
}
 
 
sub software_edit_soc {
my $soc=shift;
my $name=$soc->object_get_attribute('soc_name');
if (length($name)==0){
message_dialog("Please define the SoC name!");
return ;
}
my $target_dir = "$ENV{'PRONOC_WORK'}/SOC/$name";
my $sw = "$target_dir/sw";
my ($app,$table,$tview) = software_main($sw);
 
 
 
my $make = def_image_button('icons/gen.png','Compile');
my $regen=def_image_button('icons/refresh.png','Regenerate main.c');
$table->attach ($regen,0, 1, 1,2,'shrink','shrink',0,0);
$table->attach ($make,9, 10, 1,2,'shrink','shrink',0,0);
$regen -> signal_connect ("clicked" => sub{
my $dialog = Gtk2::MessageDialog->new (my $window,
'destroy-with-parent',
'question', # message type
'yes-no', # which set of buttons?
"Are you sure you want to regenaret the Top.v file? Note that any changes you have made will be lost");
my $response = $dialog->run;
if ($response eq 'yes') {
save_file ("$sw/main.c",main_c_template($name));
$app->load_source("$sw/main.c");
}
 
 
});
 
$make -> signal_connect("clicked" => sub{
$app->do_save();
run_make_file($sw,$tview);
 
});
 
}
 
 
 
 
############
# main
############
1429,7 → 1615,11
my $device_win=show_active_dev($soc,$ip,$infc,\$refresh_dev_win,$info);
my $generate = def_image_button('icons/gen.png','Generate');
my $generate = def_image_button('icons/gen.png','Generate RTL');
my $compile = def_image_button('icons/gate.jpg','Compile RTL');
my $software = def_image_button('icons/binary.png','Software');
my $diagram = def_image_button('icons/diagram.png','Diagram');
my $ram = def_image_button('icons/RAM.png','Memory');
 
 
1436,7 → 1626,7
 
 
my $wb = def_image_button('icons/setting.png','Wishbone address setting');
my $wb = def_image_button('icons/setting.png','Wishbone-bus addr');
1448,18 → 1638,38
#$table->attach_defaults ($event_box, $col, $col+1, $row, $row+1);
$main_table->attach_defaults ($tree_box , 0, 2, 0, 17);
$main_table->attach_defaults ($device_win , 2, 12, 0, 17);
$main_table->attach_defaults ($infobox , 0, 12, 17,19);
$main_table->attach ($open,0, 3, 19,20,'expand','shrink',2,2);
$main_table->attach_defaults ($entrybox,3, 7, 19,20);
$main_table->attach ($wb, 7, 10, 19,20,'expand','shrink',2,2);
$main_table->attach ($generate, 10, 12, 19,20,'expand','shrink',2,2);
 
 
 
 
#$main_table->attach_defaults ($tree_box , 0, 2, 0, 17);
#$main_table->attach_defaults ($device_win , 2, 12, 0, 17);
#$main_table->attach_defaults ($infobox , 0, 12, 17,19);
 
 
my $h1=gen_hpaned($tree_box,.15,$device_win);
my $v2=gen_vpaned($h1,.55,$infobox);
$main_table->attach_defaults ($v2 , 0, 12, 0,19);
 
 
 
 
$main_table->attach ($open,0, 2, 19,20,'expand','shrink',2,2);
$main_table->attach_defaults ($entrybox,2, 4, 19,20);
$main_table->attach ($wb, 4,6, 19,20,'expand','shrink',2,2);
$main_table->attach ($diagram, 6, 7, 19,20,'expand','shrink',2,2);
$main_table->attach ($generate, 7, 8, 19,20,'expand','shrink',2,2);
$main_table->attach ($software, 8, 9, 19,20,'expand','shrink',2,2);
#$main_table->attach ($ram, 9, 10, 19,20,'expand','shrink',2,2);
$main_table->attach ($compile, 10, 12, 19,20,'expand','shrink',2,2);
 
$diagram-> signal_connect("clicked" => sub{
show_tile_diagram ($soc);
});
$generate-> signal_connect("clicked" => sub{
my $name=$soc->object_get_attribute('soc_name');
1474,8 → 1684,9
message_dialog("The soc name must not end with '_number'!");
return ;
}
if ( $name =~ /\W+/ ){
message_dialog('The soc name must not contain any non-word character:("./\()\':,.;<>~!@#$%^&*|+=[]{}`~?-")!")');
my $error = check_verilog_identifier_syntax($name);
if ( defined $error ){
message_dialog("The \"$name\" is given with an unacceptable formatting. This name will be used as top level verilog module name so it must follow Verilog identifier declaration formatting:\n $error");
return ;
}
 
1485,11 → 1696,52
$soc->object_add_attribute('global_param','CORE_ID',0);
generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);
message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
exec($^X, $0, @ARGV);# reset ProNoC to apply changes
#message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
my $dialog = Gtk2::MessageDialog->new (my $window,
'destroy-with-parent',
'question', # message type
'yes-no', # which set of buttons?
"Processing Tile \"$name\" has been created successfully at $target_dir/. In order to see this tile in MPSoC Generator you need to restar the ProNoC. Do you ant to reset the ProNoC now?");
my $response = $dialog->run;
if ($response eq 'yes') {
exec($^X, $0, @ARGV);# reset ProNoC to apply changes
}
$dialog->destroy;
 
 
 
});
 
$software -> signal_connect("clicked" => sub{
software_edit_soc($soc);
 
});
 
$ram-> signal_connect("clicked" => sub{
get_ram_init($soc);
 
});
 
 
$compile -> signal_connect("clicked" => sub{
my $name=$soc->object_get_attribute('soc_name');
if (length($name)==0){
message_dialog("Please define the SoC name!");
return ;
}
my $target_dir = "$ENV{'PRONOC_WORK'}/SOC/$name";
my $top = "$target_dir/src_verilog/${name}_top.v";
if (-f $top){
select_compiler($soc,$name,$top,$target_dir);
} else {
message_dialog("Cannot find $top file. Please run RTL Generator first!");
return;
}
});
 
$wb-> signal_connect("clicked" => sub{
wb_address_setting($soc);
1496,7 → 1748,7
});
 
$open-> signal_connect("clicked" => sub{
load_soc($soc,$info);
load_soc($soc,$info,$ip);
});
 
1514,6 → 1766,14
$timeout--;
set_gui_status($soc,$state,$timeout);
}elsif ($state eq 'save_project'){
# Write object file
my $name=$soc->object_get_attribute('soc_name',undef);
open(FILE, ">lib/soc/$name.SOC") || die "Can not open: $!";
print FILE perl_file_header("$name.SOC");
print FILE Data::Dumper->Dump([\%$soc],['soc']);
close(FILE) || die "Error closing file: $!";
set_gui_status($soc,"ideal",0);
}
elsif( $state ne "ideal" ){
$refresh_dev_win->clicked;
1532,3 → 1792,9
 
}
 
 
 
 
 
 
/lib/perl/software_editor.pl
0,0 → 1,764
#!/usr/bin/perl
 
use strict;
use warnings;
 
use Glib qw(TRUE FALSE);
use Gtk2 '-init';
use Gtk2::SourceView2;
use Data::Dumper;
 
 
use base 'Class::Accessor::Fast';
require "widget.pl";
 
 
__PACKAGE__->mk_accessors(qw{
window
sourceview
buffer
filename
search_regexp
search_case
search_entry
regexp
highlighted
});
 
my $NAME = 'Otec';
 
 
exit main() unless caller;
 
 
sub software_main {
my ($sw,$file) = @_;
 
 
my $app = __PACKAGE__->new();
my ($table,$tview,$window)=$app->build_gui($sw);
my $main_c=(defined $file)? "$sw/$file" : "$sw/main.c";
$app->load_source($main_c) if (-f $main_c );
 
#Gtk2->main();
 
return ($app,$table,$tview,$window);
}
 
 
sub build_gui {
my ($self,$sw) = @_;
 
my $window = def_popwin_size (75,75,'Source Editore','percent');
my $table= def_table(2,10,FALSE);
 
 
 
my $hpaned = Gtk2::HPaned -> new;
my $vpaned = Gtk2::VPaned -> new;
$table->attach_defaults ($vpaned,0, 10, 0,1);
#my $make = def_image_button('icons/run.png','Compile');
#$table->attach ($make,9, 10, 1,2,'shrink','shrink',0,0);
#$make -> signal_connect("clicked" => sub{
#$self->do_save();
#run_make_file($sw,$tview);
 
#});
 
$window -> add ( $table);
 
my($width,$hight)=max_win_size();
my $scwin_dirs = Gtk2::ScrolledWindow -> new;
$scwin_dirs -> set_policy ('automatic', 'automatic');
$hpaned -> pack1 ($scwin_dirs, TRUE, TRUE);
$hpaned ->set_position ($width*.15);
 
my $scwin_text = Gtk2::ScrolledWindow -> new;
$scwin_text -> set_policy ('automatic', 'automatic');
$hpaned -> pack2 ($scwin_text, TRUE, TRUE);
 
my ($scwin_info,$tview)= create_text();
add_colored_tag($tview,'red');
add_colored_tag($tview,'blue');
$vpaned-> pack1 ($hpaned, TRUE, TRUE);
$vpaned ->set_position ($hight*.5);
$vpaned-> pack2 ($scwin_info, TRUE, TRUE);
 
 
 
 
# Directory name, full path
my $tree_store = Gtk2::TreeStore->new('Glib::String', 'Glib::String');
my $tree_view = Gtk2::TreeView->new($tree_store);
my $column = Gtk2::TreeViewColumn->new_with_attributes('', Gtk2::CellRendererText->new(), text => "0");
$tree_view->append_column($column);
$tree_view->set_headers_visible(FALSE);
$tree_view->signal_connect (button_release_event => sub{
my $tree_model = $tree_view->get_model();
my $selection = $tree_view->get_selection();
my $iter = $selection->get_selected();
if(defined $iter){
my $path = $tree_model->get($iter, 1) ;
$path= substr $path, 0, -1;
$self->load_source($path) if(-f $path);
}
return;
});
 
 
$tree_view->signal_connect ('row-expanded' => sub {
my ($tree_view, $iter, $tree_path) = @_;
my $tree_model = $tree_view->get_model();
my ($dir, $path) = $tree_model->get($iter);
 
# for each of $iter's children add any subdirectories
my $child = $tree_model->iter_children ($iter);
while ($child) {
my ($dir, $path) = $tree_model->get($child, 0, 1);
add_to_tree($tree_view,$tree_store, $child, $dir, $path);
$child = $tree_model->iter_next ($child);
}
return;
});
 
 
$scwin_dirs -> add($tree_view);
 
 
 
my $child = $tree_store->append(undef);
$tree_store->set($child, 0, $sw, 1, '/');
add_to_tree($tree_view,$tree_store, $child, '/', "$sw/");
#print "$sw/\n";
 
#my $window = Gtk2::Window->new();
#$window->set_size_request(480, 360);
#$window->set_title($NAME);
$self->window($window);
 
my $vbox = Gtk2::VBox->new(FALSE, 0);
$scwin_text->add_with_viewport($vbox);
 
$vbox->pack_start($self->build_menu, FALSE, FALSE, 0);
$vbox->pack_start($self->build_search_box, FALSE, FALSE, 0);
 
my $scroll = Gtk2::ScrolledWindow->new();
$scroll->set_policy('automatic', 'automatic');
$scroll->set_shadow_type('in');
$vbox->pack_start($scroll, TRUE, TRUE, 0);
 
my $buffer = $self->create_buffer();
my $sourceview = Gtk2::SourceView2::View->new_with_buffer($buffer);
$sourceview->set_show_line_numbers(TRUE);
$sourceview->set_tab_width(2);
$sourceview->set_indent_on_tab(TRUE);
$sourceview->set_highlight_current_line(TRUE);
# $sourceview->set_draw_spaces(['tab', 'newline']);
 
#
# Fix Gtk2::TextView's annoying paste behaviour when pasting with the mouse
# (middle button click). By default gtk will scroll the text view to the
# original place where the cursor is.
#
$sourceview->signal_connect(button_press_event => sub {
my ($view, $event) = @_;
 
# We're only interested on middle mouse clicks (mouse-paste)
return FALSE unless $event->button == 2;
 
# Remember the position of the paste
my (@coords) = $sourceview->window_to_buffer_coords('text', $event->x, $event->y);
my ($iter) = $sourceview->get_iter_at_position(@coords);
$self->{paste_mark} = $buffer->create_mark('paste', $iter, FALSE);
 
return FALSE;
});
 
 
#
# If a paste is done through the middle click then place the cursor at the end
# of the pasted text.
#
$buffer->signal_connect('paste-done' => sub {
my $mark = delete $self->{paste_mark} or return;
 
my $iter = $buffer->get_iter_at_mark($mark);
$buffer->place_cursor($iter);
 
$self->sourceview->scroll_to_mark(
$mark,
0.0,
FALSE,
0.0, 0.5
);
$buffer->delete_mark($mark);
});
 
 
$scroll->add($sourceview);
$self->sourceview($sourceview);
$self->buffer($sourceview->get_buffer);
 
$window->signal_connect(delete_event => sub {
Gtk2->main_quit();
return TRUE;
});
 
$window->show_all();
return ($table,$tview,$window);
}
 
 
sub build_search_box {
my $self = shift;
 
# Elements of the search box
my $hbox = Gtk2::HBox->new(FALSE, 0);
 
my $search_entry = Gtk2::Entry->new();
$search_entry->signal_connect(activate => sub {$self->do_search()});
$search_entry->signal_connect(icon_release => sub {$self->do_search()});
$self->search_entry($search_entry);
 
my $search_regexp = Gtk2::CheckButton->new('RegExp');
$search_regexp->signal_connect(toggled => sub {
$self->search_regexp($search_regexp->get_active);
});
 
my $search_case = Gtk2::CheckButton->new('Case');
$search_case->signal_connect(toggled => sub {
$self->search_case($search_case->get_active);
});
 
my $search_icon = Gtk2::Button->new_from_stock('gtk-find');
$search_entry->set_icon_from_stock(primary => 'gtk-find');
 
$hbox->pack_start($search_entry, TRUE, TRUE , 0);
$hbox->pack_start($search_regexp, FALSE, FALSE, 0);
$hbox->pack_start($search_case, FALSE, FALSE, 0);
 
return $hbox;
}
 
 
sub create_buffer {
my $self = shift;
my $tags = Gtk2::TextTagTable->new();
 
add_tag($tags, search => {
background => 'yellow',
});
add_tag($tags, goto_line => {
'paragraph-background' => 'orange',
});
 
my $buffer = Gtk2::SourceView2::Buffer->new($tags);
$buffer->signal_connect('notify::cursor-position' => sub {
$self->clear_highlighted();
});
 
return $buffer;
}
 
 
sub add_tag {
my ($tags, $name, $properties) = @_;
 
my $tag = Gtk2::TextTag->new($name);
$tag->set(%{ $properties });
$tags->add($tag);
}
 
 
sub detect_language {
my $self = shift;
my ($filename) = @_;
 
# Guess the programming language of the file
my $manager = Gtk2::SourceView2::LanguageManager->get_default;
my $language = $manager->guess_language($filename);
$self->buffer->set_language($language);
}
 
 
sub load_source {
my $self = shift;
my ($filename) = @_;
my $buffer = $self->buffer;
 
# Guess the programming language of the file
$self->detect_language($filename);
 
# Loading a file should not be undoable.
my $content;
do {
open my $handle, $filename or die "Can't read file $filename because $!";
local $/;
$content = <$handle>;
close $handle;
};
$buffer->begin_not_undoable_action();
$buffer->set_text($content);
$buffer->end_not_undoable_action();
 
$buffer->set_modified(FALSE);
$buffer->place_cursor($buffer->get_start_iter);
 
$self->filename($filename);
$self->window->set_title("$filename - $NAME");
}
 
 
sub clear_highlighted {
my $self = shift;
 
my $highlighted = delete $self->{highlighted} or return;
 
my $buffer = $self->buffer;
 
my @iters;
foreach my $mark (@{ $highlighted->{marks} }) {
my $iter = $buffer->get_iter_at_mark($mark);
push @iters, $iter;
$buffer->delete_mark($mark);
}
 
$buffer->remove_tag_by_name($highlighted->{name}, @iters);
}
 
 
sub get_text {
my $self = shift;
my $buffer = $self->buffer;
return $buffer->get_text($buffer->get_start_iter, $buffer->get_end_iter, FALSE);
}
 
 
sub do_search {
my $self = shift;
my $criteria = $self->search_entry->get_text;
if ($criteria eq '') {return;}
 
my $case = $self->search_case;
my $buffer = $self->buffer;
 
 
# Start the search at the last search result or from the current cursor's
# position. As a fall back we also add the beginning of the document. Once we
# have the start position we can erase the previous search results.
my @start;
if (my $highlighted = $self->highlighted) {
# Search from the last match
push @start, $buffer->get_iter_at_mark($highlighted->{marks}[1]);
$self->clear_highlighted();
}
else {
# Search from the cursor
push @start, $buffer->get_iter_at_offset(
$buffer->get_property('cursor-position')
);
}
push @start, $buffer->get_start_iter;
 
my @iters;
if ($self->search_regexp) {
# Gtk2::SourceView2 nor Gtk2::SourceView support regular expressions so we
# have to do the search by hand!
 
my $text = $self->get_text;
my $regexp = $case ? qr/$criteria/m : qr/$criteria/im;
 
foreach my $iter (@start) {
# Tell Perl where to start the regexp lookup
pos($text) = $iter->get_offset;
 
if ($text =~ /($regexp)/g) {
my $word = $1;
my $pos = pos($text);
@iters = (
$buffer->get_iter_at_offset($pos - length($word)),
$buffer->get_iter_at_offset($pos),
);
last;
}
}
}
else {
# Use the builtin search mechanism
my $flags = $case ? [ ] : [ 'case-insensitive' ];
foreach my $iter (@start) {
@iters = Gtk2::SourceView2::Iter->forward_search($iter, $criteria, $flags);
last if @iters;
}
}
 
$self->show_highlighted(search => @iters) if @iters;
}
 
 
sub show_highlighted {
my $self = shift;
my ($tag_name, $start, $end) = @_;
my $buffer = $self->buffer;
 
# Highlight the region, remember it and scroll to it
my $match_start = $buffer->create_mark('match-start', $start, TRUE);
my $match_end = $buffer->create_mark('match-end', $end, FALSE);
 
$buffer->apply_tag_by_name($tag_name, $start, $end);
 
# We have a callback that listens to when the cursor is placed and we don't
# want it to undo our work! So let's unhighlight the previous entry.
delete $self->{highlighted};
$buffer->place_cursor($end);
 
$self->sourceview->scroll_to_mark(
$match_start,
0.2,
FALSE,
0.0, 0.5
);
 
# Keep a reference to the markers once they have been added to the buffer.
# Using them before can be catastrophic (segmenation fault).
#
$self->highlighted({
name => $tag_name,
marks => [$match_start, $match_end],
});
}
 
 
sub do_file_new {
my $self = shift;
my $buffer = $self->buffer;
 
# Set no language
$buffer->set_language(undef);
 
# Showing a blank editor should not be undoable.
$buffer->begin_not_undoable_action();
$buffer->set_text('');
$buffer->end_not_undoable_action();
 
$buffer->set_modified(FALSE);
$buffer->place_cursor($buffer->get_start_iter);
 
$self->filename('');
$self->window->set_title("Untitled - $NAME");
}
 
 
sub do_file_open {
my $self = shift;
my ($window, $action, $menu_item) = @_;
 
my $dialog = Gtk2::FileSelection->new("Open file...");
$dialog->signal_connect(response => sub {
my ($dialog, $response) = @_;
 
if ($response eq 'ok') {
my $file = $dialog->get_filename;
return if -d $file;
$self->load_source($file);
}
 
$dialog->destroy();
});
$dialog->show();
}
 
 
sub do_show_about_dialog {
my $self = shift;
 
my $dialog = Gtk2::AboutDialog->new();
$dialog->set_authors("Emmanuel Rodriguez");
$dialog->set_comments("Gtk2::SourceView2 Demo");
$dialog->signal_connect(response => sub {
my ($dialog, $response) = @_;
$dialog->destroy();
});
$dialog->show();
}
 
 
sub do_ask_goto_line {
my $self = shift;
 
my $dialog = Gtk2::Dialog->new_with_buttons(
"Goto to line",
$self->window,
[ 'modal' ],
'gtk-cancel' => 'cancel',
'gtk-ok' => 'ok',
);
 
my $hbox = Gtk2::HBox->new(FALSE, 0);
$hbox->pack_start(
Gtk2::Label->new("Line number: "),
FALSE, FALSE, 0
);
my $entry = Gtk2::Entry->new();
$hbox->pack_start($entry, TRUE, TRUE, 0);
 
$dialog->get_content_area->add($hbox);
$dialog->show_all();
 
 
# Signal handlers
$entry->signal_connect(activate => sub {
if ($entry->get_text =~ /(\d+)/) {
$dialog->response('ok');
}
});
 
# Run the dialog
my $response = $dialog->run();
$dialog->destroy();
return unless $response eq 'ok';
 
return unless my ($line) = ($entry->get_text =~ /(\d+)/);
my $buffer = $self->buffer;
my $start = $buffer->get_iter_at_line($line - 1);
my $end = $start->copy;
$end->forward_to_line_end;
 
$self->clear_highlighted();
$self->show_highlighted(goto_line => $start, $end);
}
 
 
sub do_quit {
my $self = shift;
Gtk2->main_quit();
}
 
 
sub do_save_as {
my $self = shift;
 
# If no file is associated with the editor then ask the user for a file where
# to save the contents of the buffer.
my $dialog = Gtk2::FileChooserDialog->new(
"Save file", $self->window, 'save',
'gtk-cancel' => 'cancel',
'gtk-save' => 'ok',
);
 
my $response = $dialog->run();
if ($response eq 'ok') {
$self->filename($dialog->get_filename);
$self->do_save();
}
$dialog->destroy();
}
 
 
sub do_save {
my $self = shift;
 
my $filename = $self->filename;
 
# If there's no file then do a save as...
if (! $filename) {
$self->do_save_as();
return;
}
 
my $buffer = $self->buffer;
open my $handle, '>:encoding(UTF-8)', $filename or die "Can't write to $filename: $!";
print $handle $self->get_text;
close $handle;
 
if (! $buffer->get_language) {
$self->detect_language($filename);
}
}
 
 
sub build_menu {
my $self = shift;
 
my $entries = [
# name, stock id, label
[ "FileMenu", undef, "_File" ],
[ "SearchMenu", undef, "_Search" ],
[ "HelpMenu", undef, "_Help" ],
 
# name, stock id, label, accelerator, tooltip, method
[
"New",
'gtk-new',
"_New",
"<control>N",
"Create a new file",
sub { $self->do_file_new(@_) }
],
[
"Open",
'gtk-open',
"_Open",
"<control>O",
"Open a file",
sub { $self->do_file_open(@_) }
],
[
"Save",
'gtk-save',
"_Save",
"<control>S",
"Save current file",
sub { $self->do_save(@_) }
],
[
"SaveAs",
'gtk-save',
"Save _As...",
"<control><shift>S",
"Save to a file",
sub { $self->do_save_as(@_) }
],
[
"Quit",
'gtk-quit',
"_Quit",
"<control>Q",
"Quit",
sub { $self->do_quit() }
],
[
"About",
'gtk-about',
"_About",
undef,
"About",
sub { $self->do_show_about_dialog(@_) }
],
[
"GotoLine",
undef,
"Goto to _Line",
"<control>L",
"Go to line",
sub { $self->do_ask_goto_line(@_) }
],
];
 
my $actions = Gtk2::ActionGroup->new("Actions");
$actions->add_actions($entries, undef);
 
my $ui = Gtk2::UIManager->new();
$ui->insert_action_group($actions, 0);
$ui->add_ui_from_string(<<'__UI__');
<ui>
<menubar name='MenuBar'>
<menu action='FileMenu'>
<menuitem action='New'/>
<menuitem action='Open'/>
<separator/>
<menuitem action='Save'/>
<menuitem action='SaveAs'/>
<separator/>
<menuitem action='Quit'/>
</menu>
<menu action='SearchMenu'>
<menuitem action='GotoLine'/>
</menu>
<menu action='HelpMenu'>
<menuitem action='About'/>
</menu>
</menubar>
</ui>
__UI__
 
$self->window->add_accel_group($ui->get_accel_group);
 
return $ui->get_widget('/MenuBar');
}
 
 
 
sub add_to_tree {
my ($tree_view,$tree_store, $parent, $dir, $path) = @_;
my $tree_model = $tree_view->get_model();
 
# If $parent already has children, then remove them first
my $child = $tree_model->iter_children ($parent);
while ($child) {
$tree_store->remove ($child);
$child = $tree_model->iter_children ($parent);
}
 
# Add children from directory listing
opendir(DIRHANDLE, $path) || return ; #die "Cannot open directory:$path $!\n";
foreach my $subdir (sort readdir(DIRHANDLE)) {
if ($subdir ne '.' and $subdir ne '..'
# and -d $path.$subdir and -r $path.$subdir
) {
my $child = $tree_store->append($parent);
$tree_store->set($child, 0, $subdir, 1, "$path$subdir/");
}
}
closedir(DIRHANDLE);
}
 
 
# Directory expanded. Populate subdirectories in readiness.
 
sub populate_tree {
 
# $iter has been expanded
my ($tree_view,$tree_store, $iter, $tree_path) = @_;
my $tree_model = $tree_view->get_model();
my ($dir, $path) = $tree_model->get($iter);
 
# for each of $iter's children add any subdirectories
my $child = $tree_model->iter_children ($iter);
while ($child) {
my ($dir, $path) = $tree_model->get($child, 0, 1);
add_to_tree($tree_view,$tree_store, $child, $dir, $path);
$child = $tree_model->iter_next ($child);
}
return;
}
 
 
sub run_make_file {
my ($dir,$outtext)=@_;
my $cmd = "cd \"$dir/\" \n make ";
my $error=0;
show_info(\$outtext,"$cmd\n");
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout( $cmd);
 
if($stderr){
$stderr=~ s/[‘,’]//g;
add_info(\$outtext,"$stdout\n");
add_colored_info(\$outtext,"$stderr\n","red");
add_colored_info(\$outtext,"Compilation failed.\n",'red');
 
}else{
 
add_info(\$outtext,"$stdout\n");
add_colored_info(\$outtext,"Compilation finished successfully.\n",'blue');
}
#add_info(\$outtext,"**********Quartus compilation is done successfully in $target_dir!*************\n") if($error==0);
 
 
 
}
 
 
 
 
1;
 
/lib/perl/verilog_gen.pl
19,7 → 19,7
#####################
 
sub soc_generate_verilog{
my ($soc)= @_;
my ($soc,$sw_path)= @_;
my $soc_name=$soc->object_get_attribute('soc_name');
#my $top_ip=ip_gen->ip_gen_new();
my $top_ip=ip_gen->top_gen_new();
29,12 → 29,13
my $io_sim_v;
my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
$core_id= 0 if(!defined $core_id);
my $param_as_in_v="\tparameter\tCORE_ID=$core_id";
my $param_as_in_v="\tparameter\tCORE_ID=$core_id,
\tparameter\tSW_LOC=\"$sw_path\"";
 
 
 
 
my $param_pass_v="\t.CORE_ID(CORE_ID)";
my $param_pass_v="\t.CORE_ID(CORE_ID),\n\t.SW_LOC(SW_LOC)";
my $body_v;
my ($param_v_all, $local_param_v_all, $wire_def_v_all, $inst_v_all, $plugs_assign_v_all, $sockets_assign_v_all,$io_full_v_all);
84,7 → 85,7
add_text_to_string(\$soc_v,"endmodule\n\n");
$soc->soc_add_top($top_ip);
$soc->object_add_attribute('top_ip',undef,$top_ip);
#print @assigned_wires;
 
#generate topmodule
91,7 → 92,7
my $top_v = (defined $param_as_in_v )? "module ${soc_name}_top #(\n $param_as_in_v\n)(\n$io_sim_v\n);\n": "module ${soc_name}_top (\n $io_sim_v\n);\n";
my $ins= gen_soc_instance_v($soc,$soc_name,$param_pass_v);
 
add_text_to_string(\$top_v,$functions_all);
add_text_to_string(\$top_v,$local_param_v_all."\n".$io_full_v_all);
add_text_to_string(\$top_v,$ins);
my ($readme,$prog)=gen_system_info($soc,$param_as_in_v);
728,12 → 729,12
$v= $soc->object_get_attribute('global_param',$JTAG_INDEX);
$JTAG_INDEX = $v if (defined $v);
my $BINFILE=$soc->soc_get_module_param_value($instance_id,'INIT_FILE_NAME');
my $BINFILE=$soc->soc_get_module_param_value($instance_id,'JTAG_MEM_FILE');
($BINFILE)=$BINFILE=~ /"([^"]*)"/ if(defined $BINFILE);
$BINFILE=(defined $BINFILE) ? $BINFILE.'.bin' : 'ram0.bin';
my $OFSSET="0x00000000";
my $end=((1<<$aw)*($dw/8))-1;
my $end=((1 << $aw)*($dw/8))-1;
my $BOUNDRY=sprintf("0x%08x", $end);
if($jtag_connect =~ /JTAG_WB/){
$prog= "$prog \$JTAG_MAIN -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i \"$BINFILE\" -c";
/lib/perl/widget.pl
286,7 → 286,7
}
 
sub def_image{
sub def_icon{
my $image_file=shift;
my $font_size=get_defualt_font_size();
my $size=($font_size==10)? 25:
302,18 → 302,35
}
 
 
sub open_image{
my ($image_file,$x,$y,$unit)=@_;
if(defined $unit){
my($width,$hight)=max_win_size();
if($unit eq 'percent'){
$x= ($x * $width)/100;
$y= ($y * $hight)/100;
} # else its pixels
}
my $pixbuf = Gtk2::Gdk::Pixbuf->new_from_file_at_scale($image_file,$x,$y,TRUE);
my $image = Gtk2::Image->new_from_pixbuf($pixbuf);
return $image;
 
}
 
 
 
sub def_image_button{
my ($image_file, $label_text, $homogeneous)=@_;
# create box for image and label
$homogeneous = FALSE if(!defined $homogeneous);
my $box = def_hbox($homogeneous,0);
my $image = def_image($image_file);
my $image = def_icon($image_file) if(-f $image_file);
# now on to the image stuff
#my $image = Gtk2::Image->new_from_file($image_file);
$box->pack_start($image, FALSE, FALSE, 0);
$box->pack_start($image, FALSE, FALSE, 0) if(-f $image_file);
$box->set_border_width(0);
$box->set_spacing (0);
# Create a label for the button
337,7 → 354,7
# create box for image and label
my $box = def_hbox(FALSE,1);
# now on to the image stuff
my $image = def_image($image_file);
my $image = def_icon($image_file);
$box->pack_start($image, TRUE, FALSE, 0);
# Create a label for the button
if(defined $label_text ) {
454,13 → 471,14
############
 
sub message_dialog {
my @message=@_;
my ($message,$type)=@_;
$type = 'info' if (!defined $type);
my $window;
my $dialog = Gtk2::MessageDialog->new ($window,
[qw/modal destroy-with-parent/],
'info',
$type,
'ok',
@message);
$message);
$dialog->run;
$dialog->destroy;
500,12 → 518,18
 
 
sub def_popwin_size {
my $x=shift;
my $y=shift;
my @titel=shift;
my ($x,$y,$titel,$unit)=@_;
if(defined $unit){
my($width,$hight)=max_win_size();
if($unit eq 'percent'){
$x= ($x * $width)/100;
$y= ($y * $hight)/100;
} # else its pixels
}
#my $window = Gtk2::Window->new('popup');
my $window = Gtk2::Window->new('toplevel');
$window->set_title(@titel);
$window->set_title($titel);
$window->set_position("center");
$window->set_default_size($x, $y);
$window->set_border_width(20);
549,7 → 573,7
#print "($width,$hight)\n";
my $font_size=($width>=1600)? 10:
($width>=1400)? 9:
($width>=1200)? 8:
($width>=1200)? 9:
($width>=1000)? 7:6;
#print "$font_size\n";
return $font_size;
597,8 → 621,49
 
}
 
sub def_pack_vbox{
my( $homogeneous, $spacing , @box_list)=@_;
my $box=def_vbox($homogeneous, $spacing);
foreach my $subbox (@box_list){
$box->pack_start( $subbox, FALSE, FALSE, 3);
}
return $box;
 
}
 
 
##########
# Paned
#########
 
 
sub gen_vpaned {
my ($w1,$loc,$w2) = @_;
my $vpaned = Gtk2::VPaned -> new;
my($width,$hight)=max_win_size();
 
$vpaned -> pack1($w1, TRUE, TRUE);
$vpaned -> set_position ($hight*$loc);
$vpaned -> pack2($w2, TRUE, TRUE);
return $vpaned;
}
 
 
sub gen_hpaned {
my ($w1,$loc,$w2) = @_;
my $hpaned = Gtk2::HPaned -> new;
my($width,$hight)=max_win_size();
 
$hpaned -> pack1($w1, TRUE, TRUE);
$hpaned -> set_position ($width*$loc);
$hpaned -> pack2($w2, TRUE, TRUE);
return $hpaned;
}
 
#############
# text_view
############
688,14 → 753,38
}
 
sub show_colored_info{
my ($textview_ref,$info,$color)=@_;
my $buffer = $$textview_ref->get_buffer();
#$buffer->set_text($info);
my $textiter = $buffer->get_start_iter();
$buffer->insert_with_tags_by_name ($textiter, "$info", "${color}_tag");
}
 
sub add_colored_info{
my ($textview_ref,$info,$color)=@_;
my $buffer = $$textview_ref->get_buffer();
my $textiter = $buffer->get_end_iter();
#Insert some text into the buffer
#$buffer->insert($textiter,$info);
$buffer->insert_with_tags_by_name ($textiter, "$info", "${color}_tag");
}
 
sub add_colored_tag{
my ($textview_ref,$color)=@_;
my $buffer = $textview_ref->get_buffer();
$buffer->create_tag ("${color}_tag", foreground => $color);
}
 
 
####################
# read verilog file
# file
##################
 
 
sub read_file{
sub read_verilog_file{
my @files = @_;
my %cmd_line_defines = ();
my $quiet = 1;
718,19 → 807,131
 
sub add_color_to_gd{
foreach (my $i=0;$i<32;$i++ ) {
my ($red,$green,$blue)=get_color($i);
my ($red,$green,$blue)=get_color($i);
add_colour("my_color$i"=>[$red>>8,$green>>8,$blue>>8]);
add_colour("my_color$i"=>[$red>>8,$green>>8,$blue>>8]);
}
}
 
 
 
sub append_text_to_file {
my ($file_path,$text)=@_;
open(my $fd, ">>$file_path");
print $fd $text;
close $fd;
}
 
 
 
 
sub save_file {
my ($file_path,$text)=@_;
open(my $fd, ">$file_path");
print $fd $text;
close $fd;
}
 
sub load_file {
my $file_path=shift;
my $str;
if (-f "$file_path") {
$str = do {
local $/ = undef;
open my $fh, "<", $file_path
or die "could not open $file_path: $!";
<$fh>;
};
 
}
return $str;
}
 
 
 
 
sub merg_files {
my ($source_file_path,$dest_file_path)=@_;
local $/=undef;
open FILE, $source_file_path or die "Couldn't open file: $!";
my $string = <FILE>;
close FILE;
append_text_to_file ($dest_file_path,$string);
}
 
 
 
sub copy_file_and_folders{
my ($file_ref,$project_dir,$target_dir)=@_;
 
foreach my $f(@{$file_ref}){
my $name= basename($f);
my $n="$project_dir$f";
if (-f "$n") { #copy file
copy ("$n","$target_dir");
}elsif(-f "$f" ){
copy ("$f","$target_dir");
}elsif (-d "$n") {#copy folder
dircopy ("$n","$target_dir/$name");
}elsif(-d "$f" ){
dircopy ("$f","$target_dir/$name");
}
}
 
}
 
sub read_file_cntent {
my ($f,$project_dir)=@_;
my $n="$project_dir$f";
my $str;
if (-f "$n") {
$str = do {
local $/ = undef;
open my $fh, "<", $n
or die "could not open $n: $!";
<$fh>;
};
 
}elsif(-f "$f" ){
$str = do {
local $/ = undef;
open my $fh, "<", $f
or die "could not open $f: $!";
<$fh>;
};
}
return $str;
 
}
 
 
sub check_file_has_string {
my ($file,$string)=@_;
my $r;
open(FILE,$file);
if (grep{/$string/} <FILE>){
$r= 1; #print "word found\n";
}else{
$r= 0; #print "word not found\n";
}
close FILE;
return $r;
}
 
 
###########
# color
#########
 
 
 
 
 
sub get_color {
my $num=shift;
780,8 → 981,51
}
 
 
sub get_color_hex_string {
my $num=shift;
my @colors=(
"6495ED",#Cornflower Blue
"FAEBD7",#Antiquewhite
"C71585",#Violet Red
"C0C0C0",#silver
"ADD8E6",#Lightblue
"6A5ACD",#Slate Blue
"00CED1",#Dark Turquoise
"008080",#Teal
"2E8B57",#SeaGreen
"FFB6C1",#Light Pink
"008000",#Green
"FF0000",#red
"808080",#Gray
"808000",#Olive
"FF69B4",#Hot Pink
"FFD700",#Gold
"DAA520",#Goldenrod
"FFA500",#Orange
"32CD32",#LimeGreen
"0000FF",#Blue
"FF8C00",#DarkOrange
"A0522D",#Sienna
"FF6347",#Tomato
"0000CD",#Medium Blue
"FF4500",#OrangeRed
"DC143C",#Crimson
"9932CC",#Dark Orchid
"800000",#marron
"800080",#Purple
"4B0082",#Indigo
"FFFFFF",#white
"000000" #Black
);
my $color= ($num< scalar (@colors))? $colors[$num]: "FFFFFF";
return $color;
}
 
 
 
##############
# clone_obj
#############
888,6 → 1132,8
sub get_file_name {
my ($object,$title,$entry,$attribute1,$attribute2,$extension,$lable,$open_in)= @_;
my $browse= def_image_button("icons/browse.png");
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../"); #mpsoc directory address
 
$browse->signal_connect("clicked"=> sub{
my $entry_ref=$_[1];
912,12 → 1158,16
}
if ( "ok" eq $dialog->run ) {
$file = $dialog->get_filename;
$file = $dialog->get_filename;
#remove $project_dir form beginig of each file
$file =~ s/$project_dir//;
$$entry_ref->set_text($file);
$object->object_add_attribute($attribute1,$attribute2,$file);
$object->object_add_attribute($attribute1,$attribute2,$file) if(defined $object);
my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
$lable->set_markup("<span foreground= 'black' ><b>$name$suffix</b></span>");
$lable->show;
if(defined $lable){
$lable->set_markup("<span foreground= 'black' ><b>$name$suffix</b></span>");
$lable->show;
}
#check_input_file($file,$socgen,$soc_state,$info);
#print "file = $file\n";
1028,8 → 1278,10
}
 
 
sub gen_check_box_object {
my ($object,$attribute1,$attribute2,$content,$value,$default,$status,$timeout)=@_;
sub gen_check_box_object_array {
my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
my $value=$object->object_get_attribute($attribute1,$attribute2);
$value = $default if (!defined $value);
my $widget = def_hbox(FALSE,0);
my @check;
for (my $i=0;$i<$content;$i++){
1074,6 → 1326,39
 
 
 
 
 
sub gen_check_box_object {
my ($object,$attribute1,$attribute2,$default,$status,$timeout)=@_;
my $value=$object->object_get_attribute($attribute1,$attribute2);
if (!defined $value){
#set initial value
$object->object_add_attribute($attribute1,$attribute2,$default);
$value = $default
}
my $widget = Gtk2::CheckButton->new;
if($value == 1) {$widget->set_active(TRUE);}
else {$widget->set_active(FALSE);}
#get new value
$widget-> signal_connect("toggled" => sub{
my $new_val;
if($widget->get_active()) {$new_val=1;}
else {$new_val=0;}
$object->object_add_attribute($attribute1,$attribute2,$new_val);
#print "\$new_val=$new_val\n";
set_gui_status($object,$status,$timeout) if (defined $status);
});
return $widget;
 
}
 
 
 
 
 
 
sub get_dir_in_object {
my ($object,$attribute1,$attribute2,$content,$status,$timeout)=@_;
my $widget = def_hbox(FALSE,0);
1103,7 → 1388,7
$lable=gen_label_in_center($name.$suffix);
} else {
$lable=gen_label_in_center("Selecet a $extension file");
$lable=gen_label_in_center("Selecet a file");
$lable->set_markup("<span foreground= 'red' ><b>No file has been selected yet</b></span>");
}
my $entry=gen_entry();
1269,54 → 1554,7
}
 
 
sub copy_file_and_folders{
my ($file_ref,$project_dir,$target_dir)=@_;
 
foreach my $f(@{$file_ref}){
my $name= basename($f);
my $n="$project_dir$f";
if (-f "$n") { #copy file
copy ("$n","$target_dir");
}elsif(-f "$f" ){
copy ("$f","$target_dir");
}elsif (-d "$n") {#copy folder
dircopy ("$n","$target_dir/$name");
}elsif(-d "$f" ){
dircopy ("$f","$target_dir/$name");
}
}
 
}
 
sub read_file_cntent {
my ($f,$project_dir)=@_;
my $n="$project_dir$f";
my $str;
if (-f "$n") { #copy file
$str = do {
local $/ = undef;
open my $fh, "<", $n
or die "could not open $n: $!";
<$fh>;
};
 
}elsif(-f "$f" ){
$str = do {
local $/ = undef;
open my $fh, "<", $f
or die "could not open $f: $!";
<$fh>;
};
}
return $str
 
}
 
 
sub metric_conversion{
my $size=shift;
my $size_text= $size==0 ? 'Error':
1327,4 → 1565,38
return $size_text;
}
 
 
 
sub check_verilog_identifier_syntax {
my $in=shift;
my $error=0;
my $message='';
# an Identifiers must begin with an alphabetic character or the underscore character
if ($in =~ /^[0-9\$]/){
return 'an Identifier must begin with an alphabetic character or the underscore character';
}
 
# Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $ )
if ($in =~ /[^a-zA-Z0-9_\$]+/){
print "use of illegal character after\n" ;
my @w= split /([^a-zA-Z0-9_\$]+)/, $in;
return "Contain illegal character of \"$w[1]\". Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ \$ )\n";
}
 
 
# check Verilog reserved words
my @keys = ("always","and","assign","automatic","begin","buf","bufif0","bufif1","case","casex","casez","cell","cmos","config","deassign","default","defparam","design","disable","edge","else","end","endcase","endconfig","endfunction","endgenerate","endmodule","endprimitive","endspecify","endtable","endtask","event","for","force","forever","fork","function","generate","genvar","highz0","highz1","if","ifnone","incdir","include","initial","inout","input","instance","integer","join","large","liblist","library","localparam","macromodule","medium","module","nand","negedge","nmos","nor","noshowcancelled","not","notif0","notif1","or","output","parameter","pmos","posedge","primitive","pull0","pull1","pulldown","pullup","pulsestyle_onevent","pulsestyle_ondetect","remos","real","realtime","reg","release","repeat","rnmos","rpmos","rtran","rtranif0","rtranif1","scalared","showcancelled","signed","small","specify","specparam","strong0","strong1","supply0","supply1","table","task","time","tran","tranif0","tranif1","tri","tri0","tri1","triand","trior","trireg","unsigned","use","vectored","wait","wand","weak0","weak1","while","wire","wor","xnor","xor");
if( grep (/^$in$/,@keys)){
return "$in is a Verlig reserved word.";
}
return undef;
}
 
 
 
 
 
1
/lib/soc/Tutorial_lm32.SOC
3,7 → 3,7
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.5.0
## This file is part of ProNoC 1.7.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
10,203 → 10,174
################################################################################
 
$soc = bless( {
'instance_order' => [
'clk_source0',
'wishbone_bus0',
'gpo0',
'gpo1',
'ext_int0',
'timer0',
'jtag_wb0',
'lm320',
'dual_port_ram0'
],
'compile_pin' => {
'hex1_port_o' => 'HEX1',
'source_reset_in' => 'KEY',
'lm32_en_i' => '*VCC',
'source_clk_in' => 'CLOCK_50',
'hex0_port_o' => 'HEX0',
'ext_int_ext_int_i' => 'KEY'
},
'gpo1' => {},
'hdl_files' => undef,
'soc_name' => 'Tutorial_lm32',
'lm320' => {},
'ext_int0' => {},
'global_param' => {
'CORE_ID' => 0
},
'compile_pin_range_hsb' => {
'hex1_port_o' => '6',
'ext_int_ext_int_i' => '2',
'hex0_port_o' => '6'
},
'timer0' => {},
'compile_assign_type' => {
'ext_int_ext_int_i' => 'Direct',
'source_clk_in' => 'Direct',
'source_reset_in' => 'Negate(~)',
'lm32_en_i' => 'Direct'
},
'compile_pin_range_lsb' => {
'source_reset_in' => '0',
'hex1_port_o' => '0',
'hex0_port_o' => '0',
'ext_int_ext_int_i' => '1'
},
'compile_pin_pos' => {
'hex1_port_o' => [
8,
0
],
'lm32_en_i' => [
2,
0
],
'source_reset_in' => [
13,
0
],
'source_clk_in' => [
4,
0
],
'ext_int_ext_int_i' => [
13,
0
],
'hex0_port_o' => [
7,
0
]
},
'top_ip' => bless( {
'ports' => {
'lm32_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'lm320',
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'lm320',
'range' => '',
'type' => 'input'
'range' => ''
},
'hex0_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'source_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
},
'hex1_port_o' => {
'instance_name' => 'gpo1',
'intfc_name' => 'IO',
'range' => 'hex1_PORT_WIDTH-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
},
'hex0_port_o' => {
'instance_name' => 'gpo0',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO'
},
'ext_int_ext_int_i' => {
'intfc_port' => 'IO',
'type' => 'input',
'instance_name' => 'ext_int0',
'intfc_name' => 'IO',
'instance_name' => 'ext_int0',
'range' => 'ext_int_EXT_INT_NUM-1 : 0',
'type' => 'input'
'intfc_port' => 'IO'
},
'source_clk_in' => {
'intfc_port' => 'clk_i',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'hex1_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'gpo1',
'range' => 'hex1_PORT_WIDTH-1 : 0',
'type' => 'output'
}
'type' => 'input',
'intfc_port' => 'clk_i'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'lm32_en_i' => {
'intfc_port' => 'enable_i',
'instance_name' => 'lm320',
'range' => '',
'type' => 'input'
}
}
},
'IO' => {
'ports' => {
'hex0_port_o' => {
'intfc_port' => 'IO',
'instance_name' => 'gpo0',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'ext_int_ext_int_i' => {
'intfc_port' => 'IO',
'instance_name' => 'ext_int0',
'range' => 'ext_int_EXT_INT_NUM-1 : 0',
'type' => 'input'
},
'hex1_port_o' => {
'intfc_port' => 'IO',
'instance_name' => 'gpo1',
'range' => 'hex1_PORT_WIDTH-1 : 0',
'type' => 'output'
}
}
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
'instance_ids' => {
'jtag_wb0' => {
'category' => 'JTAG',
'instance' => 'jtag_wb',
'module_name' => 'vjtag_wb',
'module' => 'jtag_wb'
},
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'gpo0' => {
'parameters' => {
'hex0_PORT_WIDTH' => {
'info' => 'output port width',
'deafult' => 7,
'global_param' => 'Parameter',
'content' => '1,32,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'ports' => {
'hex0_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'type' => 'output'
}
},
'module_name' => 'gpo',
'category' => 'GPIO',
'instance' => 'hex0',
'module' => 'gpo'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
'category' => 'Bus'
},
'dual_port_ram0' => {
'module_name' => 'wb_dual_port_ram',
'category' => 'RAM',
'instance' => 'dual_port_ram0',
'module' => 'dual_port_ram'
},
'gpo1' => {
'parameters' => {
'hex1_PORT_WIDTH' => {
'info' => 'output port width',
'deafult' => 7,
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'content' => '1,32,1',
'redefine_param' => 1,
'type' => 'Spin-button'
'info' => 'output port width',
'redefine_param' => 1
}
},
'category' => 'GPIO',
'instance' => 'hex1',
'ports' => {
'hex1_port_o' => {
'intfc_port' => 'IO',
'range' => 'hex1_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'range' => 'hex1_PORT_WIDTH-1 : 0',
'type' => 'output'
}
},
'module_name' => 'gpo',
'category' => 'GPIO',
'instance' => 'hex1',
'module' => 'gpo'
'module' => 'gpo',
'module_name' => 'gpo'
},
'clk_source0' => {
'ports' => {
'source_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'source_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'clk_source',
'category' => 'Source',
'instance' => 'source',
'module' => 'clk_source'
},
'ext_int0' => {
'category' => 'Interrupt',
'ports' => {
'ext_int_ext_int_i' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'ext_int_EXT_INT_NUM-1 : 0',
'type' => 'input'
'type' => 'input',
'intfc_port' => 'IO'
}
},
'module_name' => 'ext_int',
'category' => 'Interrupt',
'instance' => 'ext_int',
'module' => 'ext_int'
'module' => 'ext_int',
'module_name' => 'ext_int'
},
'lm320' => {
'instance' => 'lm32',
'ports' => {
'lm32_en_i' => {
'intfc_port' => 'enable_i',
215,101 → 186,269
'type' => 'input'
}
},
'module_name' => 'lm32',
'category' => 'Processor',
'instance' => 'lm32',
'module' => 'lm32'
'module' => 'lm32',
'module_name' => 'lm32'
},
'jtag_wb0' => {
'parameters' => {
'jtag_wb_VJTAG_INDEX' => {
'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.',
'deafult' => 'CORE_ID',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Entry'
}
},
'module_name' => 'vjtag_wb',
'category' => 'JTAG',
'instance' => 'jtag_wb',
'module' => 'jtag_wb'
},
'dual_port_ram0' => {
'instance' => 'ram',
'category' => 'RAM',
'module' => 'dual_port_ram',
'module_name' => 'wb_dual_port_ram'
},
'clk_source0' => {
'module' => 'clk_source',
'module_name' => 'clk_source',
'category' => 'Source',
'ports' => {
'source_reset_in' => {
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'source_clk_in' => {
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i'
}
},
'instance' => 'source'
},
'timer0' => {
'module_name' => 'timer',
'instance' => 'timer',
'category' => 'Timer',
'instance' => 'timer',
'module' => 'timer'
}
}
'module' => 'timer',
'module_name' => 'timer'
},
'gpo0' => {
'module' => 'gpo',
'module_name' => 'gpo',
'ports' => {
'hex0_port_o' => {
'type' => 'output',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO'
}
},
'instance' => 'hex0',
'parameters' => {
'hex0_PORT_WIDTH' => {
'deafult' => 7,
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'output port width'
}
},
'category' => 'GPIO'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'lm32_en_i' => {
'type' => 'input',
'instance_name' => 'lm320',
'range' => '',
'intfc_port' => 'enable_i'
}
}
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'IO' => {
'ports' => {
'hex0_port_o' => {
'type' => 'output',
'instance_name' => 'gpo0',
'range' => 'hex0_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO'
},
'ext_int_ext_int_i' => {
'range' => 'ext_int_EXT_INT_NUM-1 : 0',
'instance_name' => 'ext_int0',
'type' => 'input',
'intfc_port' => 'IO'
},
'hex1_port_o' => {
'instance_name' => 'gpo1',
'range' => 'hex1_PORT_WIDTH-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
}
}
}
}, 'ip_gen' ),
'jtag_wb0' => {},
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
},
'wishbone_bus0' => {},
'dual_port_ram0' => {
'version' => 6
},
'modules' => {},
'clk_source0' => {},
'soc_name' => 'Tutorial_lm32',
'compile' => {
'modelsim_bin' => '/home/alireza/altera/modeltech/bin',
'type' => 'Modelsim',
'board' => 'DE2_115',
'quartus_bin' => '/home/alireza/altera/13.0sp1/quartus/bin'
},
'instances' => {
'clk_source0' => {
'module_name' => 'clk_source',
'instance_name' => 'source',
'parameters' => {},
'module' => 'clk_source',
'plugs' => {
'clk' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_id' => 'IO',
'connect_socket' => undef,
'name' => 'clk'
}
}
},
'reset' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'IO',
'connect_socket_num' => undef,
'connect_socket' => undef
}
}
}
},
'sockets' => {
'clk' => {
'connection_num' => 'multi connection',
'nums' => {
'0' => {
'name' => 'clk'
}
},
'value' => 1,
'type' => 'num'
},
'reset' => {
'connection_num' => 'multi connection',
'nums' => {
'0' => {
'name' => 'reset'
}
},
'value' => 1,
'type' => 'num'
}
},
'clk_source0' => {},
'category' => 'Source',
'parameters_order' => []
},
'gpo0' => {
'module_name' => 'gpo',
'instance_name' => 'hex0',
'parameters' => {
'SELw' => {
'value' => ' 4'
},
'TAGw' => {
'value' => ' 3'
},
'PORT_WIDTH' => {
'value' => 7
},
'Aw' => {
'value' => ' 2'
},
'Dw' => {
'value' => 'PORT_WIDTH'
}
},
'module' => 'gpo',
'gpo0' => {},
'instance_name' => 'hex0',
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
'connect_id' => 'clk_source0'
}
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk'
}
},
'type' => 'num'
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'base' => 2432696320,
'name' => 'wb',
'connect_socket_num' => '0',
'width' => 5,
'connect_socket_num' => '0',
'name' => 'wb',
'end' => 2432696351,
'connect_socket' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O',
'connect_socket' => 'wb_slave'
}
},
'value' => 1,
'type' => 'num'
}
},
'clk' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk'
}
},
'value' => 1,
'type' => 'num'
}
},
'parameters' => {
'PORT_WIDTH' => {
'value' => 7
},
'Aw' => {
'value' => ' 2'
},
'TAGw' => {
'value' => ' 3'
},
'SELw' => {
'value' => ' 4'
},
'Dw' => {
'value' => 'PORT_WIDTH'
}
},
'sockets' => {},
'category' => 'GPIO',
'parameters_order' => [
'PORT_WIDTH',
'Aw',
316,108 → 455,231
'TAGw',
'SELw',
'Dw'
],
'sockets' => {},
'module_name' => 'gpo',
'category' => 'GPIO',
'module' => 'gpo'
]
},
'dual_port_ram0' => {
'dual_port_ram0' => {},
'instance_name' => 'dual_port_ram0',
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'type' => 'num'
},
'clk' => {
'connection_num' => undef,
'timer0' => {
'parameters' => {
'Aw' => {
'value' => ' 3'
},
'CNTw' => {
'value' => '32 '
},
'SELw' => {
'value' => ' 4'
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => ' 32'
}
},
'module_name' => 'timer',
'instance_name' => 'timer',
'category' => 'Timer',
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw'
],
'module' => 'timer',
'timer0' => {},
'plugs' => {
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'name' => 'reset'
}
},
'value' => 1,
'type' => 'num'
},
'interrupt_peripheral' => {
'nums' => {
'0' => {
'name' => 'interrupt_peripheral',
'connect_socket_num' => '1',
'connect_id' => 'lm320',
'connect_socket' => 'interrupt_peripheral'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
},
'clk' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'connect_socket' => 'clk'
}
},
'connection_num' => undef
},
'wb_slave' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => '3',
'width' => 5,
'base' => 2516582400,
'name' => 'wb',
'connect_id' => 'wishbone_bus0',
'end' => 2516582431,
'connect_socket' => 'wb_slave',
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl'
}
},
'value' => 1,
'type' => 'num'
}
},
'sockets' => {}
},
'jtag_wb0' => {
'category' => 'JTAG',
'parameters_order' => [
'DW',
'AW',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'VJTAG_INDEX'
],
'module' => 'jtag_wb',
'sockets' => {},
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
},
'clk' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef
},
'wb_master' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => 'wb_master',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk'
'name' => 'wbm'
}
},
'type' => 'num'
'connection_num' => undef
}
},
'parameters' => {
'TAGw' => {
'value' => ' 3'
},
'wb_slave' => {
'connection_num' => undef,
'value' => 2,
'nums' => {
'1' => {
'base' => 16384,
'width' => 'WB_Aw',
'connect_socket_num' => '5',
'name' => 'wb_b',
'end' => 32767,
'connect_socket' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
},
'0' => {
'base' => 0,
'width' => 'WB_Aw',
'connect_socket_num' => '4',
'name' => 'wb_a',
'end' => 16383,
'connect_socket' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
}
},
'type' => 'num'
}
},
'DW' => {
'value' => '32'
},
'SELw' => {
'value' => ' 4'
},
'AW' => {
'value' => '32'
},
'VJTAG_INDEX' => {
'value' => 'CORE_ID'
},
'S_Aw' => {
'value' => ' 7'
},
'M_Aw' => {
'value' => ' 32'
}
},
'jtag_wb0' => {},
'module_name' => 'vjtag_wb',
'instance_name' => 'jtag_wb'
},
'dual_port_ram0' => {
'parameters' => {
'SELw' => {
'value' => 'Dw/8'
},
'PORT_B_BURST_MODE' => {
'value' => '"ENABLED" '
},
'Aw' => {
'value' => '12'
},
'Dw' => {
'value' => '32'
},
'BTEw' => {
'value' => '2'
'INITIAL_EN' => {
'value' => '"YES"'
},
'RAM_INDEX' => {
'value' => 'CORE_ID'
},
'SELw' => {
'value' => 'Dw/8'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'RAM_INDEX' => {
'value' => 'CORE_ID'
},
'Aw' => {
'value' => '12'
},
'TAGw' => {
'value' => '3'
},
'CTIw' => {
'value' => '3'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'PORT_A_BURST_MODE' => {
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'FPGA_VENDOR' => {
'value' => '"GENERIC"'
},
'PORT_B_BURST_MODE' => {
'value' => '"ENABLED"'
},
'CTIw' => {
'value' => '3'
'BTEw' => {
'value' => '2'
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
}
'PORT_A_BURST_MODE' => {
'value' => '"ENABLED"'
}
},
'module_name' => 'wb_dual_port_ram',
'instance_name' => 'ram',
'dual_port_ram0' => {},
'category' => 'RAM',
'parameters_order' => [
'Dw',
'Aw',
430,416 → 692,183
'WB_Aw',
'RAM_INDEX',
'PORT_A_BURST_MODE',
'PORT_B_BURST_MODE'
'PORT_B_BURST_MODE',
'INITIAL_EN',
'MEM_CONTENT_FILE_NAME',
'INIT_FILE_PATH'
],
'module' => 'dual_port_ram',
'sockets' => {},
'module_name' => 'wb_dual_port_ram',
'category' => 'RAM',
'module' => 'dual_port_ram'
},
'wishbone_bus0' => {
'wishbone_bus0' => {},
'instance_name' => 'bus',
'plugs' => {
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
}
},
'parameters' => {
'S' => {
'value' => 6
'plugs' => {
'reset' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset'
}
}
},
'SELw' => {
'value' => 'Dw/8'
},
'Dw' => {
'value' => '32'
},
'BTEw' => {
'value' => '2 '
},
'Aw' => {
'value' => '32'
},
'M' => {
'value' => 3
},
'TAGw' => {
'value' => '3'
},
'CTIw' => {
'value' => '3'
'clk' => {
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'connect_socket' => 'clk'
}
},
'value' => 1,
'type' => 'num'
},
'wb_slave' => {
'nums' => {
'1' => {
'connect_id' => 'wishbone_bus0',
'end' => 32767,
'connect_socket' => 'wb_slave',
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'width' => 'WB_Aw',
'connect_socket_num' => '5',
'name' => 'wb_b',
'base' => 16384
},
'0' => {
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'connect_socket' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'end' => 16383,
'name' => 'wb_a',
'base' => 0,
'connect_socket_num' => '4',
'width' => 'WB_Aw'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 2
}
},
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'sockets' => {
'wb_master' => {
'connection_num' => 'single connection',
'value' => 'M',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_master'
}
}
},
'wb_addr_map' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
}
},
'wb_slave' => {
'connection_num' => 'single connection',
'value' => 'S',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
}
}
},
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'module' => 'wishbone_bus'
},
'gpo1' => {
'instance_name' => 'hex1',
'gpo1' => {},
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'type' => 'num'
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk'
}
},
'type' => 'num'
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'base' => 2432696352,
'width' => 5,
'connect_socket_num' => '1',
'name' => 'wb',
'end' => 2432696383,
'connect_socket' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
}
},
'type' => 'num'
}
},
'parameters' => {
'PORT_WIDTH' => {
'value' => 7
},
'Aw' => {
'value' => ' 2'
},
'TAGw' => {
'value' => ' 3'
},
'SELw' => {
'value' => ' 4'
},
'Dw' => {
'value' => 'PORT_WIDTH'
}
},
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'sockets' => {},
'module_name' => 'gpo',
'category' => 'GPIO',
'module' => 'gpo'
},
}
},
'lm320' => {
'instance_name' => 'lm32',
'parameters_order' => [
'INTR_NUM',
'CFG_PL_MULTIPLY',
'CFG_PL_BARREL_SHIFT',
'CFG_SIGN_EXTEND',
'CFG_MC_DIVIDE'
],
'category' => 'Processor',
'plugs' => {
'enable' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => undef,
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'enable'
}
},
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset'
}
},
'value' => 1,
'type' => 'num'
},
'wb_master' => {
'connection_num' => undef,
'value' => 2,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'1' => {
'connect_socket' => 'wb_master',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '2',
'name' => 'dwb',
'connect_socket' => 'wb_master'
'name' => 'dwb'
},
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1',
'name' => 'iwb',
'connect_socket' => 'wb_master'
'connect_socket' => 'wb_master',
'name' => 'iwb'
}
}
},
'enable' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'enable',
'connect_socket' => undef
}
}
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
'connect_socket_num' => '0'
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
}
}
},
'sockets' => {
'interrupt_peripheral' => {
'type' => 'param',
'value' => 'INTR_NUM',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
},
'connection_num' => 'single connection'
}
},
'module' => 'lm32',
'parameters' => {
'CFG_SIGN_EXTEND' => {
'value' => '"ENABLED"'
},
'CFG_MC_DIVIDE' => {
'value' => '"DISABLED"'
},
'CFG_PL_BARREL_SHIFT' => {
'value' => '"ENABLED"'
},
'CFG_SIGN_EXTEND' => {
'value' => '"ENABLED"'
},
'CFG_PL_MULTIPLY' => {
'value' => '"ENABLED"'
},
'INTR_NUM' => {
'value' => '32'
},
'CFG_MC_DIVIDE' => {
'value' => '"DISABLED"'
}
}
},
'lm320' => {},
'parameters_order' => [
'INTR_NUM',
'CFG_PL_MULTIPLY',
'CFG_PL_BARREL_SHIFT',
'CFG_SIGN_EXTEND',
'CFG_MC_DIVIDE'
],
'sockets' => {
'interrupt_peripheral' => {
'connection_num' => 'single connection',
'value' => 'INTR_NUM',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
}
}
},
'module_name' => 'lm32',
'category' => 'Processor',
'module' => 'lm32'
'instance_name' => 'lm32',
'module_name' => 'lm32'
},
'clk_source0' => {
'instance_name' => 'source',
'plugs' => {
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'clk',
'connect_socket' => undef
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'reset',
'connect_socket' => undef
}
}
}
},
'parameters' => {},
'clk_source0' => {},
'parameters_order' => [],
'sockets' => {
'clk' => {
'connection_num' => 'multi connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk'
}
}
},
'reset' => {
'connection_num' => 'multi connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset'
}
}
}
},
'module_name' => 'clk_source',
'category' => 'Source',
'module' => 'clk_source'
},
'ext_int0' => {
'module_name' => 'ext_int',
'ext_int0' => {},
'instance_name' => 'ext_int',
'plugs' => {
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
}
}
},
'interrupt_peripheral' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'lm320',
'connect_socket_num' => '0',
'name' => 'interrupt',
'connect_socket' => 'interrupt_peripheral'
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '2',
'width' => 5,
'base' => 2650800128,
'name' => 'wb',
'connect_socket' => 'wb_slave',
'end' => 2650800159,
'connect_id' => 'wishbone_bus0',
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller'
}
}
}
},
'parameters' => {
'EXT_INT_NUM' => {
'value' => 2
},
'Dw' => {
'value' => '32'
},
'Aw' => {
'value' => '3'
},
848,216 → 877,257
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'EXT_INT_NUM' => {
'value' => 2
}
}
},
'ext_int0' => {},
'parameters_order' => [
'Dw',
'Aw',
'TAGw',
'SELw',
'EXT_INT_NUM'
],
'sockets' => {},
'module_name' => 'ext_int',
'category' => 'Interrupt',
'module' => 'ext_int'
},
'jtag_wb0' => {
'instance_name' => 'jtag_wb',
'module' => 'ext_int',
'plugs' => {
'wb_master' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0',
'name' => 'wbm',
'connect_socket' => 'wb_master'
}
}
},
'wb_slave' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => 'wb_slave',
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller',
'end' => 2650800159,
'connect_id' => 'wishbone_bus0',
'name' => 'wb',
'base' => 2650800128,
'connect_socket_num' => '2',
'width' => 5
}
},
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
}
}
},
'reset' => {
'connection_num' => undef,
'type' => 'num',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
'connect_id' => 'clk_source0'
}
}
}
},
'connection_num' => undef
},
'interrupt_peripheral' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'interrupt',
'connect_socket_num' => '0',
'connect_id' => 'lm320',
'connect_socket' => 'interrupt_peripheral'
}
},
'connection_num' => undef
}
},
'parameters' => {
'AW' => {
'value' => '32'
},
'SELw' => {
'value' => ' 4'
},
'TAGw' => {
'value' => ' 3'
},
'VJTAG_INDEX' => {
'value' => 'CORE_ID'
},
'DW' => {
'value' => '32'
},
'M_Aw' => {
'value' => ' 32'
},
'S_Aw' => {
'value' => ' 7'
}
},
'sockets' => {},
'category' => 'Interrupt',
'parameters_order' => [
'DW',
'AW',
'S_Aw',
'M_Aw',
'Dw',
'Aw',
'TAGw',
'SELw',
'VJTAG_INDEX'
],
'sockets' => {},
'module_name' => 'vjtag_wb',
'jtag_wb0' => {},
'category' => 'JTAG',
'module' => 'jtag_wb'
'EXT_INT_NUM'
]
},
'timer0' => {
'instance_name' => 'timer',
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'type' => 'num'
'gpo1' => {
'gpo1' => {},
'module_name' => 'gpo',
'instance_name' => 'hex1',
'parameters' => {
'PORT_WIDTH' => {
'value' => 7
},
'TAGw' => {
'value' => ' 3'
},
'SELw' => {
'value' => ' 4'
},
'Aw' => {
'value' => ' 2'
},
'interrupt_peripheral' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '1',
'connect_id' => 'lm320',
'name' => 'interrupt_peripheral',
'connect_socket' => 'interrupt_peripheral'
}
},
'type' => 'num'
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'Dw' => {
'value' => 'PORT_WIDTH'
}
},
'module' => 'gpo',
'sockets' => {},
'plugs' => {
'wb_slave' => {
'nums' => {
'0' => {
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O',
'connect_socket' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'end' => 2432696383,
'base' => 2432696352,
'name' => 'wb',
'connect_socket_num' => '1',
'width' => 5
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
},
'clk' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
},
'connection_num' => undef
},
'reset' => {
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk'
'connect_socket' => 'reset',
'name' => 'reset'
}
},
'type' => 'num'
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'base' => 2516582400,
'width' => 5,
'connect_socket_num' => '3',
'name' => 'wb',
'end' => 2516582431,
'connect_socket' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl'
}
},
'type' => 'num'
}
},
'parameters' => {
'Aw' => {
'value' => ' 3'
},
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => ' 4'
},
'Dw' => {
'value' => ' 32'
},
'CNTw' => {
'value' => '32 '
}
},
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw'
],
'sockets' => {},
'module_name' => 'timer',
'category' => 'Timer',
'module' => 'timer',
'timer0' => {}
}
'connection_num' => undef,
'type' => 'num',
'value' => 1
}
},
'category' => 'GPIO',
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
]
},
'wishbone_bus0' => {
'parameters' => {
'Aw' => {
'value' => '32'
},
'M' => {
'value' => 3
},
'Dw' => {
'value' => '32'
},
'CTIw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
},
'TAGw' => {
'value' => '3'
},
'BTEw' => {
'value' => '2 '
},
'S' => {
'value' => 6
}
},
'module_name' => 'wishbone_bus',
'wishbone_bus0' => {},
'instance_name' => 'bus',
'category' => 'Bus',
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'module' => 'wishbone_bus',
'plugs' => {
'clk' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef
},
'reset' => {
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
}
},
'sockets' => {
'wb_slave' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
},
'value' => 'S',
'type' => 'param'
},
'wb_master' => {
'value' => 'M',
'type' => 'param',
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'wb_master'
}
}
},
'wb_addr_map' => {
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'connection_num' => 'single connection',
'type' => 'num',
'value' => 1
}
}
}
},
'instance_order' => [
'clk_source0',
'wishbone_bus0',
'gpo0',
'gpo1',
'ext_int0',
'timer0',
'jtag_wb0',
'lm320',
'dual_port_ram0'
],
'modules' => {},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'global_param' => {
'CORE_ID' => 0
}
'gpo0' => {}
}, 'soc' );
/lib/soc/aeMB_tile.SOC
0,0 → 1,1312
#######################################################################
## File: aeMB_tile.SOC
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.7.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$soc = bless( {
'hdl_files' => undef,
'global_param' => {
'CORE_ID' => 3
},
'ni_master0' => {
'version' => 37
},
'compile_pin' => {
'ni_credit_out' => 'HEX0',
'aeMB_sys_ena_i' => '*VCC',
'ni_credit_in' => 'SW',
'led_port_o' => 'LEDR'
},
'instance_order' => [
'wishbone_bus0',
'clk_source0',
'aeMB0',
'gpo0',
'single_port_ram0',
'sim_uart0',
'ni_master0'
],
'ni0' => {
'version' => 0
},
'diagrame' => {
'show_reset' => 1,
'show_unused' => 1,
'show_clk' => 1
},
'compile_pin_range_lsb' => {
'ni_credit_in' => '0',
'ni_credit_out' => '0',
'led_port_o' => '0'
},
'compile_pin_pos' => {
'led_port_o' => [
19,
0
],
'ni_credit_out' => [
7,
0
],
'ni_credit_in' => [
17,
0
],
'aeMB_sys_ena_i' => [
2,
0
]
},
'compile_assign_type' => {
'ss_reset_in' => 'Direct',
'aeMB_sys_ena_i' => 'Direct',
'ni_credit_in' => 'Direct',
'ni_flit_in_wr' => 'Direct',
'ss_clk_in' => 'Direct',
'ni_current_x' => 'Direct',
'ni_flit_in' => 'Direct',
'ni_current_y' => 'Direct'
},
'aeMB0' => {},
'top_ip' => bless( {
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
},
'ni_current_x' => {
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_x'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni_master0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'input'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
}
}
},
'plug:enable[0]' => {
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'aeMB0',
'range' => ''
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0',
'intfc_port' => 'reset_i'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'intfc_port' => 'IO'
}
}
}
},
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'aeMB_sys_ena_i' => {
'type' => 'input',
'instance_name' => 'aeMB0',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'intfc_port' => 'enable_i'
},
'ni_credit_in' => {
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Yw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'clk_source0'
}
},
'instance_ids' => {
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'module' => 'wishbone_bus',
'category' => 'Bus',
'instance' => 'bus'
},
'sim_uart0' => {
'instance' => 'sim_uart',
'category' => 'Other',
'module_name' => 'simulator_UART',
'module' => 'sim_uart'
},
'aeMB0' => {
'category' => 'Processor',
'instance' => 'aeMB',
'ports' => {
'aeMB_sys_ena_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => ''
}
},
'module' => 'aeMB',
'module_name' => 'aeMB_top'
},
'gpo0' => {
'category' => 'GPIO',
'parameters' => {
'led_PORT_WIDTH' => {
'deafult' => ' 1',
'content' => '1,32,1',
'type' => 'Spin-button',
'redefine_param' => 1,
'info' => 'output port width',
'global_param' => 'Parameter'
}
},
'ports' => {
'led_port_o' => {
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
},
'instance' => 'led',
'module' => 'gpo',
'module_name' => 'gpo'
},
'clk_source0' => {
'module_name' => 'clk_source',
'module' => 'clk_source',
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input'
}
},
'instance' => 'ss',
'category' => 'Source'
},
'single_port_ram0' => {
'module_name' => 'wb_single_port_ram',
'module' => 'single_port_ram',
'category' => 'RAM',
'parameters' => {
'ram_Dw' => {
'redefine_param' => 1,
'info' => 'Memory data width in Bits.',
'global_param' => 'Parameter',
'type' => 'Spin-button',
'content' => '8,1024,1',
'deafult' => '32'
},
'ram_Aw' => {
'deafult' => 13,
'content' => '4,31,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Memory address width'
}
},
'instance' => 'ram'
},
'ni_master0' => {
'module' => 'ni_master',
'module_name' => 'ni_master',
'ports' => {
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output'
},
'ni_flit_in_wr' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr'
},
'ni_current_y' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_y'
},
'ni_current_x' => {
'range' => 'ni_Xw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_x'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
}
},
'instance' => 'ni',
'category' => 'NoC',
'parameters' => {
'ni_Fpay' => {
'type' => 'Fixed',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'deafult' => '32',
'content' => ''
},
'ni_DEBUG_EN' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'deafult' => '0',
'content' => ''
},
'ni_C' => {
'content' => '',
'deafult' => 0,
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_NY' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => ' 2'
},
'ni_V' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '2'
},
'ni_ROUTE_NAME' => {
'type' => 'Fixed',
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'deafult' => '"XY"',
'content' => ''
},
'ni_TOPOLOGY' => {
'content' => '',
'deafult' => '"MESH"',
'global_param' => 'Parameter',
'info' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => ' 2'
},
'ni_B' => {
'deafult' => '4',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'redefine_param' => 1
}
}
}
}
}, 'ip_gen' ),
'compile_pin_range_hsb' => {
'ni_credit_out' => '3',
'ni_credit_in' => '3',
'led_port_o' => '0'
},
'wishbone_bus0' => {},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'modules' => {},
'single_port_ram0' => {
'version' => 19
},
'instances' => {
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'sockets' => {
'wb_slave' => {
'value' => 'S',
'type' => 'param',
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
}
},
'wb_master' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'wb_master'
}
},
'value' => 'M',
'type' => 'param'
},
'wb_addr_map' => {
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'connection_num' => 'single connection',
'type' => 'num',
'value' => 1
}
},
'plugs' => {
'clk' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
}
},
'reset' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'connection_num' => undef
}
},
'category' => 'Bus',
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'module_name' => 'wishbone_bus',
'wishbone_bus0' => {},
'instance_name' => 'bus',
'parameters' => {
'S' => {
'value' => 4
},
'BTEw' => {
'value' => '2 '
},
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
},
'CTIw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'M' => {
'value' => ' 4'
},
'Aw' => {
'value' => '32'
}
}
},
'sim_uart0' => {
'description_pdf' => undef,
'parameters' => {
'TAGw' => {
'value' => ' 3'
},
'BUFFER_SIZE' => {
'value' => '100'
},
'SELw' => {
'value' => ' 4'
},
'WAIT_COUNT' => {
'value' => '1000'
},
'S_Aw' => {
'value' => ' 7'
},
'Dw' => {
'value' => ' 32'
},
'M_Aw' => {
'value' => ' 32'
}
},
'instance_name' => 'sim_uart',
'module_name' => 'simulator_UART',
'parameters_order' => [
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'BUFFER_SIZE',
'WAIT_COUNT'
],
'category' => 'Other',
'plugs' => {
'reset' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'reset'
}
},
'connection_num' => undef
},
'clk' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
}
},
'wb_slave' => {
'nums' => {
'0' => {
'end' => 2768240641,
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_slave',
'addr' => '0xa500_0000 0xa5ff_ffff Debug',
'connect_socket_num' => '0',
'width' => 1,
'base' => 2768240640,
'name' => 'wb_slave'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
}
},
'sockets' => {},
'module' => 'sim_uart'
},
'aeMB0' => {
'parameters' => {
'AEMB_MUL' => {
'value' => ' 1'
},
'AEMB_ICH' => {
'value' => ' 11'
},
'AEMB_IWB' => {
'value' => ' 32'
},
'AEMB_BSF' => {
'value' => ' 1'
},
'AEMB_IDX' => {
'value' => ' 6'
},
'AEMB_XWB' => {
'value' => ' 7'
},
'STACK_SIZE' => {
'value' => '0x400'
},
'AEMB_DWB' => {
'value' => ' 32'
},
'HEAP_SIZE' => {
'value' => '0x400'
}
},
'instance_name' => 'aeMB',
'module_name' => 'aeMB_top',
'parameters_order' => [
'AEMB_IWB',
'AEMB_DWB',
'AEMB_XWB',
'AEMB_ICH',
'AEMB_IDX',
'AEMB_BSF',
'AEMB_MUL',
'STACK_SIZE',
'HEAP_SIZE'
],
'category' => 'Processor',
'plugs' => {
'reset' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'name' => 'reset'
}
},
'connection_num' => undef
},
'interrupt_cpu' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'connect_id' => 'NC',
'connect_socket_num' => undef,
'connect_socket' => undef,
'name' => 'intrp'
}
},
'connection_num' => undef
},
'enable' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_id' => 'IO',
'connect_socket' => undef,
'name' => 'enable'
}
},
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'value' => 1,
'type' => 'num'
},
'wb_master' => {
'connection_num' => undef,
'nums' => {
'1' => {
'name' => 'dwb',
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master'
},
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '2',
'connect_socket' => 'wb_master',
'name' => 'iwb'
}
},
'value' => 2,
'type' => 'num'
}
},
'sockets' => {},
'module' => 'aeMB',
'aeMB0' => {}
},
'gpo0' => {
'sockets' => {},
'gpo0' => {},
'plugs' => {
'clk' => {
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
},
'wb_slave' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '2',
'width' => 5,
'name' => 'wb',
'base' => 2432696320,
'end' => 2432696351,
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_slave',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
}
},
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'name' => 'reset'
}
},
'value' => 1,
'type' => 'num'
}
},
'module' => 'gpo',
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'category' => 'GPIO',
'instance_name' => 'led',
'module_name' => 'gpo',
'parameters' => {
'Aw' => {
'value' => ' 2'
},
'TAGw' => {
'value' => ' 3'
},
'PORT_WIDTH' => {
'value' => ' 1'
},
'SELw' => {
'value' => ' 4'
},
'Dw' => {
'value' => 'PORT_WIDTH'
}
}
},
'clk_source0' => {
'module' => 'clk_source',
'sockets' => {
'reset' => {
'connection_num' => 'multi connection',
'nums' => {
'0' => {
'name' => 'reset'
}
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'nums' => {
'0' => {
'name' => 'clk'
}
},
'connection_num' => 'multi connection',
'type' => 'num',
'value' => 1
}
},
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_socket' => undef,
'connect_socket_num' => undef,
'connect_id' => 'IO',
'name' => 'reset'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
},
'clk' => {
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => undef,
'connect_id' => 'IO',
'connect_socket_num' => undef
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
}
},
'category' => 'Source',
'clk_source0' => {},
'parameters_order' => [],
'module_name' => 'clk_source',
'instance_name' => 'ss',
'parameters' => {}
},
'single_port_ram0' => {
'module_name' => 'wb_single_port_ram',
'instance_name' => 'ram',
'parameters' => {
'WB_Aw' => {
'value' => 'Aw+2'
},
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'CTIw' => {
'value' => '3'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'BTEw' => {
'value' => '2'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'FPGA_VENDOR' => {
'value' => '"GENERIC"'
},
'Aw' => {
'value' => 13
},
'Dw' => {
'value' => '32'
},
'JTAG_CONNECT' => {
'value' => '"DISABLED"'
},
'INITIAL_EN' => {
'value' => '"YES"'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
}
},
'single_port_ram0' => {},
'module' => 'single_port_ram',
'plugs' => {
'clk' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk'
}
},
'value' => 1,
'type' => 'num'
},
'wb_slave' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'base' => 0,
'name' => 'wb',
'connect_socket_num' => '1',
'width' => 'WB_Aw',
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'connect_socket' => 'wb_slave',
'end' => 32767,
'connect_id' => 'wishbone_bus0'
}
},
'connection_num' => undef
},
'reset' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'name' => 'reset'
}
},
'connection_num' => undef
}
},
'sockets' => {},
'category' => 'RAM',
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH'
]
},
'ni_master0' => {
'module' => 'ni_master',
'plugs' => {
'clk' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'connect_socket' => 'clk',
'name' => 'clk'
}
},
'value' => 1,
'type' => 'num'
},
'wb_slave' => {
'connection_num' => undef,
'nums' => {
'0' => {
'end' => 3087008767,
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_slave',
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'name' => 'wb_slave',
'base' => 3087007744,
'connect_socket_num' => '3',
'width' => 10
}
},
'value' => 1,
'type' => 'num'
},
'wb_master' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => 'wb_master',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0',
'name' => 'wb_send'
},
'1' => {
'name' => 'wb_receive',
'connect_socket' => 'wb_master',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1'
}
},
'value' => 2,
'type' => 'num'
},
'interrupt_peripheral' => {
'nums' => {
'0' => {
'name' => 'interrupt',
'connect_id' => 'NC',
'connect_socket_num' => undef,
'connect_socket' => undef
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
},
'reset' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset'
}
}
}
},
'sockets' => {
'ni' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'ni'
}
},
'connection_num' => 'single connection'
}
},
'category' => 'NoC',
'parameters_order' => [
'CLASS_HDR_WIDTH',
'ROUTING_HDR_WIDTH',
'DST_ADR_HDR_WIDTH',
'SRC_ADR_HDR_WIDTH',
'TOPOLOGY',
'ROUTE_NAME',
'NX',
'NY',
'C',
'V',
'B',
'Fpay',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'DEBUG_EN',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'Xw',
'Yw',
'Fw',
'CRC_EN'
],
'module_name' => 'ni_master',
'instance_name' => 'ni',
'description_pdf' => '/mpsoc/src_peripheral/ni/NI_master.pdf',
'parameters' => {
'ROUTE_NAME' => {
'value' => '"XY"'
},
'B' => {
'value' => '4'
},
'NX' => {
'value' => ' 2'
},
'CRC_EN' => {
'value' => '"NO"'
},
'Fw' => {
'value' => '2+V+Fpay'
},
'DST_ADR_HDR_WIDTH' => {
'value' => '8'
},
'COMBINATION_TYPE' => {
'value' => '"COMB_NONSPEC"'
},
'TOPOLOGY' => {
'value' => '"MESH"'
},
'MAX_TRANSACTION_WIDTH' => {
'value' => '13'
},
'V' => {
'value' => '2'
},
'MUX_TYPE' => {
'value' => '"BINARY"'
},
'TAGw' => {
'value' => '3'
},
'ROUTING_HDR_WIDTH' => {
'value' => '8'
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => '1\'b0'
},
'CONGESTION_INDEX' => {
'value' => 3
},
'ROUTE_SUBFUNC' => {
'value' => '"XY"'
},
'C' => {
'value' => 0
},
'CLASS_HDR_WIDTH' => {
'value' => '8'
},
'Yw' => {
'value' => 'log2(NY)'
},
'SSA_EN' => {
'value' => '"NO"'
},
'DEBUG_EN' => {
'value' => '0'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 0
},
'Fpay' => {
'value' => '32'
},
'NY' => {
'value' => ' 2'
},
'ROUTE_TYPE' => {
'value' => ' '
},
'VC_REALLOCATION_TYPE' => {
'value' => '"NONATOMIC"'
},
'Xw' => {
'value' => 'log2(NX)'
},
'MAX_BURST_SIZE' => {
'value' => '32'
},
'P' => {
'value' => '5'
},
'SELw' => {
'value' => '4'
},
'AVC_ATOMIC_EN' => {
'value' => 0
},
'S_Aw' => {
'value' => '8'
},
'ESCAP_VC_MASK' => {
'value' => '2\'b01'
},
'M_Aw' => {
'value' => '32'
},
'Dw' => {
'value' => '32'
},
'SRC_ADR_HDR_WIDTH' => {
'value' => '8'
}
}
}
},
'sim_uart0' => {
'version' => 6
},
'compile' => {
'board' => 'DE2_115',
'type' => 'Modelsim',
'quartus_bin' => '/home/alireza/altera/13.0sp1/quartus/bin',
'modelsim_bin' => '/home/alireza/altera/modeltech/bin'
},
'new_ni0' => {
'version' => 12
},
'gpo0' => {
'version' => 1
},
'clk_source0' => {},
'soc_name' => 'aeMB_tile'
}, 'soc' );
/lib/soc/lm32_tile.SOC
3,7 → 3,7
##
## Copyright (C) 2014-2016 Alireza Monemi
##
## This file is part of ProNoC 1.5.0
## This file is part of ProNoC 1.7.0
##
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
## MAY CAUSE UNEXPECTED BEHAIVOR.
10,180 → 10,212
################################################################################
 
$soc = bless( {
'hdl_files' => undef,
'soc_name' => 'lm32_tile',
'modules' => {},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'wishbone_bus0' => {},
'jtag_wb0' => {},
'single_port_ram0' => {
'version' => 19
},
'gpo0' => {
'version' => 1
},
'instances' => {
'single_port_ram0' => {
'single_port_ram0' => {},
'instance_name' => 'ram',
'plugs' => {
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'plugs' => {
'clk' => {
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
},
'value' => 1,
'type' => 'num'
},
'reset' => {
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
}
},
'sockets' => {
'wb_addr_map' => {
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'connection_num' => 'single connection',
'type' => 'num',
'value' => 1
},
'wb_master' => {
'nums' => {
'0' => {
'connect_socket_num' => '0',
'width' => 'WB_Aw',
'base' => 0,
'name' => 'wb',
'connect_socket' => 'wb_slave',
'end' => 16383,
'connect_id' => 'wishbone_bus0',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
'name' => 'wb_master'
}
}
}
},
'parameters' => {
'SELw' => {
'value' => 'Dw/8'
},
'Dw' => {
'value' => '32'
},
'BTEw' => {
'value' => '2'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'Aw' => {
'value' => '12'
},
'TAGw' => {
'value' => '3'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
},
'JTAG_CONNECT' => {
'value' => '"DISABLED"'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'INIT_FILE_NAME' => {
'value' => '"ram0"'
},
'connection_num' => 'single connection',
'type' => 'param',
'value' => 'M'
},
'wb_slave' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
},
'CTIw' => {
'value' => '3'
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
}
},
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE'
],
'sockets' => {},
'module_name' => 'wb_single_port_ram',
'category' => 'RAM',
'module' => 'single_port_ram'
},
'value' => 'S',
'type' => 'param'
}
},
'category' => 'Bus',
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'wishbone_bus0' => {},
'module_name' => 'wishbone_bus',
'instance_name' => 'bus',
'parameters' => {
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
},
'CTIw' => {
'value' => '3'
},
'S' => {
'value' => 3
},
'BTEw' => {
'value' => '2 '
},
'Aw' => {
'value' => '32'
},
'Dw' => {
'value' => '32'
},
'M' => {
'value' => 5
}
}
},
'lm320' => {
'instance_name' => 'cpu',
'parameters_order' => [
'INTR_NUM',
'CFG_PL_MULTIPLY',
'CFG_PL_BARREL_SHIFT',
'CFG_SIGN_EXTEND',
'CFG_MC_DIVIDE'
],
'category' => 'Processor',
'plugs' => {
'wb_master' => {
'connection_num' => undef,
'value' => 2,
'type' => 'num',
'nums' => {
'1' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1',
'name' => 'dwb',
'connect_socket' => 'wb_master'
},
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '0',
'name' => 'iwb',
'connect_socket' => 'wb_master'
}
}
},
'reset' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
}
},
'enable' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'enable',
'connect_socket' => undef
'connect_socket' => undef,
'name' => 'enable'
}
}
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
'name' => 'clk'
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
}
'wb_master' => {
'nums' => {
'0' => {
'connect_socket' => 'wb_master',
'connect_socket_num' => '0',
'connect_id' => 'wishbone_bus0',
'name' => 'iwb'
},
'1' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1',
'connect_socket' => 'wb_master',
'name' => 'dwb'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 2
}
},
'sockets' => {
'interrupt_peripheral' => {
'value' => 'INTR_NUM',
'type' => 'param',
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
}
}
},
'module' => 'lm32',
'parameters' => {
'INTR_NUM' => {
'value' => '32'
},
'CFG_PL_MULTIPLY' => {
'value' => '"ENABLED"'
},
'CFG_PL_BARREL_SHIFT' => {
'value' => '"ENABLED"'
},
190,970 → 222,977
'CFG_SIGN_EXTEND' => {
'value' => '"ENABLED"'
},
'CFG_PL_MULTIPLY' => {
'value' => '"ENABLED"'
},
'INTR_NUM' => {
'value' => '32'
},
'CFG_MC_DIVIDE' => {
'value' => '"DISABLED"'
}
},
'instance_name' => 'cpu',
'lm320' => {},
'parameters_order' => [
'INTR_NUM',
'CFG_PL_MULTIPLY',
'CFG_PL_BARREL_SHIFT',
'CFG_SIGN_EXTEND',
'CFG_MC_DIVIDE'
],
'sockets' => {
'interrupt_peripheral' => {
'connection_num' => 'single connection',
'value' => 'INTR_NUM',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
}
}
'module_name' => 'lm32'
},
'gpo0' => {
'module' => 'gpo',
'sockets' => {},
'plugs' => {
'wb_slave' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'base' => 2432696320,
'name' => 'wb',
'width' => 5,
'connect_socket_num' => '1',
'connect_id' => 'wishbone_bus0',
'end' => 2432696351,
'connect_socket' => 'wb_slave',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
}
}
},
'clk' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0'
}
},
'connection_num' => undef
},
'reset' => {
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0'
}
},
'connection_num' => undef,
'type' => 'num',
'value' => 1
}
},
'category' => 'GPIO',
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'module_name' => 'gpo',
'instance_name' => 'gpo',
'parameters' => {
'Dw' => {
'value' => 'PORT_WIDTH'
},
'Aw' => {
'value' => ' 2'
},
'TAGw' => {
'value' => ' 3'
},
'PORT_WIDTH' => {
'value' => ' 1'
},
'SELw' => {
'value' => ' 4'
}
},
'module_name' => 'lm32',
'category' => 'Processor',
'module' => 'lm32'
},
'description_pdf' => undef
},
'clk_source0' => {
'instance_name' => 'ss',
'plugs' => {
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'clk',
'connect_socket' => undef
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'reset',
'connect_socket' => undef
'connect_socket' => undef,
'name' => 'reset'
}
}
}
},
'clk' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket' => undef,
'connect_socket_num' => undef,
'connect_id' => 'IO'
}
},
'connection_num' => undef
}
},
'parameters' => {},
'clk_source0' => {},
'parameters_order' => [],
'sockets' => {
'clk' => {
'connection_num' => 'multi connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk'
}
}
},
'reset' => {
'connection_num' => 'multi connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset'
}
}
}
},
'module_name' => 'clk_source',
'category' => 'Source',
'module' => 'clk_source'
},
'gpo0' => {
'gpo0' => {},
'instance_name' => 'gpo',
'plugs' => {
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '1',
'width' => 5,
'base' => 2432696320,
'name' => 'wb',
'connect_socket' => 'wb_slave',
'end' => 2432696351,
'connect_id' => 'wishbone_bus0',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
}
}
}
},
'parameters' => {
'PORT_WIDTH' => {
'value' => ' 1'
},
'Aw' => {
'value' => ' 2'
},
'SELw' => {
'value' => ' 4'
},
'TAGw' => {
'value' => ' 3'
},
'Dw' => {
'value' => 'PORT_WIDTH'
}
},
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'sockets' => {},
'module_name' => 'gpo',
'category' => 'GPIO',
'module' => 'gpo'
},
'wishbone_bus0' => {
'wishbone_bus0' => {},
'instance_name' => 'bus',
'plugs' => {
},
'connection_num' => 'multi connection',
'type' => 'num',
'value' => 1
},
'clk' => {
'connection_num' => undef,
'type' => 'num',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
'name' => 'clk'
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
}
},
'connection_num' => 'multi connection'
}
},
'parameters' => {
'S' => {
'value' => 3
},
'SELw' => {
'value' => 'Dw/8'
},
'Dw' => {
'value' => '32'
},
'BTEw' => {
'value' => '2 '
},
'Aw' => {
'value' => '32'
},
'M' => {
'value' => 4
},
'TAGw' => {
'value' => '3'
},
'CTIw' => {
'value' => '3'
}
},
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'sockets' => {
'wb_master' => {
'connection_num' => 'single connection',
'value' => 'M',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_master'
}
}
'module' => 'clk_source',
'parameters_order' => [],
'clk_source0' => {},
'category' => 'Source',
'instance_name' => 'ss',
'module_name' => 'clk_source',
'parameters' => {}
},
'jtag_wb0' => {
'parameters' => {
'M_Aw' => {
'value' => ' 32'
},
'S_Aw' => {
'value' => ' 7'
},
'VJTAG_INDEX' => {
'value' => 'CORE_ID'
},
'wb_addr_map' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
}
},
'wb_slave' => {
'connection_num' => 'single connection',
'value' => 'S',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
}
}
},
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'module' => 'wishbone_bus'
},
'ni0' => {
'instance_name' => 'ni',
'plugs' => {
'wb_master' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '2',
'name' => 'wb_master',
'connect_socket' => 'wb_master'
}
}
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket' => 'clk'
}
}
},
'interrupt_peripheral' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'lm320',
'connect_socket_num' => '0',
'name' => 'int_peripheral',
'connect_socket' => 'interrupt_peripheral'
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
},
'wb_slave' => {
'DW' => {
'value' => '32'
},
'SELw' => {
'value' => ' 4'
},
'AW' => {
'value' => '32'
},
'TAGw' => {
'value' => ' 3'
}
},
'jtag_wb0' => {},
'module_name' => 'vjtag_wb',
'instance_name' => 'jtag_wb',
'category' => 'JTAG',
'parameters_order' => [
'DW',
'AW',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'VJTAG_INDEX'
],
'module' => 'jtag_wb',
'sockets' => {},
'plugs' => {
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '2',
'width' => 9,
'base' => 3087007744,
'name' => 'wb_slave',
'connect_socket' => 'wb_slave',
'end' => 3087008255,
'connect_id' => 'wishbone_bus0',
'addr' => '0xb800_0000 0xbfff_ffff custom devices'
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'clk'
}
}
}
},
'parameters' => {
'Dw' => {
'value' => ' 32'
},
'DEBUG_EN' => {
'value' => '0'
},
'NY' => {
'value' => ' 2'
},
'NX' => {
'value' => ' 2'
},
'V' => {
'value' => ' 4'
},
'CONGESTION_INDEX' => {
'value' => '3'
},
'COMB_PCK_SIZE_W' => {
'value' => '12'
},
'Fw' => {
'value' => '2+V+Fpay'
},
'TAGw' => {
'value' => '3'
},
'COMB_MEM_PTR_W' => {
'value' => '20'
},
'M_Aw' => {
'value' => '32'
},
'ROUTE_NAME' => {
'value' => '"XY"'
},
'Xw ' => {
'value' => 'log2(NX)'
},
'Fpay' => {
'value' => ' 32'
},
'ROUTE_TYPE' => {
'value' => '"DETERMINISTIC"'
},
'SELw' => {
'value' => '4 '
},
'P' => {
'value' => ' 5'
},
'B' => {
'value' => ' 4'
},
'S_Aw' => {
'value' => '7'
},
'TOPOLOGY' => {
'value' => '"MESH"'
},
'Xw' => {
'value' => 'log2(NX)'
},
'Yw' => {
'value' => 'log2(NY)'
},
'SSA_EN' => {
'value' => '"NO"'
},
'Xwj' => {
'value' => 'fvf'
}
},
'parameters_order' => [
'V',
'B',
'NX',
'NY',
'Fpay',
'TOPOLOGY',
'ROUTE_NAME',
'DEBUG_EN',
'COMB_MEM_PTR_W',
'COMB_PCK_SIZE_W',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'Yw',
'Fw',
'Xw'
],
'sockets' => {
'ni' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'ni'
}
}
}
},
'ni0' => {},
'module_name' => 'ni',
'category' => 'NoC',
'module' => 'ni'
},
'jtag_wb0' => {
'instance_name' => 'jtag_wb0',
'plugs' => {
'value' => 1,
'type' => 'num'
},
'wb_master' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0',
'name' => 'wbm',
'connect_socket' => 'wb_master'
'connect_socket' => 'wb_master',
'name' => 'wbm'
}
},
'type' => 'num'
'connection_num' => undef,
'type' => 'num',
'value' => 1
},
'reset' => {
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'value' => 1
}
}
},
'ni_master0' => {
'module' => 'ni_master',
'sockets' => {
'ni' => {
'nums' => {
'0' => {
'name' => 'ni'
}
},
'connection_num' => 'single connection',
'type' => 'num',
'value' => 1
}
},
'plugs' => {
'interrupt_peripheral' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'lm320',
'connect_socket' => 'interrupt_peripheral',
'name' => 'interrupt'
}
}
},
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'value' => 1,
'type' => 'num'
},
'wb_slave' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'end' => 3087008767,
'connect_id' => 'wishbone_bus0',
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'connect_socket' => 'wb_slave',
'base' => 3087007744,
'name' => 'wb_slave',
'width' => 10,
'connect_socket_num' => '2'
}
},
'connection_num' => undef
},
'wb_master' => {
'connection_num' => undef,
'nums' => {
'1' => {
'connect_socket' => 'wb_master',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '4',
'name' => 'wb_receive'
},
'0' => {
'name' => 'wb_send',
'connect_socket_num' => '2',
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master'
}
},
'value' => 2,
'type' => 'num'
},
'clk' => {
'value' => 1,
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk'
}
},
'type' => 'num'
}
}
},
'category' => 'NoC',
'parameters_order' => [
'CLASS_HDR_WIDTH',
'ROUTING_HDR_WIDTH',
'DST_ADR_HDR_WIDTH',
'SRC_ADR_HDR_WIDTH',
'TOPOLOGY',
'ROUTE_NAME',
'NX',
'NY',
'C',
'V',
'B',
'Fpay',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'DEBUG_EN',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'Xw',
'Yw',
'Fw',
'CRC_EN'
],
'module_name' => 'ni_master',
'instance_name' => 'ni',
'parameters' => {
'AW' => {
'value' => '32'
},
'TAGw' => {
'value' => ' 3'
'value' => '3'
},
'SELw' => {
'value' => ' 4'
'value' => '4'
},
'VJTAG_INDEX' => {
'value' => 'CORE_ID'
},
'DW' => {
'S_Aw' => {
'value' => '8'
},
'ROUTING_HDR_WIDTH' => {
'value' => '8'
},
'M_Aw' => {
'value' => '32'
},
'Dw' => {
'value' => '32'
},
'S_Aw' => {
'value' => ' 7'
'SRC_ADR_HDR_WIDTH' => {
'value' => '8'
},
'Yw' => {
'value' => 'log2(NY)'
},
'CLASS_HDR_WIDTH' => {
'value' => '8'
},
'C' => {
'value' => ' 4'
},
'NX' => {
'value' => ' 4'
},
'Fpay' => {
'value' => ' 32'
},
'M_Aw' => {
'value' => ' 32'
}
'NY' => {
'value' => ' 4'
},
'ROUTE_NAME' => {
'value' => '"XY" '
},
'DEBUG_EN' => {
'value' => ' 1'
},
'B' => {
'value' => ' 4'
},
'P' => {
'value' => '5'
},
'MAX_TRANSACTION_WIDTH' => {
'value' => '13'
},
'V' => {
'value' => '4'
},
'ROUTE_TYPE' => {
'value' => ' '
},
'CRC_EN' => {
'value' => '"NO"'
},
'Fw' => {
'value' => '2+V+Fpay'
},
'DST_ADR_HDR_WIDTH' => {
'value' => '8'
},
'MAX_BURST_SIZE' => {
'value' => '16'
},
'Xw' => {
'value' => 'log2(NX)'
},
'TOPOLOGY' => {
'value' => '"MESH"'
}
},
'parameters_order' => [
'DW',
'AW',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'VJTAG_INDEX'
],
'sockets' => {},
'module_name' => 'vjtag_wb',
'jtag_wb0' => {},
'category' => 'JTAG',
'module' => 'jtag_wb'
}
'description_pdf' => '/mpsoc/src_peripheral/ni/NI_master.pdf'
},
'single_port_ram0' => {
'description_pdf' => undef,
'parameters' => {
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'CTIw' => {
'value' => '3'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
},
'BTEw' => {
'value' => '2'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'FPGA_VENDOR' => {
'value' => '"GENERIC"'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'Aw' => {
'value' => '12'
},
'INITIAL_EN' => {
'value' => '"NO"'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
},
'Dw' => {
'value' => '32'
},
'JTAG_CONNECT' => {
'value' => '"DISABLED"'
}
},
'instance_name' => 'ram',
'module_name' => 'wb_single_port_ram',
'parameters_order' => [
'Dw',
'Aw',
'BYTE_WR_EN',
'FPGA_VENDOR',
'JTAG_CONNECT',
'JTAG_INDEX',
'TAGw',
'SELw',
'CTIw',
'BTEw',
'WB_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH'
],
'category' => 'RAM',
'plugs' => {
'clk' => {
'type' => 'num',
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
},
'connection_num' => undef
},
'wb_slave' => {
'connection_num' => undef,
'nums' => {
'0' => {
'end' => 16383,
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_slave',
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'width' => 'WB_Aw',
'connect_socket_num' => '0',
'name' => 'wb',
'base' => 0
}
},
'value' => 1,
'type' => 'num'
},
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset'
}
},
'value' => 1,
'type' => 'num'
}
},
'sockets' => {},
'module' => 'single_port_ram'
}
},
'soc_name' => 'lm32_tile',
'clk_source0' => {},
'lm320' => {},
'global_param' => {
'CORE_ID' => 0
},
'hdl_files' => undef,
'instance_order' => [
'lm320',
'clk_source0',
'wishbone_bus0',
'jtag_wb0',
'single_port_ram0',
'gpo0',
'ni_master0'
],
'ni0' => {},
'ni_master0' => {
'version' => 37
},
'top_ip' => bless( {
'instance_ids' => {
'lm320' => {
'module_name' => 'lm32',
'module' => 'lm32',
'ports' => {
'cpu_en_i' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i'
}
},
'instance' => 'cpu',
'category' => 'Processor'
},
'gpo0' => {
'module' => 'gpo',
'module_name' => 'gpo',
'instance' => 'gpo',
'ports' => {
'gpo_port_o' => {
'range' => 'gpo_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO'
}
},
'category' => 'GPIO',
'parameters' => {
'gpo_PORT_WIDTH' => {
'deafult' => ' 1',
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'info' => 'output port width',
'redefine_param' => 1
}
}
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'instance' => 'bus'
},
'single_port_ram0' => {
'module' => 'single_port_ram',
'module_name' => 'wb_single_port_ram',
'instance' => 'ram',
'parameters' => {
'ram_Aw' => {
'content' => '4,31,1',
'deafult' => '12',
'global_param' => 'Parameter',
'info' => 'Memory address width',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Dw' => {
'content' => '8,1024,1',
'deafult' => '32',
'info' => 'Memory data width in Bits.',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button'
}
},
'category' => 'RAM'
},
'ni_master0' => {
'parameters' => {
'ni_NY' => {
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter',
'deafult' => ' 4',
'content' => ''
},
'ni_C' => {
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter',
'deafult' => ' 4',
'content' => ''
},
'ni_DEBUG_EN' => {
'deafult' => ' 1',
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter'
},
'ni_Fpay' => {
'content' => '',
'deafult' => ' 32',
'global_param' => 'Parameter',
'info' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'deafult' => ' 4',
'content' => ''
},
'ni_TOPOLOGY' => {
'info' => 'Parameter',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'deafult' => '"MESH"'
},
'ni_V' => {
'deafult' => '4',
'content' => '',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter'
},
'ni_ROUTE_NAME' => {
'content' => '',
'deafult' => '"XY" ',
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_B' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'info' => 'Parameter',
'deafult' => ' 4',
'content' => ''
}
},
'category' => 'NoC',
'ports' => {
'ni_current_x' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_x'
},
'ni_flit_in' => {
'type' => 'input',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in'
},
'ni_current_y' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_y'
},
'ni_flit_in_wr' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
}
},
'instance' => 'ni',
'module' => 'ni_master',
'module_name' => 'ni_master'
},
'jtag_wb0' => {
'module_name' => 'vjtag_wb',
'module' => 'jtag_wb',
'category' => 'JTAG',
'instance' => 'jtag_wb'
},
'clk_source0' => {
'instance' => 'ss',
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]'
},
'ss_reset_in' => {
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i'
}
},
'category' => 'Source',
'module' => 'clk_source',
'module_name' => 'clk_source'
}
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
'type' => 'input',
'intfc_port' => 'clk_i'
},
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'instance_name' => 'lm320',
'range' => '',
'intfc_port' => 'enable_i'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'ni_current_y' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_y'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_out'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
'instance_name' => 'ni_master0'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
'range' => '',
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'gpo_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'intfc_port' => 'IO',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'instance_name' => 'gpo0',
'type' => 'output'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
'type' => 'input',
'intfc_port' => 'reset_i'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'lm320',
'range' => '',
'type' => 'input'
'intfc_port' => 'enable_i'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'instance_name' => 'ni0',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'instance_name' => 'ni_master0'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'instance_name' => 'ni0',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
'ni_credit_out' => {
'type' => 'output',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_out'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'instance_name' => 'ni0',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni0',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'instance_name' => 'ni0',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'instance_name' => 'ni0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_in'
},
'ni_current_x' => {
'type' => 'input',
'range' => 'ni_Xw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_x'
},
'ni_current_y' => {
'type' => 'input',
'range' => 'ni_Yw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_y'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => ''
}
}
},
'IO' => {
'ports' => {
'gpo_port_o' => {
'intfc_port' => 'IO',
'instance_name' => 'gpo0',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input'
}
}
}
},
'instance_ids' => {
'single_port_ram0' => {
'parameters' => {
'ram_Dw' => {
'info' => 'Memory data width in Bits.',
'deafult' => '32',
'global_param' => 'Parameter',
'content' => '8,1024,1',
'redefine_param' => 1,
'type' => 'Spin-button'
},
'ram_Aw' => {
'info' => 'Memory address width',
'deafult' => '12',
'global_param' => 'Parameter',
'content' => '4,31,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'module_name' => 'wb_single_port_ram',
'category' => 'RAM',
'instance' => 'ram',
'module' => 'single_port_ram'
},
'lm320' => {
'ports' => {
'cpu_en_i' => {
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'lm32',
'category' => 'Processor',
'instance' => 'cpu',
'module' => 'lm32'
},
'clk_source0' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
}
},
'module_name' => 'clk_source',
'category' => 'Source',
'instance' => 'ss',
'module' => 'clk_source'
},
'gpo0' => {
'parameters' => {
'gpo_PORT_WIDTH' => {
'info' => 'output port width',
'deafult' => ' 1',
'global_param' => 'Parameter',
'content' => '1,32,1',
'redefine_param' => 1,
'type' => 'Spin-button'
}
},
'ports' => {
'gpo_port_o' => {
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output'
}
},
'module_name' => 'gpo',
'category' => 'GPIO',
'instance' => 'gpo',
'module' => 'gpo'
},
'wishbone_bus0' => {
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'ni0' => {
'parameters' => {
'ni_TOPOLOGY' => {
'info' => undef,
'deafult' => '"MESH"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_Fpay' => {
'info' => undef,
'deafult' => ' 32',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NX' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_NY' => {
'info' => undef,
'deafult' => ' 2',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_B' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_V' => {
'info' => '',
'deafult' => ' 4',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'info' => undef,
'deafult' => '0',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'info' => undef,
'deafult' => '"XY"',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed'
}
},
'ports' => {
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'output'
},
'ni_current_x' => {
'intfc_port' => 'current_x',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Xw-1 : 0',
'type' => 'input'
},
'ni_current_y' => {
'intfc_port' => 'current_y',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Yw-1 : 0',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1: 0',
'type' => 'output'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input'
}
},
'module_name' => 'ni',
'category' => 'NoC',
'instance' => 'ni',
'module' => 'ni'
},
'jtag_wb0' => {
'parameters' => {
'jtag_wb0_VJTAG_INDEX' => {
'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.',
'deafult' => 'CORE_ID',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Entry'
}
},
'module_name' => 'vjtag_wb',
'category' => 'JTAG',
'instance' => 'jtag_wb0',
'module' => 'jtag_wb'
}
}
}, 'ip_gen' ),
'instance_order' => [
'lm320',
'single_port_ram0',
'gpo0',
'clk_source0',
'wishbone_bus0',
'ni0',
'jtag_wb0'
],
'modules' => {},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'global_param' => {
'CORE_ID' => 3
}
'IO' => {
'ports' => {
'gpo_port_o' => {
'instance_name' => 'gpo0',
'range' => 'gpo_PORT_WIDTH-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
}
}
}
}, 'ip_gen' )
}, 'soc' );

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.