OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

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  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui
    from Rev 39 to Rev 41
    ↔ Reverse comparison
  •

Rev 39 → Rev 41

/ProNoC.pl
26,19 → 26,52
use File::Basename;
 
 
our $VERSION = '1.8.0';
our $VERSION = '1.8.1';
 
sub main{
# check if envirement variables are defined
my $project_dir = get_project_dir(); #mpsoc dir addr
my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
 
if (-f $paths_file){#} && defined $ENV{PRONOC_WORK} ) {
my $paths= do $paths_file;
main_window();
}
else{
setting(1);
}
}
 
sub set_path_env{
my $project_dir = get_project_dir(); #mpsoc dir addr
my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
my $paths= do $paths_file;
 
my $pronoc_work = $paths->object_get_attribute("PATH","PRONOC_WORK");
my $quartus = $paths->object_get_attribute("PATH","QUARTUS_BIN");
my $modelsim = $paths->object_get_attribute("PATH","MODELSIM_BIN");
 
my($width,$hight)=max_win_size();
set_defualt_font_size();
$ENV{'PRONOC_WORK'}= $pronoc_work if( defined $pronoc_work);
$ENV{'QUARTUS_BIN'}= $quartus if( defined $quartus);
$ENV{'MODELSIM_BIN'}= $modelsim if( defined $modelsim);
}
 
 
# check if envirement variables are defined
if ( !defined $ENV{PRONOC_WORK} || !defined $ENV{QUARTUS_BIN}) {
 
sub main_window{
set_path_env();
 
 
my($width,$hight)=max_win_size();
set_defualt_font_size();
 
 
 
 
if ( !defined $ENV{PRONOC_WORK} ) {
my $message;
if ( !defined $ENV{PRONOC_WORK}) {
my $dir = Cwd::getcwd();
50,9 → 83,9
 
 
$message= $message."Warning: QUARTUS_BIN environment variable has not been set. It is required only for working with NoC emulator." if(!defined $ENV{QUARTUS_BIN});
#$message= $message."Warning: QUARTUS_BIN environment variable has not been set. It is required only for working with NoC emulator." if(!defined $ENV{QUARTUS_BIN});
$message= $message."\n\nPlease add aformentioned variables to ~\.bashrc file e.g: export PRONOC_WORK=[path_to]/mpsoc_work.";
#$message= $message."\n\nPlease add aformentioned variables to ~\.bashrc file e.g: export PRONOC_WORK=[path_to]/mpsoc_work.";
message_dialog("$message");
}
71,6 → 104,7
 
my @menu_items = (
[ "/_File", undef, undef, 0, "<Branch>" ],
[ "/File/_Setting", "<control>O", sub { setting(0); }, 0, undef ],
[ "/File/_Quit", "<control>Q", sub { Gtk2->main_quit }, 0, "<StockItem>", 'gtk-quit' ],
[ "/_View", undef, undef, 0, "<Branch>" ],
[ "/_View/_ProNoC System Generator", undef, sub{ open_page($notebook,$noteref,$table,'Generator'); } , 0, undef ],
227,8 → 261,92
 
}
 
sub setting{
my $reset=shift;
my $project_dir = get_project_dir(); #mpsoc dir addr
my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
 
__PACKAGE__->mk_accessors(qw{
PRONOC_WORK
});
my $self;
if (-f $paths_file ){
$self= do $paths_file;
}else{
$self = __PACKAGE__->new();
}
my $table=def_table(10,10,FALSE);
my $set_win=def_popwin_size(40,80,"Configuration setting",'percent');
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
$scrolled_win->set_policy( "automatic", "automatic" );
$scrolled_win->add_with_viewport($table);
my $row=0; my $col=0;
#title
my $title=gen_label_in_center("setting");
$table->attach ($title , 0, 10, $row, $row+1,'expand','shrink',2,2); $row++;
my $separator = Gtk2::HSeparator->new;
$table->attach ($separator , 0, 10 , $row, $row+1,'fill','fill',2,2); $row++;
 
my @paths = (
{ label=>"PRONOC_WORK", param_name=>"PRONOC_WORK", type=>"DIR_path", default_val=>"$project_dir/mpsoc_work", content=>undef, info=>"Define the working directory where the projects' files will be created", param_parent=>'PATH',ref_delay=>undef },
{ label=>"QUARTUS_BIN", param_name=>"QUARTUS_BIN", type=>"DIR_path", default_val=>undef, content=>undef, info=>"Define the path to QuartusII compiler bin directory. Setting of this variable is optional and is needed if you are going to use Altera FPGAs for implementation or emulation", param_parent=>'PATH',ref_delay=>undef },
{ label=>"MODELSIM_BIN", param_name=>"MODELSIM_BIN", type=>"DIR_path", default_val=>undef, content=>undef, info=>"Define the path to Modelsim simulator bin directory. Setting of this variable is optional and is needed if you have installed Modelsim simulator and you want ProNoC to auto-generate the
simulation models using Modelsim software", param_parent=>'PATH',ref_delay=>undef },
);
 
 
foreach my $d (@paths) {
#$mpsoc,$name,$param, $default,$type,$content,$info, $table,$row,$column,$show,$attribut1,$ref_delay,$new_status,$loc
($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},undef,"vertical");
}
 
 
my $ok = def_image_button('icons/select.png','OK');
my $mtable = def_table(10, 1, TRUE);
 
$mtable->attach_defaults($scrolled_win,0,1,0,9);
$mtable-> attach ($ok , 0, 1, 9, 10,'expand','shrink',2,2);
$set_win->add ($mtable);
$set_win->show_all();
my $old_pronoc_work = $self->object_get_attribute("PATH","PRONOC_WORK");
my $old_quartus = $self->object_get_attribute("PATH","QUARTUS_BIN");
my $old_modelsim = $self->object_get_attribute("PATH","MODELSIM_BIN");
$ok->signal_connect("clicked"=> sub{
#save setting
open(FILE, ">$paths_file") || die "Can not open: $!";
print FILE perl_file_header("Paths");
print FILE Data::Dumper->Dump([\%$self],['setting']);
close(FILE) || die "Error closing file: $!";
my $pronoc_work = $self->object_get_attribute("PATH","PRONOC_WORK");
my $quartus = $self->object_get_attribute("PATH","QUARTUS_BIN");
my $modelsim = $self->object_get_attribute("PATH","MODELSIM_BIN");
make_undef_as_string(\$old_pronoc_work,\$old_quartus,\$old_modelsim,\$pronoc_work,\$quartus,\$modelsim);
append_text_to_file ("$ENV{HOME}/.bashrc", "\nexport PRONOC_WORK=$pronoc_work\n") if(($old_pronoc_work ne $pronoc_work) || !defined $ENV{PRONOC_WORK}) ;
append_text_to_file ("$ENV{HOME}/.bashrc", "export QUARTUS_BIN=$quartus\n") if($old_quartus ne $quartus) ;
append_text_to_file ("$ENV{HOME}/.bashrc", "export MODELSIM_BIN=$modelsim\n") if($old_modelsim ne $modelsim) ;
set_path_env();
if(($old_pronoc_work ne $pronoc_work) || $old_quartus ne $quartus ||$old_modelsim ne $modelsim){
 
}
 
my ($file_path,$text)=@_;
$set_win->destroy;
main_window() if($reset);
 
});
}
 
sub generate_main_notebook {
my $mode =shift;
/lib/perl/emulate_ram_gen.pl
30,8 → 30,8
use constant PROBE_ST => 0x2;
use constant SOURCE_ST => 0x1;
use constant BYPAS_ST => 0x0;
use constant RAM_BIN_FILE => "$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin";
use constant RAM_SIM_FILE => "$ENV{'PRONOC_WORK'}/emulate/ram";
#use constant RAM_BIN_FILE => "$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin";
#use constant RAM_SIM_FILE => "$ENV{'PRONOC_WORK'}/emulate/ram";
 
 
230,7 → 230,7
my $ram;
if(SIM_RAM_GEN){
my $ext= sprintf("%02u.txt",$num);
open( $ram, '>', RAM_SIM_FILE.$ext) || die "Can not create: \">lib/emulate/emulate_ram.bin\" $!";
open( $ram, '>', "$ENV{'PRONOC_WORK'}/emulate/ram".$ext) || die "Can not create: \"$ENV{'PRONOC_WORK'}/emulate/ram.$ext\" $!";
}
for ($line_num= 0; $line_num<RAM_SIZE; $line_num++ ) {
my ($value_s,$value_l)=gen_synthetic_traffic_ram_line ($emulate, $x, $y, $sample, $ratio ,$line_num,$rnd);
287,8 → 287,8
if ( $xn <2 || $xn >16 ){ add_info($info,"programe_pck_gens:invalid X value: ($xn). should be between 2 and 16 \n"); help(); return 0;}
if ( $yn <2 || $yn >16 ){ add_info($info,"programe_pck_gens:invalid Y value:($yn). should be between 2 and 16 \n"); help(); return 0;}
#open file pointer
#open(my $file, RAM_BIN_FILE) || die "Can not create: \">lib/emulate/emulate_ram.bin\" $!";
open(my $file, '>', RAM_BIN_FILE) || die "Can not create: \">lib/emulate/emulate_ram.bin\" $!";
#open(my $file, '>', RAM_BIN_FILE) || die "Can not create: \">lib/emulate/emulate_ram.bin\" $!";
open(my $file, '>', "$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin") || die "Can not create: \"$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin\" $!";
#generate each node ram data
for (my $y=0; $y<$yn; $y=$y+1){
323,7 → 323,7
 
#programe packet generators rams
my $cmd= "sh $jtag_intfc \"-n ".JTAG_RAM_INDEX." -w 8 -i ".RAM_BIN_FILE." -c\" ";
my $cmd= "sh $jtag_intfc \"-n ".JTAG_RAM_INDEX." -w 8 -i $ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin -c\" ";
#my ($result,$exit) = run_cmd_in_back_ground_get_stdout($cmd);
return 0 if(run_cmd_update_info ($cmd,$info));
/lib/perl/mpsoc_gen.pl
1782,7 → 1782,7
 
$make -> signal_connect("clicked" => sub{
$app->do_save();
apend_to_textview($tview,' ');
append_to_textview($tview,' ');
run_make_file($sw,$tview);
 
});
/lib/perl/temp.pl
3,7 → 3,90
use strict;
use warnings;
use Gtk2;
use Time::HiRes qw( usleep ualarm gettimeofday tv_interval nanosleep clock_gettime clock_getres clock_nanosleep clock stat );
use Proc::Background;
use IO::CaptureOutput qw(capture qxx qxy);
 
my $scalar = "a1b.2";
$scalar =~ s/\D//g;
print "\n $scalar \n";
$ENV{TEMP}="ALIREZA";
 
 
my $cmd = "xterm -e sh t.sh";
my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout( $cmd);
 
 
 
##########
# run external commands
##########
 
sub run_cmd_in_back_ground
{
my $command = shift;
#print "\t$command\n";
### Start running the Background Job:
my $proc = Proc::Background->new($command);
my $PID = $proc->pid;
my $start_time = $proc->start_time;
my $alive = $proc->alive;
 
### While $alive is NOT '0', then keep checking till it is...
# *When $alive is '0', it has finished executing.
while($alive ne 0)
{
$alive = $proc->alive;
 
# This while loop will cause Gtk2 to conti processing events, if
# there are events pending... *which there are...
while (Gtk2->events_pending) {
Gtk2->main_iteration;
}
Gtk2::Gdk->flush;
 
usleep(1000);
}
my $end_time = $proc->end_time;
# print "*Command Completed at $end_time, with PID = $PID\n\n";
 
# Since the while loop has exited, the BG job has finished running:
# so close the pop-up window...
# $popup_window->hide;
 
# Get the RETCODE from the Background Job using the 'wait' method
my $retcode = $proc->wait;
$retcode /= 256;
 
print "\t*RETCODE == $retcode\n\n";
Gtk2::Gdk->flush;
### Check if the RETCODE returned with an Error:
if ($retcode ne 0) {
print "Error: The Background Job ($command) returned with an Error...!\n";
return 1;
} else {
#print "Success: The Background Job Completed Successfully...!\n";
return 0;
}
}
 
 
 
sub run_cmd_in_back_ground_get_stdout
{
my $cmd=shift;
my $exit;
my ($stdout, $stderr);
capture { $exit=run_cmd_in_back_ground($cmd) } \$stdout, \$stderr;
return ($stdout,$exit,$stderr);
}
 
 
 
 
 
 
 
#system ("sh t.sh");
/lib/perl/widget.pl
953,7 → 953,7
 
sub append_text_to_file {
my ($file_path,$text)=@_;
open(my $fd, ">>$file_path");
open(my $fd, ">>$file_path") or die "could not open $file_path: $!";
print $fd $text;
close $fd;
}
1264,10 → 1264,16
 
}
 
sub get_project_dir{ #mpsoc directory address
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../");
return $project_dir;
}
 
 
sub remove_project_dir_from_addr{
my $file=shift;
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../"); #mpsoc directory address
my $file=shift;
my $project_dir = get_project_dir();
$file =~ s/$project_dir//;
return $file;
}
1274,8 → 1280,7
 
sub add_project_dir_to_addr{
my $file=shift;
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/../../"); #mpsoc directory address
my $project_dir = get_project_dir();
return $file if(-f $file );
return "$project_dir/$file";
1914,4 → 1919,12
}
 
 
sub make_undef_as_string {
foreach my $p (@_){
$$p= 'undef' if (! defined $$p);
}
}
 
 
1
/lib/soc/tutorial.SOC
10,112 → 10,161
################################################################################
 
$soc = bless( {
'instance_order' => [
'clk_source0',
'wishbone_bus0',
'gpo0',
'mor1kx0',
'timer0',
'single_port_ram0',
'jtag_uart0'
],
'compile_pin_range_hsb' => {
'led_port_o' => '3'
},
'clk_source0' => {
'version' => 0
},
'compile_pin_pos' => {
'source_clk_in' => [
4,
0
],
'source_reset_in' => [
6,
0
],
'led_port_o' => [
3,
0
],
'cpu_cpu_en' => [
2,
0
],
'led_port_o' => [
3,
0
]
'source_reset_in' => [
6,
0
]
},
'compile_pin_range_lsb' => {
'source_reset_in' => '0',
'led_port_o' => '0'
},
'compile_pin' => {
'cpu_cpu_en' => '*VCC',
'source_reset_in' => 'KEY',
'source_clk_in' => 'FPGA_CLK1_50',
'led_port_o' => 'LED'
},
'global_param' => {
'CORE_ID' => 0
},
'instances' => {
'gpo0' => {
'category' => 'GPIO',
'module_name' => 'gpo',
'instance_name' => 'led',
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'parameters' => {
'Aw' => {
'value' => ' 2'
},
'Dw' => {
'value' => 'PORT_WIDTH'
},
'PORT_WIDTH' => {
'value' => 4
},
'TAGw' => {
'value' => ' 3'
},
'SELw' => {
'value' => ' 4'
}
'mor1kx0' => {
'sockets' => {
'interrupt_peripheral' => {
'type' => 'param',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
},
'connection_num' => 'single connection',
'value' => 'IRQ_NUM'
}
},
'sockets' => {},
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'name' => 'reset'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'clk' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_socket_num' => '0'
}
},
'value' => 1,
'connection_num' => undef
},
'wb_slave' => {
'type' => 'num',
'category' => 'Processor',
'description_pdf' => undef,
'plugs' => {
'clk' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
}
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'name' => 'wb',
'connect_socket' => 'wb_slave',
'connect_id' => 'wishbone_bus0',
'width' => 5,
'end' => 2432696351,
'base' => 2432696320,
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'name' => 'reset'
}
},
'value' => 1,
'connection_num' => undef
}
},
'module' => 'gpo',
'description_pdf' => undef
},
'type' => 'num'
},
'wb_master' => {
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'name' => 'iwb',
'connect_socket_num' => '0',
'connect_socket' => 'wb_master'
},
'1' => {
'connect_socket' => 'wb_master',
'connect_socket_num' => '1',
'name' => 'dwb',
'connect_id' => 'wishbone_bus0'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 2
},
'enable' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'enable',
'connect_socket_num' => undef,
'connect_socket' => undef
}
}
}
},
'module' => 'mor1kx',
'instance_name' => 'cpu',
'parameters' => {
'IRQ_NUM' => {
'value' => '32'
},
'OPTION_OPERAND_WIDTH' => {
'value' => '32'
}
},
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM'
],
'module_name' => 'mor1k'
},
'jtag_uart0' => {
'parameters_order' => [
'FPGA_VENDOR',
'SIM_BUFFER_SIZE',
'SIM_WAIT_COUNT'
],
'module_name' => 'jtag_uart_wb',
'category' => 'Communication',
'instance_name' => 'uart',
'module' => 'jtag_uart',
'plugs' => {
'interrupt_peripheral' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_socket' => undef,
'connect_id' => 'NC',
'name' => 'interrupt_peripheral'
}
},
'value' => 1,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'value' => 1,
122,9 → 171,9
'nums' => {
'0' => {
'connect_socket_num' => '0',
'name' => 'reset',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0'
'connect_id' => 'clk_source0',
'name' => 'reset'
}
},
'type' => 'num'
132,145 → 181,207
'clk' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket' => 'clk',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_socket_num' => '0'
'connect_id' => 'clk_source0'
}
}
},
'type' => 'num'
},
'wb_slave' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '2',
'name' => 'wb_slave',
'connect_socket' => 'wb_slave',
'width' => 5,
'connect_id' => 'wishbone_bus0',
'end' => 2415919135,
'base' => 2415919104,
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
'connect_socket' => 'wb_slave',
'name' => 'wb_slave',
'connect_socket_num' => '2',
'width' => 5
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'interrupt_peripheral' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral',
'connect_socket_num' => undef,
'connect_id' => 'NC',
'connect_socket' => undef
}
}
}
'value' => 1,
'connection_num' => undef
}
},
'module_name' => 'jtag_uart_wb',
'parameters_order' => [
'FPGA_VENDOR',
'SIM_BUFFER_SIZE',
'SIM_WAIT_COUNT'
],
'parameters' => {
'SIM_WAIT_COUNT' => {
'value' => '1000'
},
'FPGA_VENDOR' => {
'value' => ' "ALTERA"'
},
'SIM_BUFFER_SIZE' => {
'value' => '100'
}
},
'SIM_WAIT_COUNT' => {
'value' => '1000'
}
},
'sockets' => {
'RxD_sim' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'RxD_sim'
}
},
'type' => 'num'
'connection_num' => 'single connection',
'value' => 1
}
},
'module' => 'jtag_uart',
'description_pdf' => undef
'description_pdf' => undef,
'category' => 'Communication'
},
'clk_source0' => {
'plugs' => {
'reset' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'reset',
'connect_socket_num' => undef,
'connect_socket' => undef
}
}
},
'clk' => {
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_socket' => undef,
'connect_id' => 'IO',
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'module' => 'clk_source',
'instance_name' => 'source',
'parameters_order' => [],
'parameters' => {},
'module_name' => 'clk_source',
'sockets' => {
'reset' => {
'value' => 1,
'connection_num' => 'multi connection',
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset'
}
}
},
'clk' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk'
}
},
'connection_num' => 'multi connection',
'value' => 1
}
},
'category' => 'Source',
'description_pdf' => undef
},
'timer0' => {
'plugs' => {
'interrupt_peripheral' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'interrupt_peripheral',
'connect_id' => 'mor1kx0',
'name' => 'intrp',
'connect_socket_num' => '0'
}
},
'value' => 1,
'connection_num' => undef
},
'wb_slave' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '1',
'name' => 'wb',
'width' => 5,
'end' => 2516582431,
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_slave',
'end' => 2516582431,
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl',
'base' => 2516582400,
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl'
'name' => 'wb',
'width' => 5,
'connect_socket_num' => '1'
}
}
},
'type' => 'num'
},
'interrupt_peripheral' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'interrupt_peripheral',
'connect_id' => 'mor1kx0',
'name' => 'intrp'
}
}
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket_num' => '0'
}
},
'type' => 'num'
}
},
'reset' => {
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'name' => 'reset',
'connect_socket_num' => '0'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
'value' => 1,
'connection_num' => undef
}
},
'module' => 'timer',
'instance_name' => 'timer',
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw',
'PRESCALER_WIDTH'
],
'parameters' => {
'Dw' => {
'value' => '32'
},
'SELw' => {
'value' => '4'
},
'Aw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => '4'
},
'PRESCALER_WIDTH' => {
'value' => '8'
},
278,150 → 389,164
'value' => '32 '
}
},
'module_name' => 'timer',
'sockets' => {},
'category' => 'Timer',
'instance_name' => 'timer',
'module_name' => 'timer',
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw',
'PRESCALER_WIDTH'
],
'description_pdf' => '/mpsoc/src_peripheral/timer/timer.pdf',
'module' => 'timer'
'description_pdf' => '/mpsoc/src_peripheral/timer/timer.pdf'
},
'mor1kx0' => {
'category' => 'Processor',
'instance_name' => 'cpu',
'module_name' => 'mor1k',
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM'
],
'parameters' => {
'OPTION_OPERAND_WIDTH' => {
'value' => '32'
},
'IRQ_NUM' => {
'value' => '32'
}
},
'sockets' => {
'interrupt_peripheral' => {
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
},
'type' => 'param',
'connection_num' => 'single connection',
'value' => 'IRQ_NUM'
}
'gpo0' => {
'description_pdf' => undef,
'category' => 'GPIO',
'sockets' => {},
'module_name' => 'gpo',
'parameters_order' => [
'PORT_WIDTH',
'Aw',
'TAGw',
'SELw',
'Dw'
],
'parameters' => {
'SELw' => {
'value' => ' 4'
},
'Aw' => {
'value' => ' 2'
},
'Dw' => {
'value' => 'PORT_WIDTH'
},
'PORT_WIDTH' => {
'value' => 4
},
'TAGw' => {
'value' => ' 3'
}
},
'plugs' => {
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0'
}
},
'type' => 'num'
},
'reset' => {
'instance_name' => 'led',
'module' => 'gpo',
'plugs' => {
'clk' => {
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_socket_num' => '0'
}
},
'type' => 'num'
},
'wb_slave' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset'
'end' => 2449473567,
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_slave',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O',
'base' => 2449473536,
'name' => 'wb',
'width' => 5,
'connect_socket_num' => '0'
}
}
},
'wb_master' => {
'connection_num' => undef,
'value' => 2,
'nums' => {
'1' => {
'connect_socket_num' => '1',
'name' => 'dwb',
'connect_socket' => 'wb_master',
'connect_id' => 'wishbone_bus0'
},
'0' => {
'name' => 'iwb',
'connect_socket_num' => '0',
'connect_socket' => 'wb_master',
'connect_id' => 'wishbone_bus0'
}
},
'type' => 'num'
},
'enable' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => undef,
'name' => 'enable',
'connect_id' => 'IO',
'connect_socket' => undef
}
},
'type' => 'num'
}
},
'module' => 'mor1kx',
'description_pdf' => undef
},
},
'type' => 'num'
}
}
},
'wishbone_bus0' => {
'sockets' => {
'wb_master' => {
'value' => 'M',
'connection_num' => 'single connection',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_master'
}
}
},
'wb_addr_map' => {
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'type' => 'num',
'connection_num' => 'single connection',
'value' => 1
},
'wb_slave' => {
'value' => 'S',
'connection_num' => 'single connection',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
}
}
},
'category' => 'Bus',
'description_pdf' => undef,
'module' => 'wishbone_bus',
'plugs' => {
'reset' => {
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'name' => 'reset'
'connect_socket_num' => '0'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'clk' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_socket_num' => '0'
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'module' => 'wishbone_bus',
'instance_name' => 'bus',
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'parameters' => {
'BTEw' => {
'value' => '2 '
},
'TAGw' => {
'value' => '3'
},
'M' => {
'value' => 2
},
428,200 → 553,38
'Dw' => {
'value' => '32'
},
'CTIw' => {
'S' => {
'value' => '4'
},
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
'BTEw' => {
'value' => '2 '
},
'Aw' => {
'value' => '32'
},
'S' => {
'value' => '4'
}
'CTIw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
}
},
'sockets' => {
'wb_slave' => {
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
},
'value' => 'S',
'connection_num' => 'single connection'
},
'wb_addr_map' => {
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
},
'type' => 'num',
'connection_num' => 'single connection',
'value' => 1
},
'wb_master' => {
'value' => 'M',
'connection_num' => 'single connection',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_master'
}
}
}
},
'category' => 'Bus',
'module_name' => 'wishbone_bus',
'instance_name' => 'bus',
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
]
'module_name' => 'wishbone_bus'
},
'clk_source0' => {
'description_pdf' => undef,
'module' => 'clk_source',
'plugs' => {
'reset' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => undef,
'connect_id' => 'IO',
'connect_socket_num' => undef,
'name' => 'reset'
}
},
'value' => 1,
'connection_num' => undef
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => undef,
'name' => 'clk',
'connect_socket' => undef,
'connect_id' => 'IO'
}
},
'type' => 'num'
}
},
'sockets' => {
'clk' => {
'connection_num' => 'multi connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk'
}
},
'type' => 'num'
},
'reset' => {
'value' => 1,
'connection_num' => 'multi connection',
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset'
}
}
}
},
'parameters' => {},
'module_name' => 'clk_source',
'category' => 'Source',
'instance_name' => 'source',
'parameters_order' => []
},
'single_port_ram0' => {
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf',
'instance_name' => 'ram',
'module' => 'single_port_ram',
'sockets' => {},
'parameters' => {
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'SELw' => {
'value' => 'Dw/8'
},
'CTIw' => {
'value' => '3'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'INITIAL_EN' => {
'value' => '"YES"'
},
'Aw' => {
'value' => 14
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'JTAG_CONNECT' => {
'value' => ' "JTAG_WB" '
},
'TAGw' => {
'value' => '3'
},
'BTEw' => {
'value' => '2'
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'Dw' => {
'value' => '32'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
}
},
'plugs' => {
'wb_slave' => {
'nums' => {
'0' => {
'connect_id' => 'wishbone_bus0',
'width' => 'WB_Aw',
'connect_socket' => 'wb_slave',
'connect_socket_num' => '3',
'name' => 'wb',
'base' => 0,
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'end' => 65535
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'clk' => {
'nums' => {
'0' => {
'connect_socket' => 'clk',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket_num' => '0',
'name' => 'clk'
'connect_socket' => 'clk'
}
},
'type' => 'num',
631,20 → 594,35
'reset' => {
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
}
'value' => 1,
'connection_num' => undef
},
'wb_slave' => {
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'wb',
'connect_socket_num' => '3',
'width' => 'WB_Aw',
'connect_id' => 'wishbone_bus0',
'end' => 65535,
'base' => 0,
'connect_socket' => 'wb_slave',
'addr' => '0x0000_0000 0x3fff_ffff RAM'
}
},
'type' => 'num'
}
},
'instance_name' => 'ram',
'module_name' => 'wb_single_port_ram',
'category' => 'RAM',
'parameters_order' => [
'Dw',
'Aw',
661,264 → 639,209
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH'
]
],
'parameters' => {
'Aw' => {
'value' => 14
},
'CTIw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
},
'BTEw' => {
'value' => '2'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'WB_Aw' => {
'value' => 'Aw+2'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'Dw' => {
'value' => '32'
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'TAGw' => {
'value' => '3'
},
'JTAG_CONNECT' => {
'value' => ' "JTAG_WB" '
},
'INITIAL_EN' => {
'value' => '"YES"'
}
},
'sockets' => {},
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf',
'category' => 'RAM'
}
},
'soc_name' => 'tutorial',
'compile_pin_range_lsb' => {
'source_reset_in' => '0',
'led_port_o' => '0'
},
'timer0' => {
'version' => 9
},
'jtag_uart0' => {
'version' => 14
},
'wishbone_bus0' => {
'version' => 0
},
'single_port_ram0' => {
'version' => 22
},
'hdl_files' => undef,
'compile' => {
'type' => 'Modelsim',
'board' => 'DE10_Nano_VB2',
'quartus_bin' => '/home/alireza/intelFPGA_lite/17.1/quartus/bin',
'modelsim_bin' => '/home/alireza/altera/modeltech/bin',
'compilers' => 'QuartusII,Verilator,Modelsim'
'compilers' => 'QuartusII,Verilator,Modelsim',
'quartus_bin' => '/home/alireza/intelFPGA_lite/17.1/quartus/bin'
},
'compile_assign_type' => {
'source_clk_in' => 'Direct',
'source_reset_in' => 'Negate(~)',
'cpu_cpu_en' => 'Direct'
},
'modules' => {},
'instance_order' => [
'clk_source0',
'wishbone_bus0',
'gpo0',
'mor1kx0',
'timer0',
'single_port_ram0',
'jtag_uart0'
],
'wishbone_bus0' => {
'version' => 0
},
'hdl_files' => undef,
'global_param' => {
'CORE_ID' => 0
},
'mor1kx0' => {
'version' => 13
},
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
},
'tile_diagram' => {
'show_reset' => 1,
'show_clk' => 1,
'show_unused' => 1
'show_unused' => 1,
'show_reset' => 1
},
'single_port_ram0' => {
'version' => 22
},
'compile_pin_range_hsb' => {
'led_port_o' => '3'
},
'jtag_uart0' => {
'version' => 14
},
'gpo0' => {
'version' => 2
},
'compile_pin' => {
'cpu_cpu_en' => '*VCC',
'led_port_o' => 'LED',
'source_clk_in' => 'FPGA_CLK1_50',
'source_reset_in' => 'KEY'
},
'timer0' => {
'version' => 9
},
'modules' => {},
'top_ip' => bless( {
'ports' => {
'uart_RxD_ready_sim' => {
'range' => '',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output',
'intfc_name' => 'socket:RxD_sim[0]',
'instance_name' => 'jtag_uart0'
},
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'instance_name' => 'jtag_uart0'
},
'uart_RxD_wr_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'range' => '',
'instance_name' => 'jtag_uart0'
},
'led_port_o' => {
'instance_name' => 'gpo0',
'intfc_port' => 'IO',
'type' => 'output',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0'
},
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]'
},
'source_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0'
},
'source_clk_in' => {
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0'
}
},
'instance_ids' => {
'mor1kx0' => {
'ports' => {
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => ''
'range' => '',
'intfc_name' => 'plug:enable[0]'
}
},
'instance' => 'cpu',
'module' => 'mor1kx',
'parameters' => {
'cpu_OPTION_OPERAND_WIDTH' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Parameter',
'info' => 'Parameter',
'content' => ''
'content' => '',
'info' => 'Parameter'
},
'cpu_IRQ_NUM' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '32',
'type' => 'Fixed',
'content' => '',
'info' => undef
}
},
'instance' => 'cpu',
'category' => 'Processor',
'module_name' => 'mor1k',
'module' => 'mor1kx'
'module_name' => 'mor1k'
},
'clk_source0' => {
'module' => 'clk_source',
'instance' => 'source',
'module_name' => 'clk_source',
'category' => 'Source',
'ports' => {
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => ''
},
'source_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'jtag_uart0' => {
'ports' => {
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'type' => 'input',
'intfc_port' => 'reset_i',
'range' => ''
}
}
},
'intfc_port' => 'RxD_din_sim'
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]'
},
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]'
}
},
'instance' => 'uart',
'module' => 'jtag_uart',
'category' => 'Communication',
'module_name' => 'jtag_uart_wb'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'instance' => 'bus',
'category' => 'Bus'
},
'single_port_ram0' => {
'instance' => 'ram',
'module' => 'single_port_ram',
'module_name' => 'wb_single_port_ram',
'parameters' => {
'ram_Dw' => {
'redefine_param' => 1,
'type' => 'Spin-button',
'global_param' => 'Parameter',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1',
'global_param' => 'Parameter',
'default' => '32',
'redefine_param' => 1,
'type' => 'Spin-button'
'default' => '32'
},
'ram_Aw' => {
'default' => 14,
'content' => '4,31,1',
'info' => 'Memory address width',
'redefine_param' => 1,
'default' => 14,
'type' => 'Spin-button',
'global_param' => 'Parameter'
'global_param' => 'Parameter',
'type' => 'Spin-button'
}
},
'module' => 'single_port_ram',
'module_name' => 'wb_single_port_ram',
'instance' => 'ram',
'category' => 'RAM'
},
'jtag_uart0' => {
'module_name' => 'jtag_uart_wb',
'instance' => 'uart',
'category' => 'Communication',
'module' => 'jtag_uart',
'ports' => {
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_name' => 'socket:RxD_sim[0]',
'clk_source0' => {
'ports' => {
'source_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => '',
'intfc_name' => 'plug:clk[0]'
},
'source_reset_in' => {
'type' => 'input',
'intfc_port' => 'RxD_din_sim'
},
'uart_RxD_ready_sim' => {
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output'
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
}
}
},
'gpo0' => {
'ports' => {
'led_port_o' => {
'intfc_name' => 'IO',
'type' => 'output',
'intfc_port' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0'
}
},
'parameters' => {
'led_PORT_WIDTH' => {
'global_param' => 'Parameter',
'type' => 'Spin-button',
'redefine_param' => 1,
'default' => 4,
'info' => 'output port width',
'content' => '1,32,1'
}
},
'module' => 'gpo',
'instance' => 'led',
'category' => 'GPIO',
'module_name' => 'gpo'
},
'intfc_port' => 'reset_i',
'range' => '',
'intfc_name' => 'plug:reset[0]'
}
},
'module' => 'clk_source',
'instance' => 'source',
'module_name' => 'clk_source',
'category' => 'Source'
},
'timer0' => {
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button',
'default' => '8',
'redefine_param' => 1,
'type' => 'Spin-button',
'content' => '1,32,1',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
926,30 → 849,95
'
}
},
'instance' => 'timer',
'category' => 'Timer',
'module_name' => 'timer',
'category' => 'Timer',
'module' => 'timer'
}
'module' => 'timer',
'instance' => 'timer'
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'content' => '1,32,1',
'default' => 4,
'info' => 'output port width',
'global_param' => 'Parameter',
'type' => 'Spin-button',
'redefine_param' => 1
}
},
'category' => 'GPIO',
'module_name' => 'gpo',
'module' => 'gpo',
'instance' => 'led',
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0'
}
}
}
},
'ports' => {
'uart_RxD_wr_sim' => {
'range' => '',
'instance_name' => 'jtag_uart0',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim'
},
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'uart_RxD_ready_sim' => {
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'instance_name' => 'jtag_uart0',
'type' => 'output',
'intfc_port' => 'RxD_ready_sim'
},
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'source_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0'
},
'uart_RxD_din_sim' => {
'type' => 'input',
'intfc_port' => 'RxD_din_sim',
'range' => '7:0 ',
'intfc_name' => 'socket:RxD_sim[0]',
'instance_name' => 'jtag_uart0'
},
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'instance_name' => 'mor1kx0',
'intfc_name' => 'plug:enable[0]'
}
},
'interface' => {
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'clk_source0'
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
957,31 → 945,31
'ports' => {
'led_port_o' => {
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0'
'type' => 'output'
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'range' => '',
'instance_name' => 'jtag_uart0'
},
'uart_RxD_din_sim' => {
'instance_name' => 'jtag_uart0',
'type' => 'input',
'intfc_port' => 'RxD_din_sim',
'instance_name' => 'jtag_uart0',
'range' => '7:0 '
},
'uart_RxD_wr_sim' => {
'instance_name' => 'jtag_uart0',
'range' => '',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim'
},
'uart_RxD_ready_sim' => {
'instance_name' => 'jtag_uart0',
'range' => '',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output',
'range' => '',
'instance_name' => 'jtag_uart0'
'type' => 'output'
}
}
},
990,18 → 978,30
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
'intfc_port' => 'enable_i',
'type' => 'input'
}
}
}
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input'
}
}
}
}
}, 'ip_gen' ),
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'clk_source0' => {
'version' => 0
}
'gpo0' => {
'version' => 2
},
'soc_name' => 'tutorial',
'compile_assign_type' => {
'source_reset_in' => 'Negate(~)',
'cpu_cpu_en' => 'Direct',
'source_clk_in' => 'Direct'
}
}, 'soc' );

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