OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui
    from Rev 53 to Rev 54
    ↔ Reverse comparison
  •

Rev 53 → Rev 54

/ProNoC.desktop
0,0 → 1,11
#!/usr/bin/env xdg-open
[Desktop Entry]
Type=Application
Terminal=true
Name=Click-Script
Icon=/usr/local/share/icons/hicolor/scalable/apps/ProNoC.svg
#Exec=gnome-terminal -- ' bash -i -c cd \\"$(dirname "\\"%k\\"")\\"; ./ProNoC.pl; $SHELL '
Exec=gnome-terminal -e "bash -i -c 'cd \\"$(dirname "\\"%k\\"")\\"; ./ProNoC.pl; $SHELL'"
Categories=Application;
Name[en_US]=ProNoC
X-Desktop-File-Install-Version=0.24
ProNoC.desktop Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: ProNoC.pl =================================================================== --- ProNoC.pl (revision 53) +++ ProNoC.pl (revision 54) @@ -1,4 +1,4 @@ -#!/usr/bin/perl -w +#!/usr/bin/perl package ProNOC; @@ -22,11 +22,12 @@ use Getopt::Long; use base 'Class::Accessor::Fast'; +our %glob_setting; +$glob_setting{'FONT_SIZE'}='default'; +$glob_setting{'ICON_SIZE'}='default'; +$glob_setting{'DSPLY_X'} ='default'; +$glob_setting{'DSPLY_Y'} ='default'; -our $FONT_SIZE='default'; -our $ICON_SIZE='default'; - - BEGIN { my $module = (Consts::GTK_VERSION==2) ? 'Gtk2' : 'Gtk3'; my $file = $module; @@ -67,14 +68,15 @@ sub main{ - # check if envirement variables are defined + # check if environment variables are defined + #STDERR->autoflush ; my $project_dir = get_project_dir(); #mpsoc dir addr my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths"; if (-f $paths_file){#} && defined $ENV{PRONOC_WORK} ) { my $paths= do $paths_file; - my %p=%{$paths}; - $FONT_SIZE= $p{'GUI_SETTING'}{'FONT_SIZE'} if (defined $p{'GUI_SETTING'}{'FONT_SIZE'}); - $ICON_SIZE= $p{'GUI_SETTING'}{'ICON_SIZE'} if (defined $p{'GUI_SETTING'}{'ICON_SIZE'}); + + set_gui_setting($paths); + main_window(); } else{ @@ -91,6 +93,8 @@ set_path_env(); my($width,$hight)=max_win_size(); + #print "($width,$hight)\n"; + set_defualt_font_size(); if ( !defined $ENV{PRONOC_WORK} ) { @@ -345,9 +349,13 @@ my ($file_path,$text)=@_; $set_win->destroy; - my $new_fontsize = $self->object_get_attribute('GUI_SETTING', 'FONT_SIZE'); - my $new_icon_size= $self->object_get_attribute('GUI_SETTING', 'ICON_SIZE'); - if($new_fontsize ne $FONT_SIZE || $new_icon_size ne $ICON_SIZE){ + my %new_setting = %{$self->object_get_attribute('GUI_SETTING')}; + my $eq=1; + foreach my $k (sort keys %new_setting){ + $eq= 0 if $new_setting{$k} ne $glob_setting{$k}; + } + + if($eq ==0){ restart_Pronoc (); } @@ -538,15 +546,27 @@ my ($self,$set_win,$reset)=@_; my $table = def_table(10, 1, FALSE); - + my $w="default"; + for (my $i=100;$i<3000;$i+=100) {$w.= ",$i";} my @gui=( - { label=>'Font size:', param_name=>'FONT_SIZE', type=>'Combo-box', default_val=> $FONT_SIZE, + { label=>'Font size:', param_name=>'FONT_SIZE', type=>'Combo-box', default_val=> $glob_setting{'FONT_SIZE'}, content=>"default,5,6,7,8,9,10,11,12,13,14,15", info=>undef, param_parent=>"GUI_SETTING", ref_delay=> undef, new_status=>undef}, - { label=>'ICON size:', param_name=>'ICON_SIZE', type=>'Combo-box', default_val=> $ICON_SIZE, + + { label=>'ICON size:', param_name=>'ICON_SIZE', type=>'Combo-box', default_val=> $glob_setting{'ICON_SIZE'}, content=>"default,11,14,17,20,23,26,29,32,35,38,41", info=>undef, - param_parent=>"GUI_SETTING", ref_delay=> undef, new_status=>undef}, + param_parent=>"GUI_SETTING", ref_delay=> undef, new_status=>undef}, + + + { label=>'Display width:', param_name=>'DSPLY_X', type=>'Combo-box', default_val=> $glob_setting{'DSPLY_X'}, + content=>"$w", info=>undef, + param_parent=>"GUI_SETTING", ref_delay=> undef, new_status=>undef}, + + + { label=>'Display height:', param_name=>'DSPLY_Y', type=>'Combo-box', default_val=> $glob_setting{'DSPLY_Y'}, + content=>"$w", info=>undef, + param_parent=>"GUI_SETTING", ref_delay=> undef, new_status=>undef}, );
/icons/ProNoC.svg
0,0 → 1,144
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg version="1.1" id="Layer_1" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" x="0px" y="0px" width="128px" height="128px" viewBox="0 0 128 128" enable-background="new 0 0 128 128" xml:space="preserve"> <image id="image0" width="128" height="128" x="0" y="0"
xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAIAAAACACAYAAADDPmHLAAAABGdBTUEAALGPC/xhBQAAACBjSFJN
AAB6JgAAgIQAAPoAAACA6AAAdTAAAOpgAAA6mAAAF3CculE8AAAABmJLR0QA/wD/AP+gvaeTAAAe
MElEQVR42u19eXwURdr/96nuOXJfhBvCTRCEIGgQVgFv1l3EG99FFwV1BVFxQcV1l3isuugKKLqu
Kyu6sv7Un+iqqLsuh6KiLyi3nCHhPkPuZCYz3c/7R/f0dCdDMjNkJg3m6U99JjPpb1V1PVVPPfU8
T1UTwqDe963LI1IGgTGKgG4AAMKocLCtFCdirNQ+UAzCSmZpw855g9c3BaPG/tln+tpfE6MAAaab
QNzSD3yGUzRtHAJTzISCHXOHvt4YpgHl3rdmFDO9T0D6ad8EtsG0HDFQRsRXb5t37spQT2Kh3Hu+
n01AQUtXupWanxgo2Pb8kEfNvwnzl9x7vi+wC/PpDMPYgQgoyL3n+4KQz5J797pRgtQVLV3JVoo9
qSxGb1sweCVgkgCC1PdbumJmoijGmZ0xdiIzrwkA+k9ZNxGCX2vpirVSHEmlW7e8NHiRrH3j2RSJ
Unt6KcGnJ8V4ccLg2QAWUf8p6/IIvC7WdbNbA8QdY8NqMWiwLIC8aCsYU+IomsDOmCgo1isUAvJk
zbxrV6XGzgs7u7ZZ+MTAKJmAbqf/o/x0iKGy3GEdnJ2/hpyxF56dY+ArujhaFnaT7arMEQgcYeXs
jDllkrzsyv0X3AP+CSmxjAgAEaBWdmDf7oujzlaWmEbaUAfSy7Hvuj7W06a5jeXO33LC8D9BTj5B
YNbL1j4dmTtBTA0wYZYxUgaAiJaAOjJiTCtFRgSA6jjx/Hlw9v2YiDQmC0EAA0RaN3BkFQHMTNB+
iJQvMnEUIjAKTCtFRuSo5KTLZ0DO3qoznyFAADMCnYEAkOQlKfUAqxWdo+KLDLanCPwpE0seThwz
HXLWDhIBZpM28gURlJpM9m4dB9++86DUZIJrM03TQGR8kVtFuf0o4cKnTMzXRzwzwDLX/DABtetu
AakOg9OnMhTlln7Yk5GdNfpYrgLknFXs7LmcAiM5IAHUulSu+uRZKMf6UXPKXjkgOuxIdtboYzEF
MoNdQ182tHwRGPlKAld9sABqWY9mZT4AyPZl/0+P5E7fw5G1jwJaPqBp/TWrbwfHgPmArgPY1Q7w
UyO5+wqLli8AqJ5k9my6JqzlXTR8sbEdwM6uvdgMAan9JgS1fq0IpXgEhBqmoI7KDqBGIVjiYwbU
vW5nCKYJYgbLGfu07HXmCwKUsu4IW0+Lgi8ickh8KBoJY2dMk3m6KiEkHwnS+pfQec61mc1fmIls
awegKMSsnTFNZ+rXmM66BIDWCYRcGdPptnUZGEdMY8R1iQACtv6AIsiQUo6HPwVEQfadAs4wTJN5
Km6CN5k15gMB27+jQ0TRehGTLGy8DLQzQ2PRCZSS7pA7bYZh/gXD2X47hPsEc21mk0VGwxcBaEpN
JCkaTOSJzjBM00k9kAez7V+AQMSUkPdes/AFzJzQdQ1DBQd+E8SEiK9oMBFfOMMwTV/+XaMgSPM0
BBxBggiJee+BnNVNt3oTdzhSj6Lz+Psp545fIW3wBywcHtZ0AI4wRYOJMNEZhgknqUf6kXI8hy2+
ADAkdxUljZp/ynxxZhcCAFyZe6ntZX+mHnePgyA1CnEVDSYO04ydMeEm79oJuh0g6A0kAMlnf0LO
nNXcKL4JvqQO/BhmO4PkqiYRD2Ee1RWvqclmU2DdljHwH+/B2ioAFrtAxtjZkDKLoyrd1W47J/f+
uqGdwU4isDUBxIJqP58JAjEIlhEr3NWUdf39kNL3cyR8IUcVt7t6NoRQTZZGgrekC9PIm34MzB42
Izs7dqLAkMKi8zqINkUQaYfAtSngqnZQivLBNVkNlngJI1/g5Py3CIDFNwAAam0ql773J/gODGpy
aSgllnD7X02HK7uQAvhAfof/VcB6UGjsmyw6svOqPkyMo4od+W9APnsppKQSIl3LDyh6RGD/vnO4
duUUKIcGGJl6vpgKZ8et7O66gcx2AUEEkVhB2ROmcPW6q7niy9vBtekUqJGZL4n9lnP2ZXMhp2jl
goOKZdXuYVy56TKi0eO3sZ1Cos4kEr1WsvPiZyCllBAAI8LHzEyYOoN30y+5+rMHQOzQVL+EMk6/
+XY4M/fpeC1f8yqBFcGe3cPh3TsQamkXkNMDOWsPknJXwp1dbHQMM95X2pn3Lvwb1No0otE3bo2c
l63bg5vESD97hZ3D/04hmW5SxEj34Qe++/cP4op3ngHqUggMiJTDnHHzFDgyDlMQbwoaCeFAsn63
lq+Ut+d9r70If3kHrXNcdMO21qHczCSPnsvyuf+PhCHmTXH9Db6bmKXjffsHccXiBYAe+UtJxzl9
/P1wt99pmQ5Il8Xhdoa6w7l8cPEcKFXZxlQjdT/r7oKWbrBQ1NIzOUseppNE4jRWjuiznJ0Xz9dG
PrFh2eOSHly36k54v5qMuq2XAZ40SNmFkGQ/Gf5/AogIctphkjMOwLtttFZUXSLVbrgSIvkEXB13
UECLJwraCYSJ6fXtCABz+ZrrcPidJ8CeVEv16ZLrtrEtZ4AWIiaVecTL4NzPId54A1SXEna/YkcN
u6aMhZRYRQGxS2DUrbmJ65ZNA7FkbfzUw5x87Sw4Om0ls5Yf0NIrljzB3h8vsWAcOT9w2uXPw9V+
G9UPHyOd+eZVg+dgXz7+6X3w7s0L3Zkvuc6uU0D853NOLGF17O+ALuu0pt01ksX7c6gxjJnEkHfY
edlzZNbylS2Xs/fDx07eiRw1nPI/0+HsspHqK4ZKTRqfWPAu2NuwEzq7rufEgZ/B3es7ONMPW7R8
f0UW1+7OR9W6MfAUD2m0A9Ol1263aQeIL6md17Iy9neg5FILA7H8tyzWjg9LCjgm3sZSh83GXj4i
cO2CD8DlHRtngruCUyZNhDPrgK61BxXGyuW3c82qSY3jndUskktAxFCrM6DWE/ONkW0DQuJNnH4Q
lFxKArqnT5+PxUXzwe2bNpYxKSzabocQZMzBakW7JpkPAOxJpeolf4SqElu9gUBS/hKw8DdaPtcl
kXKiK/lLcigS5gO6Kbg1AfKmsURbrmDo0Ti6TgYSColxswBnRaOOGJF8FJLsJ3NED/ld4ccCHOxH
3v+90bJkIwBy0nFyddoSs+e2sTuY4o4Rn84CHc/hgIZN0BpIpB8i8cvHmi4HMPbtCyJIqYfB5ONw
61KzaiKgOLm+lu/ssiFmfBGk6t6tSFI0mAgTgLhjJF8iiffmAIqL6xtrRO8vSZy3mE9aTl2ivgRj
QwuXHD5ydF8Tfn2qMslXeJ6OZ2N+dmQeiBlfhCHq7Ja4ZTCipAeJT2ZZ1tOBT3HxAlDHzRyynNp0
Uiuyuf663HXBPyKqj/9Afw0vgks8EkrM2lnES9SeTok2XknYcCULfSSSLluFpJJ03UNgV0VIsc77
8jSm6SNXEODI+YHkfsvDngbYmxRQQ4xpCHWJMeOLLgEivaLBnF4XPpkFPtadyaTVExhy+lFyXF0A
cMOwEGXtNSEtcQm/eAoi9WhYgRyO7GJDggTy8e3vHzO+CEShOUaDOd2S8LuJ3pkD1Lm4/hk9cp+v
SB7xegMMFw0l5VBvNlYB0CSInFxBSf8zHSTXNL6ScFWyu/8yiy2fFeK6wiEx44uItTLXUknNLGZ2
l/Ep5XO8B+Hj38G8LjdO57rkJYhOmxrk7/vwYYDBVls9w9lpF6XcNhXkrghZJ5CPU2/4AxxJFWSW
IJ7Nl4LL21Gs2knq0/eegrhYXKMoIhoMM9g3/DXUXTsT/hGvQ+2zEpxxQBsdFW1Baj17fFOZHulN
lH6Eqf22YDCH9klS79VQ1v0C8LmNbLiiHYmESkhdNjU440dKO0auvKXg8rbwH+0G0rQMyN3WcfqE
B+Husd44ABIMoC6JT7z5JLg2TONOFHyhX/xiV4xZGV/yd17H3lsnmc7YMbWN38HS/sGgXfmQdg8D
DuXCuLERYtnL8p23QLQzhVXp/1N3jmDv6/Mt+TApnDTxPsi9VlNAYpgVQwDguiRWjneClFqiRewg
aP4NdJoTbzzFns1RHwMbFkl9et9TEB/WREZh8CUkRlS0J3ZXMXfeSA2CJySVKP0AUc//JR66hJD/
NtBhK+CoAmrSQN7Qnj9SZeLC8yAN+Qgk+cnMTJG1j+B3Qt2TZ2CJBfm2jITcay2ktKMNmQsCST6S
U0tIctVS/c4BVeKyt38Pz4YrYsp8AKCxPy+0pzv4FBx7TH72TroV3HkLGWteQ7EydwpdnOvfuaQT
U+H54J3nA0VDQd5k63Qx8FN2jn+EtAieIFNZIfa88irUvdYgTZbqOOmGArgG/YfMRiVzBFD9+qiV
WVz21qPw7RxG8eALjf154Rk1BQRITTvE3t+MByVUGo0fsKwZzEBwTje0fP07q2A6MABcmA/eeT54
39kgVSbp6sfZce4Hutcu0LkIakU2185/C6hJbzBqHQP/wwljXoCceYisnRHGep9VwbVrx6Lqo/vA
nuSYj/wA0VVjbCoBmoGUPl+yf8K9IJDhLzcrcuYo2cBJnKGCKgAAvgRWd58DLh4M+cI3ICVVkiHO
dbxv+zCuXbggtF4hfOzouxquASsgd9oBKbkM7JehHM+Bv3AIatb8ElwV3AF8CgIwMsxVY+wqAZqn
CXxXzGUe/g9txFJwxIbqDNbvDSN0GnYOq5ZPRPB8NoV9K26L2wg+VbL1CSHRLwaD5PjsXvi6rmfq
spkAK5PZLzN2DQe6/wDhriIAsIRZoV6nqaelB/ODoWgmXP4XcNE5rBQNtnPDGiQMh0gkKRpMS1n0
VIkc/5wD1KSwofAFtHKHn8SxHNBjK8EvL2SsmMS8vx9DD5Q3mA/ozAcs5/UbmzyC/xdCpaQJD4ES
S/mU6h4vvlxz2W576gDNPAmqfVexMnEaBAkya+EgZrz2PGjbBcF1fGIZiz6rQX2/gdT3W4jkEgq1
ajBGkCm/gJbv35nPlS+/CAqW1JKPf3LMtZcXcaQ9IHCE7elG6hXzmEcuImtcPYDaFOZ5b4P0zRJm
YgZTxx0QuV9D6vs1RLcNkGSlgQIImFcFGtbz2V3s+c/t0XWAKNo4Ksy1lxadhqyMjpgUVn8zCdRt
A9VX7LBvAKsvvgZq6lRORw2LXmshn/UVpNzVkLIOWJd2+m1EBFUFV734NyiF59hWH6DrLvnpdAAA
UFOPMN9/IyixvMFuWV71K8aHMyJiFmXtYyl3NeSzvtIsfy6PpXOppe24/PEPAcVhy05g2w6gCdfI
qhYuhvt8w7h9im4fCIhujWvK3+czfryQoipH+FjqsR6Os76Gs99qUFIZqhf9Cf7debZkPgDQ9RcX
27IDhEtK212s5H0Gtf0uIP0IqDYZorw9xLafQWwf0cCcGyB1zPMsLvk7BbV83f9ek8z+Z98FlXU4
ZaYx9Jc52Zi0DmDDZUBTo9nfeRP7xs4Bd99E1MC2rytEniSWVkyCWDkBpDitjCCVMWUypF7rqL5v
QC0+i/3Pv46T7w2Mw/b4OC0D6IaL7CoBQj8Nk5+9Y5+Fb/hbEERktuXXt+0bYVKHe7FY+Dyo1LpJ
g1OPsZhxPURKeQOtXvniJlbef4AiqdvpSHTjRXtsKQFCkeqsZs/E+6D2/o5OZr6tb641tPzqDBZ/
+SvoYF9rJ+jzLUt33Qmhb9w3Og0Bda/MZd48umVEeJwkgCAVkUfNRoGJOMH6XYXKtbfdrTEfDZnP
XieDBZvj8oWpM1BSKfEdU8GpRywRurRjGPF/JxsWviCe4bz590DGAW6qbjGJTI4TX0Sg40SSosFE
nJgs332Xvwju+b0WYUPGSRksf3stu57+gBNnrSHXA2sgv7qA6UBfNi/xAjF2Iu0Y0Z13A8LH5nJ4
6VSgcCgHbPrG/QlV5Jo8w3p/iLrFIsWLL9LZOfcXRBM2HfsLxl+cdpRrf/1bCIGgwqdI7F40D84V
t5KoziACQbBE4lg3Et9eA04uBeVsaaDlU0oJEQRo53lklMOC1B9HQOR/DOGqMby5RICUdpxEYgXU
LRdSqLqd7pd9dwaZUt0FiyFJqqbw6XH6zn/fBcfm0RTqfqHK5Hj3ERJf3sTmnT0ANPylrwLZeyyj
WlS2IfW1p/XxbZ4+CM6Rb5OU919u6XaIRRIxn8ubIalnfQlDQWMGVIkdq8Y3Pb+99yDw4/lsWRUw
Q8gK0UWLGmK255PyyZ2miCHojh/ANaEAcFaFvcPndElCRCM24iii4PCw2q7Q2KNHRBClHSA8adQU
VrBE4s0/AjXJepx+0H8v5S8FEqoa7NZRl06Buv3c4A5hInBFJte98hzIm9Jkmc0mmuOG0bXHSFI0
mHCSkrWH6//GiSe0JZo+EgkMktSw8xTlbUh8eG8DLZ8cHhLd1zW8XyXyvToHankmEwB1+xD2PP7/
wVvzKRbP3JxtHA1GRBx6CiAaTGPkHfwplz18JVc89Euw7K2Xe3AON7T09ENQEyrCr8U3V4Oq0xto
+dRjfejnq8wi/6vPwLf0DvY8txCoaBN3W0C8+KK/Pj6KwprhIVV3BVfd8iD8/VcRoL8avf0uduzr
r5fAkKrTAAaDmAwzr2BSB/6XpW+vCVGrhq1Afifx5guZzv8IwfN/AEo9Ae39fyEsjtuHkrJ96EnO
0InGShOfNo4U02IxgUpyCZdPmwTuuMsSZ6923g7aO8B4HPIkk3S0O6N9kfaL0Hq6esVC4LtxXH+r
18magA70DkqQgK+AFJ2PLTUEWp5a5JAoBnPlxBngDrusjhwQ1M6bAVibV9423PjNCOfK3kvKmJct
+TbKEomteABUnv0TZr1GLXJIVN3gT6H2XUOmjZbanOxJYmKpwVZn5xfjQcQN5nDlileg9lxrBF+i
sXK7bta1ehh4FJ3dOOYkKRqMXVNcDUHegZ8zGOy94B2rLb86nRMWz+a0mauR9M4jFLS0aTjpSHeS
118cXAUQAGYIWSX1rnvA7Qu5PsZiIm23mylvRfA3Arg6ibE1/6SYxlM0GHumuLwvQHVVcsXNv4Mv
77+kLp3G/pyNwfh6XwKn/PlNyEd6UOiSNHK+9Qi8ud8xJdRYXcDJlaTM+DXjpRdYFJ5D9QU0t9nP
4t6pELJCMCQIg7+8ETC2YNlvIohGzYwKc+uwAzF1B9d12cIVk6dDbbOfrCHV2qf784mcuGRmWK3p
z/8X+297OGSINqtg6evrgS+uBR3uBqSVAPmfgMYshHB5dObrVT+cw8qj7wDeJPtO53HqAWG/Pr4u
ax/XDPoc3p5r4c86CMnvhCjPRuKGS5C44TKIEI3p7bWGS++ZDCHXBQ9LEAEtXLvdseUChFyJhHgY
x7fjCB2KWP3534jMtn0GhATChe+CRr5rVfTIXB4DnmRWX5gPCoz+eA21SCma/KOyAzRBNT3XcPkV
L6E29xsIbTO0FjGja+11g5ajsvI5Tn/jKU7Y+jMLJ51Fg+A41BNq120w2+LNWr+oSYvoYeQl06G4
a1i9eDFZ86u3SjC+B0/u5PK2rD77V+Bgb2qqnGZnjk1JOqfjbwtCKQe+7GI+estMlI+dT0qb/ST0
MWexpEFvbFcNefM/JulENjv39Q966FSJnFuHw3P+EginPyTesXEk5CPdqTFFpV4iadOFRGXZzGd/
ox36AN17V0/LD9jyCQA2j2Ce+yLoSE4kZZ3xSRrScUaB2TnAxFx20UIcnXQf/B2KyfqCo6D2CwQb
O/DdO3AlHHv7wXGkp+E0kWrSSDrSHXVDP6VQ4VuiNgXOjaMjdrKIPQNIfD1Om+s7FoKIgyHeuogm
ArC/F/PiWcA7vyWqjZ8z57S5Jg89ZAg0X/ohPnzbDNT1WBucY/XGrB9hE+wEOlP1TiI8qdxm9keQ
yttZpoOqm55g7+jFVB8Pn5tTHlkK6YQ1YDOSaVZNLGfkfQnkbAGllgJ+B+hgT/C2oaCisxtVcuyq
AsSL6I4hh5gB1PRaw4fumAZOKj3pRkipIotd+3MBSYW3+3qQu5YaKlwM95orOf3VP1saXhU+rnh4
PNScHxsclyLvOJcT57wOsnkMfTwpbsvAO4Yc4tIL3uRjNzwJkpRgmJRJkXLvOJfTl06Be9v5CNyg
OKu5/KbHUTv8X9Z1ORGYmbMf+RTyke4WhvqzDnDFY1eD3JUNOpnzo9+w+/17TffHrQnihLFntaRO
M0pnl135VyKhUtBfrovz6nRuu2gOspY8QI6SLkT6LE4gCMVJCesuha/LVqgdi8jQ8jWzLpE3Aa6t
IyxzrlSbStLBnvAP+4QC9Q0ohkqftZB3DoF0rGuwE0Z82Rljz0vq+PjuAqtWr3269gzgjnPeQkLx
yV9PSgA5tw1DzUVvQsiqRcsnZx0SvrihAVY+3IM4qYK510bT/QwhiPxnfwnp66sgPElRzQV2xtiV
hHHChbFe1h4we/FjcFZkN7lkclRmkXvjaFgidghQ2uw9KSbh7QcgFQ5g8zQAZlBqGfmm3g+Qajhp
I0l2xtg1CceJzqz1BG3kBtbTx299AKpcG9YxJ46jXRtIEJL9J71f8suU9OJ8UCBWL+ANBMC5a8l/
7Tz9LNumy7YmO2PsmUSHl+dBqLI24nStnAD4OxZSyc0FWsRME0nNPKSP5CBelLZrFCMd70SJLz8D
sMqBJWTAy+cf+wr8/b/icMq2JkR4fzwx9kwisXgQZb/9kCUOPiARaod/QFUjljQaD89JZewdsiwo
AYT2u2vH0CbFj3P9aHJ9NgkWCSQIAkT+qTPBGUfOyFh8OyVBDKQvv4USv79Ub2z9NCxdNyibUIC6
jjus++n0T1bB5bc+DHLVUmBeDFjg3KuuDisu3fXWDMi78oJzvo6n1FLyTZsOJuWMi8UPJ1GcMNre
QAbaLXwajmOdub6tHi4vHZ86DewIvuwAAKCCK25+FHVDlxEQ3EkjiODYPIydO4ZQWHOQIpFr3lxQ
dZoe8YOgRMj9gdQb5tpwPo+9DhDgS6wxIvDiE9mTSu1eegFQJG1ONkXscIdiKr31D8bakR0eLps2
DZ5L/2kwPzDyyevm1L//MYwVaPCSSzuS+4VnAD3sy/yuHh72b8DpCet1K5oEO0PsAGE+8alipPy2
MwsC84GjrC1JVRnw5K2kgHZOuldN6bKDpJL2DIcXJTMnQ8n9PuiFQ+DUa3DaC8/DuWtwxB436Ug3
gsML7reOAvmJ7y5l51OvGnaB1hSDNK3/0YBQN+jY3dO45rzPLC8kBhikyAzJD6FriobWr/GeU195
CglfXEeIkphU9j76K6D3RjgWzYL07wkR5aXLq4jKjBfGrkT3nnWswdmCiruKD//xKijt9gZHHgUe
PvBd7xREQJ2D0156Fu7vxkTN/ACp6UeZM49C2j3glPM6nUmfVWOPufesYyEx3q4/8pHHrgPJPjIz
H7C+hkU63onT5y6Ao6i5GRa3JogTxp500p1B7j39KfP1P3DZ5N8DMCt6mgAEgROX3YDkfzwMKWYv
OIgmWztj7EeN7gxKWX4TJawOvEETFls/+RxI/PctMWR+K8WDaHru8UZlmeqq5qNPXwW1wx4y5nxo
r1cRh7py1oMfhowIbqXTg5p8fbzwJFHmcy8APgcbO3L0OZA77qXKux6KkSWMzihMxAnxwUjDMx8s
aNJQU55Ncnk2vEOXkRBW753adRdRaRt2Fg5s1oBLECI2bNgZY1dDUNh7A5OW3UgJq8ayNa5fkwi1
k56Av/uW5nXc8BmGsWkSkTgQ0l5+AtLBngwE4+4FEUj2UfXMqVDdlT9Jx81p7QxiYEO4vUXyJlHG
MwsgfC4O2OoBbXWgtttPNdMebMbeSWcYJrKEeGCYv5B+lvnQeAJ1C9t5UN6GxIm28OcvM3wB0D/V
LoVElens2JHXDPoAzjCMLa89gpiLI3UhJi27nlwrxrGxDcskCWpvexJKz42n9sas1hSnxMWCIVZG
s9xI+cvjkPb1YnMEEQFwHO8I+OXWZeCpJsQew4pYKUPBeuPlOeESa/pA2lMvctncq1i4PQQwnN+M
4cR5T0PUpkSYYWgiRJ6NnTEREccew8B6AoAHupcWE5ATTT09Fy3h2mmzkPjq7+FaGpn7tjGiKNrA
zhi7EQN75hRldJMBQDAKALwWfgME/eEJy64h58ZhLB3r2OxDIpoM7YyJLP/YxikQUGB5joe6lZYR
KC3Gz9VKNiAGlz9dnJEOmE8I8WMcJKwIJ4MzQQTanWI6NSkYF/jTcAc/vT9jJTE/GisjRWuKsVEn
XAzzo0/vz1hp7jQWerhreQEBsyPsfK10GhADjz65N63A/FtIXeaRzpWjmJQPTqoTtM4BsadmnAMY
XE4sjXtif8rKUJCT0sOdKiYS1AIiyqkPijn/7bymi0MDNEe1mHkPQxQ8eSB1UWOYJunhTlV5EtQ8
Bo8i4m46dKT9m8BOmFgTfwEAzFRMoJUKxPonDySvbwr1f/P8a7wpA32AAAAAJXRFWHRkYXRlOmNy
ZWF0ZQAyMDIxLTA0LTE4VDE0OjI3OjMyKzAyOjAwUnasxQAAACV0RVh0ZGF0ZTptb2RpZnkAMjAy
MC0wNy0yMlQyMjowNzozNyswMjowMOase9gAAAAASUVORK5CYII=" />
</svg>
/lib/ip/Bus/wishbone_bus.IP
343,7 → 343,8
'hdl_files' => [
'/mpsoc/rtl/src_peripheral/bus/wishbone_bus.v',
'/mpsoc/rtl/main_comp.v',
'/mpsoc/rtl/arbiter.v'
'/mpsoc/rtl/arbiter.v',
'/mpsoc/rtl/pronoc_def.v'
],
'parameters_order' => [
'M',
/lib/ip/DMA/dma.IP
318,6 → 318,7
'hdl_files' => [
'/mpsoc/rtl/main_comp.v',
'/mpsoc/rtl/arbiter.v',
'/mpsoc/rtl/pronoc_def.v',
'/mpsoc/rtl/src_peripheral/DMA/dma_multi_chanel_wb.v'
],
'ip_name' => 'dma',
/lib/ip/NoC/ni_master.IP
423,6 → 423,7
'/mpsoc/rtl/src_peripheral/ni/ni_crc32.v',
'/mpsoc/rtl/main_comp.v',
'/mpsoc/rtl/arbiter.v',
'/mpsoc/rtl/pronoc_def.v',
'/mpsoc/rtl/src_topolgy/',
'/mpsoc/rtl/src_noc/'
],
/lib/mpsoc/mor1k_mpsoc.MPSOC
9,6952 → 9,781
## MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
 
$mpsoc = bless( {
'SOURCE_SET' => {
'REDEFINE_TOP' => 0,
'clk_0_name' => 'clk',
'SOC' => bless( {
'TOP' => {
'version' => 0
},
'SOURCE_SET' => {
'IP' => bless( {
'parameters_order' => [],
'ports_order' => [],
'plugs' => {
'clk' => {
'type' => 'num',
'1' => {},
'0' => {
'name' => 'clk'
},
'value' => 1
},
'reset' => {
'1' => {},
'0' => {
'name' => 'reset'
},
'value' => 1,
'type' => 'num'
}
},
'module_name' => 'TOP',
'file_name' => undef,
'hdl_files' => [],
'hdl_files_ticked' => [],
'ip_name' => 'TOP',
'ports' => {
'clk' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => undef,
'intfc_name' => 'plug:clk[0]'
},
'reset' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => undef
}
},
'category' => 'TOP',
'GUI_REMOVE_SET' => 'DISABLE'
}, 'ip_gen' )
},
'instance_order' => [
'TOP'
],
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'hdl_files' => undef,
'instances' => {
'TOP' => {
'sockets' => {},
'parameters_order' => [],
'module' => 'TOP',
'module_name' => 'TOP',
'plugs' => {
'clk' => {
'value' => 1,
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'IO',
'connect_socket' => undef,
'connect_socket_num' => undef
$mor1k_mpsoc = bless( {
'RAM3' => {
'end' => 65536,
'start' => 49152
},
'mpsoc_name' => 'mor1k_mpsoc',
'compile_pin_range_lsb' => {
'processors_en' => 0
},
'ROM3' => {
'end' => 49152,
'start' => 0
},
'compile' => {
'cpu_num' => '4',
'modelsim_bin' => 'export LM_LICENSE_FILE=1717@epi03.bsc.es; /home/alireza/intelFPGA_lite/questa/questasim/bin',
'type' => 'QuartusII',
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim',
'board' => 'DE10_Nano_VB2',
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin'
},
'MEM2' => {
'percent' => '75',
'width' => '14'
},
'socs' => {
'mor1k_tile' => {
'tile_nums' => [
0,
1,
2,
3
],
'top' => bless( {
'interface' => {
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input'
},
'uart_RxD_ready_sim' => {
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'range' => ''
},
'uart_RxD_wr_sim' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'instance_name' => 'ProNoC_jtag_uart0'
}
}
},
'type' => 'num',
'connection_num' => undef
},
'reset' => {
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_socket' => undef,
'connect_id' => 'IO',
'name' => 'reset'
}
},
'value' => 1,
'type' => 'num',
'connection_num' => undef
}
},
'instance_name' => 'TOP',
'description_pdf' => undef,
'category' => 'TOP'
}
},
'modules' => {},
'soc_name' => {
'TOP' => undef
},
'device_win_adj' => {
'ha' => '0',
'va' => '0'
}
}, 'soc' ),
'clk_number' => 1,
'reset_number' => 1,
'reset_0_name' => 'reset'
},
'tile' => {
'2' => {},
'1' => {},
'0' => {},
'3' => {}
},
'soc_param' => {
'default' => {
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JSTATUSw' => '8',
'uart_JTAG_CHAIN' => '3',
'ram_Aw' => '14',
'ram_JTAG_CHAIN' => '4',
'ram_Dw' => '32',
'uart_JINDEXw' => '8',
'ram_JAw' => '32',
'ram_JDw' => 'ram_Dw',
'ram_JINDEXw' => '8',
'uart_JDw' => '32'
}
},
'ROM1' => {
'end' => 49152,
'start' => 0
},
'noc_param' => {
'SSA_EN' => '"NO"',
'SWA_ARBITER_TYPE' => '"RRA"',
'B' => '4',
'MUX_TYPE' => '"BINARY"',
'DEBUG_EN' => '0',
'Fpay' => '32',
'ROUTE_NAME' => '"XY"',
'AVC_ATOMIC_EN' => 0,
'ESCAP_VC_MASK' => '2\'b01',
'TOPOLOGY' => '"MESH"',
'T3' => '1',
'T2' => '2',
'BYTE_EN' => '1',
'T1' => '2',
'WEIGHTw' => '4',
'CONGESTION_INDEX' => 3,
'V' => '2',
'MIN_PCK_SIZE' => '2',
'FIRST_ARBITER_EXT_P_EN' => 1,
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'C' => 0
},
'MEM3' => {
'width' => '14',
'percent' => '75'
},
'RAM2' => {
'start' => 49152,
'end' => 65536
},
'liststore' => {
'ha' => '0',
'va' => '0'
},
'RAM3' => {
'end' => 65536,
'start' => 49152
},
'ROM0' => {
'end' => 22937,
'start' => 0
},
'MEM2' => {
'percent' => '75',
'width' => '14'
},
'MEM0' => {
'percent' => '70',
'width' => '13'
},
'mpsoc_name' => 'mor1k_mpsoc',
'compile' => {
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin',
'type' => 'Modelsim',
'modelsim_bin' => 'export LM_LICENSE_FILE=1717@epi03.bsc.es; /home/alireza/intelFPGA_lite/questa/questasim/bin',
'board' => 'DE5',
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim'
},
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'SOURCE_SET_CONNECT' => {
'NoC_clk' => 'clk',
'T0_cs_reset_in' => 'reset',
'T1_ss_clk_in' => 'clk0',
'T2_cs_reset_in' => 'reset',
'T3_cs_clk_in' => 'clk',
'NoC_reset' => 'reset',
'T3_cs_reset_in' => 'reset',
'T1_cs_clk_in' => 'clk',
'T3_ss_clk_in' => 'clk0',
'T0_cs_clk_in' => 'clk',
'T0_ss_clk_in' => 'clk0',
'T1_ss_reset_in' => 'reset0',
'T1_cs_reset_in' => 'reset',
'T2_ss_clk_in' => 'clk0',
'T2_ss_reset_in' => 'reset0',
'T2_cs_clk_in' => 'clk',
'T3_ss_reset_in' => 'reset0',
'T0_ss_reset_in' => 'reset0'
},
'socs' => {
'mor1k_xilinx_tile' => {
'top' => bless( {
'parameters' => {
'ram1_JAw' => '32',
'ram2_JDw' => 'ram2_Dw',
'ram2_JTAG_INDEX' => 'CORE_ID',
'ram1_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram2_JINDEXw' => '8',
'ram2_WB2Jw' => '(ram2_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram2_JSTATUSw+ram2_JINDEXw+1+ram2_JDw : 1',
'ram1_JSTATUSw' => '8',
'ram1_JDw' => 'ram1_Dw',
'ram2_JAw' => '32',
'ram1_Dw' => '32',
'ram2_J2WBw' => '(ram2_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram2_JDw+ram2_JAw : 1',
'ram1_JINDEXw' => '8',
'ram2_Dw' => '32',
'ram2_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram2_JTAG_CHAIN' => '4',
'ram1_J2WBw' => '(ram1_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram1_JDw+ram1_JAw : 1',
'ram1_JTAG_INDEX' => 'CORE_ID',
'ram2_JSTATUSw' => '8',
'ram1_WB2Jw' => '(ram1_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram1_JSTATUSw+ram1_JINDEXw+1+ram1_JDw : 1',
'ram1_JTAG_CHAIN' => '4'
},
'interface' => {
'plug:reset[0]' => {
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'range' => '',
'type' => 'input',
'instance_name' => 'clk_source0',
'intfc_port' => 'clk_i'
}
}
},
'plug:enable[0]' => {
'ports' => {
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
}
'cpu_cpu_en' => {
'range' => '',
'instance_name' => 'mor1kx0',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'socket:ni[0]' => {
'plug:reset[0]' => {
'ports' => {
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'range' => '',
'instance_name' => 'ni_master0'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out',
'type' => 'output'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'range' => '',
'instance_name' => 'ni_master0'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0'
}
'source_reset_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'intfc_port' => 'IO',
'type' => 'output'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'instance_name' => 'mor1kx0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram1_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'single_port_ram0',
'range' => 'ram1_WB2Jw-1 : 0'
},
'ram2_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'ram2_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram1'
},
'ram2_jtag_to_wb' => {
'range' => 'ram2_J2WBw-1 : 0',
'instance_name' => 'single_port_ram1',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'ram1_jtag_to_wb' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram1_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
}
}
},
'ports' => {
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ram2_jtag_to_wb' => {
'instance_name' => 'single_port_ram1',
'range' => 'ram2_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => ''
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ram2_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram2_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram1',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'led_port_o' => {
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'type' => 'output',
'intfc_port' => 'IO'
},
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'ram1_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram1_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'ram1_jtag_to_wb' => {
'range' => 'ram1_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'type' => 'input'
}
},
'instance_ids' => {
'mor1kx0' => {
'instance' => 'cpu',
'module_name' => 'mor1k',
'localparam' => {
'cpu_FEATURE_DMMU' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1
},
'cpu_OPTION_OPERAND_WIDTH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'cpu_IRQ_NUM' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '32',
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'cpu_FEATURE_IMMU' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => ''
},
'cpu_OPTION_DCACHE_SNOOP' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'cpu_FEATURE_DATACACHE' => {
'default' => '"ENABLED"',
'info' => '',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"'
}
},
'category' => 'Processor',
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
}
},
'module' => 'mor1kx'
},
'single_port_ram1' => {
'category' => 'RAM',
'localparam' => {
'ram2_CORE_NUM' => {
'default' => 'CORE_ID',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ram2_INITIAL_EN' => {
'content' => '"YES","NO"',
'redefine_param' => 1,
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram2_BURST_MODE' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'default' => '"ENABLED"',
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1
},
'ram2_INIT_FILE_PATH' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => 'SW_LOC'
},
'ram2_BTEw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '2',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram2_CTIw' => {
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'ram2_MEM_CONTENT_FILE_NAME' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Entry',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"'
},
'ram2_BYTE_WR_EN' => {
'content' => '"YES","NO"',
'redefine_param' => 1,
'default' => '"YES"',
'info' => 'Byte enable',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ram2_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => 'ram2_Dw/8',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram2_TAGw' => {
'default' => '3',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ram2_Aw' => {
'redefine_param' => 1,
'content' => '4,31,1',
'default' => '14',
'info' => 'Memory address width',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'ram2_WB_Aw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'default' => 'ram2_Aw+2',
'content' => '4,31,1',
'redefine_param' => 1
},
'ram2_FPGA_VENDOR' => {
'content' => '"ALTERA","XILINX","GENERIC"',
'redefine_param' => 1,
'info' => '',
'default' => '"XILINX"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
}
},
'module_name' => 'wb_single_port_ram',
'instance' => 'ram2',
'parameters' => {
'ram2_WB2Jw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => undef,
'default' => '(ram2_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram2_JSTATUSw+ram2_JINDEXw+1+ram2_JDw : 1'
},
'ram2_JSTATUSw' => {
'info' => 'Parameter',
'default' => '8',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram2_JTAG_INDEX' => {
'type' => 'Entry',
'global_param' => 'Parameter',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'content' => '',
'redefine_param' => 1
},
'ram2_JINDEXw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram2_JTAG_CHAIN' => {
'global_param' => 'Parameter',
'type' => 'Combo-box',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'redefine_param' => 0,
'content' => '1,2,3,4'
},
'ram2_Dw' => {
'content' => '8,1024,1',
'redefine_param' => 1,
'info' => 'Memory data width in Bits.',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Spin-button'
},
'ram2_JTAG_CONNECT' => {
'redefine_param' => 1,
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"XILINX_JTAG_WB"'
},
'ram2_JDw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => 'ram2_Dw',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ram2_JAw' => {
'info' => 'Parameter',
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram2_J2WBw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(ram2_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram2_JDw+ram2_JAw : 1',
'info' => undef,
'content' => '',
'redefine_param' => 1
}
},
'module' => 'single_port_ram',
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram2_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram2_J2WBw-1 : 0',
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ram2_wb_to_jtag' => {
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'single_port_ram0',
'type' => 'input'
},
'uart_wb_to_jtag' => {
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram2_WB2Jw-1 : 0'
}
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'output',
'intfc_port' => 'jwb_o'
}
}
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'localparam' => {
'bus_Aw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'The wishbone Bus address width',
'redefine_param' => 1,
'content' => '4,128,1'
},
'bus_SELw' => {
'default' => 'bus_Dw/8',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'bus_BTEw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '2 ',
'info' => undef
},
'bus_TAGw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef
},
'bus_S' => {
'info' => 'Number of wishbone slave interface',
'default' => '5',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_Dw' => {
'content' => '8,512,8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '32',
'info' => 'The wishbone Bus data width in bits.'
},
'bus_CTIw' => {
'content' => '',
'redefine_param' => 1,
'default' => '3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_M' => {
'info' => 'Number of wishbone master interface',
'default' => ' 4',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '1,256,1'
}
},
'category' => 'Bus'
},
'timer0' => {
'localparam' => {
'timer_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => '4',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'timer_Dw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '32',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'timer_PRESCALER_WIDTH' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'default' => '8',
'redefine_param' => 1,
'content' => '1,32,1'
},
'timer_TAGw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => undef
},
'timer_Aw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '3',
'redefine_param' => 1,
'content' => ''
},
'timer_CNTw' => {
'info' => undef,
'default' => '32 ',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
}
},
'category' => 'Timer',
'module_name' => 'timer',
'instance' => 'timer',
'module' => 'timer'
},
'ni_master0' => {
'parameters' => {
'ni_T3' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '1',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_RAw' => {
'info' => undef,
'default' => '16',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 0,
'content' => ''
},
'ni_Fpay' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter'
},
'ni_BYTE_EN' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => 0
'socket:ni[0]' => {
'ports' => {
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr',
'instance_name' => 'ni_master0'
},
'ni_TOPOLOGY' => {
'default' => '"MESH"',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_B' => {
'content' => '',
'redefine_param' => 1,
'default' => '4',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
'ni_chan_in' => {
'range' => 'smartflit_chanel_t',
'intfc_port' => 'chan_in',
'instance_name' => 'ni_master0',
'type' => 'input'
},
'ni_chan_out' => {
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'chan_out'
},
'ni_DEBUG_EN' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '0',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_T1' => {
'redefine_param' => 1,
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'intfc_port' => 'current_r_addr',
'type' => 'input',
'instance_name' => 'ni_master0'
}
}
}
},
'parameters' => {
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JINDEXw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_JAw' => '32',
'ram_Dw' => '32',
'uart_JAw' => '32',
'uart_JTAG_CHAIN' => '3',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JSTATUSw' => '8',
'uart_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'ram_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1'
},
'instance_ids' => {
'timer0' => {
'module' => 'timer',
'localparam' => {
'timer_CNTw' => {
'content' => '',
'default' => '2',
'info' => 'Parameter',
'info' => undef,
'default' => '32 ',
'type' => 'Fixed',
'global_param' => 'Parameter'
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ni_C' => {
'default' => 0,
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_EAw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '16',
'info' => undef,
'redefine_param' => 0,
'content' => ''
},
'ni_T2' => {
'timer_SELw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '2',
'global_param' => 'Parameter',
'global_param' => 'Localparam',
'default' => '4',
'type' => 'Fixed'
},
'ni_V' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2'
},
'ni_ROUTE_NAME' => {
'default' => '"XY"',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
}
},
'ports' => {
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'ni_flit_out_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'type' => 'output'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
}
},
'module' => 'ni_master',
'module_name' => 'ni_master',
'localparam' => {
'ni_Fw' => {
'default' => '2+ni_V+ni_Fpay',
'info' => undef,
'timer_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'content' => ''
},
'timer_PRESCALER_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '8',
'type' => 'Spin-button',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'content' => '1,32,1'
},
'timer_Dw' => {
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => undef
},
'timer_TAGw' => {
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'redefine_param' => 0
},
'ni_MAX_TRANSACTION_WIDTH' => {
'redefine_param' => 1,
'content' => '4,32,1',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'default' => '13'
},
'ni_MAX_BURST_SIZE' => {
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1,
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ni_S_Aw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_M_Aw' => {
'content' => 'Dw',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter'
},
'ni_HDATA_PRECAPw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'default' => 4,
'content' => '0,8,1',
'redefine_param' => 1
},
'ni_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '4',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'wishbone_bus data width in bits.',
'default' => '32',
'content' => '32,256,8',
'redefine_param' => 1
},
'ni_CRC_EN' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'default' => '"NO"',
'redefine_param' => 1,
'content' => '"YES","NO"'
}
},
'category' => 'NoC',
'instance' => 'ni'
},
'single_port_ram0' => {
'module_name' => 'wb_single_port_ram',
'localparam' => {
'ram1_CORE_NUM' => {
'info' => undef
}
},
'category' => 'Timer',
'instance' => 'timer',
'module_name' => 'timer'
},
'ProNoC_jtag_uart0' => {
'category' => 'Communication',
'parameters' => {
'uart_JTAG_CONNECT' => {
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box'
},
'uart_JSTATUSw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'default' => '8',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => 'CORE_ID',
'type' => 'Fixed',
'global_param' => 'Localparam'
'content' => ''
},
'ram1_MEM_CONTENT_FILE_NAME' => {
'type' => 'Entry',
'global_param' => 'Localparam',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"',
'redefine_param' => 1,
'content' => ''
},
'ram1_FPGA_VENDOR' => {
'content' => '"ALTERA","XILINX","GENERIC"',
'redefine_param' => 1,
'default' => '"XILINX"',
'info' => '',
'global_param' => 'Localparam',
'type' => 'Combo-box'
},
'ram1_INITIAL_EN' => {
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'default' => '"YES"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'redefine_param' => 1
},
'ram1_Aw' => {
'redefine_param' => 1,
'content' => '4,31,1',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '14',
'info' => 'Memory address width'
},
'ram1_BYTE_WR_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'default' => '"YES"',
'info' => 'Byte enable',
'global_param' => 'Localparam',
'type' => 'Combo-box'
},
'ram1_BTEw' => {
'info' => 'Parameter',
'default' => '2',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'ram1_TAGw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram1_WB_Aw' => {
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'default' => 'ram1_Aw+2',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'uart_J2WBw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'content' => '4,31,1'
'global_param' => 'Parameter',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'type' => 'Fixed'
},
'ram1_BURST_MODE' => {
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1
},
'ram1_SELw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'ram1_Dw/8',
'info' => 'Parameter'
},
'ram1_INIT_FILE_PATH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'SW_LOC',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'ram1_CTIw' => {
'default' => '3',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
}
},
'category' => 'RAM',
'instance' => 'ram1',
'parameters' => {
'ram1_Dw' => {
'redefine_param' => 1,
'content' => '8,1024,1',
'default' => '32',
'info' => 'Memory data width in Bits.',
'type' => 'Spin-button',
'global_param' => 'Parameter'
},
'ram1_JINDEXw' => {
'redefine_param' => 1,
'uart_JDw' => {
'content' => '',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JINDEXw' => {
'content' => '',
'info' => 'Parameter',
'default' => '8',
'global_param' => 'Parameter',
'type' => 'Fixed'
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram1_JAw' => {
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Entry',
'default' => '126-CORE_ID'
},
'uart_JAw' => {
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
'info' => 'Parameter'
},
'ram1_JTAG_CONNECT' => {
'redefine_param' => 1,
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'default' => '"XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'type' => 'Combo-box',
'global_param' => 'Parameter'
},
'ram1_J2WBw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(ram1_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram1_JDw+ram1_JAw : 1',
'info' => undef
},
'ram1_JTAG_INDEX' => {
'type' => 'Entry',
'global_param' => 'Parameter',
'default' => 'CORE_ID',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'redefine_param' => 1,
'content' => ''
},
'ram1_WB2Jw' => {
'default' => '(ram1_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram1_JSTATUSw+ram1_JINDEXw+1+ram1_JDw : 1',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram1_JSTATUSw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram1_JTAG_CHAIN' => {
'global_param' => 'Parameter',
'type' => 'Combo-box',
'default' => '4',
'uart_JTAG_CHAIN' => {
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'content' => '1,2,3,4',
'redefine_param' => 0
'global_param' => 'Parameter',
'redefine_param' => 0,
'default' => '3',
'type' => 'Combo-box'
},
'ram1_JDw' => {
'redefine_param' => 1,
'content' => '',
'default' => 'ram1_Dw',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
}
'uart_WB2Jw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'info' => '',
'content' => ''
}
},
'ports' => {
'ram1_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'ram1_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram1_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram1_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
}
},
'module' => 'single_port_ram'
},
'gpo0' => {
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
}
},
'module' => 'gpo',
'instance' => 'led',
'module_name' => 'gpo',
'localparam' => {
'led_PORT_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'output port width',
'default' => ' 1',
'content' => '1,32,1',
'redefine_param' => 1
},
'led_TAGw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => ' 3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'led_Dw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => 'led_PORT_WIDTH',
'content' => '',
'redefine_param' => 1
},
'led_SELw' => {
'default' => ' 4',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'led_Aw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => ' 2'
}
},
'category' => 'GPIO'
},
'clk_source0' => {
'module' => 'clk_source',
'ports' => {
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ss_clk_in' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input'
}
},
'instance' => 'ss',
'category' => 'Source',
'module_name' => 'clk_source'
}
}
}, 'ip_gen' ),
'tile_nums' => undef
},
'lm32_new_tile' => {
'top' => bless( {
'instance_ids' => {
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'localparam' => {
'bus_CTIw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'bus_M' => {
'content' => '1,256,1',
'redefine_param' => 1,
'default' => ' 4',
'info' => 'Number of wishbone master interface',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'bus_S' => {
'content' => '1,256,1',
'redefine_param' => 1,
'default' => 5,
'info' => 'Number of wishbone slave interface',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'bus_Dw' => {
'default' => '32',
'info' => 'The wishbone Bus data width in bits.',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'content' => '8,512,8',
'redefine_param' => 1
},
'bus_Aw' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '32',
'info' => 'The wishbone Bus address width',
'content' => '4,128,1',
'redefine_param' => 1
},
'bus_BTEw' => {
'info' => undef,
'default' => '2 ',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'bus_TAGw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => undef
},
'bus_SELw' => {
'default' => 'bus_Dw/8',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
}
},
'instance' => 'bus'
},
'ProNoC_jtag_uart0' => {
'module' => 'ProNoC_jtag_uart',
'ports' => {
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
},
'parameters' => {
'uart_JDw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '32'
},
'uart_WB2Jw' => {
'info' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'global_param' => 'Parameter',
'module' => 'ProNoC_jtag_uart',
'localparam' => {
'uart_BUFF_Aw' => {
'default' => '4',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '2,16,1',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.'
},
'uart_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter',
'content' => ''
},
'uart_JINDEXw' => {
'uart_TAGw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '3',
'info' => 'Parameter',
'default' => '8',
'content' => ''
},
'uart_SELw' => {
'content' => '',
'redefine_param' => 1
},
'uart_JSTATUSw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '8',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'default' => '126-CORE_ID',
'type' => 'Entry',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_BUFF_Aw' => {
'content' => '2,16,1',
'info' => 'Parameter',
'type' => 'Fixed',
'default' => '4',
'redefine_param' => 1,
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => '6',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.'
'global_param' => 'Localparam'
},
'uart_J2WBw' => {
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter',
'uart_Aw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'uart_JAw' => {
'info' => 'Parameter',
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'uart_JTAG_CONNECT' => {
'default' => '"XILINX_JTAG_WB"',
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"'
},
'uart_JTAG_CHAIN' => {
'global_param' => 'Parameter',
'type' => 'Combo-box',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '3',
'redefine_param' => 0,
'content' => '1,2,3,4'
}
},
'instance' => 'uart',
'category' => 'Communication',
'localparam' => {
'uart_SELw' => {
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'uart_TAGw' => {
'default' => '3',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'uart_Dw' => {
'content' => '',
'redefine_param' => 1,
'default' => '1',
'type' => 'Fixed'
}
},
'instance' => 'uart',
'module_name' => 'pronoc_jtag_uart',
'ports' => {
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0'
},
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
}
}
},
'wishbone_bus0' => {
'localparam' => {
'bus_SELw' => {
'type' => 'Fixed',
'default' => 'bus_Dw/8',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '32'
},
'uart_Aw' => {
'redefine_param' => 1,
'content' => '',
'default' => '1',
'info' => 'Parameter',
'info' => undef
},
'bus_CTIw' => {
'type' => 'Fixed',
'global_param' => 'Localparam'
}
},
'module_name' => 'pronoc_jtag_uart'
},
'lm32_new0' => {
'module_name' => 'lm32',
'category' => 'Processor',
'localparam' => {
'lm32_new_INTR_NUM' => {
'info' => undef,
'default' => '32',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
}
},
'instance' => 'lm32_new',
'ports' => {
'lm32_new_en_i' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'module' => 'lm32_new'
},
'clk_source0' => {
'module' => 'clk_source',
'ports' => {
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ss_clk_in' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input'
}
},
'instance' => 'ss',
'category' => 'Source',
'module_name' => 'clk_source'
},
'single_port_ram0' => {
'category' => 'RAM',
'localparam' => {
'ram_CTIw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '3'
},
'ram_INITIAL_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram_SELw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => 'ram_Dw/8',
'info' => 'Parameter'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Entry',
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . '
},
'ram_BTEw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '2',
'info' => 'Parameter'
'info' => undef
},
'ram_CORE_NUM' => {
'content' => '',
'redefine_param' => 1,
'default' => 'CORE_ID',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram_BURST_MODE' => {
'redefine_param' => 1,
'content' => '"DISABLED","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'default' => '"ENABLED"'
},
'ram_TAGw' => {
'bus_S' => {
'content' => '1,256,1',
'info' => 'Number of wishbone slave interface',
'default' => '4',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'bus_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '3'
'redefine_param' => 1
},
'ram_INIT_FILE_PATH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => 'SW_LOC',
'redefine_param' => 1,
'content' => ''
},
'ram_BYTE_WR_EN' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'Byte enable',
'default' => '"YES"',
'content' => '"YES","NO"',
'redefine_param' => 1
}
},
'module_name' => 'wb_single_port_ram',
'instance' => 'ram',
'parameters' => {
'ram_JTAG_CONNECT' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'redefine_param' => 1
},
'ram_JINDEXw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram_WB2Jw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'redefine_param' => 1,
'content' => ''
},
'ram_JAw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '32',
'redefine_param' => 1,
'content' => ''
},
'ram_JDw' => {
'info' => 'Parameter',
'default' => 'ram_Dw',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_FPGA_VENDOR' => {
'info' => '',
'default' => '"XILINX"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"'
},
'ram_JTAG_INDEX' => {
'type' => 'Entry',
'global_param' => 'Parameter',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'content' => '',
'redefine_param' => 1
},
'ram_JSTATUSw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'redefine_param' => 0,
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'ram_J2WBw' => {
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ram_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1',
'redefine_param' => 1
},
'ram_Aw' => {
'global_param' => 'Parameter',
'type' => 'Spin-button',
'info' => 'Memory address width',
'default' => '14',
'content' => '4,31,1',
'redefine_param' => 1
}
},
'module' => 'single_port_ram',
'ports' => {
'ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
}
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'redefine_param' => 1,
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => ' 1',
'info' => 'output port width'
}
},
'module' => 'gpo',
'ports' => {
'led_port_o' => {
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
},
'localparam' => {
'led_TAGw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => ' 3',
'redefine_param' => 1,
'content' => ''
},
'led_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => ' 4',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'led_Aw' => {
'info' => undef,
'default' => ' 2',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'led_Dw' => {
'info' => undef,
'default' => 'led_PORT_WIDTH',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
}
},
'category' => 'GPIO',
'module_name' => 'gpo',
'instance' => 'led'
},
'ni_master0' => {
'instance' => 'ni',
'module_name' => 'ni_master',
'category' => 'NoC',
'localparam' => {
'ni_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'wishbone_bus data width in bits.',
'default' => '32',
'content' => '32,256,8',
'redefine_param' => 1
},
'ni_SELw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '4'
},
'ni_TAGw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => 'Parameter'
},
'ni_CRC_EN' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'default' => '"NO"',
'redefine_param' => 1,
'content' => '"YES","NO"'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'content' => '4,32,1',
'redefine_param' => 1,
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'default' => '13'
},
'ni_Fw' => {
'redefine_param' => 0,
'content' => '',
'default' => '2+ni_V+ni_Fpay',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_HDATA_PRECAPw' => {
'default' => '4',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '0,8,1',
'redefine_param' => 1
},
'ni_M_Aw' => {
'default' => '32',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => 'Dw'
},
'ni_S_Aw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'ni_MAX_BURST_SIZE' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1
}
},
'ports' => {
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'type' => 'output'
}
},
'module' => 'ni_master',
'parameters' => {
'ni_TOPOLOGY' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '"MESH"',
'redefine_param' => 1,
'content' => ''
},
'ni_B' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '4',
'content' => '',
'redefine_param' => 1
},
'ni_DEBUG_EN' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '0'
},
'ni_T3' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '1'
},
'ni_BYTE_EN' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => 0,
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'ni_RAw' => {
'content' => '',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '16'
},
'ni_Fpay' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter'
},
'ni_T2' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '2',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_EAw' => {
'redefine_param' => 0,
'content' => '',
'info' => undef,
'default' => '16',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_ROUTE_NAME' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '"XY"'
},
'ni_V' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '2'
},
'ni_C' => {
'info' => 'Parameter',
'default' => 0,
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_T1' => {
'info' => 'Parameter',
'default' => '2',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
}
}
},
'timer0' => {
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'default' => '8'
}
},
'ports' => {
'timer_irq' => {
'type' => 'output',
'intfc_port' => 'int_o',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'range' => ''
}
},
'module' => 'timer',
'module_name' => 'timer',
'localparam' => {
'timer_TAGw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'timer_Aw' => {
'default' => '3',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'timer_CNTw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '32 '
},
'timer_SELw' => {
'default' => '4',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'timer_Dw' => {
'default' => '32',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
}
},
'category' => 'Timer',
'instance' => 'timer'
}
},
'ports' => {
'timer_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'instance_name' => 'timer0',
'intfc_name' => 'plug:interrupt_peripheral[0]'
},
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:clk[0]'
},
'ram_wb_to_jtag' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'lm32_new_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'lm32_new0',
'range' => '',
'intfc_name' => 'plug:enable[0]'
},
'ni_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_r_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'intfc_port' => 'jwb_o'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'lm32_new_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'instance_name' => 'lm32_new0'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_WB2Jw-1 : 0'
},
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0'
},
'uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0'
},
'ram_jtag_to_wb' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'type' => 'output',
'intfc_port' => 'IO'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'ni_current_r_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_flit_in_wr' => {
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'timer_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'range' => '',
'instance_name' => 'timer0'
}
}
}
},
'parameters' => {
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'uart_BUFF_Aw' => '6',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JSTATUSw' => '8',
'ram_FPGA_VENDOR' => '"XILINX"',
'uart_JTAG_CHAIN' => '3',
'ram_Aw' => '14',
'timer_PRESCALER_WIDTH' => '8',
'led_PORT_WIDTH' => ' 1',
'ram_JTAG_CHAIN' => '4',
'ram_Dw' => '32',
'uart_JINDEXw' => '8',
'ram_JAw' => '32',
'ram_JDw' => 'ram_Dw',
'ram_JINDEXw' => '8',
'uart_JDw' => '32'
}
}, 'ip_gen' ),
'tile_nums' => undef
},
'Tile' => {
'tile_nums' => undef,
'top' => bless( {
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'range' => '',
'instance_name' => 'ni_master0',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_out_wr' => {
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'ni_credit_out' => {
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out',
'type' => 'output'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram_wb_to_jtag' => {
'instance_name' => 'single_port_ram0',
'range' => 'WB2Jw-1 : 0',
'intfc_port' => 'wb_to_jtag',
'type' => 'output'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jtag_to_wb',
'instance_name' => 'single_port_ram0',
'range' => 'J2WBw-1 : 0'
}
}
},
'IO' => {
'ports' => {
'key_port_i' => {
'instance_name' => 'gpi0',
'range' => 'key_PORT_WIDTH-1 : 0',
'intfc_port' => 'IO',
'type' => 'input'
}
}
}
},
'parameters' => {
'cpu_FEATURE_DMMU' => '"ENABLED"',
'cpu_OPTION_OPERAND_WIDTH' => '32',
'cpu_OPTION_DCACHE_SNOOP' => '"ENABLED"',
'cpu_FEATURE_IMMU' => '"ENABLED"',
'ram_Aw' => 14,
'timer_PRESCALER_WIDTH' => '8',
'cpu_IRQ_NUM' => '32',
'key_PORT_WIDTH' => ' 1',
'ram_Dw' => '32',
'cpu_FEATURE_DATACACHE' => '"ENABLED"',
'cpu_FEATURE_INSTRUCTIONCACHE' => '"ENABLED"'
},
'instance_ids' => {
'gpi0' => {
'category' => 'GPIO',
'localparam' => {
'key_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => ' 4',
'redefine_param' => 1,
'content' => ''
},
'key_Dw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => 'key_PORT_WIDTH',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'key_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => ' 2',
'content' => '',
'redefine_param' => 1
},
'key_TAGw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => ' 3',
'type' => 'Fixed',
'global_param' => 'Localparam'
}
},
'module_name' => 'gpi',
'instance' => 'key',
'parameters' => {
'key_PORT_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'info' => 'Input port width ',
'default' => ' 1',
'redefine_param' => 1,
'content' => '1,32,1'
}
},
'module' => 'gpi',
'ports' => {
'key_port_i' => {
'type' => 'input',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'key_PORT_WIDTH-1 : 0'
}
}
},
'timer0' => {
'instance' => 'timer',
'localparam' => {
'timer_TAGw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'timer_CNTw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '32 ',
'redefine_param' => 1,
'content' => ''
},
'timer_Aw' => {
'redefine_param' => 1,
'content' => '',
'default' => '3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'timer_Dw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'timer_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '4',
'redefine_param' => 1,
'content' => ''
}
},
'category' => 'Timer',
'module_name' => 'timer',
'module' => 'timer',
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'global_param' => 'Parameter',
'type' => 'Spin-button',
'content' => '1,32,1',
'redefine_param' => 1
}
}
},
'ni_master0' => {
'instance' => 'ni',
'localparam' => {
'ni_CRC_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'default' => '"NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box'
},
'ni_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_SELw' => {
'info' => 'Parameter',
'default' => '4',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_Dw' => {
'content' => '32,256,8',
'redefine_param' => 1,
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'wishbone_bus data width in bits.',
'default' => '32'
},
'ni_MAX_BURST_SIZE' => {
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1
},
'ni_M_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw',
'redefine_param' => 1
},
'ni_S_Aw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '8',
'info' => 'Parameter'
},
'ni_Fw' => {
'content' => '',
'redefine_param' => 0,
'default' => '2+ni_V+ni_Fpay',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '4,32,1',
'redefine_param' => 1
}
},
'category' => 'NoC',
'module_name' => 'ni_master',
'module' => 'ni_master',
'ports' => {
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_in_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0'
}
},
'parameters' => {
'ni_TOPOLOGY' => {
'redefine_param' => 1,
'content' => '',
'default' => '"MESH"',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_B' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '4',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_DEBUG_EN' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '0',
'redefine_param' => 1,
'content' => ''
},
'ni_T3' => {
'default' => '1',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_RAw' => {
'redefine_param' => 0,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '16'
},
'ni_Fpay' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32'
},
'ni_EAw' => {
'default' => '16',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 0
},
'ni_T2' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2'
},
'ni_V' => {
'redefine_param' => 1,
'content' => '',
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_ROUTE_NAME' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '"XY"',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_C' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => 0,
'content' => '',
'redefine_param' => 1
},
'ni_T1' => {
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
}
}
},
'clk_source0' => {
'module' => 'clk_source',
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]'
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
},
'instance' => 'ss',
'category' => 'Source',
'module_name' => 'clk_source'
},
'single_port_ram0' => {
'module' => 'single_port_ram',
'ports' => {
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'wb_to_jtag'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jtag_to_wb',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'J2WBw-1 : 0'
}
},
'parameters' => {
'ram_Dw' => {
'default' => '32',
'info' => 'Memory data width in Bits.',
'global_param' => 'Parameter',
'type' => 'Spin-button',
'content' => '8,1024,1',
'redefine_param' => 1
},
'ram_Aw' => {
'content' => '4,31,1',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button',
'default' => 14,
'info' => 'Memory address width'
}
},
'instance' => 'ram',
'category' => 'RAM',
'localparam' => {
'ram_MEM_CONTENT_FILE_NAME' => {
'type' => 'Entry',
'global_param' => 'Localparam',
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'content' => '',
'redefine_param' => 1
},
'ram_BTEw' => {
'redefine_param' => 1,
'content' => '',
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ram_JTAG_CONNECT' => {
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'redefine_param' => 1,
'default' => ' "ALTERA_JTAG_WB" ',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ram_CTIw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram_INITIAL_EN' => {
'content' => '"YES","NO"',
'redefine_param' => 1,
'type' => 'Combo-box',
'bus_M' => {
'content' => '1,256,1',
'info' => 'Number of wishbone master interface',
'type' => 'Spin-button',
'default' => ' 4',
'global_param' => 'Localparam',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'default' => '"YES"'
'redefine_param' => 1
},
'ram_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => 'ram_Dw/8',
'content' => '',
'redefine_param' => 1
},
'ram_JTAG_INDEX' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Entry',
'global_param' => 'Localparam',
'default' => 'CORE_ID',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
'
},
'ram_TAGw' => {
'info' => 'Parameter',
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ram_FPGA_VENDOR' => {
'info' => '',
'default' => '"ALTERA"',
'bus_Dw' => {
'info' => 'The wishbone Bus data width in bits.',
'content' => '8,512,8',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"'
'type' => 'Spin-button',
'default' => '32'
},
'ram_INIT_FILE_PATH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'SW_LOC',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'ram_BYTE_WR_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'Byte enable',
'default' => '"YES"'
},
'ram_BURST_MODE' => {
'redefine_param' => 1,
'content' => '"DISABLED","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. '
}
},
'module_name' => 'wb_single_port_ram'
},
'mor1kx0' => {
'instance' => 'cpu',
'category' => 'Processor',
'module_name' => 'mor1k',
'module' => 'mor1kx',
'ports' => {
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:enable[0]'
}
},
'parameters' => {
'cpu_FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'info' => '',
'default' => '"ENABLED"',
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'default' => '"ENABLED"',
'info' => '',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"'
},
'cpu_FEATURE_IMMU' => {
'info' => '',
'default' => '"ENABLED"',
'global_param' => 'Parameter',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"ENABLED"',
'info' => ''
},
'cpu_IRQ_NUM' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'cpu_FEATURE_DMMU' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'default' => '"ENABLED"',
'info' => '',
'type' => 'Combo-box',
'global_param' => 'Parameter'
},
'cpu_OPTION_OPERAND_WIDTH' => {
'bus_Aw' => {
'info' => 'The wishbone Bus address width',
'content' => '4,128,1',
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
}
}
},
'wishbone_bus0' => {
'category' => 'Bus',
'localparam' => {
'bus_M' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => 4,
'info' => 'Number of wishbone master interface',
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_CTIw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef
},
'bus_Dw' => {
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '8,512,8'
},
'bus_S' => {
'content' => '1,256,1',
'redefine_param' => 1,
'info' => 'Number of wishbone slave interface',
'default' => 5,
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'bus_TAGw' => {
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'bus_BTEw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '2 ',
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'bus_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => 'bus_Dw/8',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_Aw' => {
'content' => '4,128,1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '32',
'info' => 'The wishbone Bus address width'
}
},
'module_name' => 'wishbone_bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'jtag_uart0' => {
'instance' => 'uart',
'category' => 'Communication',
'localparam' => {
'uart_SIM_WAIT_COUNT' => {
'info' => 'This parameter is valid only in simulation.
If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.',
'default' => '1000',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '2,100000,1'
},
'uart_SIM_BUFFER_SIZE' => {
'info' => 'Internal buffer size.
This parameter is valid only in simulation.
If internal buffer overflows, the buffer content are displayed on simulator terminal.',
'default' => 1000,
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '10,10000,1'
},
'uart_FPGA_VENDOR' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => ' "ALTERA"',
'info' => 'FPGA VENDOR name. Only Altera FPGA is supported. Currently the Generic serial port is not supported. ',
'redefine_param' => 1,
'content' => ' "ALTERA"'
}
},
'module_name' => 'jtag_uart_wb',
'module' => 'jtag_uart'
}
},
'ports' => {
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => ''
},
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'single_port_ram0',
'range' => 'WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'wb_to_jtag'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => ''
},
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_name' => 'plug:enable[0]'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'ss_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0'
},
'ni_flit_out' => {
'type' => 'output',
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0'
},
'key_port_i' => {
'intfc_name' => 'IO',
'instance_name' => 'gpi0',
'range' => 'key_PORT_WIDTH-1 : 0',
'type' => 'input',
'intfc_port' => 'IO'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jtag_to_wb',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'J2WBw-1 : 0',
'instance_name' => 'single_port_ram0'
}
}
}, 'ip_gen' )
},
'mor1k_tile_kc' => {
'top' => bless( {
'instance_ids' => {
'clk_source0' => {
'module' => 'clk_source',
'ports' => {
'ss_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => ''
},
'ss_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => ''
}
},
'instance' => 'ss',
'category' => 'Source',
'module_name' => 'clk_source'
},
'single_port_ram0' => {
'instance' => 'ram',
'module_name' => 'wb_single_port_ram',
'category' => 'RAM',
'localparam' => {
'ram_TAGw' => {
'type' => 'Spin-button'
},
'bus_BTEw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'default' => '3',
'info' => 'Parameter',
'global_param' => 'Localparam',
'default' => '2 ',
'type' => 'Fixed'
},
'ram_JTAG_INDEX' => {
'content' => '',
'redefine_param' => 1,
'default' => 'CORE_ID',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'global_param' => 'Localparam',
'type' => 'Entry'
},
'ram_BYTE_WR_EN' => {
'content' => '"YES","NO"',
'redefine_param' => 1,
'info' => 'Byte enable',
'default' => '"YES"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ram_INIT_FILE_PATH' => {
'content' => '',
'redefine_param' => 1,
'default' => 'SW_LOC',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ram_CORE_NUM' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => 'CORE_ID',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_BURST_MODE' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'redefine_param' => 1,
'content' => '"DISABLED","ENABLED"'
},
'ram_BTEw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '2',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Entry',
'global_param' => 'Localparam',
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . '
},
'ram_CTIw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => 'Parameter'
},
'ram_SELw' => {
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ram_INITIAL_EN' => {
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"YES","NO"'
}
}
},
'ports' => {
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
}
},
'module' => 'single_port_ram',
'parameters' => {
'ram_JTAG_CONNECT' => {
'module' => 'wishbone_bus',
'category' => 'Bus',
'module_name' => 'wishbone_bus',
'instance' => 'bus'
},
'clk_source0' => {
'category' => 'Source',
'module' => 'clk_source',
'localparam' => {
'source_FPGA_VENDOR' => {
'default' => '"ALTERA"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'redefine_param' => 1
},
'ram_JDw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => 'ram_Dw',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ram_JAw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32'
},
'ram_WB2Jw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'redefine_param' => 1,
'content' => ''
},
'ram_JINDEXw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram_JSTATUSw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '8',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_FPGA_VENDOR' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'info' => '',
'default' => '"XILINX"',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"'
},
'ram_Aw' => {
'content' => '4,31,1',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Spin-button',
'default' => '14',
'info' => 'Memory address width'
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX"',
'info' => ''
}
},
'ports' => {
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ram_Dw' => {
'redefine_param' => 1,
'content' => '8,1024,1',
'info' => 'Memory data width in Bits.',
'default' => '32',
'type' => 'Spin-button',
'global_param' => 'Parameter'
},
'ram_J2WBw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'type' => 'Fixed',
'global_param' => 'Parameter'
'source_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => ''
}
},
'instance' => 'source',
'module_name' => 'clk_source'
},
'ni_master0' => {
'ports' => {
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0'
},
'ram_JTAG_CHAIN' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'redefine_param' => 0,
'content' => '1,2,3,4'
}
}
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'content' => '1,32,1',
'redefine_param' => 1,
'default' => ' 1',
'info' => 'output port width',
'global_param' => 'Parameter',
'type' => 'Spin-button'
}
},
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
}
},
'module' => 'gpo',
'module_name' => 'gpo',
'localparam' => {
'led_TAGw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => ' 3',
'info' => undef
},
'led_Dw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => 'led_PORT_WIDTH'
},
'led_SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => ' 4',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'led_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => ' 2',
'redefine_param' => 1,
'content' => ''
}
},
'category' => 'GPIO',
'instance' => 'led'
},
'ni_master0' => {
'module_name' => 'ni_master',
'localparam' => {
'ni_S_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_M_Aw' => {
'redefine_param' => 1,
'content' => 'Dw',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '32'
},
'ni_HDATA_PRECAPw' => {
'content' => '0,8,1',
'redefine_param' => 1,
'default' => '4',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'ni_MAX_BURST_SIZE' => {
'redefine_param' => 1,
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. '
},
'ni_MAX_TRANSACTION_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'default' => '13',
'content' => '4,32,1',
'redefine_param' => 1
},
'ni_Fw' => {
'info' => undef,
'default' => '2+ni_V+ni_Fpay',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 0
},
'ni_CRC_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '
},
'ni_Dw' => {
'default' => '32',
'info' => 'wishbone_bus data width in bits.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '32,256,8',
'redefine_param' => 1
},
'ni_TAGw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_SELw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '4',
'info' => 'Parameter'
}
},
'category' => 'NoC',
'instance' => 'ni',
'parameters' => {
'ni_T1' => {
'info' => 'Parameter',
'default' => ' 4',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_C' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => ' 4',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_T2' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => ' 4',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_EAw' => {
'redefine_param' => 0,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => undef,
'default' => '16'
},
'ni_V' => {
'info' => 'Parameter',
'default' => '4',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_ROUTE_NAME' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '"XY" ',
'info' => 'Parameter'
},
'ni_T3' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '1',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_RAw' => {
'content' => '',
'redefine_param' => 0,
'info' => undef,
'default' => '16',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_Fpay' => {
'redefine_param' => 1,
'content' => '',
'default' => ' 32',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_BYTE_EN' => {
'info' => undef,
'default' => '0',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_TOPOLOGY' => {
'default' => '"MESH"',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_B' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => ' 4',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_DEBUG_EN' => {
'default' => ' 1',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
}
},
'ports' => {
'ni_flit_in' => {
'type' => 'input',
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0'
},
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_in_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_credit_out' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'ni_chan_out' => {
'type' => 'output',
'range' => '',
'intfc_port' => 'chan_out',
'range' => 'smartflit_chanel_t',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
}
},
'module' => 'ni_master'
},
'timer0' => {
'module_name' => 'timer',
'category' => 'Timer',
'localparam' => {
'timer_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => '4',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'timer_Dw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '32',
'content' => '',
'redefine_param' => 1
},
'timer_CNTw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '32 '
},
'timer_Aw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef
},
'timer_TAGw' => {
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
}
},
'instance' => 'timer',
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
'
}
},
'module' => 'timer'
},
'wishbone_bus0' => {
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'localparam' => {
'bus_S' => {
'default' => 5,
'info' => 'Number of wishbone slave interface',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '1,256,1'
'ni_chan_in' => {
'intfc_port' => 'chan_in',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'bus_Dw' => {
'default' => '32',
'info' => 'The wishbone Bus data width in bits.',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'content' => '8,512,8',
'redefine_param' => 1
},
'bus_CTIw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '3'
},
'bus_M' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'Number of wishbone master interface',
'default' => ' 4',
'content' => '1,256,1',
'redefine_param' => 1
},
'bus_Aw' => {
'redefine_param' => 1,
'content' => '4,128,1',
'info' => 'The wishbone Bus address width',
'default' => '32',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'bus_SELw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => 'bus_Dw/8',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_BTEw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '2 ',
'info' => undef,
'redefine_param' => 1,
'content' => ''
}
},
'category' => 'Bus',
'module' => 'wishbone_bus'
},
'ProNoC_jtag_uart0' => {
'parameters' => {
'uart_JINDEXw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_JSTATUSw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '8',
'redefine_param' => 1,
'content' => ''
},
'uart_WB2Jw' => {
'redefine_param' => 1,
'content' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'uart_JDw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_JTAG_CONNECT' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"XILINX_JTAG_WB"',
'info' => undef,
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'redefine_param' => 1
},
'uart_JAw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32'
},
'uart_JTAG_CHAIN' => {
'default' => '3',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'content' => '1,2,3,4',
'redefine_param' => 0
},
'uart_BUFF_Aw' => {
'redefine_param' => 1,
'content' => '2,16,1',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'default' => '6',
'type' => 'Spin-button',
'global_param' => 'Parameter'
},
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'default' => '126-CORE_ID',
'type' => 'Entry',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'uart_J2WBw' => {
'content' => '',
'redefine_param' => 1,
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter'
}
},
'ports' => {
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
}
},
'module' => 'ProNoC_jtag_uart',
'module_name' => 'pronoc_jtag_uart',
'category' => 'Communication',
'localparam' => {
'uart_TAGw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '3'
},
'uart_Aw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '1',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'uart_Dw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter'
},
'uart_SELw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '4',
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'instance' => 'uart'
},
'mor1kx0' => {
'category' => 'Processor',
'module_name' => 'mor1k',
'instance' => 'cpu',
'parameters' => {
'cpu_IRQ_NUM' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'cpu_FEATURE_DMMU' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'default' => '"ENABLED"',
'info' => '',
'type' => 'Combo-box',
'global_param' => 'Parameter'
},
'cpu_OPTION_OPERAND_WIDTH' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Combo-box',
'info' => '',
'default' => '"ENABLED"'
},
'cpu_FEATURE_DATACACHE' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"ENABLED"',
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"ENABLED"',
'info' => ''
},
'cpu_FEATURE_IMMU' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'global_param' => 'Parameter',
'type' => 'Combo-box'
}
},
'module' => 'mor1kx',
'ports' => {
'cpu_cpu_en' => {
'type' => 'input',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'range' => ''
}
}
}
},
'ports' => {
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out',
'type' => 'output'
},
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
},
'ni_current_r_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_in_wr' => {
'range' => '',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
},
'interface' => {
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'instance_name' => 'mor1kx0',
'intfc_port' => 'enable_i',
'type' => 'input'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'uart_jtag_to_wb' => {
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0'
},
'uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_WB2Jw-1 : 0'
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => ''
},
'ni_credit_in' => {
'type' => 'input',
'intfc_port' => 'credit_in',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_current_r_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => ''
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_out',
'type' => 'output'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
}
}
}
},
'parameters' => {
'cpu_FEATURE_DMMU' => '"ENABLED"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'cpu_FEATURE_IMMU' => '"ENABLED"',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'cpu_OPTION_DCACHE_SNOOP' => '"ENABLED"',
'uart_BUFF_Aw' => '6',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'cpu_FEATURE_DATACACHE' => '"ENABLED"',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JAw' => '32',
'ram_JINDEXw' => '8',
'cpu_OPTION_OPERAND_WIDTH' => '32',
'uart_JDw' => '32',
'ram_JAw' => '32',
'ram_JDw' => 'ram_Dw',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_Dw' => '32',
'ram_Aw' => '14',
'timer_PRESCALER_WIDTH' => '8',
'led_PORT_WIDTH' => ' 1',
'cpu_IRQ_NUM' => '32',
'ram_FPGA_VENDOR' => '"XILINX"',
'cpu_FEATURE_INSTRUCTIONCACHE' => '"ENABLED"',
'uart_JTAG_CHAIN' => '3',
'ram_JSTATUSw' => '8'
}
}, 'ip_gen' ),
'tile_nums' => undef
},
'ooo' => {
'tile_nums' => undef,
'top' => bless( {
'ports' => {
'ni_master0_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_master0_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_master0_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_master0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_master0_irq' => {
'intfc_port' => 'int_o',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]'
},
'ni_master0_flit_out' => {
'type' => 'output',
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_Fw-1 : 0'
},
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'ni_master0_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'bus_snoop_adr_o' => {
'intfc_port' => 'snoop_adr_o',
'type' => 'output',
'instance_name' => 'wishbone_bus0',
'range' => 'bus_Aw-1 : 0',
'intfc_name' => 'socket:snoop[0]'
},
'ni_master0_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'bus_snoop_en_o' => {
'intfc_name' => 'socket:snoop[0]',
'range' => '',
'instance_name' => 'wishbone_bus0',
'type' => 'output',
'intfc_port' => 'snoop_en_o'
},
'ni_master0_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ss_clk_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input'
}
},
'instance_ids' => {
'clk_source0' => {
'instance' => 'ss',
'module_name' => 'clk_source',
'category' => 'Source',
'ports' => {
'ss_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
}
},
'module' => 'clk_source',
'parameters' => {
'ss_FPGA_VENDOR' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"ALTERA"',
'info' => '',
'content' => '"ALTERA","XILINX"',
'redefine_param' => 1
}
}
},
'wishbone_bus0' => {
'category' => 'Bus',
'localparam' => {
'bus_Aw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'The wishbone Bus address width',
'default' => '32',
'redefine_param' => 1,
'content' => '4,128,1'
},
'bus_CTIw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '3',
'content' => '',
'redefine_param' => 1
},
'bus_BTEw' => {
'content' => '',
'redefine_param' => 1,
'default' => '2 ',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_TAGw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef
},
'bus_S' => {
'info' => 'Number of wishbone slave interface',
'default' => '4',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'content' => '1,256,1',
'redefine_param' => 1
},
'bus_SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => 'bus_Dw/8',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'The wishbone Bus data width in bits.',
'content' => '8,512,8',
'redefine_param' => 1
}
},
'module_name' => 'wishbone_bus',
'instance' => 'bus',
'parameters' => {
'bus_M' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => ' 4',
'info' => 'Number of wishbone master interface',
'redefine_param' => 1,
'content' => '1,256,1'
}
},
'module' => 'wishbone_bus',
'ports' => {
'bus_snoop_en_o' => {
'range' => '',
'intfc_name' => 'socket:snoop[0]',
'intfc_port' => 'snoop_en_o',
'type' => 'output'
},
'bus_snoop_adr_o' => {
'intfc_name' => 'socket:snoop[0]',
'range' => 'bus_Aw-1 : 0',
'type' => 'output',
'intfc_port' => 'snoop_adr_o'
}
}
},
'ni_master0' => {
'ports' => {
'ni_master0_credit_out' => {
'range' => 'ni_master0_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_out',
'type' => 'output'
},
'ni_master0_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_master0_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_master0_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_master0_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_master0_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_master0_V-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_master0_flit_out' => {
'type' => 'output',
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_master0_Fw-1 : 0'
},
'ni_master0_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_master0_irq' => {
'range' => '',
'intfc_name' => 'plug:interrupt_peripheral[0]',
'intfc_port' => 'int_o',
'type' => 'output'
},
'ni_master0_flit_out_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ni_master0_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_master0_EAw-1 : 0'
}
},
'module' => 'ni_master',
'parameters' => {
'ni_master0_Fpay' => {
'default' => '32',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ni_master0_T1' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '2',
'info' => 'Parameter'
},
'ni_master0_TOPOLOGY' => {
'info' => 'Parameter',
'default' => '"MESH"',
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_e_addr',
'type' => 'input'
}
},
'instance' => 'ni',
'module_name' => 'ni_master',
'category' => 'NoC',
'parameters' => {
'ni_RAw' => {
'content' => '',
'info' => undef,
'default' => '16',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
'redefine_param' => 0,
'global_param' => 'Parameter'
},
'ni_master0_BYTE_EN' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => 0,
'redefine_param' => 1,
'content' => ''
},
'ni_master0_DEBUG_EN' => {
'info' => 'Parameter',
'default' => '0',
'ni_EAw' => {
'global_param' => 'Parameter',
'redefine_param' => 0,
'default' => '16',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_master0_ROUTE_NAME' => {
'info' => 'Parameter',
'default' => '"XY"',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_master0_C' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => 0,
'info' => 'Parameter'
},
'ni_master0_B' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '4'
},
'ni_master0_EAw' => {
'content' => '',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '16'
},
'ni_master0_RAw' => {
'content' => '',
'redefine_param' => 0,
'info' => undef,
'default' => '16',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_master0_T2' => {
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_master0_V' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '2',
'info' => 'Parameter'
},
'ni_master0_T3' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '1',
'redefine_param' => 1,
'content' => ''
}
},
'instance' => 'ni_master0',
'module_name' => 'ni_master',
'category' => 'NoC',
'localparam' => {
'ni_master0_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ni_master0_S_Aw' => {
'info' => 'Parameter',
'default' => '8',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ni_master0_M_Aw' => {
'content' => 'Dw',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_master0_HDATA_PRECAPw' => {
'default' => '0',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '0,8,1'
},
'ni_master0_CRC_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ni_master0_Fw' => {
'info' => undef,
'default' => '2+ni_master0_V+ni_master0_Fpay',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 0,
'content' => ''
},
'ni_master0_Dw' => {
'default' => '32',
'info' => 'wishbone_bus data width in bits.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '32,256,8'
},
'ni_master0_MAX_BURST_SIZE' => {
'redefine_param' => 1,
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'info' => 'Maximum burst size in words.
'info' => undef,
'content' => ''
}
},
'module' => 'ni_master',
'localparam' => {
'ni_MAX_BURST_SIZE' => {
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ni_master0_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '4',
'redefine_param' => 1,
'content' => ''
},
'ni_master0_MAX_TRANSACTION_WIDTH' => {
'redefine_param' => 1,
'content' => '4,32,1',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '13',
'info' => 'maximum packet size width in words.
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '16',
'type' => 'Combo-box'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'default' => '13',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '4,32,1',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.'
}
}
}
},
'parameters' => {
'ss_FPGA_VENDOR' => '"ALTERA"',
'bus_M' => ' 4'
},
'interface' => {
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'plug:interrupt_peripheral[0]' => {
'ports' => {
'ni_master0_irq' => {
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'int_o'
}
}
},
'socket:snoop[0]' => {
'ports' => {
'bus_snoop_en_o' => {
'intfc_port' => 'snoop_en_o',
'type' => 'output',
'range' => '',
'instance_name' => 'wishbone_bus0'
},
'bus_snoop_adr_o' => {
'range' => 'bus_Aw-1 : 0',
'instance_name' => 'wishbone_bus0',
'type' => 'output',
'intfc_port' => 'snoop_adr_o'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_master0_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_master0_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_master0_credit_in' => {
'range' => 'ni_master0_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_master0_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_master0_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_master0_V-1 : 0'
},
'ni_master0_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'range' => 'ni_master0_RAw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_master0_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_master0_Fw-1 : 0',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_master0_current_e_addr' => {
'range' => 'ni_master0_EAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_master0_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => ''
}
}
}
}
}, 'ip_gen' )
},
'mor1k_tile' => {
'tile_nums' => [
0,
1,
2,
3
],
'top' => bless( {
'parameters' => {
'uart_JSTATUSw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'uart_JINDEXw' => '8',
'ram_JDw' => 'ram_Dw',
'ram_JAw' => '32',
'uart_JDw' => '32',
'ram_JINDEXw' => '8',
'ram_JSTATUSw' => '8',
'uart_JTAG_CHAIN' => '3',
'ram_Aw' => '14',
'ram_Dw' => '32',
'ram_JTAG_CHAIN' => '4'
},
'tiles' => {
'2' => {},
'1' => {},
'0' => {},
'3' => {}
},
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_flit_in' => {
'type' => 'input',
'intfc_port' => 'flit_in',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_credit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'instance_name' => 'ni_master0',
'range' => ''
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'instance_name' => 'ni_master0'
},
'ni_current_r_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0'
}
}
},
'plug:reset[0]' => {
'ports' => {
'cs_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:clk[0]' => {
'ports' => {
'cs_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'range' => '',
'instance_name' => 'clk_source0'
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_ready_sim' => {
'instance_name' => 'ProNoC_jtag_uart1',
'range' => '',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output'
},
'uart_RxD_wr_sim' => {
'range' => '',
'instance_name' => 'ProNoC_jtag_uart1',
'intfc_port' => 'RxD_wr_sim',
'type' => 'input'
},
'uart_RxD_din_sim' => {
'instance_name' => 'ProNoC_jtag_uart1',
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'type' => 'input',
'intfc_port' => 'enable_i',
'instance_name' => 'mor1kx0',
'range' => ''
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram_jtag_to_wb' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart1'
},
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart1'
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0'
}
}
}
},
'ports' => {
'ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'cs_clk_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input'
},
'ni_flit_out_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart1',
'type' => 'input',
'intfc_port' => 'RxD_din_sim'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'cs_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'uart_RxD_wr_sim' => {
'instance_name' => 'ProNoC_jtag_uart1',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_wr_sim',
'type' => 'input'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'cpu_cpu_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_name' => 'plug:enable[0]'
},
'ni_current_e_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'instance_name' => 'gpo0',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'type' => 'input'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart1',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'uart_RxD_ready_sim' => {
'range' => '',
'instance_name' => 'ProNoC_jtag_uart1',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_ready_sim',
'type' => 'output'
}
},
'instance_ids' => {
'mor1kx0' => {
'module' => 'mor1kx',
'ports' => {
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'instance' => 'cpu',
'category' => 'Processor',
'localparam' => {
'cpu_IRQ_NUM' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => undef
},
'cpu_OPTION_OPERAND_WIDTH' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32',
'content' => '',
'redefine_param' => 1
},
'cpu_FEATURE_DMMU' => {
},
'ni_M_Aw' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => ''
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw'
},
'cpu_FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => ''
},
'cpu_OPTION_DCACHE_SNOOP' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'info' => '',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"'
},
'cpu_FEATURE_IMMU' => {
'content' => '"NONE","ENABLED"',
'ni_S_Aw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => '',
'default' => '"ENABLED"'
'default' => '8',
'type' => 'Fixed'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => '',
'default' => '"ENABLED"'
}
},
'module_name' => 'mor1k'
},
'ProNoC_jtag_uart1' => {
'instance' => 'uart',
'module_name' => 'pronoc_jtag_uart',
'localparam' => {
'uart_Aw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '1',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_Dw' => {
'redefine_param' => 1,
'content' => '',
'default' => '32',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'uart_TAGw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '3'
},
'uart_SELw' => {
'info' => 'Parameter',
'default' => '4',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'uart_BUFF_Aw' => {
'default' => '4',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '2,16,1'
}
},
'category' => 'Communication',
'ports' => {
'uart_RxD_ready_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'type' => 'output',
'intfc_port' => 'RxD_ready_sim'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0'
},
'uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]'
},
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
}
},
'module' => 'ProNoC_jtag_uart',
'parameters' => {
'uart_JTAG_CHAIN' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '3',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'redefine_param' => 0,
'content' => '1,2,3,4'
},
'uart_JTAG_CONNECT' => {
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'default' => '"XILINX_JTAG_WB"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"'
},
'uart_JAw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'uart_J2WBw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'uart_JTAG_INDEX' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Entry',
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'default' => '126-CORE_ID'
},
'uart_JSTATUSw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '8'
},
'uart_JINDEXw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '8',
'content' => '',
'redefine_param' => 1
},
'uart_JDw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_WB2Jw' => {
'redefine_param' => 1,
'content' => '',
'info' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'global_param' => 'Parameter',
'type' => 'Fixed'
}
}
},
'wishbone_bus0' => {
'category' => 'Bus',
'localparam' => {
'bus_M' => {
'default' => ' 4',
'info' => 'Number of wishbone master interface',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_CTIw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '3',
'info' => undef,
'content' => '',
'redefine_param' => 1
},
'bus_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'redefine_param' => 1,
'content' => '8,512,8'
},
'bus_S' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'Number of wishbone slave interface',
'default' => 5,
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_TAGw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => undef
},
'bus_BTEw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '2 '
},
'bus_SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => 'bus_Dw/8',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'bus_Aw' => {
'content' => '4,128,1',
'redefine_param' => 1,
'default' => '32',
'info' => 'The wishbone Bus address width',
'type' => 'Spin-button',
'global_param' => 'Localparam'
}
},
'module_name' => 'wishbone_bus',
'instance' => 'bus',
'module' => 'wishbone_bus'
},
'timer0' => {
'module' => 'timer',
'localparam' => {
'timer_TAGw' => {
'default' => '3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'timer_PRESCALER_WIDTH' => {
'content' => '1,32,1',
'redefine_param' => 1,
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'global_param' => 'Localparam',
'type' => 'Spin-button'
},
'timer_Aw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'timer_CNTw' => {
'info' => undef,
'default' => '32 ',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'timer_Dw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '32',
'redefine_param' => 1,
'content' => ''
},
'timer_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => '4',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam'
}
},
'category' => 'Timer',
'module_name' => 'timer',
'instance' => 'timer'
},
'ni_master0' => {
'parameters' => {
'ni_C' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => 0,
'info' => 'Parameter'
},
'ni_T1' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2',
'content' => '',
'redefine_param' => 1
},
'ni_T2' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '2',
'info' => 'Parameter'
},
'ni_EAw' => {
'info' => undef,
'default' => '16',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 0
},
'ni_ROUTE_NAME' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '"XY"',
'ni_SELw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'content' => ''
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '4'
},
'ni_V' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2'
},
'ni_T3' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '1'
},
'ni_BYTE_EN' => {
'info' => undef,
'default' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ni_Fpay' => {
'default' => '32',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ni_RAw' => {
'redefine_param' => 0,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '16',
'info' => undef
},
'ni_TOPOLOGY' => {
'info' => 'Parameter',
'default' => '"MESH"',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_DEBUG_EN' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '0',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_B' => {
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
}
},
'module' => 'ni_master',
'ports' => {
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'output',
'intfc_port' => 'flit_out'
},
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'credit_in',
'type' => 'input'
}
},
'localparam' => {
'ni_CRC_EN' => {
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'default' => '"NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'redefine_param' => 1
},
'ni_Dw' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'wishbone_bus data width in bits.',
'default' => '32',
'redefine_param' => 1,
'content' => '32,256,8'
},
'ni_TAGw' => {
'content' => '',
'redefine_param' => 1,
'default' => '3',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '4',
'redefine_param' => 1,
'content' => ''
},
'ni_S_Aw' => {
'redefine_param' => 1,
'content' => '',
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ni_M_Aw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32',
'redefine_param' => 1,
'content' => 'Dw'
},
'ni_HDATA_PRECAPw' => {
'redefine_param' => 1,
'content' => '0,8,1',
'default' => '4',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'ni_MAX_BURST_SIZE' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '16',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1
},
'ni_MAX_TRANSACTION_WIDTH' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1',
'redefine_param' => 1
},
'ni_Fw' => {
'redefine_param' => 0,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '2+ni_V+ni_Fpay',
'info' => undef
}
},
'category' => 'NoC',
'module_name' => 'ni_master',
'instance' => 'ni'
},
'single_port_ram0' => {
'parameters' => {
'ram_JDw' => {
'global_param' => 'Parameter',
'ni_TAGw' => {
'default' => '3',
'type' => 'Fixed',
'default' => 'ram_Dw',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_JAw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
'info' => 'Parameter'
},
'ram_WB2Jw' => {
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'ni_CRC_EN' => {
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
'type' => 'Combo-box',
'default' => '"NO"'
},
'ram_JINDEXw' => {
'redefine_param' => 1,
'content' => '',
'default' => '8',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ram_JTAG_CONNECT' => {
'ni_Dw' => {
'default' => '32',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '32,256,8',
'info' => 'wishbone_bus data width in bits.'
},
'ni_HDATA_PRECAPw' => {
'type' => 'Spin-button',
'default' => '0',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'global_param' => 'Parameter',
'content' => '0,8,1',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.'
}
}
},
'mor1kx0' => {
'category' => 'Processor',
'localparam' => {
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"'
},
'cpu_OPTION_SHIFTER' => {
'info' => 'Specify the shifter implementation',
'content' => '"BARREL","SERIAL"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"BARREL"'
},
'cpu_FEATURE_DMMU' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'type' => 'Combo-box'
},
'cpu_FEATURE_MULTIPLIER' => {
'type' => 'Combo-box',
'default' => '"THREESTAGE"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'info' => 'Specify the multiplier implementation'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'default' => '"ENABLED"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"',
'info' => ''
},
'cpu_OPTION_OPERAND_WIDTH' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32'
},
'cpu_FEATURE_IMMU' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Combo-box',
'default' => '"ENABLED"'
},
'cpu_FEATURE_DIVIDER' => {
'default' => '"SERIAL"',
'type' => 'Combo-box',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"XILINX_JTAG_WB"'
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"SERIAL","NONE"',
'info' => 'Specify the divider implementation'
},
'ram_Aw' => {
'default' => '14',
'info' => 'Memory address width',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'content' => '4,31,1',
'redefine_param' => 1
},
'ram_Dw' => {
'content' => '8,1024,1',
'redefine_param' => 1,
'default' => '32',
'info' => 'Memory data width in Bits.',
'type' => 'Spin-button',
'global_param' => 'Parameter'
},
'ram_JTAG_CHAIN' => {
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'global_param' => 'Parameter',
'type' => 'Combo-box',
'content' => '1,2,3,4',
'redefine_param' => 0
},
'ram_J2WBw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'info' => undef
},
'ram_JSTATUSw' => {
'content' => '',
'redefine_param' => 1,
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ram_JTAG_INDEX' => {
'content' => '',
'redefine_param' => 1,
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID',
'type' => 'Entry',
'global_param' => 'Parameter'
}
},
'module' => 'single_port_ram',
'ports' => {
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
},
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
},
'localparam' => {
'ram_CTIw' => {
'type' => 'Fixed',
'cpu_IRQ_NUM' => {
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'default' => '3',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram_SELw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => 'ram_Dw/8',
'type' => 'Fixed',
'global_param' => 'Localparam'
'default' => '32'
},
'ram_INITIAL_EN' => {
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"YES","NO"',
'redefine_param' => 1
},
'ram_BTEw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '2',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_WB_Aw' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '20',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'redefine_param' => 1,
'content' => '4,31,1'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'default' => '"ram0"',
'type' => 'Entry',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'ram_CORE_NUM' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => 'CORE_ID',
'content' => '',
'redefine_param' => 1
},
'ram_BURST_MODE' => {
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1
},
'ram_TAGw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ram_BYTE_WR_EN' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => 'Byte enable',
'default' => '"YES"',
'redefine_param' => 1,
'content' => '"YES","NO"'
},
'ram_FPGA_VENDOR' => {
'default' => '"XILINX"',
'info' => '',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"'
},
'ram_INIT_FILE_PATH' => {
'cpu_FEATURE_DATACACHE' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => 'SW_LOC'
'default' => '"ENABLED"',
'type' => 'Combo-box'
}
},
'category' => 'RAM',
'module_name' => 'wb_single_port_ram',
'instance' => 'ram'
},
'gpo0' => {
'ports' => {
'led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0'
}
},
'module' => 'gpo',
'instance' => 'led',
'module_name' => 'gpo',
'category' => 'GPIO',
'localparam' => {
'led_Aw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => ' 2',
'info' => undef
},
'led_SELw' => {
'info' => undef,
'default' => ' 4',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'led_Dw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'led_PORT_WIDTH',
'info' => undef
},
'led_TAGw' => {
'default' => ' 3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'led_PORT_WIDTH' => {
'default' => ' 1',
'info' => 'output port width',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '1,32,1',
'redefine_param' => 1
},
'module' => 'mor1kx',
'module_name' => 'mor1k',
'ports' => {
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'clk_source0' => {
'instance' => 'cs',
'category' => 'Source',
'localparam' => {
'cs_FPGA_VENDOR' => {
'info' => '',
'default' => '"XILINX"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX"'
}
},
'module_name' => 'clk_source',
'module' => 'clk_source',
'ports' => {
'cs_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'cs_reset_in' => {
'range' => '',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'type' => 'input'
}
}
}
}
}, 'ip_gen' )
},
'lm32_tile' => {
'top' => bless( {
'ports' => {
'ss_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'range' => ''
},
'lm32_en_i' => {
'intfc_name' => 'plug:enable[0]',
'instance_name' => 'lm320',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
},
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'range' => '',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]'
},
'uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ss_reset_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'intfc_name' => 'plug:reset[0]',
'intfc_port' => 'reset_i',
'type' => 'input'
},
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ni_current_e_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'current_e_addr',
'type' => 'input'
},
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'intfc_name' => 'IO'
}
},
'instance_ids' => {
'ProNoC_jtag_uart0' => {
'instance' => 'uart',
'module_name' => 'pronoc_jtag_uart',
'category' => 'Communication',
'localparam' => {
'uart_Dw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '32',
'content' => '',
'redefine_param' => 1
},
'uart_Aw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '1'
},
'uart_TAGw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '3'
},
'uart_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '4',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
}
},
'ports' => {
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0'
},
'uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_WB2Jw-1 : 0'
}
},
'module' => 'ProNoC_jtag_uart',
'parameters' => {
'uart_JTAG_CHAIN' => {
'default' => '3',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 0,
'content' => '1,2,3,4'
},
'instance' => 'cpu'
},
'single_port_ram0' => {
'instance' => 'ram',
'module_name' => 'wb_single_port_ram',
'ports' => {
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
},
'uart_JTAG_CONNECT' => {
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
},
'category' => 'RAM',
'module' => 'single_port_ram',
'parameters' => {
'ram_JSTATUSw' => {
'content' => '',
'info' => 'Parameter',
'default' => '8',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'ram_JINDEXw' => {
'default' => '8',
'type' => 'Fixed',
'redefine_param' => 1,
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '"XILINX_JTAG_WB"',
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.'
'content' => '',
'info' => 'Parameter'
},
'uart_JAw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'uart_J2WBw' => {
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'default' => '126-CORE_ID',
'ram_J2WBw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Entry',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'info' => undef,
'content' => ''
},
'uart_BUFF_Aw' => {
'content' => '2,16,1',
'ram_WB2Jw' => {
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => undef
},
'ram_Dw' => {
'redefine_param' => 1,
'default' => '6',
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'global_param' => 'Parameter',
'type' => 'Spin-button'
'type' => 'Spin-button',
'default' => '32',
'info' => 'Memory data width in Bits.',
'content' => '8,1024,1'
},
'uart_JSTATUSw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '8'
},
'uart_JINDEXw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '8'
},
'uart_JDw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '32',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'uart_WB2Jw' => {
'redefine_param' => 1,
'content' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'info' => '',
'type' => 'Fixed',
'global_param' => 'Parameter'
}
}
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'localparam' => {
'bus_M' => {
'redefine_param' => 1,
'content' => '1,256,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'Number of wishbone master interface',
'default' => ' 4'
},
'bus_CTIw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'bus_Dw' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'content' => '8,512,8',
'redefine_param' => 1
},
'bus_S' => {
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => 5,
'info' => 'Number of wishbone slave interface',
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_BTEw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '2 '
},
'bus_TAGw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '3'
},
'bus_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => 'bus_Dw/8',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'bus_Aw' => {
'default' => '32',
'info' => 'The wishbone Bus address width',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '4,128,1',
'redefine_param' => 1
}
}
},
'lm320' => {
'instance' => 'lm32',
'module_name' => 'lm32',
'category' => 'Processor',
'localparam' => {
'lm32_CFG_PL_BARREL_SHIFT' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '"ENABLED"',
'redefine_param' => 1,
'content' => '"ENABLED","DISABLED"'
},
'lm32_INTR_NUM' => {
'content' => '',
'redefine_param' => 1,
'default' => '32',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'lm32_CFG_MC_DIVIDE' => {
'info' => undef,
'default' => '"DISABLED"',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '"ENABLED","DISABLED"',
'redefine_param' => 1
},
'lm32_CFG_SIGN_EXTEND' => {
'redefine_param' => 1,
'content' => '"ENABLED","DISABLED"',
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '"ENABLED"'
},
'lm32_CFG_PL_MULTIPLY' => {
'content' => '"ENABLED","DISABLED"',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '"ENABLED"'
}
},
'ports' => {
'lm32_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:enable[0]'
}
},
'module' => 'lm32'
},
'single_port_ram0' => {
'module' => 'single_port_ram',
'ports' => {
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
}
},
'parameters' => {
'ram_FPGA_VENDOR' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'info' => '',
'default' => '"XILINX"',
'content' => '"ALTERA","XILINX","GENERIC"',
'redefine_param' => 1
},
'ram_JTAG_INDEX' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Entry',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
'ram_JTAG_INDEX' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'default' => 'CORE_ID',
'type' => 'Entry',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
6961,949 → 790,129
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID'
},
'ram_JSTATUSw' => {
'default' => '8',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ram_J2WBw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1'
},
'ram_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'redefine_param' => 0,
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'content' => ''
},
'ram_JAw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'ram_Dw' => {
'type' => 'Spin-button',
'global_param' => 'Parameter',
'info' => 'Memory data width in Bits.',
'default' => '32',
'redefine_param' => 1,
'content' => '8,1024,1'
},
'ram_Aw' => {
'default' => '14',
'info' => 'Memory address width',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '4,31,1'
},
'ram_JTAG_CONNECT' => {
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"XILINX_JTAG_WB"',
'global_param' => 'Parameter',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"'
},
'ram_JINDEXw' => {
'default' => '8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ram_JAw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '32'
},
'ram_WB2Jw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ram_JDw' => {
'default' => 'ram_Dw',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
}
},
'instance' => 'ram',
'category' => 'RAM',
'localparam' => {
'ram_BURST_MODE' => {
'default' => '"ENABLED"',
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"DISABLED","ENABLED"'
'default' => '32',
'type' => 'Fixed'
},
'ram_CORE_NUM' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => 'CORE_ID',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ram_INIT_FILE_PATH' => {
'default' => 'SW_LOC',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'ram_BYTE_WR_EN' => {
'ram_JTAG_CONNECT' => {
'type' => 'Combo-box',
'default' => '"ALTERA_JTAG_WB"',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
},
'ram_JDw' => {
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"YES","NO"',
'info' => 'Byte enable',
'default' => '"YES"',
'global_param' => 'Localparam',
'type' => 'Combo-box'
'default' => 'ram_Dw',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
},
'ram_TAGw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '3',
'redefine_param' => 1,
'content' => ''
},
'ram_INITIAL_EN' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"YES"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'redefine_param' => 1,
'content' => '"YES","NO"'
},
'ram_SELw' => {
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1
},
'ram_CTIw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ram_MEM_CONTENT_FILE_NAME' => {
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'type' => 'Entry',
'global_param' => 'Localparam',
'ram_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'redefine_param' => 0
}
},
'localparam' => {
'ram_CTIw' => {
'content' => '',
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_TAGw' => {
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ram_SELw' => {
'default' => 'ram_Dw/8',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ram_FPGA_VENDOR' => {
'type' => 'Combo-box',
'default' => '"ALTERA"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX","GENERIC"',
'info' => ''
},
'ram_BYTE_WR_EN' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"YES"',
'type' => 'Combo-box',
'info' => 'Byte enable',
'content' => '"YES","NO"'
},
'ram_CORE_NUM' => {
'default' => 'CORE_ID',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ram_INIT_FILE_PATH' => {
'content' => '',
'info' => undef,
'default' => 'SW_LOC',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
'global_param' => 'Localparam'
},
'ram_BTEw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '2',
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'module_name' => 'wb_single_port_ram'
},
'gpo0' => {
'parameters' => {
'led_PORT_WIDTH' => {
'redefine_param' => 1,
'content' => '1,32,1',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'default' => ' 1',
'info' => 'output port width'
}
},
'module' => 'gpo',
'ports' => {
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
}
},
'localparam' => {
'led_Dw' => {
'default' => 'led_PORT_WIDTH',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'led_SELw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => ' 4',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'led_Aw' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => ' 2',
'info' => undef
},
'led_TAGw' => {
'info' => undef,
'default' => ' 3',
'global_param' => 'Localparam',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
}
},
'category' => 'GPIO',
'module_name' => 'gpo',
'instance' => 'led'
},
'clk_source0' => {
'instance' => 'ss',
'module_name' => 'clk_source',
'category' => 'Source',
'ports' => {
'ss_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]'
},
'ss_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
}
},
'module' => 'clk_source'
},
'ni_master0' => {
'ports' => {
'ni_flit_in_wr' => {
'intfc_name' => 'socket:ni[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'flit_in_wr'
},
'ni_credit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_in' => {
'type' => 'input',
'intfc_port' => 'flit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_current_r_addr' => {
'type' => 'input',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0'
},
'ni_flit_out_wr' => {
'range' => '',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_out_wr',
'type' => 'output'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'range' => 'ni_Fw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0'
}
},
'module' => 'ni_master',
'parameters' => {
'ni_DEBUG_EN' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '0',
'info' => 'Parameter'
},
'ni_B' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '4'
},
'ni_TOPOLOGY' => {
'redefine_param' => 1,
'content' => '',
'default' => '"MESH"',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ni_RAw' => {
'redefine_param' => 0,
'content' => '',
'default' => '16',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_Fpay' => {
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_BYTE_EN' => {
'default' => 0,
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_T3' => {
'default' => '1',
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_ROUTE_NAME' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '"XY"',
'content' => '',
'redefine_param' => 1
},
'ni_V' => {
'content' => '',
'redefine_param' => 1,
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_EAw' => {
'content' => '',
'redefine_param' => 0,
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '16',
'info' => undef
},
'ni_T2' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '2',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_C' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => 0,
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'ni_T1' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '2'
}
},
'instance' => 'ni',
'module_name' => 'ni_master',
'category' => 'NoC',
'localparam' => {
'ni_MAX_BURST_SIZE' => {
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1
},
'ni_S_Aw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '8'
},
'ni_M_Aw' => {
'redefine_param' => 1,
'content' => 'Dw',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter'
},
'ni_HDATA_PRECAPw' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '4',
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'content' => '0,8,1',
'redefine_param' => 1
},
'ni_Fw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '2+ni_V+ni_Fpay',
'info' => undef,
'content' => '',
'redefine_param' => 0
},
'ni_MAX_TRANSACTION_WIDTH' => {
'content' => '4,32,1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.'
},
'ni_CRC_EN' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'redefine_param' => 1,
'content' => '"YES","NO"'
},
'ni_SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => '4',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_TAGw' => {
'redefine_param' => 1,
'content' => '',
'default' => '3',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_Dw' => {
'info' => 'wishbone_bus data width in bits.',
'default' => '32',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'content' => '32,256,8',
'redefine_param' => 1
}
}
},
'timer0' => {
'parameters' => {
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'content' => '1,32,1',
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'global_param' => 'Parameter',
'type' => 'Spin-button'
}
},
'module' => 'timer',
'localparam' => {
'timer_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '4',
'content' => '',
'redefine_param' => 1
},
'timer_Dw' => {
'default' => '32',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'timer_Aw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'timer_CNTw' => {
'default' => '32 ',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'timer_TAGw' => {
'content' => '',
'redefine_param' => 1,
'info' => undef,
'default' => '3',
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'category' => 'Timer',
'module_name' => 'timer',
'instance' => 'timer'
}
},
'parameters' => {
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JTAG_INDEX' => '126-CORE_ID',
'uart_BUFF_Aw' => '6',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'uart_JINDEXw' => '8',
'ram_JINDEXw' => '8',
'uart_JDw' => '32',
'ram_JAw' => '32',
'ram_JDw' => 'ram_Dw',
'ram_FPGA_VENDOR' => '"XILINX"',
'uart_JTAG_CHAIN' => '3',
'ram_JSTATUSw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_Dw' => '32',
'ram_Aw' => '14',
'timer_PRESCALER_WIDTH' => '8',
'led_PORT_WIDTH' => ' 1'
},
'interface' => {
'IO' => {
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_wb_to_jtag' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0'
}
}
},
'plug:enable[0]' => {
'ports' => {
'lm32_en_i' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => '',
'instance_name' => 'lm320'
}
}
},
'plug:clk[0]' => {
'ports' => {
'ss_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'ss_reset_in' => {
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_credit_in' => {
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'credit_in'
},
'ni_flit_in_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'intfc_port' => 'flit_in_wr',
'type' => 'input'
},
'ni_credit_out' => {
'intfc_port' => 'credit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0',
'intfc_port' => 'flit_out',
'type' => 'output'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_port' => 'current_r_addr',
'type' => 'input'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_current_e_addr' => {
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
}
}
}
}
}, 'ip_gen' ),
'tile_nums' => undef
},
'mor1k_atera' => {
'top' => bless( {
'interface' => {
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => 'uart_J2WBw-1 : 0'
'ram_INITIAL_EN' => {
'default' => '"YES"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"YES","NO"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
},
'ram_WB_Aw' => {
'content' => '4,31,1',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'default' => '20',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_Aw' => {
'content' => '4,31,1',
'info' => 'Memory address width',
'type' => 'Spin-button',
'default' => '14',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'uart_wb_to_jtag' => {
'instance_name' => 'ProNoC_jtag_uart1',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'ram_jtag_to_wb' => {
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
}
},
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'instance_name' => 'mor1kx0',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'type' => 'output',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => ''
},
'uart_RxD_din_sim' => {
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart1'
},
'uart_RxD_wr_sim' => {
'instance_name' => 'ProNoC_jtag_uart1',
'range' => '',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim'
}
}
},
'plug:clk[0]' => {
'ports' => {
'cs_clk_in' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'instance_name' => 'clk_source0',
'range' => ''
}
}
},
'IO' => {
'ports' => {
'led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_flit_in_wr' => {
'intfc_port' => 'flit_in_wr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => ''
},
'ni_flit_in' => {
'intfc_port' => 'flit_in',
'type' => 'input',
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0'
},
'ni_credit_in' => {
'intfc_port' => 'credit_in',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_out_wr' => {
'instance_name' => 'ni_master0',
'range' => '',
'type' => 'output',
'intfc_port' => 'flit_out_wr'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_credit_out' => {
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
},
'ni_flit_out' => {
'intfc_port' => 'flit_out',
'type' => 'output',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
}
}
},
'plug:reset[0]' => {
'ports' => {
'cs_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'range' => ''
}
}
}
},
'parameters' => {
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_INDEX' => '126-CORE_ID',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'uart_JAw' => '32',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_Aw' => '14',
'ram_JTAG_CHAIN' => '4',
'ram_Dw' => '32',
'ram_JSTATUSw' => '8',
'uart_JTAG_CHAIN' => '3',
'ram_JAw' => '32',
'ram_JDw' => 'ram_Dw',
'ram_JINDEXw' => '8',
'uart_JDw' => '32',
'uart_JINDEXw' => '8'
},
'instance_ids' => {
'clk_source0' => {
'ports' => {
'cs_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'cs_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
},
'module' => 'clk_source',
'module_name' => 'clk_source',
'localparam' => {
'cs_FPGA_VENDOR' => {
'type' => 'Combo-box',
'global_param' => 'Localparam',
'info' => '',
'default' => '"ALTERA"',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX"'
}
},
'category' => 'Source',
'instance' => 'cs'
},
'single_port_ram0' => {
'localparam' => {
'ram_BTEw' => {
'content' => '',
'redefine_param' => 1,
'default' => '2',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ram_WB_Aw' => {
'redefine_param' => 1,
'content' => '4,31,1',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '20',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). '
},
'ram_MEM_CONTENT_FILE_NAME' => {
'redefine_param' => 1,
'content' => '',
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
'ram_MEM_CONTENT_FILE_NAME' => {
'content' => '',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
7914,1590 → 923,998
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'global_param' => 'Localparam',
'type' => 'Entry'
},
'ram_SELw' => {
'content' => '',
'redefine_param' => 1,
'default' => 'ram_Dw/8',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ram_INITIAL_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'default' => '"YES"'
},
'ram_CTIw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '3',
'redefine_param' => 1,
'content' => ''
},
'ram_BYTE_WR_EN' => {
'default' => '"YES"',
'info' => 'Byte enable',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'redefine_param' => 1,
'content' => '"YES","NO"'
},
'ram_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'type' => 'Combo-box',
'info' => '',
'default' => '"ALTERA"',
'content' => '"ALTERA","XILINX","GENERIC"',
'redefine_param' => 1
},
'ram_INIT_FILE_PATH' => {
'default' => 'SW_LOC',
'info' => undef,
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'ram_TAGw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '3',
'content' => '',
'redefine_param' => 1
},
'ram_BURST_MODE' => {
'content' => '"DISABLED","ENABLED"',
'redefine_param' => 1,
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'ram_CORE_NUM' => {
'redefine_param' => 1,
'content' => '',
'default' => 'CORE_ID',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
}
},
'category' => 'RAM',
'module_name' => 'wb_single_port_ram',
'instance' => 'ram',
'parameters' => {
'ram_JINDEXw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter'
},
'ram_JDw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => 'ram_Dw',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'ram_JAw' => {
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ram_WB2Jw' => {
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'global_param' => 'Parameter',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'ram_JTAG_CONNECT' => {
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'redefine_param' => 1,
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'default' => '"ALTERA_JTAG_WB"',
'global_param' => 'Parameter',
'type' => 'Combo-box'
},
'ram_Dw' => {
'global_param' => 'Parameter',
'type' => 'Spin-button',
'default' => '32',
'info' => 'Memory data width in Bits.',
'redefine_param' => 1,
'content' => '8,1024,1'
},
'ram_J2WBw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1'
},
'ram_JTAG_CHAIN' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '4',
'redefine_param' => 0,
'content' => '1,2,3,4'
},
'ram_Aw' => {
'default' => '14',
'info' => 'Memory address width',
'type' => 'Spin-button',
'global_param' => 'Parameter',
'content' => '4,31,1',
'redefine_param' => 1
},
'ram_JSTATUSw' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '8',
'content' => '',
'redefine_param' => 1
},
'ram_JTAG_INDEX' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Entry',
'global_param' => 'Parameter',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'default' => 'CORE_ID'
}
},
'module' => 'single_port_ram',
'ports' => {
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0'
}
}
},
'gpo0' => {
'ports' => {
'led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => 'led_PORT_WIDTH-1 : 0',
'intfc_name' => 'IO'
}
},
'module' => 'gpo',
'instance' => 'led',
'module_name' => 'gpo',
'category' => 'GPIO',
'localparam' => {
'led_Dw' => {
'info' => undef,
'default' => 'led_PORT_WIDTH',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'led_Aw' => {
'redefine_param' => 1,
'content' => '',
'default' => ' 2',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'led_SELw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => ' 4'
},
'led_PORT_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'info' => 'output port width',
'default' => ' 1',
'redefine_param' => 1,
'content' => '1,32,1'
},
'led_TAGw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => ' 3'
}
}
},
'ni_master0' => {
'ports' => {
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => ''
},
'ni_credit_in' => {
'type' => 'input',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0'
},
'ni_flit_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0',
'type' => 'input',
'intfc_port' => 'flit_in'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out_wr' => {
'intfc_port' => 'flit_out_wr',
'type' => 'output',
'range' => '',
'intfc_name' => 'socket:ni[0]'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]'
},
'ni_flit_out' => {
'type' => 'output',
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_Fw-1 : 0'
},
'ni_credit_out' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'type' => 'output',
'intfc_port' => 'credit_out'
}
},
'module' => 'ni_master',
'parameters' => {
'ni_TOPOLOGY' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'default' => '"MESH"',
'content' => '',
'redefine_param' => 1
},
'ni_DEBUG_EN' => {
'default' => '0',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_B' => {
'info' => 'Parameter',
'default' => '4',
'global_param' => 'Parameter',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 1
},
'ni_T3' => {
'info' => 'Parameter',
'default' => '1',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_Fpay' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_RAw' => {
'content' => '',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '16',
'info' => undef
},
'ni_BYTE_EN' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '1',
'info' => undef
},
'ni_EAw' => {
'content' => '',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => undef,
'default' => '16'
},
'ni_T2' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '3',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_ROUTE_NAME' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => '"XY"',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_V' => {
'info' => 'Parameter',
'default' => 1,
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => ''
},
'ni_C' => {
'type' => 'Fixed',
'global_param' => 'Parameter',
'default' => 0,
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_T1' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '2',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => ''
}
},
'instance' => 'ni',
'module_name' => 'ni_master',
'category' => 'NoC',
'localparam' => {
'ni_Dw' => {
'content' => '32,256,8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'info' => 'wishbone_bus data width in bits.',
'default' => '32'
},
'ni_TAGw' => {
'redefine_param' => 1,
'content' => '',
'default' => '3',
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'ni_SELw' => {
'redefine_param' => 1,
'content' => '',
'default' => '4',
'info' => 'Parameter',
'type' => 'Fixed',
'global_param' => 'Localparam'
},
'ni_CRC_EN' => {
'redefine_param' => 1,
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '
},
'ni_MAX_TRANSACTION_WIDTH' => {
'redefine_param' => 1,
'content' => '4,32,1',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'default' => '13',
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'ni_Fw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '2+ni_V+ni_Fpay',
'content' => '',
'redefine_param' => 0
},
'ni_HDATA_PRECAPw' => {
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'default' => '4',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'redefine_param' => 1,
'content' => '0,8,1'
},
'ni_M_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '32',
'content' => 'Dw',
'redefine_param' => 1
},
'ni_S_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '8',
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1
},
'ni_MAX_BURST_SIZE' => {
'redefine_param' => 1,
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'default' => '16',
'global_param' => 'Localparam',
'type' => 'Combo-box'
}
}
},
'timer0' => {
'instance' => 'timer',
'category' => 'Timer',
'localparam' => {
'timer_SELw' => {
'redefine_param' => 1,
'content' => '',
'info' => undef,
'default' => '4',
'global_param' => 'Localparam',
'type' => 'Fixed'
},
'timer_Dw' => {
'info' => undef,
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => ''
},
'timer_Aw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '3',
'redefine_param' => 1,
'content' => ''
},
'timer_CNTw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32 ',
'info' => undef
},
'timer_PRESCALER_WIDTH' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'redefine_param' => 1,
'content' => '1,32,1'
},
'timer_TAGw' => {
'content' => '',
'redefine_param' => 1,
'default' => '3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed'
}
},
'module_name' => 'timer',
'module' => 'timer'
},
'wishbone_bus0' => {
'module' => 'wishbone_bus',
'localparam' => {
'bus_Aw' => {
'redefine_param' => 1,
'content' => '4,128,1',
'default' => '32',
'info' => 'The wishbone Bus address width',
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'bus_BTEw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '2 ',
'redefine_param' => 1,
'content' => ''
},
'bus_TAGw' => {
'default' => '3',
'info' => undef,
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'bus_SELw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => 'bus_Dw/8',
'info' => undef,
'redefine_param' => 1,
'content' => ''
},
'bus_M' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => ' 4',
'info' => 'Number of wishbone master interface',
'redefine_param' => 1,
'content' => '1,256,1'
},
'bus_CTIw' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'default' => '3'
},
'bus_Dw' => {
'redefine_param' => 1,
'content' => '8,512,8',
'info' => 'The wishbone Bus data width in bits.',
'default' => '32',
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'bus_S' => {
'type' => 'Spin-button',
'global_param' => 'Localparam',
'default' => 5,
'info' => 'Number of wishbone slave interface',
'content' => '1,256,1',
'redefine_param' => 1
}
},
'category' => 'Bus',
'module_name' => 'wishbone_bus',
'instance' => 'bus'
},
'ProNoC_jtag_uart1' => {
'instance' => 'uart',
'category' => 'Communication',
'localparam' => {
'uart_BUFF_Aw' => {
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'default' => '4',
'type' => 'Spin-button',
'type' => 'Entry',
'default' => '"ram0"',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_BTEw' => {
'default' => '2',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => '2,16,1',
'redefine_param' => 1
},
'uart_SELw' => {
'info' => 'Parameter',
'default' => '4',
'global_param' => 'Localparam',
'type' => 'Fixed',
'redefine_param' => 1,
'content' => ''
},
'uart_Dw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32',
'content' => '',
'redefine_param' => 1
},
'uart_TAGw' => {
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'default' => '3',
'content' => '',
'redefine_param' => 1
},
'uart_Aw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '1',
'type' => 'Fixed',
'global_param' => 'Localparam'
}
},
'module_name' => 'pronoc_jtag_uart',
'module' => 'ProNoC_jtag_uart',
'ports' => {
'uart_RxD_wr_sim' => {
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'type' => 'input',
'intfc_port' => 'RxD_din_sim'
},
'uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'range' => 'uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
},
'uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
}
},
'parameters' => {
'uart_JINDEXw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '8',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'redefine_param' => 1
'info' => 'Parameter'
},
'uart_JSTATUSw' => {
'redefine_param' => 1,
'content' => '',
'info' => 'Parameter',
'default' => '8',
'type' => 'Fixed',
'global_param' => 'Parameter'
},
'uart_WB2Jw' => {
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'info' => ''
},
'uart_JDw' => {
'global_param' => 'Parameter',
'type' => 'Fixed',
'info' => 'Parameter',
'default' => '32',
'content' => '',
'redefine_param' => 1
},
'uart_JTAG_CONNECT' => {
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'redefine_param' => 1,
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box',
'global_param' => 'Parameter'
},
'uart_JAw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '32',
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'uart_JTAG_CHAIN' => {
'type' => 'Combo-box',
'global_param' => 'Parameter',
'default' => '3',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'redefine_param' => 0,
'content' => '1,2,3,4'
},
'uart_J2WBw' => {
'redefine_param' => 1,
'content' => '',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'info' => undef,
'global_param' => 'Parameter',
'type' => 'Fixed'
},
'uart_JTAG_INDEX' => {
'content' => '',
'redefine_param' => 1,
'type' => 'Entry',
'global_param' => 'Parameter',
'default' => '126-CORE_ID',
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.'
}
}
},
'mor1kx0' => {
'module' => 'mor1kx',
'ports' => {
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
},
'instance' => 'cpu',
'localparam' => {
'cpu_FEATURE_DMMU' => {
'default' => '"ENABLED"',
'info' => '',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1
},
'cpu_OPTION_OPERAND_WIDTH' => {
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'global_param' => 'Localparam',
'default' => '32',
'info' => 'Parameter'
},
'cpu_IRQ_NUM' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'info' => undef,
'default' => '32',
'redefine_param' => 1,
'content' => ''
},
'cpu_FEATURE_IMMU' => {
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"'
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'content' => '"NONE","ENABLED"',
'ram_BURST_MODE' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'info' => ''
},
'cpu_FEATURE_DATACACHE' => {
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam'
},
'cpu_OPTION_DCACHE_SNOOP' => {
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'default' => '"ENABLED"',
'info' => '',
'global_param' => 'Localparam',
'type' => 'Combo-box'
}
},
'category' => 'Processor',
'module_name' => 'mor1k'
}
},
'ports' => {
'ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'ni_flit_out_wr' => {
'type' => 'output',
'intfc_port' => 'flit_out_wr',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => ''
},
'cs_clk_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
'type' => 'input'
},
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0'
},
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]'
},
'ni_flit_out' => {
'type' => 'output',
'intfc_port' => 'flit_out',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_Fw-1 : 0'
},
'cs_reset_in' => {
'type' => 'input',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0'
},
'ni_credit_out' => {
'type' => 'output',
'intfc_port' => 'credit_out',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_V-1 : 0',
'instance_name' => 'ni_master0'
},
'uart_RxD_din_sim' => {
'type' => 'input',
'intfc_port' => 'RxD_din_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart1'
},
'led_port_o' => {
'range' => 'led_PORT_WIDTH-1 : 0',
'instance_name' => 'gpo0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'ni_current_e_addr' => {
'type' => 'input',
'intfc_port' => 'current_e_addr',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0'
},
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'instance_name' => 'mor1kx0',
'type' => 'input',
'intfc_port' => 'enable_i'
},
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'ni_credit_in' => {
'type' => 'input',
'intfc_port' => 'credit_in',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_V-1 : 0'
},
'ni_flit_in' => {
'range' => 'ni_Fw-1 : 0',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'intfc_port' => 'flit_in',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'ProNoC_jtag_uart1',
'range' => 'uart_J2WBw-1 : 0'
},
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_port' => 'RxD_ready_sim',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'instance_name' => 'ProNoC_jtag_uart1'
},
'ni_flit_in_wr' => {
'type' => 'input',
'intfc_port' => 'flit_in_wr',
'intfc_name' => 'socket:ni[0]',
'range' => '',
'instance_name' => 'ni_master0'
}
}
}, 'ip_gen' )
}
},
'setting' => {
'show_tile_setting' => 1,
'soc_path' => 'lib/soc',
'show_noc_setting' => 1,
'show_adv_setting' => 0
},
'current_tile_param' => undef,
'noc_indept_param' => {},
'file_name' => undef,
'verilator' => {
'libs' => {
'Vtile0' => 'tile_0.v',
'Vtile1' => 'tile_1.v',
'Vnoc' => 'noc_connection.sv',
'Vtile3' => 'tile_3.v',
'Vrouter1' => 'router_verilator_p5.v',
'Vtile2' => 'tile_2.v'
}
},
'RAM0' => {
'end' => 32768,
'start' => 22937
},
'JTAG' => {
'M_CHAIN' => 4
},
'RAM1' => {
'start' => 49152,
'end' => 65536
},
'top_ip' => bless( {
'instance_ids' => {
'IO' => {
'ports' => {
'reset' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'clk' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:clk[0]'
},
'processors_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'type' => 'input',
'intfc_port' => 'enable_i'
}
}
},
'T1' => {
'ports' => {
'T1_ram_wb_to_jtag' => {
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'content' => '"DISABLED","ENABLED"'
}
}
}
},
'tiles' => {
'0' => {
'parameters' => {
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_JINDEXw' => '8',
'ram_JSTATUSw' => '8',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'uart_JDw' => '32',
'ram_Aw' => '14',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'uart_JTAG_CHAIN' => '3',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_JAw' => '32',
'uart_JAw' => '32',
'ram_Dw' => '32'
}
},
'1' => {
'parameters' => {
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Aw' => '14',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'ram_JINDEXw' => '8',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JAw' => '32',
'ram_Dw' => '32',
'uart_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_CHAIN' => '3',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1'
}
},
'2' => {
'parameters' => {
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_Dw' => '32',
'uart_JAw' => '32',
'uart_JTAG_CHAIN' => '3',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_JINDEXw' => '8',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'ram_Aw' => '14',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JSTATUSw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"'
}
},
'3' => {
'parameters' => {
'ram_Dw' => '32',
'ram_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'uart_JAw' => '32',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JDw' => 'ram_Dw',
'uart_JINDEXw' => '8',
'ram_JTAG_CHAIN' => '4',
'uart_JTAG_CHAIN' => '3',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Aw' => '14',
'ram_JSTATUSw' => '8',
'uart_JDw' => '32',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'ram_JINDEXw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'uart_JSTATUSw' => '8',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1'
}
}
},
'ports' => {
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_WB2Jw-1 : 0',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T1_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_uart_WB2Jw-1 : 0'
'source_clk_in' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'source_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'T1_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T1_led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => ' 1-1 : 0',
'intfc_name' => 'IO'
},
'T1_uart_jtag_to_wb' => {
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'type' => 'output',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => ''
},
'uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_uart_J2WBw-1 : 0'
}
}
},
'T2' => {
'ports' => {
'T2_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T2_uart_jtag_to_wb' => {
'range' => 'T2_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
'ni_current_r_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_r_addr'
},
'uart_RxD_wr_sim' => {
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim'
},
'T2_led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => ' 1-1 : 0'
}
}
},
'T3' => {
'ports' => {
'T3_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_ram_J2WBw-1 : 0'
},
'T3_led_port_o' => {
'intfc_port' => 'IO',
'type' => 'output',
'range' => ' 1-1 : 0',
'intfc_name' => 'IO'
'ni_chan_out' => {
'instance_name' => 'ni_master0',
'type' => 'output',
'intfc_port' => 'chan_out',
'range' => 'smartflit_chanel_t',
'intfc_name' => 'socket:ni[0]'
},
'ni_chan_in' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t',
'type' => 'input',
'intfc_port' => 'chan_in',
'instance_name' => 'ni_master0'
},
'T3_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T3_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T3_uart_wb_to_jtag' => {
'range' => 'T3_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0'
},
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output'
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T3_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_J2WBw-1 : 0'
}
}
},
'T0' => {
'ports' => {
'T0_ram_wb_to_jtag' => {
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T0_led_port_o' => {
'range' => ' 1-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'T0_ram_jtag_to_wb' => {
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'single_port_ram0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_J2WBw-1 : 0'
'range' => 'ram_J2WBw-1 : 0'
},
'T0_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T0_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
}
}
}
},
'ports' => {
'T3_ram_jtag_to_wb' => {
'range' => 'T3_ram_J2WBw-1 : 0',
'instance_name' => 'T3',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T0_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T0',
'range' => 'T0_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T0_led_port_o' => {
'range' => ' 1-1 : 0',
'instance_name' => 'T0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'T1_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T1',
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T2',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T3_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_WB2Jw-1 : 0',
'instance_name' => 'T3'
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'intfc_port' => 'enable_i',
'instance_name' => 'mor1kx0',
'type' => 'input'
}
}
}, 'ip_gen' )
}
},
'MEM1' => {
'percent' => '75',
'width' => '14'
},
'SOURCE_SET' => {
'clk_number' => 1,
'reset_number' => 1,
'reset_0_name' => 'reset',
'REDEFINE_TOP' => 0,
'clk_0_name' => 'clk',
'SOC' => bless( {
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
},
'T2_led_port_o' => {
'instance_name' => 'T2',
'range' => ' 1-1 : 0',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'T2_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'range' => 'T2_uart_WB2Jw-1 : 0'
},
'T0_uart_wb_to_jtag' => {
'instance_name' => 'T0',
'range' => 'T0_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T1_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T1',
'range' => 'T1_uart_J2WBw-1 : 0'
},
'T3_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T3_ram_WB2Jw-1 : 0',
'instance_name' => 'T3',
'intfc_name' => 'socket:jtag_to_wb[0]'
'hdl_files' => undef,
'instances' => {
'TOP' => {
'parameters_order' => [],
'sockets' => {},
'category' => 'TOP',
'description_pdf' => undef,
'module' => 'TOP',
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'reset',
'connect_socket' => undef,
'connect_socket_num' => undef
}
}
},
'clk' => {
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk',
'connect_id' => 'IO',
'connect_socket' => undef,
'connect_socket_num' => undef
}
},
'value' => 1
}
},
'module_name' => 'TOP',
'instance_name' => 'TOP'
}
},
'T0_ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'instance_name' => 'T0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T2_uart_jtag_to_wb' => {
'instance_name' => 'T2',
'range' => 'T2_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
'instance_order' => [
'TOP'
],
'SOURCE_SET' => {
'IP' => bless( {
'file_name' => undef,
'hdl_files_ticked' => [],
'parameters_order' => [],
'GUI_REMOVE_SET' => 'DISABLE',
'hdl_files' => [],
'plugs' => {
'reset' => {
'type' => 'num',
'1' => {},
'value' => 1,
'0' => {
'name' => 'reset'
}
},
'clk' => {
'type' => 'num',
'value' => 1,
'1' => {},
'0' => {
'name' => 'clk'
}
}
},
'module_name' => 'TOP',
'ports' => {
'clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => undef,
'type' => 'input',
'intfc_port' => 'clk_i'
},
'reset' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => undef
}
},
'ip_name' => 'TOP',
'ports_order' => [],
'category' => 'TOP'
}, 'ip_gen' )
},
'T1_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_J2WBw-1 : 0',
'instance_name' => 'T1',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'processors_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'instance_name' => 'IO',
'range' => '',
'intfc_name' => 'plug:enable[0]'
},
'T2_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'range' => 'T2_ram_J2WBw-1 : 0'
},
'T0_uart_jtag_to_wb' => {
'instance_name' => 'T0',
'range' => 'T0_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'clk' => {
'type' => 'input',
'intfc_port' => 'clk_i',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'instance_name' => 'IO'
},
'T3_led_port_o' => {
'range' => ' 1-1 : 0',
'instance_name' => 'T3',
'intfc_name' => 'IO',
'intfc_port' => 'IO',
'type' => 'output'
},
'T1_uart_wb_to_jtag' => {
'range' => 'T1_uart_WB2Jw-1 : 0',
'instance_name' => 'T1',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'reset' => {
'intfc_name' => 'plug:reset[0]',
'instance_name' => 'IO',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
},
'T3_uart_jtag_to_wb' => {
'range' => 'T3_uart_J2WBw-1 : 0',
'instance_name' => 'T3',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T1_led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'intfc_name' => 'IO',
'range' => ' 1-1 : 0',
'instance_name' => 'T1'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'processors_en' => {
'type' => 'input',
'intfc_port' => 'enable_i',
'range' => '',
'instance_name' => 'IO'
}
}
},
'plug:clk[0]' => {
'TOP' => {
'version' => 0
},
'soc_name' => {
'TOP' => undef
},
'device_win_adj' => {
'va' => '0',
'ha' => '0'
},
'modules' => {}
}, 'soc' )
},
'tile' => {
'2' => {},
'0' => {},
'1' => {},
'3' => {}
},
'compile_pin_pos' => {
'TOP_reset' => [
0,
0
],
'jtag_debug_reset_in' => [
0,
0
],
'TOP_clk' => [
4,
0
],
'processors_en' => [
6,
0
]
},
'current_tile_param' => undef,
'gen_tiles_adj' => {
'ha' => '0',
'va' => '0'
},
'parameters_order' => {
'noc_param' => [
'TOPOLOGY',
'T1',
'T2',
'T3',
'V',
'B',
'Fpay',
'ROUTE_NAME',
'MIN_PCK_SIZE',
'BYTE_EN',
'SSA_EN',
'CONGESTION_INDEX',
'ESCAP_VC_MASK',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'SWA_ARBITER_TYPE',
'WEIGHTw',
'AVC_ATOMIC_EN',
'LB',
'PCK_TYPE',
'CAST_TYPE',
'SMART_MAX',
'SELF_LOOP_EN'
],
'SOURCE_SET' => [
'clk_number',
'clk_0_name',
'reset_number',
'reset_0_name'
],
'noc_type' => [
'ROUTER_TYPE'
],
'compile' => [
'cpu_num'
],
'SOURCE_SET_CONNECT' => [
'NoC_clk',
'T0_ss_clk_in',
'T1_ss_clk_in',
'T2_ss_clk_in',
'T3_ss_clk_in',
'NoC_reset',
'T0_ss_reset_in',
'T1_ss_reset_in',
'T2_ss_reset_in',
'T3_ss_reset_in',
'T0_cs_clk_in',
'T1_cs_clk_in',
'T2_cs_clk_in',
'T3_cs_clk_in',
'T0_cs_reset_in',
'T1_cs_reset_in',
'T2_cs_reset_in',
'T3_cs_reset_in'
]
},
'noc_indept_param' => {},
'file_name' => undef,
'noc_param' => {
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
'T3' => '1',
'ROUTE_NAME' => '"XY"',
'C' => 0,
'V' => '2',
'SSA_EN' => '"NO"',
'CONGESTION_INDEX' => 3,
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
'WEIGHTw' => '4',
'DEBUG_EN' => '0',
'SMART_MAX' => '0',
'SWA_ARBITER_TYPE' => '"RRA"',
'FIRST_ARBITER_EXT_P_EN' => 1,
'SELF_LOOP_EN' => '"NO"',
'Fpay' => '32',
'T1' => '2',
'MUX_TYPE' => '"BINARY"',
'PCK_TYPE' => '"MULTI_FLIT"',
'BYTE_EN' => '1',
'AVC_ATOMIC_EN' => 0,
'MIN_PCK_SIZE' => '2',
'ESCAP_VC_MASK' => '2\'b01',
'T2' => '2',
'B' => '4',
'CAST_TYPE' => '"UNICAST"',
'TOPOLOGY' => '"MESH"',
'LB' => '4'
},
'compile_pin' => {
'TOP_reset' => '*GND',
'jtag_debug_reset_in' => '*GND',
'TOP_clk' => 'FPGA_CLK1_50',
'processors_en' => 'KEY'
},
'ROM2' => {
'start' => 0,
'end' => 49152
},
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
},
'SOURCE_SET_CONNECT' => {
'T2_cs_clk_in' => 'clk',
'T1_cs_clk_in' => 'clk',
'T0_cs_clk_in' => 'clk',
'T0_ss_clk_in' => 'clk0',
'T3_ss_clk_in' => 'clk0',
'T2_ss_reset_in' => 'reset0',
'T2_cs_reset_in' => 'reset',
'T0_ss_reset_in' => 'reset0',
'T1_ss_clk_in' => 'clk0',
'T3_cs_clk_in' => 'clk',
'T3_cs_reset_in' => 'reset',
'T1_ss_reset_in' => 'reset0',
'T2_ss_clk_in' => 'clk0',
'T0_cs_reset_in' => 'reset',
'NoC_clk' => 'clk',
'T1_cs_reset_in' => 'reset',
'T3_ss_reset_in' => 'reset0',
'NoC_reset' => 'reset'
},
'compile_pin_range_hsb' => {},
'setting' => {
'show_adv_setting' => 0,
'show_noc_setting' => 1,
'show_tile_setting' => 1,
'soc_path' => 'lib/soc'
},
'RAM2' => {
'start' => 49152,
'end' => 65536
},
'top_ip' => bless( {
'ports' => {
'T2_uart_wb_to_jtag' => {
'range' => 'T2_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T1_uart_jtag_to_wb' => {
'range' => 'T1_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'instance_name' => 'T1',
'intfc_port' => 'jwb_i'
},
'clk' => {
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i',
'instance_name' => 'IO',
'type' => 'input'
},
'T3_ram_wb_to_jtag' => {
'instance_name' => 'T3',
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_ram_WB2Jw-1 : 0'
},
'T3_ram_jtag_to_wb' => {
'range' => 'T3_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T3',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T1_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_uart_WB2Jw-1 : 0',
'type' => 'output',
'instance_name' => 'T1',
'intfc_port' => 'jwb_o'
},
'T3_uart_wb_to_jtag' => {
'instance_name' => 'T3',
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_WB2Jw-1 : 0'
},
'processors_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'instance_name' => 'IO',
'intfc_port' => 'enable_i',
'type' => 'input'
},
'reset' => {
'type' => 'input',
'instance_name' => 'IO',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'range' => ''
},
'T0_ram_jtag_to_wb' => {
'range' => 'T0_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'instance_name' => 'T0',
'type' => 'input'
},
'T0_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_J2WBw-1 : 0',
'instance_name' => 'T0',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T1_ram_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_J2WBw-1 : 0',
'type' => 'input',
'instance_name' => 'T1',
'intfc_port' => 'jwb_i'
},
'T3_uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'T3',
'type' => 'input'
},
'T2_uart_jtag_to_wb' => {
'instance_name' => 'T2',
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_J2WBw-1 : 0'
},
'T2_ram_jtag_to_wb' => {
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'instance_name' => 'T2',
'type' => 'input',
'intfc_port' => 'jwb_i'
},
'T1_ram_wb_to_jtag' => {
'instance_name' => 'T1',
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T0_ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'instance_name' => 'T0',
'type' => 'output'
},
'T0_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_WB2Jw-1 : 0',
'type' => 'output',
'instance_name' => 'T0',
'intfc_port' => 'jwb_o'
},
'T2_ram_wb_to_jtag' => {
'type' => 'output',
'instance_name' => 'T2',
'intfc_port' => 'jwb_o',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
},
'interface' => {
'plug:clk[0]' => {
'ports' => {
'clk' => {
'intfc_port' => 'clk_i',
'instance_name' => 'IO',
'type' => 'input',
'range' => ''
}
}
},
'plug:reset[0]' => {
'ports' => {
'reset' => {
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i',
'instance_name' => 'IO'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'T0_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'instance_name' => 'T0',
'type' => 'input',
'range' => 'T0_uart_J2WBw-1 : 0'
},
'T0_ram_jtag_to_wb' => {
'range' => 'T0_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'T0'
},
'T3_uart_jtag_to_wb' => {
'range' => 'T3_uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'T3'
},
'T2_uart_jtag_to_wb' => {
'range' => 'T2_uart_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T2'
},
'T1_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T1',
'range' => 'T1_ram_J2WBw-1 : 0'
},
'T2_ram_jtag_to_wb' => {
'range' => 'T2_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'T2',
'type' => 'input'
},
'T1_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'instance_name' => 'T1',
'type' => 'output',
'range' => 'T1_ram_WB2Jw-1 : 0'
},
'T0_ram_wb_to_jtag' => {
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T0'
},
'T0_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T0',
'range' => 'T0_uart_WB2Jw-1 : 0'
},
'T2_ram_wb_to_jtag' => {
'range' => 'T2_ram_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T2'
},
'T2_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T2',
'range' => 'T2_uart_WB2Jw-1 : 0'
},
'T1_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T1',
'range' => 'T1_uart_J2WBw-1 : 0'
},
'T3_ram_wb_to_jtag' => {
'range' => 'T3_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'instance_name' => 'T3',
'type' => 'output'
},
'T3_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'instance_name' => 'T3',
'range' => 'T3_uart_WB2Jw-1 : 0'
},
'T1_uart_wb_to_jtag' => {
'instance_name' => 'T1',
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T1_uart_WB2Jw-1 : 0'
},
'T3_ram_jtag_to_wb' => {
'range' => 'T3_ram_J2WBw-1 : 0',
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T3'
}
}
},
'plug:enable[0]' => {
'ports' => {
'processors_en' => {
'type' => 'input',
'intfc_port' => 'enable_i',
'instance_name' => 'IO',
'range' => ''
}
}
}
},
'instance_ids' => {
'IO' => {
'ports' => {
'reset' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i',
'type' => 'input'
},
'processors_en' => {
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]',
'range' => ''
},
'clk' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i',
'instance_name' => 'IO',
'range' => ''
'intfc_port' => 'clk_i'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'T2_ram_jtag_to_wb' => {
'range' => 'T2_ram_J2WBw-1 : 0',
'instance_name' => 'T2',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T0_uart_jtag_to_wb' => {
'range' => 'T0_uart_J2WBw-1 : 0',
'instance_name' => 'T0',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T3_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T3',
'range' => 'T3_uart_J2WBw-1 : 0'
},
'T1_uart_wb_to_jtag' => {
'instance_name' => 'T1',
'range' => 'T1_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T0_ram_jtag_to_wb' => {
'instance_name' => 'T0',
'range' => 'T0_ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T3_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T3_ram_J2WBw-1 : 0',
'instance_name' => 'T3'
},
'T3_uart_wb_to_jtag' => {
'range' => 'T3_uart_WB2Jw-1 : 0',
'instance_name' => 'T3',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T2_ram_wb_to_jtag' => {
'instance_name' => 'T2',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T1_ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'T1',
'range' => 'T1_ram_WB2Jw-1 : 0'
},
'T1_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T1_uart_J2WBw-1 : 0',
'instance_name' => 'T1'
},
'T0_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T0_uart_WB2Jw-1 : 0',
'instance_name' => 'T0'
},
'T2_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'range' => 'T2_uart_WB2Jw-1 : 0',
'instance_name' => 'T2'
},
'T2_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T2',
'range' => 'T2_uart_J2WBw-1 : 0'
},
'T1_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'instance_name' => 'T1',
'range' => 'T1_ram_J2WBw-1 : 0'
},
'T0_ram_wb_to_jtag' => {
'instance_name' => 'T0',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T3_ram_wb_to_jtag' => {
'range' => 'T3_ram_WB2Jw-1 : 0',
'instance_name' => 'T3',
'intfc_port' => 'jwb_o',
'type' => 'output'
}
}
},
'IO' => {
'ports' => {
'T0_led_port_o' => {
'instance_name' => 'T0',
'range' => ' 1-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
},
'T3_led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'range' => ' 1-1 : 0',
'instance_name' => 'T3'
},
'T2_led_port_o' => {
'type' => 'output',
'intfc_port' => 'IO',
'instance_name' => 'T2',
'range' => ' 1-1 : 0'
},
'T1_led_port_o' => {
'instance_name' => 'T1',
'range' => ' 1-1 : 0',
'type' => 'output',
'intfc_port' => 'IO'
}
}
},
'plug:reset[0]' => {
'ports' => {
'reset' => {
'instance_name' => 'IO',
'range' => '',
'type' => 'input',
'intfc_port' => 'reset_i'
}
}
}
'T0' => {
'ports' => {
'T0_uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T0_uart_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T0_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T0_ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T0_ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'type' => 'output'
},
'T0_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'T0_ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
}
},
'T3' => {
'ports' => {
'T3_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_ram_WB2Jw-1 : 0'
},
'T3_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_J2WBw-1 : 0'
},
'T3_uart_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_uart_WB2Jw-1 : 0'
},
'T3_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T3_ram_J2WBw-1 : 0'
}
}
},
'T1' => {
'ports' => {
'T1_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'T1_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T1_uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_uart_J2WBw-1 : 0'
},
'T1_uart_wb_to_jtag' => {
'range' => 'T1_uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'T1_ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T1_ram_J2WBw-1 : 0'
}
}
},
'T2' => {
'ports' => {
'T2_ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'T2_ram_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'T2_uart_jtag_to_wb' => {
'range' => 'T2_uart_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'T2_ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_ram_J2WBw-1 : 0'
},
'T2_uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'T2_uart_WB2Jw-1 : 0'
}
}
}
}
}, 'ip_gen' ),
'ROM0' => {
'start' => 0,
'end' => 22937
},
'soc_param' => {
'default' => {
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_JSTATUSw' => '8',
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'ram_Aw' => '14',
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'uart_JDw' => '32',
'ram_JSTATUSw' => '8',
'ram_JINDEXw' => '8',
'uart_JTAG_INDEX' => '126-CORE_ID',
'ram_JAw' => '32',
'ram_JTAG_INDEX' => 'CORE_ID',
'ram_Dw' => '32',
'uart_JAw' => '32',
'ram_JTAG_CHAIN' => '4',
'uart_JINDEXw' => '8',
'ram_JDw' => 'ram_Dw',
'uart_JTAG_CHAIN' => '3'
}
}, 'ip_gen' ),
'MEM1' => {
'width' => '14',
'percent' => '75'
},
'ROM2' => {
'start' => 0,
'end' => 49152
},
'parameters_order' => {
'SOURCE_SET' => [
'clk_number',
'clk_0_name',
'reset_number',
'reset_0_name'
],
'noc_type' => [
'ROUTER_TYPE'
],
'noc_param' => [
'TOPOLOGY',
'T1',
'T2',
'T3',
'V',
'B',
'Fpay',
'ROUTE_NAME',
'MIN_PCK_SIZE',
'BYTE_EN',
'SSA_EN',
'CONGESTION_INDEX',
'ESCAP_VC_MASK',
'VC_REALLOCATION_TYPE',
'COMBINATION_TYPE',
'MUX_TYPE',
'C',
'DEBUG_EN',
'ADD_PIPREG_AFTER_CROSSBAR',
'FIRST_ARBITER_EXT_P_EN',
'SWA_ARBITER_TYPE',
'WEIGHTw',
'AVC_ATOMIC_EN'
],
'SOURCE_SET_CONNECT' => [
'NoC_clk',
'T0_ss_clk_in',
'T1_ss_clk_in',
'T2_ss_clk_in',
'T3_ss_clk_in',
'NoC_reset',
'T0_ss_reset_in',
'T1_ss_reset_in',
'T2_ss_reset_in',
'T3_ss_reset_in',
'T0_cs_clk_in',
'T1_cs_clk_in',
'T2_cs_clk_in',
'T3_cs_clk_in',
'T0_cs_reset_in',
'T1_cs_reset_in',
'T2_cs_reset_in',
'T3_cs_reset_in'
]
},
'ROM3' => {
'start' => 0,
'end' => 49152
},
'gui_status' => {
'status' => 'ideal',
'timeout' => 0
},
'verilator' => {
'libs' => {
'Vtile3' => '--top-module tile_3',
'Vtile0' => '--top-module tile_0',
'Vrouter1' => '--top-module router_top_v -GP=5 ',
'Vtile1' => '--top-module tile_1',
'Vtile2' => '--top-module tile_2'
}
},
'JTAG' => {
'M_CHAIN' => 4
},
'get_config_adj' => {
'va' => '0',
'ha' => '0'
},
'MEM0' => {
'percent' => '70',
'width' => '13'
},
'RAM1' => {
'end' => 65536,
'start' => 49152
},
'MEM3' => {
'width' => '14',
'percent' => '75'
},
'ROM1' => {
'end' => 49152,
'start' => 0
},
'compile_assign_type' => {
'TOP_reset' => 'Direct',
'jtag_debug_reset_in' => 'Direct',
'processors_en' => 'Direct',
'TOP_clk' => 'Direct'
},
'noc_type' => {
'ROUTER_TYPE' => '"VC_BASED"'
},
'liststore' => {
'ha' => '0',
'va' => '0'
},
'fpga_param' => {},
'RAM0' => {
'end' => 32768,
'start' => 22937
}
}, 'mpsoc' );
}, 'mpsoc' );
/lib/perl/Consts.pm
1,8 → 1,8
#This file is created by /home/alireza/work/git/hca_git/ProNoC/mpsoc/intsall.sh
package Consts;
 
use constant VERSION => '1.9.1';
use constant END_YEAR => '2019';
use constant VERSION => '2.1.0';
use constant END_YEAR => '2021';
use constant GTK_VERSION => '3';
 
 
/lib/perl/common.pl
1,3 → 1,5
#!/usr/bin/perl -w
 
use strict;
use warnings;
 
12,7 → 14,21
use Term::ANSIColor qw(:constants);
use IPC::Run qw(start pump finish timeout pumpable);
use FindBin;
use lib $FindBin::Bin;
use constant::boolean;
use IO::CaptureOutput qw(capture qxx qxy);
 
 
our %glob_setting;
$glob_setting{'FONT_SIZE'}='default';
$glob_setting{'ICON_SIZE'}='default';
$glob_setting{'DSPLY_X'} ='default';
$glob_setting{'DSPLY_Y'} ='default';
 
 
 
 
sub log2{
my $num=shift;
my $log=($num <=1) ? 1: 0;
175,8 → 191,7
$all_lib=$all_lib." lib$lib_num";
$lib_num++;
}
 
my $make= "
default: sim
199,14 → 214,21
CPPFLAGS += -W -Werror -Wall
endif
 
SLIB =
HLIB =
ifneq (\$(wildcard synful/synful.a),)
SLIB += synful/synful.a
HLIB += synful/synful.h
endif
 
#######################################################################
# Linking final exe -- presumes have a sim_main.cpp
 
 
sim: testbench.o \$(VK_GLOBAL_OBJS) $p
sim: testbench.o \$(VK_GLOBAL_OBJS) $p \$(SLIB)
\$(LINK) \$(LDFLAGS) -g \$^ \$(LOADLIBES) \$(LDLIBS) -o testbench \$(LIBS) -Wall -O3 -lpthread 2>&1 | c++filt
 
testbench.o: testbench.cpp $h
testbench.o: testbench.cpp $h \$(HLIB)
 
clean:
rm *.o *.a testbench
434,7 → 456,7
while (<$fh>) {
chomp;
#FIXME: this regex isn't quite good enough
next unless my ($var, $value) = /\s*(\w+)=([^#]+)/;
next unless my ($var, $value) = /\s*(\w+)=([^#]+)/;
$ENV{$var} = $value;
}
return undef;
811,7 → 833,13
0x800080,#Purple
0x4B0082,#Indigo
0xFFFFFF,#white
0x000000 #Black
0x000000, #Black
#heatmap
0xbdff00, # (189,255,0)
0xe3f018, # (227,240,24)
0xffce00, # (255,206,0)
0xff6612, # (255,102,18)
0xc12424, # (193,36,36)
);
my $color= ($num< scalar (@colors))? $colors[$num]: 0xFFFFFF;
859,7 → 887,15
"800080",#Purple
"4B0082",#Indigo
"FFFFFF",#white
"000000" #Black
"000000", #Black
#heatmap
"bdff00", # (189,255,0)
"e3f018", # (227,240,24)
"ffce00", # (255,206,0)
"ff6612", # (255,102,18)
"c12424", # (193,36,36)
);
my $color= ($num< scalar (@colors))? $colors[$num]: "FFFFFF";
1052,7 → 1088,7
$scale= 1 if (!defined $scale);
my $diagram;
my $cmd = "echo \'$dotfile\' | dot -Tpng";
my $cmd = "echo \'$dotfile\' | dot -Tpng -q";
my ($stdout,$exit,$stderr)= run_cmd_in_back_ground_get_stdout ($cmd);
if ( length( $stderr || '' ) !=0) {
message_dialog("$stderr\nHave you installed graphviz? If not run \n \t \"sudo apt-get install graphviz\" \n in terminal",'error');
1299,5 → 1335,74
}
 
 
#get the list of files matching the given extention
sub get_file_list_by_extention {
my ($open_in, $ext)=@_;
my @files = glob "$open_in/*";
my $file_list="";
foreach my $file (@files){
my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
if($suffix eq $ext || $suffix eq ".$ext" ){
$file_list.=",$name";
}
}
return ($file_list,\@files);
}
 
 
 
 
sub set_gui_setting{
my $paths=shift;
my %p=%{$paths};
$glob_setting{'FONT_SIZE'}= $p{'GUI_SETTING'}{'FONT_SIZE'} if (defined $p{'GUI_SETTING'}{'FONT_SIZE'});
$glob_setting{'ICON_SIZE'}= $p{'GUI_SETTING'}{'ICON_SIZE'} if (defined $p{'GUI_SETTING'}{'ICON_SIZE'});
$glob_setting{'DSPLY_X'} = $p{'GUI_SETTING'}{'DSPLY_X'} if (defined $p{'GUI_SETTING'}{'DSPLY_X'});
$glob_setting{'DSPLY_Y'} = $p{'GUI_SETTING'}{'DSPLY_Y'} if (defined $p{'GUI_SETTING'}{'DSPLY_Y'});
}
 
my ($screen_x,$screen_y);
 
sub get_default_screen_size{
return ($screen_x,$screen_y) if (defined $screen_x && defined $screen_y);
my $fh= 'xrandr --current | awk \'$2~/\*/{print $1}\'' ;
my ($stdout, $stderr, $success) = qxx( ($fh) );
my @a = split ("\n",$stdout);
($screen_x,$screen_y) = split ("x",$a[0]);
$screen_x = 600 if(!defined $screen_x);
$screen_y = 800 if(!defined $screen_y);
return ($screen_x,$screen_y);
}
 
 
sub get_current_monitor_working_area{
my $screen = get_default_screen();
my $hight = $screen->get_height();
my $active = $screen->get_active_window();
my $monitor = $screen->get_monitor_at_window($active);
my $warea = $screen->get_monitor_workarea($monitor);#get_width();
#print Data::Dumper->Dump ([$warea],['ttt']);
return ($warea->{'width'},$warea->{'height'});
}
 
 
 
 
sub max_win_size {
my ($x,$y);
$x= int($glob_setting{'DSPLY_X'}) if ($glob_setting{'DSPLY_X'} ne 'default');
$y= int($glob_setting{'DSPLY_Y'}) if ($glob_setting{'DSPLY_Y'} ne 'default');
if (!defined $x || !defined $y){
my ($X,$Y)=get_current_monitor_working_area();
$x=$X if (!defined $x);
$y=$Y if (!defined $y);
}
return ($x,$y);
}
 
 
1
/lib/perl/diagram.pl
11,9 → 11,9
require "emulator.pl";
use File::Copy;
 
use Chart::Gnuplot;
 
 
 
sub get_dot_file{
my $self= shift;
my $self_name=$self->object_get_attribute('soc_name');
248,15 → 248,49
 
 
sub show_topology_diagram {
my $self= shift;
 
my ($self)= @_;
my $table=def_table(20,20,FALSE);
my $window=def_popwin_size(80,80,"NoC-based MPSoC topology block diagram",'percent');
my $scrolled_win = add_widget_to_scrolled_win();
$window->add ($table);
my $notebook = gen_notebook();
$notebook->set_tab_pos ('top');
$notebook->set_scrollable(TRUE);
$window->add($notebook);
my @data;
my $ref =$self->object_get_attribute('noc_param');
if(defined $ref){
my %param=%{$ref};
foreach my $p (sort keys %param){
push (@data, {0 => "$p", 1 =>"$param{$p}"});
}
}
# create list store
my @clmn_type = ('Glib::String', 'Glib::String');
my @clmns = (" Parameter Name ", " Value ");
my $page2=add_widget_to_scrolled_win(gen_list_store (\@data,\@clmn_type,\@clmns));
$notebook->append_page ($table,gen_label_with_mnemonic ("Topology diagram")) ;
$notebook->append_page ($page2,gen_label_with_mnemonic ("NoC parameters")) ;
 
 
my $plus = def_image_button('icons/plus.png',undef,TRUE);
my $minues = def_image_button('icons/minus.png',undef,TRUE);
my $save = def_image_button('icons/save.png',undef,TRUE);
304,7 → 338,7
});
$minues -> signal_connect("clicked" => sub{
$scale*=.9 if ($scale >0.1); ;
$scale*=.9 if ($scale >0.1);
$self->object_add_attribute("topology_diagram","scale", $scale );
gen_show_diagram($self,$scrolled_win,'topology',"topology_diagram");
});
331,6 → 365,7
gen_show_diagram($self,$scrolled_win,'topology',"topology_diagram");
$window->show_all();
$notebook->set_current_page (0);
}
 
 
390,8 → 425,8
 
 
sub show_diagram {
my ($self,$scrolled_win,$name)=@_;
my ($self,$scrolled_win,$name,$image_name)=@_;
$image_name="diagram.png" if (!defined $image_name);
my @list = $scrolled_win->get_children();
foreach my $l (@list){
$scrolled_win->remove($l);
401,7 → 436,7
my $scale=$self->object_get_attribute($name,"scale");
$scale= 1 if (!defined $scale);
my $tmp_dir = "$ENV{'PRONOC_WORK'}/tmp";
my $diagram=open_image("$tmp_dir/diagram.png",70*$scale,70*$scale,'percent');
my $diagram=open_image("$tmp_dir/$image_name",70*$scale,70*$scale,'percent');
add_widget_to_scrolled_win($diagram,$scrolled_win);
$scrolled_win->show_all();
671,6 → 706,181
##################################
 
 
 
 
sub generate_heat_map_table{
my ($d)=@_ ;
return (def_table (1, 1, FALSE),def_table (1, 1, FALSE)) if (!defined $d);
my %data=%{$d};
my @xs = (sort {$a<=>$b} keys %data);
my $max=0;
#for(my $y=0; $y<$dim; $y++){
# for(my $x=0; $x<$dim; $x++){
foreach my $y (@xs){
foreach my $x (@xs){
#$data{$x}{$y}=int(rand(50000));
#$data{$x}{$y}=$y*64+$x;
$max = $data{$x}{$y} if( $max < $data{$x}{$y});
}
}
 
my $width_max = length int $max;
my $table = def_table (1, 1, FALSE);
#for(my $y=0; $y<$dim; $y++){
foreach my $y (@xs){
my $l=gen_label_in_center("$y");
$table->attach ($l, $y+1,$y+2,0,1,'expand','shrink',2,2);
}
#for(my $x=0; $x<$dim; $x++){
foreach my $x (@xs){
my $l=gen_label_in_center("$x");
$table->attach ($l, 0,1,$x+1,$x+2,'expand','shrink',2,2);
}
#for(my $y=0; $y<$dim; $y++){
# for(my $x=0; $x<$dim; $x++){
foreach my $y (@xs){
foreach my $x (@xs){
my $d=$data{$x}{$y};
my $c = int (((5*$d))/($max+1));
my $v = length int $d;
until ($v >= $width_max){
$d=" ".$d;
$v++;
}
my $l =gen_colored_label( " " ,32+$c);
set_tip($l,"E[$x]->E[$y]=$d");
$table->attach ($l, $y+1,$y+2,$x+1,$x+2,'expand','shrink',2,2);
}
}
my $scale = def_table (1, 1, FALSE);
my $v=gen_label_in_center("0");
$scale->attach ($v, 1,2,0,1,'expand','shrink',2,2);
for (my $i=0; $i<5; $i++){
my $l =gen_colored_label( " " ,32+$i);
my $val =int( (2*$i+1)*$max/10);
my $v=gen_label_in_center($val);
$scale->attach ($v, 0,1,$i+1,$i+2,'expand','shrink',2,2);
$scale->attach ($l, 1,2,$i+1,$i+2,'expand','shrink',2,2);
$scale->attach (gen_label_in_center("$max"), 1,2,$i+2,$i+3,'expand','shrink',2,2) if($i==4);
}
return ($table,$scale);
}
 
 
sub generate_heat_map_img_file{
my ($d,$image_file,$title)=@_ ;
return if (!defined $d);
my %hash=%{$d};
my @data;
my @xs = (sort {$a<=>$b} keys %hash);
foreach my $y (@xs){
my @b;
push (@data ,\@b) if ($y!=0);
foreach my $x (@xs){
my @a=($x,$y, $hash{$x}{$y});
push (@data ,\@a);
}
}
my $length = @xs;
$length+=1;
 
my $chart = Chart::Gnuplot->new(
bg => 'white',
view => 'map',
palette => 'defined (0 0 0 1, 1 1 1 0, 2 1 0 0)',
output => "$image_file",
title => "$title",
xlabel => 'Endp-ID',
ylabel => 'Endp-ID',
xrange => [-1, $length],
size => 'ratio -1',
xtics => {
labels => \@xs,
},
ytics => {
labels => \@xs,
},
mxtics => '2',
mytics => '2',
border => undef,
grid => 'front mxtics mytics lw 1.5 lt -1 lc rgb \'white\'',
);
my $dataSet = Chart::Gnuplot::DataSet->new(
points => \@data,
view => 'map',
type => 'matrix',
using => "1:2:3 with image",
);
 
 
$chart->plot2d($dataSet);
}
 
 
 
sub generate_heat_map_dot_file{
my ($data,$dim)=@_ ;
my $dotfile=
"digraph G {
graph [layout = neato, rankdir = RL , splines = true, overlap = true];
node[shape=record];
";
for(my $y=0; $y<$dim; $y++){
for(my $x=0; $x<$dim; $x++){
my $tx=$x*2+0.5;
my $ty=($dim-$y-1)*2+0.5;
my $w=2;
$tx/=2;
$ty/=2;
$w/=2;
$dotfile.="
\"t${x}_$y\"[
label = \"8822255\"
pos = \"$tx,$ty!\"
width =$w
height=$w
style=filled
fontsize=\"12\"
fillcolor=orange
];
"
}
}
$dotfile=$dotfile."\n}\n";
return $dotfile;
}
 
 
 
sub generate_mesh_dot_file{
my $self=shift;
/lib/perl/emulator.pl
64,19 → 64,19
my @range=split(':',$p);
my $size= scalar @range;
if($size==1){ # its a number
if ( $range[0] <= 0 || $range[0] >100 ) { message_dialog ("$range[0] is out of boundery (1:100)" ); return undef; }
if ( $range[0] <= 0 || $range[0] >100 ) { message_dialog ("Injection ratio $range[0] is out of bounds: 1<=ratio=<100" ); return undef; }
push(@ratios,$range[0]);
}elsif($size ==3){# its a range
my($min,$max,$step)=@range;
if ( $min <= 0 || $min >100 ) { message_dialog ("$min in $p is out of boundery (1:100)" ); return undef; }
if ( $max <= 0 || $max >100 ) { message_dialog ("$max in $p is out of boundery (1:100)" ); return undef; }
if ( $min <= 0 || $min >100 ) { message_dialog ("Injection ratio $min in $p is out of bounds: 1<=ratio=<100" ); return undef; }
if ( $max <= 0 || $max >100 ) { message_dialog ("Injection ratio $max in $p is out of bounds: 1<=ratio=<100" ); return undef; }
for (my $i=$min; $i<=$max; $i=$i+$step){
push(@ratios,$i);
}
}else{
message_dialog ("$p has invalid format. The correct format for range is \$min:\$max:\$step" );
message_dialog ("Injection ratio $p has an invalid format. The correct format for range is \[min\]:\[max\]:\[step\]" );
return undef;
}
}#foreach
249,8 → 249,11
}
}
my $l= "Define injection ratios. You can define individual ratios seprating by comma (\',\') or define a range of injection ratios with \$min:\$max:\$step format.
As an example defining 2,3,4:10:2 will result in (2,3,4,6,8,10) injection ratios." ;
my $l= "Injection ratios in flits/clk/Endpoint (%).
E.g. Injection ratio 10% means each endpoint inject one flit every 10 cycles.
You can define individual ratios seprating by comma (\',\') or define a range of injection ratios with \$min:\$max:\$step format.
As an example defining 2,3,4:10:2 will result in (2,3,4,6,8,10) injection ratios.
" ;
my $u=get_injection_ratios ($emulate,$sample,"ratios");
attach_widget_to_table ($table,$row,gen_label_in_left("Injection ratios:"),gen_button_message ($l,"icons/help.png") , $u); $row++;
370,14 → 373,24
$l=def_image_button('icons/diagram.png',$name);
$l-> signal_connect("clicked" => sub{
__PACKAGE__->mk_accessors(qw{noc_param});
my $temp = __PACKAGE__->new();
my $st = ($mode eq "simulate" )? check_sim_sample($emulate,$sample,$info) : check_sample($emulate,$sample,$info);
return if $st==0;
my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample);
$emulate->object_add_attribute('noc_param','T1',$T1);
$emulate->object_add_attribute('noc_param','T2',$T2);
$emulate->object_add_attribute('noc_param','T3',$T3);
$emulate->object_add_attribute('noc_param','TOPOLOGY',$topology);
show_topology_diagram ($emulate);
my $ref=$emulate->object_get_attribute($sample,"noc_info");
if (defined $ref){
my %noc_info= %$ref;
foreach my $p (sort keys %noc_info){
$temp->object_add_attribute('noc_param',$p,$noc_info{$p});
}
}
show_topology_diagram ($temp);
});
my $traffic = def_button("Pattern");
873,6 → 886,7
'/mpsoc/rtl/src_peripheral/ram/',
'/mpsoc/rtl/main_comp.v',
'/mpsoc/rtl/arbiter.v',
'/mpsoc/rtl/pronoc_def.v',
'/mpsoc/rtl/src_topolgy/',
'/mpsoc/rtl/src_noc/');
 
/lib/perl/graph.pl
8,7 → 8,6
 
 
 
 
sub gen_multiple_charts{
my ($self,$pageref,$charts_ref,$image_scale)=@_;
my @pages=@{$pageref};
176,6 → 175,7
sub gen_graph {
my ($self,$chart,$image_scale,@selects)=@_;
if($chart->{type} eq '2D_line') {return gen_2D_line($self,$chart,@selects);}
if($chart->{type} eq 'Heat-map') {return gen_heat_map($self,$chart,@selects);}
return gen_3D_bar($self,$chart,$image_scale,@selects);
}
 
182,7 → 182,173
 
 
 
sub gen_heat_map{
my ($self,$chart,@selects)=@_;
my $page_id= "P$chart->{page_num}";
my $graph_id= $page_id."$chart->{graph_name}";
my $result_name= $chart->{result_name};
my $table = def_table (25, 10, FALSE);
my $plus = def_image_button('icons/plus.png',undef,TRUE);
my $minues = def_image_button('icons/minus.png',undef,TRUE);
my $setting = def_image_button('icons/setting.png',undef,TRUE);
my $save = def_image_button('icons/save.png',undef,TRUE);
my $type_combo=gen_combobox_object ($self,"${graph_id}","type","Table,Image",'Table','ref',2);
my @samples =$self->object_get_attribute_order("samples");
@samples = ('-') if (scalar @samples == 0);
my $sample_combx=gen_combobox_object ($self,${graph_id},"sample_sel",join(",", @samples),$samples[0],'ref',2);
my $sample = $self->object_get_attribute("${graph_id}","sample_sel");
my $ref=$self->object_get_attribute ($sample,$result_name);
my @ratios;
@ratios = get_uniq_keys($ref,@ratios);
@ratios = ('-') if (!defined $ratios[0]);
my $rcnt = join(",", @ratios);
my $ratio_combx=gen_combobox_object ($self,${graph_id},"ratio_sel",$rcnt,$ratios[0],'ref',2);
my $content=join( ',', @selects);
my $active_page=gen_combobox_object ($self,$page_id,"active",$content,$selects[0],'ref',2);
my $t = def_table (25, 10, FALSE);
#my $dotfile= generate_heat_map_dot_file(undef,40);
my $r_sel = $self->object_get_attribute("${graph_id}","ratio_sel");
my $dat;
$dat= $ref->{$r_sel} if (defined $ref->{$r_sel});
my $scrolled_win = add_widget_to_scrolled_win($t);
my $heatmap_type =$self->object_get_attribute("${graph_id}","type");
$heatmap_type = 'Table' if (!defined $heatmap_type);
 
my $scale= $self->object_get_attribute("${graph_id}","scale");
if(!defined $scale){
$scale = .5;
$self->object_add_attribute("${graph_id}","scale", $scale );
}
 
my $diagram;
my $map_info;
my $image ="$ENV{PRONOC_WORK}/tmp/heatmap.png";
if($chart->{'graph_name'} ne 'Select'){
if ($heatmap_type eq 'Image'){
my $regen_img= $self->object_get_attribute("${graph_id}","regen_img");
$regen_img = 0 if (!defined $regen_img);
if ($regen_img==1){
my $title= $self->object_get_attribute($page_id,"active");
generate_heat_map_img_file($dat,$image,$title);
$self->object_add_attribute("${graph_id}","regen_img",0);
}
show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png") if(-f $image);
$minues -> signal_connect("clicked" => sub{
$scale*=.9 if ($scale >0.1);
$self->object_add_attribute("${graph_id}","scale", $scale );
show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png") if(-f $image);
});
 
$plus -> signal_connect("clicked" => sub{
$scale*=1.1 if ($scale <10);
$self->object_add_attribute("${graph_id}","scale", $scale );
show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png") if(-f $image);
});
$save-> signal_connect("clicked" => sub{
my $file;
my $title ='Save as';
my @extensions=('png');
my $open_in=undef;
my $dialog=save_file_dialog ($title, @extensions);
$dialog->set_current_folder ($open_in) if(defined $open_in);
if ( "ok" eq $dialog->run ) {
$file = $dialog->get_filename;
my $ext = $dialog->get_filter;
$ext=$ext->get_name;
my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
$file = ($suffix eq ".$ext" )? $file : "$file.$ext";
copy("$image","$file");
}
$dialog->destroy;
});
set_tip($save, "Save graph");
}
else{ #heatmap table
my $t;
($t,$map_info)=generate_heat_map_table($dat);
add_widget_to_scrolled_win($t ,$scrolled_win);
$scrolled_win->show_all();
}
}
# my $scrolled_win = add_widget_to_scrolled_win($t);
# show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png");
$table->attach_defaults ($scrolled_win , 0, 9, 0, 24);
my $row=0;
$type_combo-> signal_connect("changed" => sub{
$self->object_add_attribute("${graph_id}","regen_img",1);
});
$table->attach ($active_page, 9, 10, $row, $row+1,'shrink','shrink',2,2);$row++;
$table->attach ($sample_combx, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach (gen_label_in_center("Injection-Ratio/"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach (gen_label_in_center("Task-file index"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach ($ratio_combx, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach (gen_label_in_center("Graph-Type"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach ($type_combo, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
if ($heatmap_type eq 'Image'){
$table->attach ($plus , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach ($minues, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach ($save, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
}elsif(defined $map_info){
$table->attach ($map_info , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row+=6;
}
#$table->attach ($setting, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
while ($row<10){
my $tmp=gen_label_in_left('');
$table->attach_defaults ($tmp, 9, 10, $row, $row+1);$row++;
}
return $table;
}
 
 
sub gen_3D_bar{
my ($self,$chart,$image_scale,@selects)=@_;
# $image_scale = .4 if (!defined $image_scale);
403,7 → 569,7
my $scale= $self->object_get_attribute("${graph_id}_graph_scale",undef);
$scale = 5 if(!defined $scale);
$minues -> signal_connect("clicked" => sub{
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*1.05);
$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*1.05);
set_gui_status($self,"ref",1);
});
 
426,12 → 592,12
$table->attach_defaults ($align , 0, 9, 0, 25);
$table->attach_defaults ($align , 0, 9, 0, 24);
my $row=0;
$table->attach ($active_page, 0, 9, 24, 25,'shrink','shrink',2,2);
$table->attach (gen_label_in_center("Injection-Ratio/"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach (gen_label_in_center("Task-file index"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach ($ratio_combx, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach ($active_page, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach ($ratio_combx, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
$table->attach ($dimension, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
#$table->attach ($plus , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
444,6 → 610,8
$table->attach_defaults ($tmp, 9, 10, $row, $row+1);$row++;
}
return $table;
}
 
/lib/perl/mpsoc_gen.pl
780,27 → 780,77
$type="Combo-box";
($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,'noc_param');
if($show_noc == 1){
$b1= def_image_button("icons/up.png","NoC Parameters");
$table->attach ( $b1 , 0, 2, $row,$row+1,'fill','shrink',2,2);
$row++;
#CAST_TYPE
$label='Casting Type';
$param='CAST_TYPE';
$default= '"UNICAST"';
$info='Configure a NoC as Unicast, Multicast, or Broadcast NoC. In Unicast NoC, a packet can be sent to only one destination. In Multicast, a single packet can have multiple target destination nodes, whereas, Broadcast packets are sent to all other destination nodes. For Multicast and Broadcast NoC, only one copy of a packet must be injected into the source router. The routers in the path then fork the packets to different output ports when necessary. Multicast and Broadcast can be selected as FULL, where all destinations can be included in packet destination list, or as PARTIAL where a user-defined subset of nodes (defined with MCAST_ENDP_LIST parameter) can be targeted in destination lists. The other nodes not marked in MCAST_ENDP_LIST can only receive unicast packets. ';
$content='"UNICAST","MULTICAST_PARTIAL","MULTICAST_FULL","BROADCAST_PARTIAL","BROADCAST_FULL"';
$type="Combo-box";
($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,'noc_param',1);
my $cast_type=$mpsoc->object_get_attribute('noc_param','CAST_TYPE');
my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
my $cast = $mpsoc->object_get_attribute('noc_param',"MCAST_ENDP_LIST");
if(!defined $cast){
my $h=0;
my $n="";
for (my $i=0; $i<$NE; $i++){
$h+= (1<<$i%4);
if(($i+1) % 4==0){
$n="$h".$n if($h<10);
$n=chr($h-10+97).$n if($h>9);
$h=0;
}
}
$n="$h".$n if($h!=0);
$n="'h".$n;
$mpsoc->object_add_attribute('noc_param',"MCAST_ENDP_LIST",$n);
$mpsoc->object_add_attribute_order('noc_param',"MCAST_ENDP_LIST");
# $mpsoc->object_add_attribute('noc_param',"MCAST_PRTLw",$NE);
# $mpsoc->object_add_attribute_order('noc_param',"MCAST_PRTLw");
$cast=$n;
}
$b1->signal_connect("clicked" => sub{
$show_noc=($show_noc==1)?0:1;
$mpsoc->object_add_attribute('setting','show_noc_setting',$show_noc);
set_gui_status($mpsoc,"ref",1);
});
 
#advance parameter start
my $advc;
my $adv_set=$mpsoc->object_get_attribute('setting','show_adv_setting');
if($adv_set == 0){
$advc= def_image_button("icons/down.png","Advance Parameters");
$table->attach ( $advc , 0, 2, $row,$row+1,'fill','shrink',2,2);
$row++;
if($cast_type eq '"MULTICAST_PARTIAL"' || $cast_type eq '"BROADCAST_PARTIAL"') {
#$table->attach ( gen_label_help($info,"Muticast Node list"),0 , 2, $row,$row+1,'fill','shrink',2,2);
$info='MCAST_ENDP_LIST is a one-hot coded number where the asserted bit indicates that the corresponding destination ID can be targeted in multicast/broadcast packets. The corresponding destinations with zero bit can only receive unicast packets.';
my $b1= def_image_button("icons/setting.png","Set");
my $bb= def_pack_hbox(FALSE,0,gen_label_in_left("$cast"),$b1);
my $label=gen_label_in_left("Muticast Node list");
my $inf_bt= (defined $info)? gen_button_message ($info,"icons/help.png"):gen_label_in_left(" ");
attach_widget_to_table ($table,$row,$label,$inf_bt,$bb,0);
# $table->attach ( $bb , 2, 3, $row,$row+1,'fill','shrink',2,2);
$row++;
$b1->signal_connect("clicked" => sub{
set_multicast_list($mpsoc);
});
}
#advance parameter start
# my $advc;
# my $adv_set=$mpsoc->object_get_attribute('setting','show_adv_setting');
#
# if($adv_set == 0){
# $advc= def_image_button("icons/down.png","Advance Parameters");
# $table->attach ( $advc , 0, 2, $row,$row+1,'fill','shrink',2,2);
# $row++;
# }
my $adv_set= $show_noc;
#SSA
$label='SSA Enable';
$param='SSA_EN';
1006,19 → 1056,32
#($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$wrra_show,'noc_param',undef);
if($adv_set == 1){
$advc= def_image_button("icons/up.png","Advance Parameters");
$table->attach ( $advc , 0, 2, $row,$row+1,'fill','shrink',2,2);
$row++;
if($show_noc == 1){
$b1= def_image_button("icons/up.png","NoC Parameters");
$table->attach ( $b1 , 0, 2, $row,$row+1,'fill','shrink',2,2);
$row++;
}
$advc->signal_connect("clicked" => sub{
$adv_set=($adv_set==1)?0:1;
$mpsoc->object_add_attribute('setting','show_adv_setting',$adv_set);
$b1->signal_connect("clicked" => sub{
$show_noc=($show_noc==1)?0:1;
$mpsoc->object_add_attribute('setting','show_noc_setting',$show_noc);
set_gui_status($mpsoc,"ref",1);
});
# if($adv_set == 1){
# $advc= def_image_button("icons/up.png","Advance Parameters");
# $table->attach ( $advc , 0, 2, $row,$row+1,'fill','shrink',2,2);
# $row++;
# }
# $advc->signal_connect("clicked" => sub{
# $adv_set=($adv_set==1)?0:1;
# $mpsoc->object_add_attribute('setting','show_adv_setting',$adv_set);
# set_gui_status($mpsoc,"ref",1);
# });
#other fixed parameters
1045,6 → 1108,135
}
 
 
 
 
sub set_multicast_list{
my($mpsoc)=@_;
my $window = def_popwin_size(50,40,"Select nodes invlove in multicasting ",'percent');
my $table= def_table(10,10,FALSE);
my $row=0;
my $col=0;
my $init = $mpsoc->object_get_attribute('noc_param',"MCAST_ENDP_LIST");
$init =~ s/'h//g;
my @arr= reverse split (//, $init);
my $label = "Multicast Node list (hex fromat)";
my ($Ebox,$entry) = def_h_labeled_entry ($label);
$entry->set_sensitive (FALSE);
my @sel_options= ("Select","All","None","2n","3n","4n","2n+1","3n+1","3n+2","4n+1","4n+2","4n+3");
my $combo= gen_combo(\@sel_options, 0);
$table->attach ($combo , 0, 1, $row,$row+1,'fill','shrink',2,2);
#get the number of endpoints
my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
my @check;
my $sel_val="Init";
for (my $i=0; $i<$NE; $i++){
if($i%10 == 0){ $row++;$col=0;}
my $box;
my $l=$NE -$i-1;
my $char = $arr[$l/4];
$char=0 if (!defined $char);
my $hex = hex($char);
my $bit = ($hex >> ($l%4)) & 1;
($box,$check[$l])=def_h_labeled_checkbutton("$l");
$table->attach ($box , $col, $col+1, $row,$row+1,'fill','shrink',2,2);
$col++;
if($bit==1){
$check[$l]->set_active(TRUE);
}
$check[$l]-> signal_connect("toggled" => sub{
get_multicast_val ($mpsoc,$entry,$NE,@check)if($sel_val eq "Select");
});
}
$row++;
$col=0;
$sel_val="Select";
get_multicast_val ($mpsoc,$entry,$NE,@check);
$combo-> signal_connect("changed" => sub{
$sel_val=$combo->get_active_text();
my $n=1;
my $r=0;
return if ($sel_val eq "Select");
if ($sel_val eq "None"){
for (my $i=0; $i<$NE; $i++){$check[$i]->set_active(FALSE)};
get_multicast_val ($mpsoc,$entry,$NE,@check);
$combo->set_active(0);
return;
}
($n,$r)=sscanf("%dn+%d",$sel_val);
if(!defined $r){
($n,$r)=sscanf("%dn",$sel_val);
$r=0;
$n=1 if(!defined $n);
}
for (my $i=0; $i<$NE; $i++){
if($i % $n == $r){ $check[$i]->set_active(TRUE);}
}
$combo->set_active(0);
get_multicast_val ($mpsoc,$entry,$NE,@check);
});
$table->attach ($Ebox , 0, 10, $row,$row+1,'fill','shrink',2,2);$row++;
my $main_table=def_table(10,10,FALSE);
my $ok = def_image_button('icons/select.png','OK');
$main_table->attach_defaults ($table , 0, 12, 0,11);
$main_table->attach ($ok,5, 6, 11,12,'shrink','shrink',0,0);
$ok->signal_connect('clicked', sub {
my $s=get_multicast_val ($mpsoc,$entry,$NE,@check);
my $n=$entry->get_text( );
$mpsoc->object_add_attribute('noc_param',"MCAST_ENDP_LIST",$n);
# $mpsoc->object_add_attribute('noc_param',"MCAST_PRTLw",$s);
set_gui_status($mpsoc,"ref",1);
$window->destroy;
});
my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'gen_multicast');
add_widget_to_scrolled_win($main_table,$scrolled_win);
$window->add($scrolled_win);
$window->show_all();
}
 
sub get_multicast_val {
my ($mpsoc,$entry,$NE,@check)=@_;
my $n="";
my $h=0;
my $s=0;
for (my $i=0; $i<$NE; $i++){
if($check[$i]->get_active()){$h+= (1<<$i%4);$s++;}
if(($i+1) % 4==0){
$n="$h".$n if($h<10);
$n=chr($h-10+97).$n if($h>9);
$h=0;
}
}
$n="$h".$n if($NE%4!=0);
$n="'h".$n;
$entry->set_text("$n");
return $s;
}
#############
# config_custom_topology_gui
############
/lib/perl/mpsoc_verilog_gen.pl
322,10 → 322,12
my $pass_param="";
my @params=$mpsoc->object_get_attribute_order('noc_param');
my $custom_topology = $mpsoc->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
my %noc_info;
if(defined $sample ){
my $ref=$mpsoc->object_get_attribute($sample,"noc_info");
%noc_info= %$ref;
%noc_info= %$ref;
($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_from_parameters($ref);
}
foreach my $p (@params){
333,6 → 335,10
my $val= (defined $sample) ? $noc_info{$p} :$mpsoc->object_get_attribute('noc_param',$p);
next if($p eq "CUSTOM_TOPOLOGY_NAME");
$val=$custom_topology if($p eq "TOPOLOGY" && $val eq "\"CUSTOM\"");
if($p eq 'MCAST_ENDP_LIST'){
$val="$NE".$val;
}
$param_v= $param_v."\tlocalparam $p=$val;\n";
$pass_param=$pass_param."\t\t.$p($p),\n";
#print "$p:$val\n";
376,7 → 382,11
$topology =~ s/"//g;
$param_h.="\t#define IS_${topology}\n";
my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
my @params=$mpsoc->object_get_attribute_order('noc_param');
my $custom_topology = $mpsoc->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
foreach my $p (@params){
383,6 → 393,12
my $val=$mpsoc->object_get_attribute('noc_param',$p);
next if($p eq "CUSTOM_TOPOLOGY_NAME");
$val=$custom_topology if($p eq "TOPOLOGY" && $val eq "\"CUSTOM\"");
if($p eq "MCAST_ENDP_LIST" || $p eq "ESCAP_VC_MASK"){
$val="$NE".$val if($p eq 'MCAST_ENDP_LIST');
$val =~ s/\'/\\\'/g;
$val="\"$val\"";
}
$param_h=$param_h."\t#define $p\t$val\n";
#print "$p:$val\n";
415,8 → 431,10
#add_text_to_string (\$pass_param,".CVw(CVw)\n");
#remove 'b and 'h
#$param_h =~ s/\d\'b/ /g;
#$param_h =~ s/\'h/ /g;
return $param_h;
}
 
448,7 → 466,8
.reset(noc_reset_in),
.clk(noc_clk_in),
.chan_in_all(ni_chan_out),
.chan_out_all(ni_chan_in)
.chan_out_all(ni_chan_in),
.router_event( )
);
/lib/perl/network_maker.pl
2837,6 → 2837,7
#generate_connection_v($self,$info,$dir);
add_routing_instance_v($self,$info,$dir);
add_noc_instance_v($self,$info,$dir);
add_noc_custom_h($self,$info,$dir);
save_topology_parameter_object_file($self,$info);
#create the file list
/lib/perl/run_time_jtag_debug.pl
46,9 → 46,9
 
my $NAME = 'Soure Probe';
my $path = "";
our $FONT_SIZE='default';
our $ICON_SIZE='default';
 
 
 
my %memory;
my %status;
 
60,9 → 60,7
my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
if (-f $paths_file){#} && defined $ENV{PRONOC_WORK} ) {
my $paths= do $paths_file;
my %p=%{$paths};
$FONT_SIZE= $p{'GUI_SETTING'}{'FONT_SIZE'} if (defined $p{'GUI_SETTING'}{'FONT_SIZE'});
$ICON_SIZE= $p{'GUI_SETTING'}{'ICON_SIZE'} if (defined $p{'GUI_SETTING'}{'ICON_SIZE'});
set_gui_setting($paths);
}
set_defualt_font_size();
/lib/perl/simulator.pl
45,8 → 45,8
$tops{Vpck_inj} = "--top-module packet_injector_verilator";
my $target_dir= "$ENV{PRONOC_WORK}/simulate";
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/..");
my $project_dir = get_project_dir()."/mpsoc/";
my $src_verilator_dir="$project_dir/src_verilator";
my $src_c="$project_dir/src_c";
my $src_noc_dir="$project_dir/rtl/src_noc";
73,6 → 73,7
push (@files,$src_noc_dir);
push (@files,"$project_dir/rtl/arbiter.v");
push (@files,"$project_dir/rtl/main_comp.v");
push (@files,"$project_dir/rtl/pronoc_def.v");
#my @files=(
103,8 → 104,8
}
copy_file_and_folders (\@files,$project_dir,$target_modelsim_dr);
#check if we have a custom topology
my $topology=$simulate->object_get_attribute('noc_param','TOPOLOGY');
150,6 → 151,13
return;
}
my $r;
#copy nettrace synful
dircopy("$src_c/netrace-1.0","$obj_dir/netrace-1.0") or $r=$!;
dircopy("$src_c/synfull","$obj_dir/synful") or $r=$!;
add_colored_info($info_text,"ERROR: $r\n","red") if(defined $r ) ;
#copy simulation c header files
@files = File::Find::Rule->file()
->name( '*.h')
158,16 → 166,13
copy_file_and_folders (\@files,$project_dir,$obj_dir);
copy($testbench_file,"$obj_dir/testbench.cpp");
my $r;
#copy nettrace
dircopy("$src_c/netrace-1.0","$obj_dir/netrace-1.0") or $r=$!;
add_colored_info($info_text,"ERROR: $r\n","red") if(defined $r ) ;
#compile the testbench
my $param_h=gen_noc_param_h($simulate);
my $text = gen_sim_parameter_h($param_h,$includ_h,$ne,$nr,$router_p,$fifow);
$param_h =~ s/\d\'b/ /g;
open(FILE, ">$obj_dir/parameter.h") || die "Can not open: $!";
print FILE "$text";
392,7 → 397,8
my $table=def_table(10,2,FALSE);
my $row=0;
my $scrolled_win = add_widget_to_scrolled_win ($table);
my $scrolled_win = add_widget_to_scrolled_win ($table,gen_scr_win_with_adjst($self,'noc_conf_scr_win'));
my $ok = def_image_button('icons/select.png','_OK',FALSE,1);
my $import = def_image_button('icons/import.png','I_mport',FALSE,1);
465,14 → 471,43
$exe_files="$exe_files,$name";
}
}
my $model_obj = gen_combobox_object ($self,$sample, "sof_file", $exe_files, undef,'ref_set_win',1);
attach_widget_to_table ($table,$row,gen_label_in_left(" Verilated Model:"),gen_button_message ("Select the verilator simulation file. Different NoC simulators can be generated using Generate NoC configuration tab.","icons/help.png"),
gen_combobox_object ($self,$sample, "sof_file", $exe_files, undef,'ref_set_win',1)); $row++;
$model_obj); $row++;
my $cast_type= '"UNICAST"';
#get simulation parameters here
my $s=$self->object_get_attribute($sample,"sof_file");
if (defined $s){
my ($infobox,$info)= create_txview();
my $sof=get_sim_bin_path($self,$sample,$info);
my ($name,$path,$suffix) = fileparse("$sof",qr"\..[^.]*$");
my $sof_info= "$path$name.inf";
my $pp= do $sof_info ;
my $p=$pp->{'noc_param'};
$cast_type = $p->{'CAST_TYPE'};
$cast_type= '"UNICAST"' if (!defined $cast_type);
}
my $trf_info = "Select of the following traffic models:
1- Synthetic
2- Task-graph :
The task graph traffic pattern can be generated
using ProNoC trace generator
3- Netrace:
Dependency-Tracking Trace-Based Network-on-Chip
Simulation. For downloading the trace files and more
information refere to https://www.cs.utexas.edu/~netrace/
4- SynFull:
Synthetic Traffic Models Capturing a Full Range
of Cache Coherent Behaviour
https://github.com/mariobadr/synfull-isca
";
my $coltmp=0;
($row,$coltmp)=add_param_widget ($self, "Traffic Type", "TRAFFIC_TYPE", "Synthetic", 'Combo-box', "Synthetic,Task-graph", undef, $table,$row,undef,1, $sample, 1,'ref_set_win');
($row,$coltmp)=add_param_widget ($self, "Traffic Type", "TRAFFIC_TYPE", "Synthetic", 'Combo-box', "Synthetic,Task-graph,SynFull,Netrace", $trf_info, $table,$row,undef,1, $sample, 1,'ref_set_win');
my $traffictype=$self->object_get_attribute($sample,"TRAFFIC_TYPE");
my $MIN_PCK_SIZE=$self->object_get_attribute($sample,"MIN_PCK_SIZE");
607,6 → 642,31
}
if ($cast_type ne '"UNICAST"'){
my $min=$self->object_get_attribute($sample,'MCAST_PCK_SIZ_MIN');
my $max=$self->object_get_attribute($sample,'MCAST_PCK_SIZ_MAX');
$min=5 if(!defined $min);
$max=5 if(!defined $max);
$max= $min if($max< $min);
my $s = ($cast_type eq '"BROADCAST_FULL"' || $cast_type eq '"BROADCAST_PARTIAL"')? "Broadcast" : "Milticast";
my $info1= "Define the percentage ratio of $s traffic towards Unicast traffic";
my $info2= "Define how destinations is selected in Multicast packets";
($row,$coltmp)=add_param_widget ($self, "$s Node Select" , "MCAST_TRAFFIC_TYPE" , "Uniform-Random", 'Combo-box', "Uniform-Random", $info1, $table,$row,undef,1, $sample);
($row,$coltmp)=add_param_widget ($self, "$s Traffic Ratio", "MCAST_TRAFFIC_RATIO", 5 , 'Spin-button', "0,100,1" , $info2, $table,$row,undef,1, $sample);
($row,$coltmp)=add_param_widget ($self, "$s min pck size", "MCAST_PCK_SIZ_MIN", 5 , 'Spin-button', "1,$max,1" , $info2, $table,$row,undef,1, $sample,1,'ref_set_win');
($row,$coltmp)=add_param_widget ($self, "$s max pck size", "MCAST_PCK_SIZ_MAX", 5 , 'Spin-button', "$min,100,1" , $info2, $table,$row,undef,1, $sample,1,'ref_set_win');
}
my $d= { label=>'number of message class:', param_name=>'MESSAGE_CLASS', type=>'Spin-button', default_val=>0, content=>"0,256,1", info=>"Number of packet message classes. Each message class can be configured to use specefic subset of avilable VCs", param_parent=>$sample, ref_delay=> 1, new_status=>'ref_set_win'};
($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
my $num=$self->object_get_attribute($sample,"MESSAGE_CLASS");
675,6 → 735,7
my $s=$self->object_get_attribute($sample,"sof_file");
#check if injection ratios are valid
my $r=$self->object_get_attribute($sample,"ratios");
my $h;
my $t=$self->object_get_attribute($sample,"PCK_SIZ_SEL");
690,7 → 751,12
$h= check_hotspot_parameters($self,$sample);
}
if(defined $s && defined $r && !defined $h) {
my $v;
if(defined $r ){
$v=check_inserted_ratios($r);
}
if(defined $s && defined $r && defined $v && !defined $h) {
#$set_win->destroy;
$set_win->hide();
$self->object_add_attribute("active_setting",undef,undef);
702,7 → 768,7
message_dialog($m);
} elsif (! defined $r) {
message_dialog("Please define valid injection ratio(s)!");
} else {
} elsif (defined $h){
message_dialog("$h");
}
}
771,6 → 837,129
}
if($traffictype eq "SynFull"){
#get the synful model names
my $models_dir = get_project_dir()."/mpsoc/src_c/synfull/generated-models/";
my ($flist)=get_file_list_by_extention ("$models_dir",".model");
my $model_obj = gen_combobox_object ($self,$sample, "MODEL_NAME", $flist, undef,undef,undef);
attach_widget_to_table ($table,$row,gen_label_in_left(" Traffic Model name:"),gen_button_message ("Select an application traffic model.","icons/help.png"),
$model_obj); $row++;
my @custominfo = (
{ label=>"Synful Flit-size:(Bytes)", param_name=>'SYNFUL_FLITw', type=>'Spin-button', default_val=>4, content=>"4,72,4", info=>"The synful flit size in Byte. It defines the number of flits that should be set to ProNoC for each synful packets. The ProNoC packet size is :
\t Ceil( synful packet size/synful flit size). ", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
{ label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configuration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
{ label=>"Total packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>200000, content=>"2,$max_pck_num,1", info=>"Simulation will stop when total number of sent packets by all nodes reaches packet number limit or total simulation clock reach its limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
{ label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,$max_sim_clk,1", info=>"Each node stops sending packets when it reaches packet number limit or simulation clock number limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
{ label=>"Markov Chain Random seed:", param_name=>'RND_SEED', type=>'Spin-button', default_val=>53432145, content=>"0,999999999,1", info=>"The seed valus is passe to synfull random number generator.", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
{ label=>"Exit at steady state:", param_name=>'EXIT_STEADY', type=>'Check-box', default_val=>0, content=>"1", info=>"Exit the simulation when it reaches to a steady state.", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
);
foreach my $d (@custominfo) {
($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
}
$ok->signal_connect("clicked"=> sub{
#check if sof file has been selected
my $s=$self->object_get_attribute($sample,"MODEL_NAME");
if(!defined $s){
message_dialog("Please select a SynFull traffic model");
return;
}
#$set_win->destroy;
$set_win->hide();
$self->object_add_attribute("active_setting",undef,undef);
set_gui_status($self,"ref",1);
});
}#SynFull
if($traffictype eq "Netrace"){
#get the synful model names
my $models_dir = "$ENV{PRONOC_WORK}/simulate/netrace";
my ($flist)=get_file_list_by_extention ("$models_dir",".bz2");
my $model_obj = gen_combobox_object ($self,$sample, "MODEL_NAME", $flist, undef,undef,undef);
my $download=def_image_button("icons/download.png",'Download');
my $box =def_hbox(FALSE, 0);
$box->pack_start( $model_obj , 1,1, 0);
$box->pack_start( $download, 0, 1, 3);
attach_widget_to_table ($table,$row,gen_label_in_left(" Trace name:"),gen_button_message ("Select a netrace trace file. You can download traces using download button.","icons/help.png"),
$box);
$row++;
my @custominfo = (
{ label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configuration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
{ label=>"Total packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>200000, content=>"2,$max_pck_num,1", info=>"Simulation will stop when total number of sent packets by all nodes reaches packet number limit or total simulation clock reach its limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
#{ label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,$max_sim_clk,1", info=>"Each node stops sending packets when it reaches packet number limit or simulation clock number limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
{ label=>"ignore dependencies:", param_name=>'IGNORE_DPNDCY', type=>'Check-box', default_val=>0, content=>"1", info=>"Ignore dependency between packets", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
{ label=>"Enable reader throttling:", param_name=>'READER_THRL', type=>'Check-box', default_val=>0, content=>"1", info=>"If Reader throttling is enabled, simulators offloads much of the work of reading and tracking packets to the Netrace reader,
which simplifies the code in the network simulator.", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
{ label=>"trace file start region:", param_name=>'START_RGN', type=>'Spin-button', default_val=>0, content=>"0,10000,1", info=>undef, param_parent=>$sample, ref_delay=>undef, new_status=>undef},
{ label=>"Netrace to Pronoc clk ratio:", param_name=>'SPEED_UP', type=>'Spin-button', default_val=>1, content=>"1,99,1", info=>"The ratio of netrace frequency to pronoc.The higher value results in higher injection ratio to the NoC. Default is one\n", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
);
foreach my $d (@custominfo) {
($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
}
$ok->signal_connect("clicked"=> sub{
#check if sof file has been selected
my $s=$self->object_get_attribute($sample,"MODEL_NAME");
if(!defined $s){
message_dialog("Please select a SynFull traffic model");
return;
}
#$set_win->destroy;
$set_win->hide();
$self->object_add_attribute("active_setting",undef,undef);
set_gui_status($self,"ref",1);
});
$download->signal_connect("clicked"=> sub{ download_netrace("$models_dir") });
 
 
}#netrace
add_widget_to_scrolled_win ($mtable,$set_win);
$set_win->show_all();
800,9 → 989,9
next if($status ne "run");
next if(!check_sim_sample($simulate,$sample,$info));
my $traffictype=$simulate->object_get_attribute($sample,"TRAFFIC_TYPE");
run_synthetic_simulation($simulate,$info,$sample,$name) if($traffictype eq "Synthetic");
run_task_simulation($simulate,$info,$sample,$name) if($traffictype eq "Task-graph");
if($traffictype eq "Synthetic") {run_synthetic_simulation($simulate,$info,$sample,$name);}
elsif($traffictype eq "Task-graph"){run_task_simulation($simulate,$info,$sample,$name) ;}
else {run_trace_simulation($simulate,$info,$sample,$name);}
}
878,7 → 1067,31
$custom_sv.="localparam CUSTOM_NODE_NUM=0;\n\twire [NEw-1 : 0] custom_traffic_t [NE-1 : 0];\n\twire [NE-1 : 0] custom_traffic_en;
";
}
#multicast
my $mcast="";
my $mcast_sv="";
my $p= $simulate->object_get_attribute ($sample,"noc_info");
my $cast_type=$p->{"CAST_TYPE"};
if ($cast_type ne '"UNICAST"'){
#$self->object_get_attribute ($sample, "MCAST_TRAFFIC_TYPE");
my $mr = $simulate->object_get_attribute ($sample, "MCAST_TRAFFIC_RATIO");
my $mmax = $simulate->object_get_attribute ($sample, "MCAST_PCK_SIZ_MAX");
my $mmin = $simulate->object_get_attribute ($sample, "MCAST_PCK_SIZ_MIN");
$mcast = "-u \"$mr,$mmin,$mmax\"";
$mcast_sv.= "localparam MCAST_TRAFFIC_RATIO = $mr;\n";
$mcast_sv.= "localparam MCAST_PCK_SIZ_MAX = $mmax;\n";
$mcast_sv.= "localparam MCAST_PCK_SIZ_MIN = $mmin;\n";
}else {
$mcast_sv.= "localparam MCAST_TRAFFIC_RATIO = 0;\n";
$mcast_sv.= "localparam MCAST_PCK_SIZ_MAX = 0;\n";
$mcast_sv.= "localparam MCAST_PCK_SIZ_MIN = 0;\n";
}
my $classes;
my $num=$simulate->object_get_attribute($sample,"MESSAGE_CLASS");
$classes.="-p 100" if($num==0);
979,11 → 1192,14
MAX_PACKET_SIZE=$MAX_PCK_SIZE,
STOP_PCK_NUM=$PCK_NUM_LIMIT,
STOP_SIM_CLK=$SIM_CLOCK_LIMIT;
$hotspot_sv
$custom_sv
$mcast_sv
$discrete_sv
parameter INJRATIO=90;
1053,16 → 1269,16
if ($simulator eq 'Modelsim'){
add_info($info, "Run $bin with injection ratio of $ratio_in \% \n");
my $out="$out_path/modelsim/work$c";
$cmd=" xterm -e bash -c ' cd $out; sed -i \"s/ INJRATIO=\[\[:digit:\]\]\\+/ INJRATIO=$ratio_in/\" $out/sim_param.sv; rm -Rf rtl_work; $vsim -c -do $out/model.tcl -l $out_path/sim_out$ratio_in;' &\n ";
$cmd=" xterm -e bash -c ' cd $out; sed -i \"s/ INJRATIO=\[\[:digit:\]\]\\+/ INJRATIO=$ratio_in/\" $out/sim_param.sv; rm -Rf rtl_work; $vsim -c -do $out/model.tcl -l $out_path/sim_out$ratio_in;' &\n ";
}elsif ($simulator eq 'Modelsim gui'){
add_info($info, "Run $bin with injection ratio of $ratio_in \% \n");
my $out="$out_path/modelsim/work$c";
$cmd="cd $out; sed -i \"s/ INJRATIO=\[\[:digit:\]\]\\+/ INJRATIO=$ratio_in/\" $out/sim_param.sv; rm -Rf rtl_work; $vsim -do $out/model.tcl -l $out_path/sim_out$ratio_in; ";
$cmd="cd $out; sed -i \"s/ INJRATIO=\[\[:digit:\]\]\\+/ INJRATIO=$ratio_in/\" $out/sim_param.sv; rm -Rf rtl_work; $vsim -do $out/model.tcl -l $out_path/sim_out$ratio_in; ";
}else{
add_info($info, "Run $bin with injection ratio of $ratio_in \% \n");
$cmd="$bin -t \"$patern\" $pck_size -T $thread_num -n $PCK_NUM_LIMIT -c $SIM_CLOCK_LIMIT -i $ratio_in $classes $hotspot $custom > $out_path/sim_out$ratio_in & ";
$cmd="$bin -t \"$patern\" $pck_size -T $thread_num -n $PCK_NUM_LIMIT -c $SIM_CLOCK_LIMIT -i $ratio_in $classes $hotspot $custom $mcast > $out_path/sim_out$ratio_in & ";
}
$cmds .=$cmd;
1118,45 → 1334,59
}
 
sub extract_and_update_noc_sim_statistic {
my ($simulate,$sample,$ratio_in,$stdout)=@_;
my @results = split("#node,",$stdout);
 
sub extract_st_by_name{
my($st_name, $stdout)=@_;
my @results = split($st_name,$stdout);
my %statistcs;
my @lines = split("\n",$results[1]);
#first line is statsitic names
my @lines = split("\n",$results[1]);
my @names;
my $i=0;
foreach my $line (@lines){
$line=remove_all_white_spaces($line);
$line =~ s/^#//g; #remove # from beginig of each line in modelsim
if($i==0){
@names=split(",",$line);
}else{
if($i==0) {
$i++;
next;
}
elsif($i==1){
#first line is statsitic names
@names=split(",",$line);
$i++;
next;
}elsif(length($line)>1) {
my @fileds=split(",",$line);
my $j=0;
#print ("ff :@fileds\n");
foreach my $f (@fileds){
unless($j==0){
$statistcs{$fileds[0]}{$names[$j-1]}=$f;
$statistcs{$fileds[0]}{$names[$j]}=$f;
}
$j++;
}
$i++;
}else{ #empty line end of endp statistic
last;
}
$i++;
}
#print Dumper(\%statistcs);
return %statistcs;
}
 
 
 
sub extract_and_update_noc_sim_statistic {
my ($simulate,$sample,$ratio_in,$stdout)=@_;
my $total_time =capture_number_after("Simulation clock cycles:",$stdout);
 
my %packet_rsvd_per_core = capture_cores_data("total number of received packets:",$stdout);
my %worst_rsvd_delay_per_core = capture_cores_data('worst-case-delay of received packets \(clks\):',$stdout);
my %packet_sent_per_core = capture_cores_data("total number of sent packets:",$stdout);
my %worst_sent_delay_per_core = capture_cores_data('worst-case-delay of sent packets \(clks\):',$stdout);
next if (!defined $statistcs{"total"}{'avg_latency_pck'});
my %statistcs = extract_st_by_name("Endpoints Statistics:",$stdout);
return if (!defined $statistcs{"total"}{'avg_latency_pck'});
update_result($simulate,$sample,"latency_result",$ratio_in,$statistcs{"total"}{'avg_latency_pck'});
update_result($simulate,$sample,"latency_flit_result",$ratio_in,$statistcs{"total"}{'avg_latency_flit'});
update_result($simulate,$sample,"sd_latency_result",$ratio_in,$statistcs{"total"}{'avg.std_dev'});
1173,7 → 1403,33
update_result($simulate,$sample,"worst_delay_rsvd_result",$ratio_in,$p,$statistcs{$p}{'rsvd_stat.worst_latency'});
update_result($simulate,$sample,"packet_sent_result",$ratio_in,$p,$statistcs{$p}{'sent_stat.pck_num'} );
update_result($simulate,$sample,"worst_delay_sent_result",$ratio_in,$p,$statistcs{$p}{'sent_stat.worst_latency'});
update_result($simulate,$sample,"flit_rsvd_result",$ratio_in,$p,$statistcs{$p}{'rsvd_stat.flit_num'});
update_result($simulate,$sample,"flit_sent_result",$ratio_in,$p,$statistcs{$p}{'sent_stat.flit_num'});
}
my %st1 = extract_st_by_name("Endp_to_Endp flit_num:",$stdout);
update_result($simulate,$sample,"endp-endp-flit_result",$ratio_in,\%st1);
my %st2 = extract_st_by_name("Endp_to_Endp pck_num:",$stdout);
update_result($simulate,$sample,"endp-endp-pck_result",$ratio_in,\%st2);
my %st3 = extract_st_by_name("Routers' statistics:",$stdout);
foreach my $p (sort keys %st3){
update_result($simulate,$sample,"flit_per_router_result",$ratio_in,$p,$st3{$p}{'flit_in'});
update_result($simulate,$sample,"packet_per_router_result",$ratio_in,$p,$st3{$p}{'pck_in'});
my $tmp= ($st3{$p}{'flit_in_buffered'}*100) / $st3{$p}{'flit_in'};
#print " $tmp= ($st3{$p}{'flit_in_buffered'}*100) / $st3{$p}{'flit_in'};\n";
update_result($simulate,$sample,"flit_buffered_router_ratio",$ratio_in,$p,$tmp);
$tmp= ($st3{$p}{'flit_in_bypassed'}*100) / $st3{$p}{'flit_in'};
update_result($simulate,$sample,"flit_bypass_router_ratio",$ratio_in,$p,$tmp);
}
#my $p= $simulate->object_get_attribute ($sample,"noc_info");
# my $TOPOLOGY=$p->{"TOPOLOGY"};
#print "$TOPOLOGY\n";
}
 
 
1250,6 → 1506,103
 
 
 
 
sub run_trace_simulation{
my ($simulate,$info,$sample,$name)=@_;
my $log= (defined $name)? "$ENV{PRONOC_WORK}/simulate/$name.log": "$ENV{PRONOC_WORK}/simulate/sim.log";
my $bin=get_sim_bin_path($simulate,$sample,$info);
my $project_dir = get_project_dir();
$bin= "$project_dir/$bin" if(!(-f $bin));
my $cpu_num = $simulate->object_get_attribute('compile', 'cpu_num');
$cpu_num = 1 if (!defined $cpu_num);
my @paralel_ratio;
my $jobs=0;
my $c=0;
my $cmds="";
my $out_path ="$ENV{PRONOC_WORK}/simulate/";
my $thread_num = $simulate->object_get_attribute('compile', 'thread_num');
$thread_num = 1 if (!defined $thread_num);
my $model= $simulate->object_get_attribute($sample,'MODEL_NAME');
add_info($info, "Run $bin for $model model \n");
my $cmd="$bin -T $thread_num ";
my $traffictype=$simulate->object_get_attribute($sample,"TRAFFIC_TYPE");
if($traffictype eq "Netrace"){
my $PCK_NUM_LIMIT=$simulate->object_get_attribute ($sample,"PCK_NUM_LIMIT");
my $IGNORE_DPNDCY=$simulate->object_get_attribute ($sample,"IGNORE_DPNDCY");
my $READER_THRL=$simulate->object_get_attribute ($sample,"READER_THRL");
my $START_RGN=$simulate->object_get_attribute ($sample,"START_RGN");
my $SPEED_UP=$simulate->object_get_attribute ($sample,"SPEED_UP");
my $models_dir = "$ENV{PRONOC_WORK}/simulate/netrace";
$cmd .="-F $models_dir/$model.bz2 -n $PCK_NUM_LIMIT -r $START_RGN -v 0 -s $SPEED_UP";
$cmd .=" -l " if ($READER_THRL eq "1\'b1" );
$cmd .=" -d " if ($IGNORE_DPNDCY eq "1\'b1");
}else{#synful
my $SIM_CLOCK_LIMIT=$simulate->object_get_attribute ($sample,"SIM_CLOCK_LIMIT");
my $PCK_NUM_LIMIT=$simulate->object_get_attribute ($sample,"PCK_NUM_LIMIT");
my $RND_SEED=$simulate->object_get_attribute ($sample,"RND_SEED");
my $EXIT_STEADY=$simulate->object_get_attribute ($sample,"EXIT_STEADY");
my $FLITw=$simulate->object_get_attribute ($sample,"SYNFUL_FLITw");
my $models_dir = get_project_dir()."/mpsoc/src_c/synfull/generated-models/";
$cmd .=" -S $models_dir/$model.model -n $PCK_NUM_LIMIT -r $RND_SEED -c $SIM_CLOCK_LIMIT -v 0 -w $FLITw";
$cmd .=" -s " if ($EXIT_STEADY eq "1\'b1");
 
}
$cmd .=" > $out_path/sim_out";
add_info($info, "$cmd \n");
my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout("$cmd\n wait\n");
if($exit || (length $stderr >4)){
add_colored_info($info, "Error in running simulation: $stderr \n",'red');
$simulate->object_add_attribute ($sample,"status","failed");
$simulate->object_add_attribute('status',undef,'ideal');
return;
}
$stdout = load_file("$out_path/sim_out");
my @errors = unix_grep("$out_path/sim_out","ERROR:");
if (scalar @errors ){
add_colored_info($info, "Error in running simulation: @errors \n",'red');
$simulate->object_add_attribute ($sample,"status","failed");
$simulate->object_add_attribute('status',undef,'ideal');
return;
}
extract_and_update_noc_sim_statistic ($simulate,$sample,0,$stdout);
set_gui_status($simulate,"ref",2);
$simulate->object_add_attribute ($sample,"status","done");
}
 
 
 
 
##########
# check_sample
##########
1427,10 → 1780,11
 
my @pages =(
{page_name=>" Avg. throughput/latency", page_num=>0},
{page_name=>" Injected Packet ", page_num=>1},
{page_name=>" Worst-Case Delay ",page_num=>2},
{page_name=>" Execution Time ",page_num=>3},
{page_name=>" Average/Total ", page_num=>0},
{page_name=>" Per node ", page_num=>1},
#{page_name=>" Worst-Case Delay ",page_num=>2},
#{page_name=>" Execution Time ",page_num=>3},
{page_name=>" Heat-Map. ",page_num=>4},
);
 
 
1441,20 → 1795,42
{ type=>"2D_line", page_num=>0, graph_name=> "Avg. flit Latency per hop", result_name => "latency_perhop_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Flit Latency per hop (clock)', Z_Title=>undef, Y_Max=>100},
{ type=>"2D_line", page_num=>0, graph_name=> "Avg. throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef,Y_Max=>100},
{ type=>"2D_line", page_num=>0, graph_name=> "Avg. SD latency", result_name => "sd_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency Standard Deviation (clock)', Z_Title=>undef},
{ type=>"2D_line", page_num=>0, graph_name=> "Worst pck latency (clk)", result_name => "worst_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Worst Packet Latency (clock)', Z_Title=>undef},
{ type=>"2D_line", page_num=>0, graph_name=> "Min pck latency (clk)", result_name => "min_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Minimum Packet Latency (clock)', Z_Title=>undef},
{ type=>"2D_line", page_num=>0, graph_name=> "Total injected pck", result_name =>"injected_pck_total" , X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Total Injected packets', Z_Title=>undef},
{ type=>"2D_line", page_num=>0, graph_name=> "Total injected flit",result_name =>"injected_flit_total", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Total Injected Fslits', Z_Title=>undef},
{ type=>"2D_line", page_num=>0, graph_name=> "Execuation Cycles", result_name => "exe_time_result",X_Title=>'Desired Avg. Injected Load Per Router (flits/clock (%))' , Y_Title=>'Total Simulation Time (clk)', Z_Title=>undef},
 
{ type=>"3D_bar", page_num=>1, graph_name=> "Received", result_name => "packet_rsvd_result", X_Title=>'Core ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Sent", result_name => "packet_sent_result", X_Title=>'Core ID' , Y_Title=>'Sent Packets Per Router', Z_Title=>undef},
{ type=>"3D_bar", page_num=>2, graph_name=> "Received", result_name => "worst_delay_rsvd_result",X_Title=>'Core ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
{ type=>"3D_bar", page_num=>2, graph_name=> "Sent", result_name => "worst_delay_sent_result",X_Title=>'Core ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
{ type=>"2D_line", page_num=>3, graph_name=> "-", result_name => "exe_time_result",X_Title=>'Desired Avg. Injected Load Per Router (flits/clock (%))' , Y_Title=>'Total Simulation Time (clk)', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Received packets per Endp", result_name => "packet_rsvd_result", X_Title=>'Endpoint ID' , Y_Title=>'Received Packets Per Endpoint', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Sent packets per Endp", result_name => "packet_sent_result", X_Title=>'Endpoint ID' , Y_Title=>'Sent Packets Per Endpoint', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Received flits per Endp", result_name => "flit_rsvd_result", X_Title=>'Endpoint ID' , Y_Title=>'Received Flits Per Endpoint', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Sent flits per Endp", result_name => "flit_sent_result", X_Title=>'Endpoint ID' , Y_Title=>'Sent Packets Flits Endpoint', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Flits per Router", result_name => "flit_per_router_result", X_Title=>'Router ID' , Y_Title=>'Received Flits Per Router', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Packets per Router", result_name => "packet_per_router_result", X_Title=>'Router ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Worst Received pck latency per Endp", result_name => "worst_delay_rsvd_result",X_Title=>'Endpoint ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Worst Sent pck latency per Endp", result_name => "worst_delay_sent_result",X_Title=>'Endpoint ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Buffered Flit in Ratio Per Router", result_name => "flit_buffered_router_ratio",X_Title=>'Router ID' , Y_Title=>'Flit in buffered in router/Flit in (%)', Z_Title=>undef},
{ type=>"3D_bar", page_num=>1, graph_name=> "Bypassed Flit in Ratio Per Router", result_name => "flit_bypass_router_ratio",X_Title=>'Router ID' , Y_Title=>'Flit in bypassed in router/Flit in (%)', Z_Title=>undef},
{ type=>"Heat-map", page_num=>4, graph_name=> "Select", result_name => "undef",X_Title=>'-' , Y_Title=> undef, Z_Title=>undef},
{ type=>"Heat-map", page_num=>4, graph_name=> "Endp-2-Endp Flit-num", result_name => "endp-endp-flit_result",X_Title=>'total flit number sent from an endpoint to another' , Y_Title=> undef, Z_Title=>undef},
{ type=>"Heat-map", page_num=>4, graph_name=> "Endp-2-Endp Packet-num", result_name => "endp-endp-pck_result",X_Title=>'total packet number sent from an endpoint to another' , Y_Title=> undef, Z_Title=>undef},
);
1554,3 → 1930,65
return ($core_num, -1);#off
}
 
sub download_netrace{
my ($path) =@_;
#create path if it is not exist
unless (-d $path){
mkpath("$path",1,01777);
}
my $window = def_popwin_size(30,85,"Netrace download",'percent');
my $table = def_table(1, 1, FALSE);
my $scrolled_win = add_widget_to_scrolled_win($table);
my @links =(
{ label=>"blackscholes simlarge (907M) ",name=>"blackscholes_64c_simlarge.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/blackscholes_64c_simlarge.tra.bz2"},
{ label=>"blackscholes simmedium (182M)",name=>"blackscholes_64c_simmedium.tra.bz2",url=>"https://www.cs.utexas.edu/~netrace/download/blackscholes_64c_simmedium.tra.bz2"},
{ label=>"blackscholes simsmall (55M) ",name=>"blackscholes_64c_simsmall.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/blackscholes_64c_simsmall.tra.bz2"},
{ label=>"bodytrack simlarge (3.5G) ",name=>"bodytrack_64c_simlarge.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/bodytrack_64c_simlarge.tra.bz2"},
{ label=>"canneal simmedium (3.5G) ",name=>"canneal_64c_simmedium.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/canneal_64c_simmedium.tra.bz2"},
{ label=>"dedup simmedium (4.1G) ",name=>"dedup_64c_simmedium.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/dedup_64c_simmedium.tra.bz2"},
{ label=>"ferret simmedium (2.7G) ",name=>"ferret_64c_simmedium.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/ferret_64c_simmedium.tra.bz2"},
{ label=>"fluidanimate simlarge (1.8G) ",name=>"fluidanimate_64c_simlarge.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/fluidanimate_64c_simlarge.tra.bz2"},
{ label=>"fluidanimate simmedium (677M)",name=>"fluidanimate_64c_simmedium.tra.bz2",url=>"https://www.cs.utexas.edu/~netrace/download/fluidanimate_64c_simmedium.tra.bz2"},
{ label=>"fluidanimate simsmall (317M) ",name=>"fluidanimate_64c_simsmall.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/fluidanimate_64c_simsmall.tra.bz2"},
{ label=>"swaptions simlarge (3.0G) ",name=>"swaptions_64c_simlarge.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/swaptions_64c_simlarge.tra.bz2"},
{ label=>"vips simmedium (3.1G) ",name=>"vips_64c_simmedium.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/vips_64c_simmedium.tra.bz2"},
{ label=>"x264 simmedium (5.1G) ",name=>"x264_64c_simmedium.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/x264_64c_simmedium.tra.bz2"},
{ label=>"x264 simsmall (1.2G) ",name=>"x264_64c_simsmall.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/x264_64c_simsmall.tra.bz2"},
);
 
my $row=0;
 
foreach my $d (@links){
my $srow=$row;
$table-> attach (gen_label_in_left($d->{label}) , 0, 1, $row,$row+1,'expand','shrink',2,2);
my $file="$path/$d->{name}";
if (-f $file){
}else{
my $download=def_image_button("icons/download.png",'Download');
$table-> attach ($download , 2, 3, $row,$row+1,'expand','shrink',2,2);
$download->signal_connect("clicked"=> sub{
$download ->set_sensitive (FALSE);
my $load= show_gif("icons/load.gif");
$table->attach ($load, 1, 2, $srow,$srow+ 1,'shrink','shrink',0,0);
$load->show_all;
my $o=$d->{name};
download_from_google_drive("$d->{url}" ,"$path/$o" );
$load->destroy;
$download->destroy if (-f $file);
});
}
$row++;
}
 
 
 
 
 
$window ->add($scrolled_win);
$window->show_all;
 
}
/lib/perl/software_editor.pl
55,9 → 55,9
 
my $NAME = 'ProNoC';
my $path = "";
our $FONT_SIZE='default';
our $ICON_SIZE='default';
 
 
 
exit gtk_gui_run(\&software_main_stand_alone) unless caller;
 
 
69,9 → 69,7
my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
if (-f $paths_file){#} && defined $ENV{PRONOC_WORK} ) {
my $paths= do $paths_file;
my %p=%{$paths};
$FONT_SIZE= $p{'GUI_SETTING'}{'FONT_SIZE'} if (defined $p{'GUI_SETTING'}{'FONT_SIZE'});
$ICON_SIZE= $p{'GUI_SETTING'}{'ICON_SIZE'} if (defined $p{'GUI_SETTING'}{'ICON_SIZE'});
set_gui_setting($paths);
}
set_defualt_font_size();
/lib/perl/temp.pl
1,26 → 1,38
#!/usr/bin/perl -w
 
# a perl getopts example
# alvin alexander, http://www.devdaily.com
 
use strict;
use Getopt::Std;
use warnings;
use IO::CaptureOutput qw(capture qxx qxy);
use Gtk3;
 
# declare the perl command line flags/options we want to allow
my %options=();
getopts("hj:ln:s:", \%options);
 
# test for the existence of the options on the command line.
# in a normal program you'd do more than just print these.
print "-h $options{h}\n" if defined $options{h};
print "-j $options{j}\n" if defined $options{j};
print "-l $options{l}\n" if defined $options{l};
print "-n $options{n}\n" if defined $options{n};
print "-s $options{s}\n" if defined $options{s};
 
# other things found on the command line
print "Other things found on the command line:\n" if $ARGV[0];
foreach (@ARGV)
{
print "$_\n";
my ($screen_x,$screen_y);
 
sub get_default_screen_size{
return ($screen_x,$screen_y) if (defined $screen_x && defined $screen_y);
my $fh= 'xrandr --current | awk \'$2~/\*/{print $1}\'' ;
my ($stdout, $stderr, $success) = qxx( ($fh) );
my @a = split ("\n",$stdout);
my ($screen_x,$screen_y) = split ("x",$a[0]);
$screen_x = 600 if(!defined $screen_x);
$screen_y = 800 if(!defined $screen_y);
return ($screen_x,$screen_y);
}
 
 
 
my ($x,$y) =get_default_screen_size();
print "$x,$y\n";
 
 
 
sub get_screen_size{
my $screen = Gtk3::Gdk::Screen::get_default;
my $hight = $screen->get_height();
my $width = $screen->get_width();
return ($width,$hight);
}
 
($x,$y) =get_screen_size();
print "$x,$y\n";
/lib/perl/topology.pl
22,7 → 22,21
}
 
 
sub get_topology_info_from_parameters {
my ($ref) =@_;
my %noc_info;
my %param= %$ref if(defined $ref );
my $topology=$param{'TOPOLOGY'};
my $T1 =$param{'T1'};
my $T2 =$param{'T2'};
my $T3 =$param{'T3'};
my $V =$param{'V'};
my $Fpay=$param{'Fpay'};
return get_topology_info_sub($topology, $T1, $T2, $T3,$V, $Fpay);
}
 
 
 
sub get_topology_info_sub {
 
my ($topology, $T1, $T2, $T3,$V, $Fpay)=@_;
366,6 → 380,20
}
 
 
sub mcast_partial_width {
my ($p,$NE)=@_;
my $m=0;
$p=remove_not_hex($p);
my @arr=split (//, $p);
foreach my $i (@arr) {
my $n=hex($i);
$m++ if($n & 0x1);
$m++ if($n & 0x2);
$m++ if($n & 0x4);
$m++ if($n & 0x8);
}
return $m;
}
 
 
 
376,7 → 404,11
my $T1=$self->object_get_attribute('noc_param','T1');
my $T2=$self->object_get_attribute('noc_param','T2');
my $T3=$self->object_get_attribute('noc_param','T3');
my $cast = $self->object_get_attribute('noc_param','MCAST_ENDP_LIST');
my $CAST_TYPE= $self->object_get_attribute('noc_param','CAST_TYPE');
my $DAw_OFFSETw = ($topology eq '"MESH"' || $topology eq '"TORUS"' || $topology eq '"FMESH"')? $T1 : 0;
my %tops;
my %nr_p; # number of routers have $p port num
my $router_p; #number of routers with different port number in topology
383,6 → 415,17
my ($ne, $nr, $RAw, $EAw)=get_topology_info($self);
 
my $MCAST_PRTLw= mcast_partial_width($cast,$ne);
my $MCASTw =
($CAST_TYPE eq '"MULTICAST_FULL"') ? $ne :
($CAST_TYPE eq '"MULTICAST_PARTIAL"' && $EAw >= $MCAST_PRTLw) ? $EAw +1 :
($CAST_TYPE eq '"MULTICAST_PARTIAL"' && $EAw < $MCAST_PRTLw) ? $MCAST_PRTLw +1 :
$EAw +1; #broadcast
my $DAw = ($CAST_TYPE eq '"UNICAST"') ? $EAw: $MCASTw + $DAw_OFFSETw;
print "$DAw=$DAw\n";
 
my $custom_include="";
if($topology eq '"FATTREE"') {
my $K = $T1;
450,6 → 493,7
}elsif ($topology eq '"STAR"') {
$router_p=1;# number of router with different port number
my $ports= $T1;
$nr_p{p1}=$ports;
$nr_p{1}=1;
%tops = (
#"Vrouter1" => "router_top_v_p${ports}.v",
495,7 → 539,7
}
$router_p=$i-1;
${topology_name} =~ s/\"+//g;
$custom_include="#include \"${topology_name}_noc.h\"\n";
$custom_include="#define IS_${topology_name}_noc\n";
}#else
506,14 → 550,21
}
my $rns_num = $router_p+1;
$includ_h.="int router_NRs[$rns_num];\n";
my $max_p=0;
for (my $p=1; $p<=$router_p ; $p++){
my $pnum= $nr_p{"p$p"};
$includ_h=$includ_h."#define NR${p} $nr_p{$p}\n";
my $pnum= $nr_p{"p$p"};
$includ_h=$includ_h."#define NR${p}_PNUM $pnum\n";
$includ_h=$includ_h."Vrouter${p} *router${p}[ $nr_p{$p} ]; // Instantiation of router with $pnum port number\n";
$max_p = $pnum if($max_p < $pnum);
}
$includ_h.="#define MAX_P $max_p //The maximum number of ports available in a router in this topology\n";
$includ_h.="#define DAw $DAw //The traffic generator's destination address width\n";
my $st1='';
my $st2='';
my $st3='';
520,7 → 571,9
my $st4='';
my $st5='';
my $st6='';
my $st7='';
my $st8='';
my $i=1;
my $j=0;
my $accum=0;
560,6 → 613,34
if (i<NR${i}){ router${i}[i]->eval(); return;}
i-= NR${i};
";
 
 
 
 
 
$st7.="
if (i<NR${i}){
update_router_st(
NR${i}_PNUM,
router${i}[i]->current_r_id,
router${i}[i]->router_event
);
return;
}
i-= NR${i};
";
 
$st8=$st8."
if (i<NR${i}){
router${i}[i]->reset= reset;
router${i}[i]->clk= clk ;
return;
}
i-= NR${i};
";
 
 
 
$i++;
$j++;
$accum=$accum+$nr_p{$p};
597,7 → 678,27
$st6
}
 
#define SMART_NUM ((SMART_MAX==0)? 1 : SMART_MAX)
#if SMART_NUM > 8
typedef unsigned int EVENT;
#else
typedef unsigned char EVENT;
#endif
 
extern void update_router_st (
unsigned int,
unsigned int,
EVENT *
);
void single_router_st_update(int i){
$st7
}
 
void inline single_router_reset_clk(int i){
$st8
}
 
";
 
/lib/perl/topology_verilog_gen.pl
23,7 → 23,9
}
print $fd autogen_warning();
print $fd get_license_header($top);
 
print $fd '
`include "pronoc_def.v"
';
my $param_str ="\tparameter TOPOLOGY = \"$name\",
\tparameter ROUTE_NAME = \"${name}_DETERMINISTIC\"";
71,7 → 73,8
$wires=$wires."\tinput smartflit_chanel_t ${instance}_chan_in;\n";
$wires=$wires."\toutput smartflit_chanel_t ${instance}_chan_out;\n";
$ports=$ports.",\n\t${instance}_chan_in,\n\t${instance}_chan_out";
$wires=$wires."\toutput router_event_t ${instance}_router_event;\n";
$ports=$ports.",\n\t${instance}_chan_in,\n\t${instance}_chan_out,\n\t${instance}_router_event";
foreach my $d (@ports){
my $range = ($d->{pwidth} eq 1)? " " : " [$d->{pwidth}-1 : 0]";
194,6 → 197,7
 
\tsmartflit_chanel_t ${instance}_chan_in [$Pnum-1 : 0];
\tsmartflit_chanel_t ${instance}_chan_out [$Pnum-1 : 0];
\trouter_event_t ${instance}_router_event [$Pnum-1 : 0];
 
";
 
211,9 → 215,11
(
.clk(${instance}_clk),
.reset(${instance}_reset),
.current_r_id($current_r),
.current_r_addr (${instance}_current_r_addr),
.chan_in (${instance}_chan_in),
.chan_out (${instance}_chan_out)
.chan_out (${instance}_chan_out),
.router_event (${instance}_router_event)
);
";
 
242,6 → 248,8
}else{
$router_v.=" \t\tassign ${instance}_chan_in [$i] = ${cinstance}_chan_in;\n";
$router_v.=" \t\tassign ${cinstance}_chan_out = ${instance}_chan_out [$i];\n";
$router_v.=" \t\tassign ${cinstance}_router_event = ${instance}_router_event [$i];\n";
}
my $cpplus=$cp+1;
309,7 → 317,9
}
print $fd autogen_warning();
print $fd get_license_header($top);
 
print $fd '
`include "pronoc_def.v"
';
my $param_str ="\tparameter TOPOLOGY = \"$name\",
\tparameter ROUTE_NAME = \"${name}_DETERMINISTIC\"";
341,7 → 351,8
my $ports="\treset,
\tclk,
\tchan_in_all,
\tchan_out_all
\tchan_out_all,
\trouter_event
";
my $ports_def="
\tinput reset;
349,10 → 360,14
\tinput smartflit_chanel_t chan_in_all [NE-1 : 0];
\toutput smartflit_chanel_t chan_out_all [NE-1 : 0];
 
//Events
\toutput router_event_t router_event [NR-1 : 0][MAX_P-1 : 0];
 
//all routers port
\tsmartflit_chanel_t router_chan_in [NR-1 :0][MAX_P-1 : 0];
\tsmartflit_chanel_t router_chan_out [NR-1 :0][MAX_P-1 : 0];
 
 
\twire [RAw-1 : 0] current_r_addr [NR-1 : 0];
 
 
406,8 → 421,10
';
my $offset=0;
my $assign="";
my $assign_h="";
my $assign_r2r="";
my $assign_r2e="";
my $init_h="";
my $init_gnd_h="";
my %new_h;
my $addr=0;
for ( my $i=2;$i<=12; $i++){
421,6 → 438,7
$new_h{"RNUM_${pos}"}="$rr";
$init_h.="router${Tnum}[$rr]->current_r_addr=$addr;\n";
$init_h.="router${Tnum}[$rr]->current_r_id=$addr;\n";
$addr++;
}
$offset+= $n;
435,7 → 453,7
$offset=0;
my $R_num=0;
for ( my $i=2;$i<=12; $i++){
my $n= $self->object_get_attribute("ROUTER${i}","NUM");
$n=0 if(!defined $n);
442,9 → 460,11
if($n>0){
my $router_pos= ($offset==0)? 'i' : "i+$offset";
#my $instant=get_router_genvar_instance_v($self,$i,$router_pos,$NE,$NR,$MAX_P);
my $p = $i-1;
$routers=$routers."
\tfor( i=0; i<$n; i=i+1) begin : router_${i}_port_lp
localparam RID = $router_pos;
assign current_r_addr [RID] = RID[RAw-1: 0];
 
router_top #(
.P($i)
453,9 → 473,11
(
.clk(clk),
.reset(reset),
.current_r_addr($router_pos),
.chan_in (router_chan_in\[$router_pos\]),
.chan_out (router_chan_out\[$router_pos\])
.current_r_id(RID),
.current_r_addr(current_r_addr\[RID\]),
.chan_in (router_chan_in \[RID\] \[$p : 0\]),
.chan_out (router_chan_out\[RID\] \[$p : 0\]),
.router_event(router_event\[RID\] \[$p : 0\])
);
465,10 → 487,14
for ( my $j=0;$j<$n; $j++){
my $rname ="ROUTER${i}_$j";
my ($ass_v,$ass_h)=get_wires_assignment_genvar_v($self,$rname,0,\%new_h);
my ($ass_v,$r2r_h,$r2e_h, $int_h,$gnd_h);
($ass_v,$r2r_h,$r2e_h, $int_h,$gnd_h,$R_num) = get_wires_assignment_genvar_v($self,$rname,0,\%new_h,$R_num);
$assign=$assign.$ass_v;
$assign_h.=$ass_h;
$assign_r2r.=$r2r_h;
$assign_r2e.=$r2e_h;
$init_h.=$int_h;
$init_gnd_h.=$gnd_h;
}
$offset+= $n;
492,7 → 518,8
reset,
clk,
chan_in_all,
chan_out_all
chan_out_all,
router_event
);
 
function integer log2;
539,16 → 566,46
add_colored_info($info,"Error in creating $top: $r",'red');
return;
}
my $fr2r="";
for (my $i=0;$i<$R_num ; $i++){
$fr2r.="\n" if($i%10==0);
$fr2r.=($i==0) ? "single_r2r$i" : ",single_r2r$i";
}
my $fr2e="";
for (my $i=0;$i<$NE ; $i++){
$fr2e.="\n" if($i%10==0);
$fr2e.=($i==0) ? "single_r2e$i" : ",single_r2e$i";
}
print $fd "
 
 
$assign_r2r
 
void topology_connect_all_nodes (void){
$assign_h
$assign_r2e
 
 
void (*r2r_func_ptr[$R_num])() = {$fr2r};
void (*r2e_func_ptr[$NE])() = {$fr2e};
 
void topology_connect_r2r (int n){
(*r2r_func_ptr[n])();
}
 
void topology_connect_r2e (int n){
(*r2e_func_ptr[n])();
}
 
 
 
void topology_init(void){
$init_h
R2R_TABLE_SIZ=$R_num;
$init_gnd_h
}
";
close $fd;
578,8 → 635,10
.clk(clk),
.reset(reset),
.current_r_addr($router_pos),
.current_r_id($router_pos),
.chan_in (router_chan_in\[$router_pos\]),
.chan_out(router_chan_out\[$router_pos\])
.chan_out(router_chan_out\[$router_pos\]),
.router_event(router_event\[$router_pos\])
);
593,7 → 652,7
 
 
sub get_wires_assignment_genvar_v{
my ($self,$rname,$reverse,$cref)=@_;
my ($self,$rname,$reverse,$cref,$R_num)=@_;
$reverse = 0 if(!defined $reverse);
my $instance= $self->object_get_attribute("$rname","NAME");
my $Pnum=$self->object_get_attribute("$rname",'PNUM');
603,7 → 662,12
my @ports= @{$self->object_get_attribute('Verilog','Router_ports')};
 
my $assign="";
my $ass_h="";
my $r2e_h="";
my $r2r_h="";
my $init_h="";
my $gnd_h="";
 
my @ends=get_list_of_all_endpoints($self);
my @routers=get_list_of_all_routers($self);
627,8 → 691,8
my $ctype = $self->object_get_attribute("$cname",'TYPE');
my ($cp)= sscanf("Port[%u]","$pnode");
$assign.="//Connect $instance input ports $i to $cinstance output ports $cp\n";
$ass_h.="//Connect $instance input ports $i to $cinstance output ports $cp\n";
my $cpos =($ctype eq 'ENDP')? get_scolar_pos($cname,@ends) : get_scolar_pos($cname,@routers);
my $cpplus=$cp+1;
643,6 → 707,7
#$assign = $assign."//connet $instance input port $i to $cinstance output port $cp\n";
if($type ne 'ENDP' && $ctype eq 'ENDP'){
$assign= $assign."\t\tassign router_chan_in \[$pos\]\[$i\] = chan_in_all \[$cpos\];\n" if($reverse==0);
$assign= $assign."\t\tassign chan_in_all \[$cpos\] = router_chan_in \[$pos\]\[$i\];\n" if($reverse==1);
649,14 → 714,17
$assign= $assign."\t\tassign chan_out_all \[$cpos\] = router_chan_out \[$pos\]\[$i\];\n" if($reverse==0);
$assign= $assign."\t\tassign router_chan_out \[$pos\]\[$i\] = chan_out_all \[$cpos\];\n" if($reverse==1);
$ass_h.= "\tconnect_r2e($TNUM_pos,$RNUM_pos,$i,$cpos);\n" if (defined $TNUM_pos);
$r2e_h.="//Connect $instance input ports $i to $cinstance output ports $cp\n";
$r2e_h.= "void single_r2e$cpos(void) {connect_r2e($TNUM_pos,$RNUM_pos,$i,$cpos);}\n" if (defined $TNUM_pos);
}elsif ($type ne 'ENDP' && $ctype ne 'ENDP'){
$assign= $assign."\t\tassign router_chan_in \[$pos\]\[$i\] = router_chan_out \[$cpos\]\[$cp\];\n" if($reverse==0);
$assign= $assign."\t\tassign router_chan_out \[$cpos\]\[$cp\] = router_chan_in \[$pos\]\[$i\];\n" if($reverse==1);
$ass_h.= "\tconect_r2r($TNUM_pos,$RNUM_pos,$i,$TNUM_cpos,$RNUM_cpos,$cp);\n" if (defined $TNUM_pos);
$r2r_h.="//Connect $instance input ports $i to $cinstance output ports $cp\n";
$r2r_h.= "void single_r2r$R_num(void){conect_r2r($TNUM_pos,$RNUM_pos,$i,$TNUM_cpos,$RNUM_cpos,$cp);}\n" if (defined $TNUM_pos);
$init_h.="\tr2r_cnt_all[$R_num] =(r2r_cnt_table_t){.id1=$pos, .t1=$TNUM_pos, .r1=$RNUM_pos, .p1=$i,.id2=$cpos, .t2=$TNUM_cpos, .r2=$RNUM_cpos, .p2=$cp };\n";
$R_num++;
}
667,16 → 735,19
my $TNUM_pos = $rinfo{"TNUM_${pos}" };
my $RNUM_pos = $rinfo{"RNUM_${pos}" };
$assign = $assign."//Connect $instance port $i to ground\n";
$ass_h.="//Connect $instance port $i to ground\n";
$assign = $assign."//Connect $instance port $i to ground\n";
$assign= $assign."\t\tassign router_chan_in \[$pos\]\[$i\] ={SMARTFLIT_CHANEL_w{1'b0}};\n " if($reverse==0);
$assign= $assign."\t\tassign router_chan_out \[$pos\]\[$i\] ={SMARTFLIT_CHANEL_w{1'b0}};\n " if($reverse==1);
$ass_h.= "\tconnect_r2gnd($TNUM_pos,$RNUM_pos,$i);\n" if (defined $TNUM_pos);
$gnd_h.="//Connect $instance port $i to ground\n";
$gnd_h.= "\tconnect_r2gnd($TNUM_pos,$RNUM_pos,$i);\n" if (defined $TNUM_pos);
}
}
 
return ($assign,$ass_h);
 
return ($assign,$r2r_h,$r2e_h,$init_h,$gnd_h,$R_num);
}
 
 
865,6 → 936,8
 
 
print $fd "
`include \"pronoc_def.v\"
/*******************
* ${Vname}_look_ahead_routing
*******************/
891,8 → 964,8
reg [EAw-1 :0] dest_e_addr_delay;
reg [EAw-1 :0] src_e_addr_delay;
 
always @(posedge clk)begin
if(reset)begin
always @ (`pronoc_clk_reset_edge )begin
if(`pronoc_reset)begin
dest_e_addr_delay<={EAw{1'b0}};
src_e_addr_delay<={EAw{1'b0}};
end else begin
1107,6 → 1180,8
 
 
print $fd "
`include \"pronoc_def.v\"
/*****************************
* ${Vname}_look_ahead_routing_genvar
******************************/
1132,8 → 1207,8
reg [EAw-1 :0] dest_e_addr_delay;
reg [EAw-1 :0] src_e_addr_delay;
 
always @(posedge clk)begin
if(reset)begin
always @ (`pronoc_clk_reset_edge )begin
if(`pronoc_reset) begin
dest_e_addr_delay<={EAw{1'b0}};
src_e_addr_delay<={EAw{1'b0}};
end else begin
1214,10 → 1289,12
}
print $fd autogen_warning();
print $fd get_license_header($top);
print $fd '
`include "pronoc_def.v"
';
 
 
 
 
 
1308,7 → 1385,7
';
my $offset=0;
my $assign="";
my $R_num=0;
for ( my $i=2;$i<=12; $i++){
my $n= $self->object_get_attribute("ROUTER${i}","NUM");
$n=0 if(!defined $n);
1325,7 → 1402,7
for ( my $j=0;$j<$n; $j++){
my $rname ="ROUTER${i}_$j";
my ($ass_v, $ass_h)= get_wires_assignment_genvar_v($self,$rname,1);
my ($ass_v, $r2r_h,$r2e_h, $int_h,$gnd_h,$R_num)= get_wires_assignment_genvar_v($self,$rname,1,undef,$R_num);
$assign=$assign.$ass_v;
}
1441,10 → 1518,39
}
 
sub add_noc_custom_h{
my ($self,$info,$dir)=@_;
my $name=$self->object_get_attribute('save_as');
my $str="
//do not modify this line ===${name}===
#ifdef IS_${name}_noc
#include \"${name}_noc.h\"
#endif
";
my $file = "$dir/../../../src_verilator/topology/custom/custom.h";
#check if ***$name**** exist in the file
unless (-f $file){
add_colored_info($info,"$file dose not exist\n",'red');
return;
}
my $r = check_file_has_string($file, "===${name}===");
if ($r==1){
add_info($info,"The instance ${name}_noc exists in $file. This file is not modified\n ",'blue');
}else{
my $text = read_file_cntent($file,' ');
my @a = split('endgenerate',$text);
save_file($file,"$a[0] $str $a[1]");
add_info($info,"$file has been modified. The ${name}_noc has been added to the file\n ",'blue');
}
}
 
 
 
 
sub add_routing_instance_v{
my ($self,$info,$dir)=@_;
my $name=$self->object_get_attribute('save_as');
1632,7 → 1738,8
.reset(reset),
.clk(clk),
.chan_in_all(chan_in_all),
.chan_out_all(chan_out_all)
.chan_out_all(chan_out_all),
.router_event(router_event)
);
end
1673,4 → 1780,3
 
 
1
 
/lib/perl/trace_gen.pl
162,10 → 162,10
my $dir = Cwd::getcwd();
my $project_dir = abs_path("$dir/.."); #mpsoc directory address
my $project_dir = get_project_dir()."/mpsoc/";
$add->signal_connect ( 'clicked'=> sub{
load_task_file($self,$project_dir,$tview) if($mode eq 'task');
load_orcc_file($self,$tview) if($mode eq 'orcc');
/lib/perl/widget.pl
21,4 → 21,8
}
 
 
 
 
 
 
1;
/lib/perl/widget2.pl
20,9 → 20,9
use Gtk2::Pango;
#use Tk::Animation;
 
our $FONT_SIZE;
our $ICON_SIZE;
our %glob_setting;
 
 
##############
# combo box
#############
378,11 → 378,11
sub get_icon_pixbuff{
my $icon_file=shift;
my $size;
if ($ICON_SIZE eq 'default'){
if ($glob_setting{'ICON_SIZE'} eq 'default'){
my $font_size=get_defualt_font_size();
$size=($font_size *2.5);
}else{
$size = int ($ICON_SIZE);
$size = int ($glob_setting{'ICON_SIZE'});
}
my $pixbuf = Gtk2::Gdk::Pixbuf->new_from_file_at_scale($icon_file,$size,$size,FALSE);
return $pixbuf;
819,20 → 819,14
}
 
 
sub get_default_screen {
return Gtk2::Gdk::Screen->get_default();
}
 
 
 
 
sub max_win_size{
my $screen =Gtk2::Gdk::Screen->get_default();
my $hight = $screen->get_height();
my $width = $screen->get_width();
return ($width,$hight);
}
 
 
sub get_defualt_font_size{
return int($FONT_SIZE) if ($FONT_SIZE ne 'default');
return int($glob_setting{'FONT_SIZE'}) if ($glob_setting{'FONT_SIZE'} ne 'default');
my($width,$hight)=max_win_size();
#print "($width,$hight)\n";
839,7 → 833,7
my $font_size=($width>=1600)? 10:
($width>=1400)? 9:
($width>=1200)? 9:
($width>=1000)? 7:6;
($width>=1000)? 8:7;
#print "$font_size\n";
return $font_size;
}
2047,6 → 2041,8
my $cmd=shift;
my $exit;
my ($stdout, $stderr);
STDOUT->flush();
STDERR->flush();
capture { $exit=run_cmd_in_back_ground($cmd) } \$stdout, \$stderr;
return ($stdout,$exit,$stderr);
/lib/perl/widget3.pl
3,6 → 3,9
use strict;
use warnings;
 
use FindBin;
use lib $FindBin::Bin;
 
use Data::Dumper;
use Gtk3::SourceView;
use Consts;
9,8 → 12,7
 
require "common.pl";
 
use FindBin;
use lib $FindBin::Bin;
 
use IO::CaptureOutput qw(capture qxx qxy);
 
#use ColorButton;
18,8 → 20,7
 
#use Tk::Animation;
 
our $FONT_SIZE;
our $ICON_SIZE;
our %glob_setting;
 
##############
# combo box
388,11 → 389,11
sub get_icon_pixbuff{
my $icon_file=shift;
my $size;
if ($ICON_SIZE eq 'default'){
if ($glob_setting{'ICON_SIZE'} eq 'default'){
my $font_size=get_defualt_font_size();
$size=($font_size *2.5);
}else{
$size = int ($ICON_SIZE);
$size = int ($glob_setting{'ICON_SIZE'});
}
my $pixbuf = Gtk3::Gdk::Pixbuf->new_from_file_at_scale($icon_file,$size,$size,FALSE);
return $pixbuf;
868,35 → 869,12
}
 
 
 
 
my ($scr, $curr_scr, %screens);
 
sub max_win_size{
# my $screen =Gtk3::Gdk::Screen::get_default;
 
if(!defined $curr_scr){
 
open my $fh, "xdpyinfo|" or die;
 
while (<$fh>) {
$scr = $1 if m/^\s*screen\s+#(\d+):/;
$curr_scr = $1 if m/^\s*default screen number:\s+(\d+)/;
@{$screens{$scr}}{'x','y'} = ($1, $2)
if m/^\s*dimensions:\s+(\d+)x(\d+)/;
}
close $fh;
}
 
my $width = $screens{$curr_scr}{'y'};
my $height = $screens{$curr_scr}{'x'};
return ($height,$width);
sub get_default_screen {
return Gtk3::Gdk::Screen::get_default;
}
 
 
sub get_defualt_font_size{
return int($FONT_SIZE) if ($FONT_SIZE ne 'default');
return int($glob_setting{'FONT_SIZE'}) if ($glob_setting{'FONT_SIZE'} ne 'default');
my($width,$hight)=max_win_size();
#print "($width,$hight)\n";
1008,7 → 986,7
sub save_adj {
my ($self,$adjustment,$at1,$at2)=@_;
my $value = $adjustment->get_value;
$self->object_add_attribute($at1,$at2,$value);
$self->object_add_attribute($at1,$at2,$value) if (defined $self);
}
 
 
1537,9 → 1515,7
$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
set_gui_status($object,$status,$timeout) if (defined $status);
});
return $widget;
 
return $widget;
}
 
 
1977,7 → 1953,8
my $renderer = Gtk3::CellRendererText->new;
my $column = Gtk3::TreeViewColumn->new_with_attributes ("$l",
$renderer,
text => $c );
text => $c
);
$column->set_sort_column_id ($c );
$treeview->append_column ($column);
$c++;
2190,6 → 2167,7
# This while loop will cause Gtk3 to continue processing events, if
# there are events pending... *which there are...
while (Gtk3::events_pending) {
Gtk3::main_iteration;
}
Gtk3::Gdk::flush;
2227,17 → 2205,20
my $exit;
my ($stdout, $stderr);
open(OLDERR, ">&STDERR");
open(STDERR, ">>/tmp/tmp.spderr") or die "Can't dup stdout";
select(STDOUT); $| = 1; # make unbuffered
print OLDERR ""; #this fixed an error about OLDERR not being used
#open(OLDERR, ">&STDERR");
#open(STDERR, ">>/tmp/tmp.spderr") or die "Can't dup stdout";
#select(STDOUT); $| = 1; # make unbuffered
#print OLDERR ""; #this fixed an error about OLDERR not being used
 
## do my stuff here.
STDOUT->flush();
STDERR->flush();
capture { $exit=run_cmd_in_back_ground($cmd) } \$stdout, \$stderr;
close(STDERR);
open(STDERR, ">&OLDERR");
#close(STDERR);
#open(STDERR, ">&OLDERR");
return ($stdout,$exit,$stderr);
}
/lib/soc/mor1k_tile.SOC
10,285 → 10,809
################################################################################
 
$soc = bless( {
'gui_status' => {
'timeout' => 0,
'status' => 'ideal'
'timer0' => {
'version' => 12
},
'current_module_param_type' => undef,
'SOURCE_SET' => {
'SOC' => bless( {
'modules' => {},
'hdl_files_ticked' => undef,
'SOURCE_SET' => {
'IP' => bless( {
'parameters_order' => [],
'hdl_files' => [],
'GUI_REMOVE_SET' => 'DISABLE',
'file_name' => undef,
'hdl_files_ticked' => [],
'category' => 'TOP',
'ports' => {
'source_clk_in' => {
'range' => undef,
'intfc_name' => 'plug:clk[0]',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'source_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'intfc_name' => 'plug:reset[0]',
'range' => undef
}
},
'plugs' => {
'reset' => {
'1' => {},
'0' => {
'name' => 'source_reset_in'
},
'value' => 1,
'type' => 'num'
},
'clk' => {
'value' => 1,
'0' => {
'name' => 'source_clk_in'
},
'1' => {},
'type' => 'num'
}
},
'module_name' => 'TOP',
'ip_name' => 'TOP',
'ports_order' => []
}, 'ip_gen' )
},
'soc_name' => {
'TOP' => undef
},
'TOP' => {
'version' => 0
},
'hdl_files' => undef,
'gui_status' => {
'status' => 'refresh_soc',
'timeout' => 0
},
'instances' => {
'TOP' => {
'instance_name' => 'TOP',
'plugs' => {
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_socket' => undef,
'name' => 'source_reset_in',
'connect_id' => 'IO'
}
},
'type' => 'num',
'value' => 1
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket' => undef,
'connect_socket_num' => undef,
'connect_id' => 'IO',
'name' => 'source_clk_in'
}
},
'type' => 'num'
}
},
'module_name' => 'TOP',
'parameters_order' => [],
'category' => 'TOP',
'description_pdf' => undef,
'module' => 'TOP'
}
},
'instance_order' => [
'TOP'
]
}, 'soc' ),
'REDEFINE_TOP' => 0
},
'global_param' => {
'CORE_ID' => 3,
'SW_LOC' => '/home/alireza/work/git/hca_git/mpsoc_work/SOC/mor1k_tile/sw'
},
'current_module_param' => undef,
'wishbone_bus0' => {
'version' => 1
},
'instance_order' => [
'clk_source0',
'wishbone_bus0',
'mor1kx0',
'single_port_ram0',
'ni_master0',
'timer0',
'ProNoC_jtag_uart0'
],
'instances' => {
'ni_master0' => {
'category' => 'NoC',
'parameters_type' => {
'T1' => {
'value' => 'Parameter'
},
'SELF_LOOP_EN' => {
'value' => 'Parameter'
},
'M_Aw' => {},
'TAGw' => {},
'T3' => {
'value' => 'Parameter'
},
'EAw' => {},
'T2' => {
'value' => 'Parameter'
},
'V' => {
'value' => 'Parameter'
'timer0' => {
'sockets' => {},
'parameters' => {
'Aw' => {
'value' => '3'
},
'CNTw' => {
'value' => '32 '
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'SELw' => {
'value' => '4'
},
'PRESCALER_WIDTH' => {
'value' => '8'
}
},
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw',
'PRESCALER_WIDTH'
],
'module' => 'timer',
'category' => 'Timer',
'parameters_type' => {
'Dw' => {},
'TAGw' => {},
'CNTw' => {},
'Aw' => {},
'PRESCALER_WIDTH' => {
'value' => 'Localparam'
},
'SELw' => {}
},
'description_pdf' => '/mpsoc/rtl/src_peripheral/timer/timer.pdf',
'module_name' => 'timer',
'plugs' => {
'clk' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk',
'connect_socket_num' => '0'
}
},
'WEIGHTw' => {
'value' => 'Parameter'
'value' => 1,
'connection_num' => undef
},
'interrupt_peripheral' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'mor1kx0',
'name' => 'intrp',
'connect_socket_num' => '1',
'connect_socket' => 'interrupt_peripheral'
}
},
'connection_num' => undef
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'end' => 2516582431,
'connect_socket' => 'wb_slave',
'base' => 2516582400,
'connect_socket_num' => '2',
'connect_id' => 'wishbone_bus0',
'width' => 5,
'name' => 'wb',
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl'
}
},
'type' => 'num'
},
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'reset',
'connect_id' => 'clk_source0',
'name' => 'reset'
}
},
'type' => 'num',
'value' => 1
}
},
'instance_name' => 'timer'
},
'ProNoC_jtag_uart0' => {
'sockets' => {
'jtag_to_wb' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'jtag_to_wb'
}
},
'type' => 'num'
},
'RxD_sim' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'RxD_sim'
}
},
'type' => 'num'
}
},
'parameters' => {
'SELw' => {
'value' => '4'
},
'JTAG_CONNECT' => {
'value' => '"ALTERA_JTAG_WB"'
},
'JSTATUSw' => {
'value' => '8'
},
'BUFF_Aw' => {
'value' => '4'
},
'J2WBw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'
},
'LB' => {
'value' => 'Parameter'
},
'VC_REALLOCATION_TYPE' => {
'value' => 'Parameter'
'JDw' => {
'value' => '32'
},
'Dw' => {
'value' => '32'
},
'TAGw' => {
'value' => '3'
},
'INCLUDE_SIM_PRINTF' => {
'value' => 'SIMPLE_PRINTF'
},
'Fpay' => {
'value' => 'Parameter'
'JAw' => {
'value' => '32'
},
'WB2Jw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'
},
'JTAG_CHAIN' => {
'value' => '3'
},
'Aw' => {
'value' => '1'
},
'SMART_MAX' => {
'value' => 'Parameter'
'JINDEXw' => {
'value' => '8'
},
'CONGESTION_INDEX' => {
'value' => 'Parameter'
},
'SSA_EN' => {
'value' => 'Parameter'
'JTAG_INDEX' => {
'value' => '126-CORE_ID'
}
},
'parameters_order' => [
'Aw',
'SELw',
'TAGw',
'Dw',
'BUFF_Aw',
'JTAG_INDEX',
'JDw',
'JAw',
'JINDEXw',
'JSTATUSw',
'JTAG_CHAIN',
'JTAG_CONNECT',
'J2WBw',
'WB2Jw',
'INCLUDE_SIM_PRINTF'
],
'module_name' => 'pronoc_jtag_uart',
'plugs' => {
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket_num' => '0',
'connect_socket' => 'clk'
}
},
'type' => 'num'
},
'wb_slave' => {
'nums' => {
'0' => {
'width' => 4,
'name' => 'wb_slave',
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
'connect_socket' => 'wb_slave',
'end' => 2415919119,
'base' => 2415919104,
'connect_socket_num' => '3',
'connect_id' => 'wishbone_bus0'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'reset',
'connect_socket_num' => '0',
'name' => 'reset',
'connect_id' => 'clk_source0'
}
}
}
},
'instance_name' => 'uart',
'module' => 'ProNoC_jtag_uart',
'parameters_type' => {
'SELw' => {},
'BUFF_Aw' => {
'value' => 'Localparam'
},
'JSTATUSw' => {},
'J2WBw' => {},
'JTAG_CONNECT' => {
'value' => 'Localparam'
},
'Dw' => {},
'JDw' => {},
'TAGw' => {},
'WB2Jw' => {},
'JAw' => {},
'JTAG_CHAIN' => {
'value' => 'Localparam'
},
'INCLUDE_SIM_PRINTF' => {
'value' => 'Localparam'
},
'Aw' => {},
'JTAG_INDEX' => {
'value' => 'Localparam'
},
'JINDEXw' => {}
},
'description_pdf' => undef,
'category' => 'Communication'
},
'wishbone_bus0' => {
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'sockets' => {
'wb_addr_map' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
}
},
'Dw' => {
'value' => 'Localparam'
'wb_master' => {
'connection_num' => 'single connection',
'value' => 'M',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_master'
}
}
},
'wb_slave' => {
'value' => 'S',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
},
'connection_num' => 'single connection'
},
'snoop' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'snoop'
}
}
}
},
'parameters' => {
'CTIw' => {
'value' => '3'
},
'AVC_ATOMIC_EN' => {
'value' => 'Parameter'
},
'ESCAP_VC_MASK' => {
'value' => 'Parameter'
},
'COMBINATION_TYPE' => {
'value' => 'Parameter'
},
'SELw' => {},
'ROUTE_NAME' => {
'value' => 'Parameter'
'Aw' => {
'value' => '32'
},
'M' => {
'value' => ' 4'
},
'SELw' => {
'value' => 'Dw/8'
},
'BTEw' => {
'value' => '2 '
},
'S' => {
'value' => '4'
},
'TAGw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
}
},
'category' => 'Bus',
'parameters_type' => {
'Aw' => {
'value' => 'Localparam'
},
'M' => {
'value' => 'Localparam'
},
'CTIw' => {},
'S' => {
'value' => 'Localparam'
},
'Dw' => {
'value' => 'Localparam'
},
'TAGw' => {},
'SELw' => {},
'BTEw' => {}
},
'description_pdf' => undef,
'module' => 'wishbone_bus',
'plugs' => {
'reset' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_socket_num' => '0'
}
},
'CRC_EN' => {
'value' => 'Localparam'
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => 'Parameter'
},
'RAw' => {},
'MAX_BURST_SIZE' => {
'value' => 'Localparam'
},
'TOPOLOGY' => {
'value' => 'Parameter'
'type' => 'num'
},
'clk' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk',
'connect_socket_num' => '0'
}
},
'HDATA_PRECAPw' => {
'value' => 'Localparam'
},
'DEBUG_EN' => {
'value' => 'Parameter'
'connection_num' => undef
}
},
'module_name' => 'wishbone_bus',
'instance_name' => 'bus'
},
'clk_source0' => {
'parameters_order' => [
'FPGA_VENDOR'
],
'sockets' => {
'reset' => {
'connection_num' => 'multi connection',
'nums' => {
'0' => {
'name' => 'reset'
}
},
'type' => 'num',
'value' => 1
},
'clk' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'clk'
}
},
'BYTE_EN' => {
'value' => 'Parameter'
},
'MIN_PCK_SIZE' => {
'value' => 'Parameter'
},
'SWA_ARBITER_TYPE' => {
'value' => 'Parameter'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 'Parameter'
},
'B' => {
'value' => 'Parameter'
},
'C' => {
'value' => 'Parameter'
},
'MAX_TRANSACTION_WIDTH' => {
'value' => 'Localparam'
},
'MUX_TYPE' => {
'value' => 'Parameter'
'connection_num' => 'multi connection'
}
},
'parameters' => {
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
}
},
'description_pdf' => undef,
'category' => 'Source',
'parameters_type' => {
'FPGA_VENDOR' => {
'value' => 'Localparam'
}
},
'module' => 'clk_source',
'module_name' => 'clk_source',
'plugs' => {
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'reset',
'connect_socket_num' => undef,
'connect_socket' => undef
}
},
'S_Aw' => {},
'PCK_TYPE' => {
'value' => 'Parameter'
}
},
'parameters_order' => [
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'CRC_EN',
'RAw',
'EAw',
'HDATA_PRECAPw'
],
'sockets' => {
'ni' => {
'type' => 'num',
'value' => 1
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'name' => 'ni'
'connect_socket_num' => undef,
'connect_socket' => undef,
'name' => 'clk',
'connect_id' => 'IO'
}
},
'type' => 'num',
'connection_num' => 'single connection',
'value' => 1
'type' => 'num'
}
},
'description_pdf' => '/mpsoc/rtl/src_peripheral/ni/NI.pdf',
'module' => 'ni_master',
'instance_name' => 'ni',
},
'instance_name' => 'source'
},
'ni_master0' => {
'parameters' => {
'S_Aw' => {
'value' => '8'
},
'Dw' => {
'value' => '32'
},
'COMBINATION_TYPE' => {
'value' => '"COMB_NONSPEC"'
},
'SWA_ARBITER_TYPE' => {
'value' => '"RRA"'
},
'WEIGHTw' => {
'value' => '4'
},
'CONGESTION_INDEX' => {
'value' => 3
},
'MAX_TRANSACTION_WIDTH' => {
'value' => '13'
},
'PCK_TYPE' => {
'value' => '"MULTI_FLIT"'
},
'MUX_TYPE' => {
'value' => '"BINARY"'
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 1
},
'SELF_LOOP_EN' => {
'value' => '"NO"'
},
'CRC_EN' => {
'value' => '"NO"'
},
'EAw' => {
'value' => '16'
},
'B' => {
'value' => '4'
},
'TOPOLOGY' => {
'value' => '"MESH"'
},
'MAX_TRANSACTION_WIDTH' => {
'value' => '13'
},
'V' => {
'value' => '2'
},
'C' => {
'value' => 0
},
'B' => {
'value' => '4'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 1
},
'MIN_PCK_SIZE' => {
'value' => '2'
},
'SWA_ARBITER_TYPE' => {
'value' => '"RRA"'
},
'BYTE_EN' => {
'value' => 0
},
'T3' => {
'value' => '1'
},
'VC_REALLOCATION_TYPE' => {
'value' => '"NONATOMIC"'
},
'ROUTE_NAME' => {
'value' => '"XY"'
},
'SMART_MAX' => {
'value' => '0'
},
'DEBUG_EN' => {
'value' => '0'
},
'HDATA_PRECAPw' => {
'value' => '0'
},
'TOPOLOGY' => {
'value' => '"MESH"'
},
'SSA_EN' => {
'value' => '"NO"'
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => '1\'b0'
},
'MAX_BURST_SIZE' => {
'value' => '16'
},
'RAw' => {
'value' => '16'
},
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => '1\'b0'
},
'CRC_EN' => {
'value' => '"NO"'
},
'ROUTE_NAME' => {
'value' => '"XY"'
},
'COMBINATION_TYPE' => {
'value' => '"COMB_NONSPEC"'
},
'SELw' => {
'value' => '4'
'TAGw' => {
'value' => '3'
},
'ESCAP_VC_MASK' => {
'value' => '2\'b01'
},
'AVC_ATOMIC_EN' => {
'value' => 0
},
'Dw' => {
'value' => '32'
},
'CONGESTION_INDEX' => {
'value' => 3
},
'SSA_EN' => {
'value' => '"NO"'
},
'SMART_MAX' => {
'value' => '0'
},
'MIN_PCK_SIZE' => {
'value' => '2'
},
'S_Aw' => {
'value' => '8'
},
'Fpay' => {
'value' => '32'
},
'VC_REALLOCATION_TYPE' => {
'value' => '"NONATOMIC"'
},
'T1' => {
'value' => '2'
},
'MUX_TYPE' => {
'value' => '"BINARY"'
},
'SELw' => {
'value' => '4'
},
'BYTE_EN' => {
'value' => '1'
},
'M_Aw' => {
'value' => '32'
},
'LB' => {
'value' => '4'
},
'V' => {
'value' => '2'
},
'WEIGHTw' => {
'value' => '4'
},
'HDATA_PRECAPw' => {
'value' => '0'
},
'ESCAP_VC_MASK' => {
'value' => '2\'b01'
},
'T2' => {
'value' => '2'
},
'EAw' => {
'RAw' => {
'value' => '16'
},
'T3' => {
'value' => '1'
},
'TAGw' => {
'value' => '3'
},
'M_Aw' => {
'value' => '32'
},
'SELF_LOOP_EN' => {
'value' => '"NO"'
},
'T1' => {
'value' => '2'
}
'CAST_TYPE' => {
'value' => '"UNICAST"'
}
},
'module_name' => 'ni_master',
'sockets' => {
'ni' => {
'connection_num' => 'single connection',
'nums' => {
'0' => {
'name' => 'ni'
}
},
'type' => 'num',
'value' => 1
}
},
'parameters_order' => [
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'Dw',
'S_Aw',
'M_Aw',
'TAGw',
'SELw',
'CRC_EN',
'RAw',
'EAw',
'HDATA_PRECAPw'
],
'instance_name' => 'ni',
'plugs' => {
'reset' => {
'connection_num' => undef,
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_socket_num' => '0'
}
},
'type' => 'num',
'value' => 1
},
'wb_master' => {
'connection_num' => undef,
'value' => 2,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'wb_send',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '2',
'connect_socket' => 'wb_master'
},
'1' => {
'name' => 'wb_receive',
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master',
'connect_socket_num' => '3'
}
}
},
'wb_slave' => {
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '1',
'end' => 3087008767,
'connect_socket_num' => '1',
'width' => 10,
'connect_socket' => 'wb_slave',
'base' => 3087007744,
'connect_id' => 'wishbone_bus0',
'name' => 'wb_slave',
'width' => 10,
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
'base' => 3087007744
'name' => 'wb_slave'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'interrupt_peripheral' => {
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'interrupt',
'connect_id' => 'mor1kx0',
'connect_socket_num' => '0',
'connect_socket' => 'interrupt_peripheral'
}
},
'value' => 1
},
'clk' => {
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
298,626 → 822,372
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'wb_master' => {
'nums' => {
'1' => {
'connect_socket_num' => '3',
'connect_socket' => 'wb_master',
'connect_id' => 'wishbone_bus0',
'name' => 'wb_receive'
},
'0' => {
'name' => 'wb_send',
'connect_id' => 'wishbone_bus0',
'connect_socket' => 'wb_master',
'connect_socket_num' => '2'
}
},
'type' => 'num',
'value' => 2,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_socket_num' => '0'
}
}
},
'interrupt_peripheral' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'name' => 'interrupt',
'connect_id' => 'mor1kx0',
'connect_socket' => 'interrupt_peripheral'
}
}
}
}
},
'clk_source0' => {
'parameters' => {
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
}
},
'module_name' => 'clk_source',
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_socket' => undef,
'name' => 'reset',
'connect_id' => 'IO',
'connect_socket_num' => undef
}
'connection_num' => undef
}
},
'module_name' => 'ni_master',
'module' => 'ni_master',
'description_pdf' => '/mpsoc/rtl/src_peripheral/ni/NI.pdf',
'parameters_type' => {
'EAw' => {},
'B' => {
'value' => 'Parameter'
},
'TOPOLOGY' => {
'value' => 'Parameter'
},
'value' => 1,
'connection_num' => undef,
'type' => 'num'
},
'clk' => {
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_socket' => undef,
'name' => 'clk',
'connect_id' => 'IO'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
}
},
'instance_name' => 'source',
'description_pdf' => undef,
'sockets' => {
'clk' => {
'nums' => {
'0' => {
'name' => 'clk'
}
'MAX_TRANSACTION_WIDTH' => {
'value' => 'Localparam'
},
'PCK_TYPE' => {
'value' => 'Parameter'
},
'type' => 'num',
'connection_num' => 'multi connection',
'value' => 1
},
'reset' => {
'connection_num' => 'multi connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset'
}
}
}
},
'module' => 'clk_source',
'category' => 'Source',
'parameters_type' => {
'FPGA_VENDOR' => {
'value' => 'Localparam'
}
},
'parameters_order' => [
'FPGA_VENDOR'
]
},
'ProNoC_jtag_uart0' => {
'parameters_order' => [
'Aw',
'SELw',
'TAGw',
'Dw',
'BUFF_Aw',
'JTAG_INDEX',
'JDw',
'JAw',
'JINDEXw',
'JSTATUSw',
'JTAG_CHAIN',
'JTAG_CONNECT',
'J2WBw',
'WB2Jw',
'INCLUDE_SIM_PRINTF'
],
'category' => 'Communication',
'parameters_type' => {
'JTAG_CHAIN' => {
'value' => 'Localparam'
},
'JINDEXw' => {},
'BUFF_Aw' => {
'value' => 'Localparam'
},
'SELw' => {},
'TAGw' => {},
'JDw' => {},
'Dw' => {},
'J2WBw' => {},
'JTAG_INDEX' => {
'value' => 'Localparam'
},
'JTAG_CONNECT' => {
'value' => 'Localparam'
},
'Aw' => {},
'WB2Jw' => {},
'JAw' => {},
'INCLUDE_SIM_PRINTF' => {
'value' => 'Localparam'
},
'JSTATUSw' => {}
},
'module' => 'ProNoC_jtag_uart',
'sockets' => {
'RxD_sim' => {
'nums' => {
'0' => {
'name' => 'RxD_sim'
}
},
'type' => 'num',
'connection_num' => 'single connection',
'value' => 1
'SELF_LOOP_EN' => {
'value' => 'Parameter'
},
'FIRST_ARBITER_EXT_P_EN' => {
'value' => 'Parameter'
},
'CRC_EN' => {
'value' => 'Localparam'
},
'jtag_to_wb' => {
'nums' => {
'0' => {
'name' => 'jtag_to_wb'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => 'single connection'
}
},
'description_pdf' => undef,
'instance_name' => 'uart',
'module_name' => 'pronoc_jtag_uart',
'parameters' => {
'SELw' => {
'value' => '4'
},
'BUFF_Aw' => {
'value' => '4'
'SWA_ARBITER_TYPE' => {
'value' => 'Parameter'
},
'WEIGHTw' => {
'value' => 'Parameter'
},
'CONGESTION_INDEX' => {
'value' => 'Parameter'
},
'Dw' => {
'value' => 'Localparam'
},
'COMBINATION_TYPE' => {
'value' => 'Parameter'
},
'LB' => {
'value' => 'Parameter'
},
'M_Aw' => {},
'HDATA_PRECAPw' => {
'value' => 'Localparam'
},
'T2' => {
'value' => 'Parameter'
},
'ESCAP_VC_MASK' => {
'value' => 'Parameter'
},
'RAw' => {},
'CAST_TYPE' => {
'value' => 'Parameter'
},
'JTAG_CHAIN' => {
'value' => '3'
'AVC_ATOMIC_EN' => {
'value' => 'Parameter'
},
'TAGw' => {},
'MIN_PCK_SIZE' => {
'value' => 'Parameter'
},
'JINDEXw' => {
'value' => '8'
},
'Dw' => {
'value' => '32'
'S_Aw' => {},
'MUX_TYPE' => {
'value' => 'Parameter'
},
'Fpay' => {
'value' => 'Parameter'
},
'J2WBw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'
'T1' => {
'value' => 'Parameter'
},
'SELw' => {},
'BYTE_EN' => {
'value' => 'Parameter'
},
'TAGw' => {
'value' => '3'
'SMART_MAX' => {
'value' => 'Parameter'
},
'DEBUG_EN' => {
'value' => 'Parameter'
},
'SSA_EN' => {
'value' => 'Parameter'
},
'JDw' => {
'value' => '32'
},
'JTAG_CONNECT' => {
'value' => '"ALTERA_JTAG_WB"'
'ADD_PIPREG_AFTER_CROSSBAR' => {
'value' => 'Parameter'
},
'MAX_BURST_SIZE' => {
'value' => 'Localparam'
},
'JTAG_INDEX' => {
'value' => '126-CORE_ID'
},
'JSTATUSw' => {
'value' => '8'
},
'INCLUDE_SIM_PRINTF' => {
'value' => 'SIMPLE_PRINTF'
'V' => {
'value' => 'Parameter'
},
'C' => {
'value' => 'Parameter'
},
'T3' => {
'value' => 'Parameter'
},
'VC_REALLOCATION_TYPE' => {
'value' => 'Parameter'
},
'JAw' => {
'value' => '32'
},
'Aw' => {
'value' => '1'
},
'WB2Jw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'
}
},
'plugs' => {
'wb_slave' => {
'nums' => {
'0' => {
'base' => 2415919104,
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller',
'connect_id' => 'wishbone_bus0',
'name' => 'wb_slave',
'connect_socket' => 'wb_slave',
'width' => 4,
'connect_socket_num' => '3',
'end' => 2415919119
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk',
'connect_socket' => 'clk'
}
}
},
'reset' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0'
}
}
}
}
},
'ROUTE_NAME' => {
'value' => 'Parameter'
}
},
'category' => 'NoC'
},
'mor1kx0' => {
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM',
'OPTION_DCACHE_SNOOP',
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU',
'FEATURE_MULTIPLIER',
'FEATURE_DIVIDER',
'OPTION_SHIFTER'
],
'description_pdf' => undef,
'parameters_type' => {
'OPTION_OPERAND_WIDTH' => {},
'IRQ_NUM' => {},
'FEATURE_MULTIPLIER' => {
'value' => 'Localparam'
},
'OPTION_DCACHE_SNOOP' => {
'value' => 'Localparam'
},
'FEATURE_DMMU' => {
'value' => 'Localparam'
},
'FEATURE_IMMU' => {
'value' => 'Localparam'
},
'IRQ_NUM' => {},
'FEATURE_DIVIDER' => {
'value' => 'Localparam'
},
'OPTION_SHIFTER' => {
'value' => 'Localparam'
},
'OPTION_OPERAND_WIDTH' => {},
'FEATURE_DATACACHE' => {
'value' => 'Localparam'
},
'OPTION_SHIFTER' => {
'value' => 'Localparam'
},
'FEATURE_DIVIDER' => {
'value' => 'Localparam'
},
'FEATURE_IMMU' => {
'value' => 'Localparam'
},
'FEATURE_INSTRUCTIONCACHE' => {
'value' => 'Localparam'
},
'OPTION_DCACHE_SNOOP' => {
'value' => 'Localparam'
},
'FEATURE_DMMU' => {
'value' => 'Localparam'
}
}
},
'category' => 'Processor',
'module' => 'mor1kx',
'description_pdf' => undef,
'sockets' => {
'interrupt_peripheral' => {
'value' => 'IRQ_NUM',
'connection_num' => 'single connection',
'type' => 'param',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
}
}
},
'instance_name' => 'cpu',
'plugs' => {
'enable' => {
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_socket' => undef,
'name' => 'enable',
'connect_id' => 'IO'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
},
'wb_master' => {
'value' => 2,
'nums' => {
'1' => {
'connect_socket_num' => '1',
'connect_socket' => 'wb_master',
'name' => 'dwb',
'connect_id' => 'wishbone_bus0'
},
'0' => {
'connect_socket' => 'wb_master',
'connect_socket_num' => '0',
'connect_socket' => 'wb_master',
'name' => 'iwb',
'connect_id' => 'wishbone_bus0'
},
'1' => {
'connect_socket' => 'wb_master',
'name' => 'dwb',
'connect_id' => 'wishbone_bus0',
'connect_socket_num' => '1'
}
},
'connection_num' => undef,
'value' => 2,
'type' => 'num'
'type' => 'num',
'connection_num' => undef
},
'reset' => {
'value' => 1,
'connection_num' => undef,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
}
},
'clk' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_socket' => 'clk',
'connect_socket_num' => '0',
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket' => 'clk'
'name' => 'clk'
}
}
},
'type' => 'num'
},
'snoop' => {
'nums' => {
'0' => {
'connect_socket' => 'snoop',
'connect_socket_num' => '0',
'connect_id' => 'wishbone_bus0',
'name' => 'snoop',
'connect_socket' => 'snoop',
'connect_socket_num' => '0'
'name' => 'snoop'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'reset' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num'
}
'type' => 'num',
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket_num' => '0',
'connect_socket' => 'reset'
}
}
},
'enable' => {
'nums' => {
'0' => {
'name' => 'enable',
'connect_id' => 'IO',
'connect_socket' => undef,
'connect_socket_num' => undef
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
}
},
'module_name' => 'mor1k',
'parameters_order' => [
'OPTION_OPERAND_WIDTH',
'IRQ_NUM',
'OPTION_DCACHE_SNOOP',
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU',
'FEATURE_MULTIPLIER',
'FEATURE_DIVIDER',
'OPTION_SHIFTER'
],
'parameters' => {
'FEATURE_INSTRUCTIONCACHE' => {
'value' => '"ENABLED"'
},
'FEATURE_DATACACHE' => {
'value' => '"ENABLED"'
},
'OPTION_SHIFTER' => {
'value' => '"BARREL"'
},
'OPTION_OPERAND_WIDTH' => {
'value' => '32'
},
'FEATURE_DIVIDER' => {
'value' => '"SERIAL"'
},
'IRQ_NUM' => {
'value' => '32'
},
'FEATURE_MULTIPLIER' => {
'value' => '"THREESTAGE"'
},
'FEATURE_DATACACHE' => {
'value' => '"ENABLED"'
},
'FEATURE_IMMU' => {
'value' => '"ENABLED"'
},
'FEATURE_DIVIDER' => {
'value' => '"SERIAL"'
},
'OPTION_SHIFTER' => {
'value' => '"BARREL"'
},
'FEATURE_INSTRUCTIONCACHE' => {
'value' => '"ENABLED"'
},
'OPTION_DCACHE_SNOOP' => {
'value' => '"ENABLED"'
},
'FEATURE_DMMU' => {
'value' => '"ENABLED"'
},
'OPTION_DCACHE_SNOOP' => {
'value' => '"ENABLED"'
}
}
'FEATURE_MULTIPLIER' => {
'value' => '"THREESTAGE"'
}
},
'sockets' => {
'interrupt_peripheral' => {
'connection_num' => 'single connection',
'value' => 'IRQ_NUM',
'nums' => {
'0' => {
'name' => 'interrupt_peripheral'
}
},
'type' => 'param'
}
}
},
'single_port_ram0' => {
'instance_name' => 'ram',
'plugs' => {
'clk' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'connect_socket_num' => '0',
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket' => 'clk'
}
}
},
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'width' => 'WB_Byte_Aw',
'connect_socket' => 'wb_slave',
'name' => 'wb',
'connect_id' => 'wishbone_bus0',
'end' => 4194303,
'connect_socket_num' => '0',
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'base' => 0
}
}
},
'reset' => {
'type' => 'num',
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset',
'connect_socket_num' => '0'
}
}
}
},
'sockets' => {
'jtag_to_wb' => {
'connection_num' => 'single connection',
'value' => 1,
'nums' => {
'0' => {
'name' => 'jtag_to_wb'
}
},
'type' => 'num'
}
},
'parameters' => {
'JTAG_CHAIN' => {
'value' => '4'
'BURST_MODE' => {
'value' => '"ENABLED"'
},
'SELw' => {
'value' => 'Dw/8'
},
'JDw' => {
'value' => 'Dw'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'Dw' => {
'value' => '32'
},
'BTEw' => {
'value' => '2'
},
'JTAG_CONNECT' => {
'value' => '"ALTERA_JTAG_WB"'
},
'Aw' => {
'value' => '14'
},
'BURST_MODE' => {
'value' => '"ENABLED"'
'INITIAL_EN' => {
'value' => '"YES"'
},
'WB_Aw' => {
'value' => '20'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'JSTATUSw' => {
'value' => '8'
},
'JAw' => {
'value' => '32'
},
'JSTATUSw' => {
'value' => '8'
},
'INITIAL_EN' => {
'value' => '"YES"'
},
'CTIw' => {
'value' => '3'
},
'CORE_NUM' => {
'value' => 'CORE_ID'
},
'JINDEXw' => {
'value' => '8'
},
'JTAG_CHAIN' => {
'value' => '4'
},
'INIT_FILE_PATH' => {
'value' => 'SW_LOC'
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'WB_Byte_Aw' => {
'value' => 'WB_Aw+2'
},
'BYTE_WR_EN' => {
'value' => '"YES"'
},
'BTEw' => {
'value' => '2'
},
'SELw' => {
'value' => 'Dw/8'
},
'TAGw' => {
'value' => '3'
},
'JDw' => {
'value' => 'Dw'
},
'J2WBw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1'
},
'JTAG_INDEX' => {
'value' => 'CORE_ID'
},
'JTAG_CONNECT' => {
'value' => '"ALTERA_JTAG_WB"'
},
'CORE_NUM' => {
'value' => 'CORE_ID'
},
'WB2Jw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'
},
'JINDEXw' => {
'value' => '8'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => '"ram0"'
},
'WB2Jw' => {
'value' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'
'WB_Aw' => {
'value' => '20'
},
'FPGA_VENDOR' => {
'value' => '"ALTERA"'
}
'Aw' => {
'value' => '14'
}
},
'module_name' => 'wb_single_port_ram',
'parameters_type' => {
'JTAG_CHAIN' => {
'value' => 'Localparam'
},
'SELw' => {},
'JDw' => {},
'BYTE_WR_EN' => {
'value' => 'Localparam'
},
'Dw' => {
'value' => 'Localparam'
},
'BTEw' => {},
'JTAG_CONNECT' => {
'value' => 'Localparam'
},
'BURST_MODE' => {
'value' => 'Localparam'
},
'Aw' => {
'value' => 'Localparam'
},
'INIT_FILE_PATH' => {},
'JAw' => {},
'WB_Aw' => {
'value' => 'Localparam'
},
'JSTATUSw' => {},
'INITIAL_EN' => {
'value' => 'Localparam'
},
'JINDEXw' => {},
'CORE_NUM' => {},
'CTIw' => {},
'WB_Byte_Aw' => {},
'TAGw' => {},
'J2WBw' => {},
'JTAG_INDEX' => {
'value' => 'Localparam'
},
'MEM_CONTENT_FILE_NAME' => {
'value' => 'Localparam'
},
'WB2Jw' => {},
'FPGA_VENDOR' => {
'value' => 'Localparam'
}
},
'category' => 'RAM',
'parameters_order' => [
'Dw',
'Aw',
944,875 → 1214,842
'WB2Jw',
'JTAG_CHAIN'
],
'module' => 'single_port_ram',
'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf',
'sockets' => {
'jtag_to_wb' => {
'nums' => {
'0' => {
'name' => 'jtag_to_wb'
}
},
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num'
}
},
'module' => 'single_port_ram'
},
'timer0' => {
'instance_name' => 'timer',
'plugs' => {
'wb_slave' => {
'type' => 'num',
'connection_num' => undef,
'value' => 1,
'nums' => {
'0' => {
'end' => 2516582431,
'connect_socket_num' => '2',
'connect_socket' => 'wb_slave',
'width' => 5,
'connect_id' => 'wishbone_bus0',
'name' => 'wb',
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl',
'base' => 2516582400
}
}
},
'clk' => {
'nums' => {
'0' => {
'connect_socket_num' => '0',
'name' => 'clk',
'connect_id' => 'clk_source0',
'connect_socket' => 'clk'
}
},
'value' => 1,
'connection_num' => undef,
'type' => 'num'
},
'reset' => {
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket' => 'reset'
}
},
'value' => 1,
'connection_num' => undef,
'type' => 'num'
},
'interrupt_peripheral' => {
'nums' => {
'0' => {
'connect_socket' => 'interrupt_peripheral',
'connect_id' => 'mor1kx0',
'name' => 'intrp',
'connect_socket_num' => '1'
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
}
},
'module_name' => 'timer',
'parameters' => {
'Aw' => {
'value' => '3'
},
'Dw' => {
'value' => '32'
},
'TAGw' => {
'value' => '3'
},
'PRESCALER_WIDTH' => {
'value' => '8'
},
'CNTw' => {
'value' => '32 '
},
'SELw' => {
'value' => '4'
}
},
'parameters_type' => {
'Dw' => {},
'TAGw' => {},
'PRESCALER_WIDTH' => {
'category' => 'RAM',
'parameters_type' => {
'JAw' => {},
'JTAG_CHAIN' => {
'value' => 'Localparam'
},
'CTIw' => {},
'INIT_FILE_PATH' => {},
'FPGA_VENDOR' => {
'value' => 'Localparam'
},
'JTAG_INDEX' => {
'value' => 'Localparam'
},
'BURST_MODE' => {
'value' => 'Localparam'
},
'Dw' => {
'value' => 'Localparam'
},
'INITIAL_EN' => {
'value' => 'Localparam'
},
'JSTATUSw' => {},
'CORE_NUM' => {},
'WB2Jw' => {},
'JINDEXw' => {},
'MEM_CONTENT_FILE_NAME' => {
'value' => 'Localparam'
},
'WB_Aw' => {
'value' => 'Localparam'
},
'Aw' => {},
'SELw' => {},
'CNTw' => {}
},
'category' => 'Timer',
'parameters_order' => [
'CNTw',
'Dw',
'Aw',
'TAGw',
'SELw',
'PRESCALER_WIDTH'
],
'sockets' => {},
'description_pdf' => '/mpsoc/rtl/src_peripheral/timer/timer.pdf',
'module' => 'timer'
},
'wishbone_bus0' => {
'instance_name' => 'bus',
'module_name' => 'wishbone_bus',
'parameters' => {
'S' => {
'value' => '4'
},
'Aw' => {
'value' => '32'
},
'M' => {
'value' => ' 4'
},
'Dw' => {
'value' => '32'
},
'BTEw' => {
'value' => '2 '
},
'TAGw' => {
'value' => '3'
},
'SELw' => {
'value' => 'Dw/8'
},
'CTIw' => {
'value' => '3'
}
},
'plugs' => {
'clk' => {
'nums' => {
'0' => {
'connect_socket_num' => '0',
'connect_socket' => 'clk',
'name' => 'clk',
'connect_id' => 'clk_source0'
}
'Aw' => {
'value' => 'Localparam'
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
},
'reset' => {
'nums' => {
'0' => {
'name' => 'reset',
'connect_id' => 'clk_source0',
'connect_socket' => 'reset',
'connect_socket_num' => '0'
}
},
'connection_num' => undef,
'value' => 1,
'type' => 'num'
}
},
'category' => 'Bus',
'parameters_type' => {
'TAGw' => {},
'Dw' => {
'value' => 'Localparam'
},
'BTEw' => {},
'CTIw' => {},
'SELw' => {},
'Aw' => {
'value' => 'Localparam'
},
'S' => {
'value' => 'Localparam'
},
'M' => {
'value' => 'Localparam'
}
},
'parameters_order' => [
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw'
],
'sockets' => {
'snoop' => {
'nums' => {
'0' => {
'name' => 'snoop'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => 'single connection'
},
'wb_slave' => {
'type' => 'param',
'connection_num' => 'single connection',
'value' => 'S',
'nums' => {
'0' => {
'name' => 'wb_slave'
}
}
},
'wb_master' => {
'WB_Byte_Aw' => {},
'BTEw' => {},
'BYTE_WR_EN' => {
'value' => 'Localparam'
},
'SELw' => {},
'JDw' => {},
'TAGw' => {},
'JTAG_CONNECT' => {
'value' => 'Localparam'
},
'J2WBw' => {}
},
'plugs' => {
'wb_slave' => {
'connection_num' => undef,
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'wb_master'
'width' => 'WB_Byte_Aw',
'name' => 'wb',
'addr' => '0x0000_0000 0x3fff_ffff RAM',
'base' => 0,
'end' => 4194303,
'connect_socket' => 'wb_slave',
'connect_socket_num' => '0',
'connect_id' => 'wishbone_bus0'
}
},
'connection_num' => 'single connection',
'value' => 'M',
'type' => 'param'
}
},
'wb_addr_map' => {
'connection_num' => 'single connection',
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'name' => 'wb_addr_map'
}
}
}
},
'description_pdf' => undef,
'module' => 'wishbone_bus'
}
'clk' => {
'nums' => {
'0' => {
'connect_socket' => 'clk',
'connect_socket_num' => '0',
'connect_id' => 'clk_source0',
'name' => 'clk'
}
},
'type' => 'num',
'value' => 1,
'connection_num' => undef
},
'reset' => {
'value' => 1,
'type' => 'num',
'nums' => {
'0' => {
'connect_id' => 'clk_source0',
'name' => 'reset',
'connect_socket_num' => '0',
'connect_socket' => 'reset'
}
},
'connection_num' => undef
}
},
'module_name' => 'wb_single_port_ram',
'instance_name' => 'ram'
}
},
'single_port_ram0' => {
'version' => 39
},
'current_module_param_type' => undef,
'device_win_adj' => {
'ha' => '0',
'va' => '0'
},
'RAM0' => {
'end' => 65536,
'start' => 49152
},
'soc_name' => 'mor1k_tile',
'compile' => {
'modelsim_bin' => '/home/alireza/intelFPGA_lite/questa/questasim/bin',
'type' => 'Modelsim',
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin',
'board' => 'DE5',
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim'
},
'hdl_files' => undef,
'tile_diagram' => {
'show_clk' => 0,
'show_unused' => 1,
'show_reset' => 0
},
'Unset-intfc' => {},
'parameters_order' => {
'current_module_param' => [
'FPGA_VENDOR',
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw',
'OPTION_OPERAND_WIDTH',
'IRQ_NUM',
'OPTION_DCACHE_SNOOP',
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU',
'FEATURE_MULTIPLIER',
'FEATURE_DIVIDER',
'OPTION_SHIFTER',
'WB_Aw',
'BYTE_WR_EN',
'JTAG_CONNECT',
'JTAG_INDEX',
'CORE_NUM',
'WB_Byte_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH',
'JDw',
'JAw',
'JSTATUSw',
'JINDEXw',
'J2WBw',
'WB2Jw',
'JTAG_CHAIN',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'S_Aw',
'M_Aw',
'CRC_EN',
'RAw',
'EAw',
'HDATA_PRECAPw',
'CNTw',
'PRESCALER_WIDTH',
'BUFF_Aw',
'INCLUDE_SIM_PRINTF'
]
},
'ROM0' => {
'start' => 0,
'end' => 49152
},
'SOURCE_SET' => {
'REDEFINE_TOP' => 0,
'SOC' => bless( {
'modules' => {},
'gui_status' => {
'timeout' => 0,
'status' => 'refresh_soc'
},
'instances' => {
'TOP' => {
'parameters_order' => [],
'instance_name' => 'TOP',
'category' => 'TOP',
'module_name' => 'TOP',
'plugs' => {
'reset' => {
'nums' => {
'0' => {
'connect_id' => 'IO',
'name' => 'source_reset_in',
'connect_socket' => undef,
'connect_socket_num' => undef
}
},
'type' => 'num',
'connection_num' => undef,
'value' => 1
},
'clk' => {
'type' => 'num',
'value' => 1,
'connection_num' => undef,
'nums' => {
'0' => {
'connect_socket_num' => undef,
'connect_id' => 'IO',
'name' => 'source_clk_in',
'connect_socket' => undef
}
}
}
},
'module' => 'TOP',
'description_pdf' => undef
}
},
'soc_name' => {
'TOP' => undef
},
'hdl_files' => undef,
'hdl_files_ticked' => undef,
'instance_order' => [
'TOP'
],
'SOURCE_SET' => {
'IP' => bless( {
'ports_order' => [],
'hdl_files' => [],
'plugs' => {
'reset' => {
'1' => {},
'0' => {
'name' => 'source_reset_in'
},
'type' => 'num',
'value' => 1
},
'clk' => {
'1' => {},
'type' => 'num',
'0' => {
'name' => 'source_clk_in'
},
'value' => 1
}
},
'module_name' => 'TOP',
'category' => 'TOP',
'file_name' => undef,
'GUI_REMOVE_SET' => 'DISABLE',
'ports' => {
'source_clk_in' => {
'range' => undef,
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]'
},
'source_reset_in' => {
'range' => undef,
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
}
},
'parameters_order' => [],
'ip_name' => 'TOP',
'hdl_files_ticked' => []
}, 'ip_gen' )
},
'TOP' => {
'version' => 0
}
}, 'soc' )
'gui_status' => {
'timeout' => 0,
'status' => 'save_project'
},
'current_module_param' => undef,
'graph_save' => {},
'noc_param' => {},
'modules' => {},
'top_ip' => bless( {
'instance_ids' => {
'ni_master0' => {
'ports' => {
'ni_current_r_addr' => {
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_RAw-1 : 0',
'intfc_port' => 'current_r_addr'
},
'ni_chan_out' => {
'range' => 'smartflit_chanel_t',
'intfc_port' => 'chan_out',
'intfc_name' => 'socket:ni[0]',
'type' => 'output'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_e_addr',
'range' => 'ni_EAw-1 : 0'
},
'ni_chan_in' => {
'interface' => {
'socket:ni[0]' => {
'ports' => {
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0'
},
'ni_chan_in' => {
'range' => 'smartflit_chanel_t',
'intfc_port' => 'chan_in',
'instance_name' => 'ni_master0',
'type' => 'input'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'type' => 'input',
'instance_name' => 'ni_master0',
'range' => 'ni_EAw-1 : 0'
},
'ni_chan_out' => {
'range' => 'smartflit_chanel_t',
'intfc_port' => 'chan_in',
'type' => 'input',
'intfc_name' => 'socket:ni[0]'
'instance_name' => 'ni_master0',
'intfc_port' => 'chan_out',
'type' => 'output'
}
},
'category' => 'NoC',
'module' => 'ni_master',
'localparam' => {
'ni_M_Aw' => {
'redefine_param' => 1,
'info' => 'Parameter',
'content' => 'Dw',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32'
},
'ni_MAX_BURST_SIZE' => {
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '16',
'redefine_param' => 1,
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. '
},
'ni_TAGw' => {
'content' => '',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'redefine_param' => 1
},
'ni_Dw' => {
'type' => 'Spin-button',
'default' => '32',
'global_param' => 'Localparam',
'content' => '32,256,8',
'redefine_param' => 1,
'info' => 'wishbone_bus data width in bits.'
},
'ni_SELw' => {
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '4',
'content' => ''
},
'ni_MAX_TRANSACTION_WIDTH' => {
'content' => '4,32,1',
'global_param' => 'Localparam',
'default' => '13',
'type' => 'Spin-button',
'redefine_param' => 1,
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.'
},
'ni_CRC_EN' => {
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
'redefine_param' => 1,
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"NO"'
},
'ni_HDATA_PRECAPw' => {
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'redefine_param' => 1,
'content' => '0,8,1',
'default' => '0',
'type' => 'Spin-button',
'global_param' => 'Localparam'
},
'ni_S_Aw' => {
'content' => '',
'global_param' => 'Localparam',
'default' => '8',
'type' => 'Fixed',
'redefine_param' => 1,
'info' => 'Parameter'
}
},
'module_name' => 'ni_master',
'parameters' => {
'ni_EAw' => {
'global_param' => 'Parameter',
'default' => '16',
'type' => 'Fixed',
'content' => '',
'redefine_param' => 0,
'info' => undef
},
'ni_RAw' => {
'content' => '',
'default' => '16',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => undef,
'redefine_param' => 0
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_wr_sim' => {
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'RxD_wr_sim',
'type' => 'input',
'range' => ''
},
'uart_RxD_din_sim' => {
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'RxD_din_sim',
'type' => 'input',
'range' => '7:0 '
},
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'range' => ''
}
}
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input',
'instance_name' => 'clk_source0'
}
},
'instance' => 'ni'
},
'clk_source0' => {
'category' => 'Source',
}
},
'plug:enable[0]' => {
'ports' => {
'source_reset_in' => {
'range' => '',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
},
'source_clk_in' => {
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => '',
'intfc_port' => 'clk_i'
}
},
'instance' => 'source',
'module_name' => 'clk_source',
'module' => 'clk_source',
'localparam' => {
'source_FPGA_VENDOR' => {
'info' => '',
'redefine_param' => 1,
'content' => '"ALTERA","XILINX"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ALTERA"'
}
}
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'intfc_port' => 'enable_i',
'type' => 'input',
'range' => ''
}
}
},
'ProNoC_jtag_uart0' => {
'category' => 'Communication',
'socket:jtag_to_wb[0]' => {
'ports' => {
'ram_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'type' => 'output',
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0'
},
'uart_wb_to_jtag' => {
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output'
'instance_name' => 'ProNoC_jtag_uart0'
},
'uart_jtag_to_wb' => {
'range' => 'uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'instance_name' => 'single_port_ram0',
'range' => 'ram_J2WBw-1 : 0'
}
}
},
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'instance_name' => 'clk_source0',
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => ''
}
}
}
},
'instance_ids' => {
'ProNoC_jtag_uart0' => {
'instance' => 'uart',
'ports' => {
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'intfc_port' => 'RxD_ready_sim',
'range' => ''
'type' => 'output'
},
'uart_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i'
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'uart_RxD_wr_sim' => {
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '',
'intfc_port' => 'RxD_wr_sim'
},
'uart_RxD_din_sim' => {
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 ',
'type' => 'input',
'range' => '7:0 ',
'intfc_port' => 'RxD_din_sim'
}
},
'uart_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_WB2Jw-1 : 0',
'type' => 'output',
'intfc_port' => 'jwb_o'
},
'uart_RxD_wr_sim' => {
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]'
}
},
'instance' => 'uart',
'module_name' => 'pronoc_jtag_uart',
'localparam' => {
'uart_TAGw' => {
'content' => '',
'info' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam'
'global_param' => 'Localparam',
'redefine_param' => 1
},
'uart_SELw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '4',
'type' => 'Fixed'
},
'uart_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '1',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
},
'uart_BUFF_Aw' => {
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.',
'content' => '2,16,1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '4',
'type' => 'Spin-button',
'content' => '2,16,1'
'type' => 'Spin-button'
},
'uart_SELw' => {
'global_param' => 'Localparam',
'default' => '4',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'redefine_param' => 1
},
'uart_Dw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'content' => '',
'info' => 'Parameter',
'redefine_param' => 1
},
'uart_Aw' => {
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '1',
'info' => 'Parameter',
'redefine_param' => 1
'content' => ''
}
},
'module' => 'ProNoC_jtag_uart',
'parameters' => {
'uart_JTAG_CONNECT' => {
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'redefine_param' => 1,
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'type' => 'Combo-box',
'default' => '"ALTERA_JTAG_WB"',
'global_param' => 'Parameter'
},
'uart_JINDEXw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => '8',
'global_param' => 'Parameter'
'type' => 'Fixed'
},
'uart_JAw' => {
'content' => '',
'info' => 'Parameter',
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Parameter',
'redefine_param' => 1
},
'uart_JTAG_INDEX' => {
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Entry',
'default' => '126-CORE_ID'
},
'uart_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'default' => '3',
'type' => 'Combo-box',
'redefine_param' => 0,
'global_param' => 'Parameter'
},
'uart_WB2Jw' => {
'content' => '',
'info' => '',
'type' => 'Fixed',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
'global_param' => 'Parameter',
'info' => '',
'redefine_param' => 1
},
'uart_JTAG_INDEX' => {
'content' => '',
'global_param' => 'Parameter',
'type' => 'Entry',
'default' => '126-CORE_ID',
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
'redefine_param' => 1
},
'uart_JSTATUSw' => {
'redefine_param' => 1,
'info' => 'Parameter',
'content' => '',
'global_param' => 'Parameter',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '8',
'content' => ''
'default' => '8'
},
'uart_JTAG_CHAIN' => {
'default' => '3',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'content' => '1,2,3,4',
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'redefine_param' => 0
},
'uart_JAw' => {
'default' => '32',
'type' => 'Fixed',
'global_param' => 'Parameter',
'uart_JTAG_CONNECT' => {
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'uart_J2WBw' => {
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
'type' => 'Fixed',
'info' => undef,
'content' => ''
},
'uart_JDw' => {
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter'
},
'uart_JDw' => {
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32',
'content' => ''
},
'uart_J2WBw' => {
'info' => undef,
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1'
}
'redefine_param' => 1,
'global_param' => 'Parameter'
}
},
'module_name' => 'pronoc_jtag_uart'
'category' => 'Communication'
},
'mor1kx0' => {
'instance' => 'cpu',
'localparam' => {
'cpu_FEATURE_IMMU' => {
'redefine_param' => 1,
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'content' => '"NONE","ENABLED"'
},
'cpu_OPTION_SHIFTER' => {
'timer0' => {
'module' => 'timer',
'localparam' => {
'timer_Aw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '3',
'info' => undef,
'content' => ''
},
'timer_CNTw' => {
'info' => undef,
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32 '
},
'timer_SELw' => {
'default' => '4',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1,
'content' => '',
'info' => undef
},
'timer_TAGw' => {
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'type' => 'Fixed'
},
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '8',
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'content' => '1,32,1'
},
'timer_Dw' => {
'content' => '',
'info' => undef,
'type' => 'Fixed',
'default' => '32',
'global_param' => 'Localparam',
'redefine_param' => 1
}
},
'category' => 'Timer',
'instance' => 'timer',
'module_name' => 'timer'
},
'wishbone_bus0' => {
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'category' => 'Bus',
'localparam' => {
'bus_Dw' => {
'info' => 'The wishbone Bus data width in bits.',
'content' => '8,512,8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '32'
},
'bus_Aw' => {
'default' => '32',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '4,128,1',
'info' => 'The wishbone Bus address width'
},
'bus_BTEw' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Fixed',
'default' => '2 ',
'info' => undef,
'content' => ''
},
'bus_CTIw' => {
'content' => '',
'info' => undef,
'type' => 'Fixed',
'default' => '3',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'bus_SELw' => {
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => 'bus_Dw/8',
'type' => 'Fixed'
},
'bus_S' => {
'info' => 'Number of wishbone slave interface',
'content' => '1,256,1',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '4',
'type' => 'Spin-button'
},
'bus_M' => {
'content' => '1,256,1',
'info' => 'Number of wishbone master interface',
'default' => ' 4',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'bus_TAGw' => {
'content' => '',
'info' => undef,
'default' => '3',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam'
}
},
'module' => 'wishbone_bus'
},
'clk_source0' => {
'category' => 'Source',
'localparam' => {
'source_FPGA_VENDOR' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ALTERA"',
'type' => 'Combo-box',
'info' => '',
'content' => '"ALTERA","XILINX"'
}
},
'module' => 'clk_source',
'module_name' => 'clk_source',
'ports' => {
'source_clk_in' => {
'intfc_port' => 'clk_i',
'type' => 'input',
'intfc_name' => 'plug:clk[0]',
'range' => ''
},
'source_reset_in' => {
'intfc_port' => 'reset_i',
'type' => 'input',
'range' => '',
'intfc_name' => 'plug:reset[0]'
}
},
'instance' => 'source'
},
'ni_master0' => {
'category' => 'NoC',
'localparam' => {
'ni_CRC_EN' => {
'default' => '"NO"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"YES","NO"',
'info' => 'The parameter can be selected as "YES" or "NO".
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '
},
'ni_Dw' => {
'info' => 'wishbone_bus data width in bits.',
'content' => '32,256,8',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '32'
},
'ni_HDATA_PRECAPw' => {
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.',
'content' => '0,8,1',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '0',
'type' => 'Spin-button'
},
'ni_MAX_BURST_SIZE' => {
'info' => 'Maximum burst size in words.
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '16',
'type' => 'Combo-box'
},
'ni_MAX_TRANSACTION_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Spin-button',
'default' => '13',
'info' => 'maximum packet size width in words.
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
'content' => '4,32,1'
},
'ni_M_Aw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => 'Parameter',
'content' => 'Dw'
},
'ni_S_Aw' => {
'default' => '8',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '',
'info' => 'Parameter'
},
'ni_SELw' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '4',
'info' => 'Parameter',
'content' => ''
},
'ni_TAGw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'type' => 'Fixed'
}
},
'parameters' => {
'ni_EAw' => {
'redefine_param' => 0,
'global_param' => 'Parameter',
'default' => '16',
'type' => 'Fixed',
'info' => undef,
'content' => ''
},
'ni_RAw' => {
'info' => undef,
'content' => '',
'redefine_param' => 0,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '16'
}
},
'module' => 'ni_master',
'instance' => 'ni',
'ports' => {
'ni_current_e_addr' => {
'range' => 'ni_EAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_chan_in' => {
'type' => 'input',
'intfc_port' => 'chan_in',
'range' => 'smartflit_chanel_t',
'intfc_name' => 'socket:ni[0]'
},
'ni_chan_out' => {
'intfc_port' => 'chan_out',
'type' => 'output',
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_r_addr'
}
},
'module_name' => 'ni_master'
},
'single_port_ram0' => {
'category' => 'RAM',
'localparam' => {
'ram_INIT_FILE_PATH' => {
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => 'SW_LOC',
'type' => 'Fixed'
},
'ram_INITIAL_EN' => {
'content' => '"YES","NO"',
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'type' => 'Combo-box',
'default' => '"YES"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_WB_Aw' => {
'type' => 'Spin-button',
'default' => '20',
'global_param' => 'Localparam',
'default' => '"BARREL"',
'type' => 'Combo-box',
'content' => '"BARREL","SERIAL"',
'info' => 'Specify the shifter implementation',
'redefine_param' => 1
'redefine_param' => 1,
'content' => '4,31,1',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). '
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'info' => '',
'redefine_param' => 1,
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"'
},
'cpu_OPTION_OPERAND_WIDTH' => {
'redefine_param' => 1,
'info' => 'Parameter',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'content' => ''
},
'cpu_OPTION_DCACHE_SNOOP' => {
'content' => '"NONE","ENABLED"',
'ram_Aw' => {
'content' => '4,31,1',
'info' => 'Memory address width',
'default' => '14',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_MEM_CONTENT_FILE_NAME' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'type' => 'Entry',
'default' => '"ram0"',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'content' => ''
},
'ram_BURST_MODE' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'global_param' => 'Localparam',
'info' => '',
'redefine_param' => 1
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'content' => '"DISABLED","ENABLED"'
},
'cpu_FEATURE_DMMU' => {
'content' => '"NONE","ENABLED"',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'global_param' => 'Localparam',
'info' => '',
'redefine_param' => 1
},
'cpu_FEATURE_MULTIPLIER' => {
'type' => 'Combo-box',
'default' => '"THREESTAGE"',
'global_param' => 'Localparam',
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'info' => 'Specify the multiplier implementation',
'redefine_param' => 1
},
'cpu_FEATURE_DIVIDER' => {
'redefine_param' => 1,
'info' => 'Specify the divider implementation',
'global_param' => 'Localparam',
'default' => '"SERIAL"',
'type' => 'Combo-box',
'content' => '"SERIAL","NONE"'
},
'cpu_FEATURE_DATACACHE' => {
'ram_BTEw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '2',
'type' => 'Fixed'
},
'ram_CTIw' => {
'content' => '',
'info' => 'Parameter',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'ram_SELw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => 'ram_Dw/8',
'type' => 'Fixed'
},
'ram_TAGw' => {
'info' => 'Parameter',
'content' => '',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '3',
'type' => 'Fixed'
},
'ram_BYTE_WR_EN' => {
'content' => '"YES","NO"',
'info' => 'Byte enable',
'default' => '"YES"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam'
},
'ram_CORE_NUM' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"ENABLED"',
'content' => '"NONE","ENABLED"',
'info' => '',
'redefine_param' => 1
'type' => 'Fixed',
'default' => 'CORE_ID'
},
'cpu_IRQ_NUM' => {
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32',
'info' => undef,
'redefine_param' => 1
}
},
'module' => 'mor1kx',
'module_name' => 'mor1k',
'category' => 'Processor',
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'intfc_port' => 'enable_i',
'intfc_name' => 'plug:enable[0]',
'type' => 'input'
}
}
},
'single_port_ram0' => {
'ports' => {
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'ram_wb_to_jtag' => {
'range' => 'ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'output'
}
},
'category' => 'RAM',
'module_name' => 'wb_single_port_ram',
'ram_FPGA_VENDOR' => {
'content' => '"ALTERA","XILINX","GENERIC"',
'info' => '',
'default' => '"ALTERA"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1
}
},
'parameters' => {
'ram_JDw' => {
'default' => 'ram_Dw',
'type' => 'Fixed',
'redefine_param' => 1,
'global_param' => 'Parameter',
'content' => '',
'info' => 'Parameter'
},
'ram_JTAG_CHAIN' => {
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved',
'content' => '1,2,3,4',
'redefine_param' => 0,
'global_param' => 'Parameter',
'default' => '4',
'type' => 'Combo-box'
},
'ram_JAw' => {
'info' => 'Parameter',
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'type' => 'Fixed',
'default' => '32'
},
'ram_JTAG_CONNECT' => {
'type' => 'Combo-box',
'default' => '"ALTERA_JTAG_WB"',
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
},
'ram_Dw' => {
'content' => '8,1024,1',
'info' => 'Memory data width in Bits.',
'default' => '32',
'type' => 'Spin-button',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram_JTAG_INDEX' => {
'redefine_param' => 1,
'content' => '',
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
1820,583 → 2057,359
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
'content' => '',
'global_param' => 'Parameter',
'default' => 'CORE_ID',
'type' => 'Entry',
'default' => 'CORE_ID'
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram_JDw' => {
'redefine_param' => 1,
'info' => 'Parameter',
'content' => '',
'type' => 'Fixed',
'default' => 'ram_Dw',
'global_param' => 'Parameter'
},
'ram_JAw' => {
'info' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'global_param' => 'Parameter',
'default' => '32',
'type' => 'Fixed'
},
'ram_JINDEXw' => {
'default' => '8',
'type' => 'Fixed',
'global_param' => 'Parameter',
'content' => '',
'info' => 'Parameter',
'redefine_param' => 1
'type' => 'Fixed',
'default' => '8',
'redefine_param' => 1,
'global_param' => 'Parameter'
},
'ram_JSTATUSw' => {
'content' => '',
'redefine_param' => 1,
'global_param' => 'Parameter',
'default' => '8',
'type' => 'Fixed',
'global_param' => 'Parameter',
'info' => 'Parameter',
'redefine_param' => 1
'content' => ''
},
'ram_JTAG_CHAIN' => {
'content' => '1,2,3,4',
'global_param' => 'Parameter',
'default' => '4',
'type' => 'Combo-box',
'redefine_param' => 0,
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
4: JTAG runtime memory programmers.
3: UART
1,2: reserved'
},
'ram_WB2Jw' => {
'info' => undef,
'global_param' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'type' => 'Fixed',
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
'global_param' => 'Parameter'
'info' => undef,
'content' => ''
},
'ram_Dw' => {
'redefine_param' => 1,
'info' => 'Memory data width in Bits.',
'global_param' => 'Parameter',
'default' => '32',
'type' => 'Spin-button',
'content' => '8,1024,1'
},
'ram_J2WBw' => {
'redefine_param' => 1,
'info' => undef,
'global_param' => 'Parameter',
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
'type' => 'Fixed',
'info' => undef,
'content' => ''
},
'ram_JTAG_CONNECT' => {
'default' => '"ALTERA_JTAG_WB"',
'type' => 'Combo-box',
'global_param' => 'Parameter',
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
'redefine_param' => 1
}
}
},
'module' => 'single_port_ram',
'localparam' => {
'ram_CTIw' => {
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'content' => '',
'redefine_param' => 1,
'info' => 'Parameter'
},
'ram_Aw' => {
'global_param' => 'Localparam',
'default' => '14',
'type' => 'Spin-button',
'content' => '4,31,1',
'info' => 'Memory address width',
'redefine_param' => 1
},
'ram_FPGA_VENDOR' => {
'redefine_param' => 1,
'info' => '',
'content' => '"ALTERA","XILINX","GENERIC"',
'global_param' => 'Localparam',
'default' => '"ALTERA"',
'type' => 'Combo-box'
},
'ram_BYTE_WR_EN' => {
'redefine_param' => 1,
'info' => 'Byte enable',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"YES"',
'content' => '"YES","NO"'
},
'ram_SELw' => {
'info' => 'Parameter',
'redefine_param' => 1,
'content' => '',
'type' => 'Fixed',
'default' => 'ram_Dw/8',
'global_param' => 'Localparam'
},
'ram_INITIAL_EN' => {
'redefine_param' => 1,
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
'content' => '"YES","NO"',
'global_param' => 'Localparam',
'type' => 'Combo-box',
'default' => '"YES"'
},
'ram_BTEw' => {
'redefine_param' => 1,
'info' => 'Parameter',
'default' => '2',
'type' => 'Fixed',
'global_param' => 'Localparam',
'content' => ''
},
'ram_INIT_FILE_PATH' => {
'info' => undef,
'redefine_param' => 1,
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'SW_LOC',
'content' => ''
},
'ram_WB_Aw' => {
'module_name' => 'wb_single_port_ram',
'ports' => {
'ram_wb_to_jtag' => {
'type' => 'output',
'intfc_port' => 'jwb_o',
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0'
},
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_port' => 'jwb_i',
'range' => 'ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
},
'instance' => 'ram'
},
'mor1kx0' => {
'module' => 'mor1kx',
'localparam' => {
'cpu_FEATURE_DIVIDER' => {
'default' => '"SERIAL"',
'type' => 'Combo-box',
'redefine_param' => 1,
'global_param' => 'Localparam',
'content' => '"SERIAL","NONE"',
'info' => 'Specify the divider implementation'
},
'cpu_IRQ_NUM' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'info' => undef,
'content' => ''
},
'cpu_FEATURE_IMMU' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'type' => 'Combo-box'
},
'cpu_FEATURE_DATACACHE' => {
'content' => '"NONE","ENABLED"',
'info' => '',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_FEATURE_INSTRUCTIONCACHE' => {
'info' => '',
'content' => '"NONE","ENABLED"',
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Combo-box'
},
'cpu_FEATURE_DMMU' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '"ENABLED"',
'type' => 'Combo-box',
'info' => '',
'content' => '"NONE","ENABLED"'
},
'cpu_OPTION_SHIFTER' => {
'content' => '"BARREL","SERIAL"',
'info' => 'Specify the shifter implementation',
'type' => 'Combo-box',
'default' => '"BARREL"',
'global_param' => 'Localparam',
'type' => 'Spin-button',
'default' => '20',
'content' => '4,31,1',
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
'redefine_param' => 1
},
'ram_BURST_MODE' => {
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
'cpu_FEATURE_MULTIPLIER' => {
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
'info' => 'Specify the multiplier implementation',
'type' => 'Combo-box',
'default' => '"THREESTAGE"',
'global_param' => 'Localparam',
'redefine_param' => 1
},
'cpu_OPTION_OPERAND_WIDTH' => {
'global_param' => 'Localparam',
'redefine_param' => 1,
'default' => '32',
'type' => 'Fixed',
'info' => 'Parameter',
'content' => ''
},
'cpu_OPTION_DCACHE_SNOOP' => {
'redefine_param' => 1,
'global_param' => 'Localparam',
'default' => '"ENABLED"',
'type' => 'Combo-box',
'content' => '"DISABLED","ENABLED"'
},
'ram_CORE_NUM' => {
'content' => '',
'default' => 'CORE_ID',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => 'Parameter',
'redefine_param' => 1
},
'ram_MEM_CONTENT_FILE_NAME' => {
'content' => '',
'global_param' => 'Localparam',
'default' => '"ram0"',
'type' => 'Entry',
'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
'redefine_param' => 1
},
'ram_TAGw' => {
'content' => '',
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'redefine_param' => 1,
'info' => 'Parameter'
}
},
'instance' => 'ram'
},
'wishbone_bus0' => {
'instance' => 'bus',
'module_name' => 'wishbone_bus',
'localparam' => {
'bus_M' => {
'default' => ' 4',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'content' => '1,256,1',
'info' => 'Number of wishbone master interface',
'redefine_param' => 1
},
'bus_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => 'bus_Dw/8',
'content' => '',
'redefine_param' => 1,
'info' => undef
},
'bus_Dw' => {
'info' => 'The wishbone Bus data width in bits.',
'redefine_param' => 1,
'type' => 'Spin-button',
'default' => '32',
'global_param' => 'Localparam',
'content' => '8,512,8'
},
'bus_TAGw' => {
'redefine_param' => 1,
'info' => undef,
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'content' => ''
},
'bus_Aw' => {
'redefine_param' => 1,
'info' => 'The wishbone Bus address width',
'default' => '32',
'type' => 'Spin-button',
'global_param' => 'Localparam',
'content' => '4,128,1'
},
'bus_CTIw' => {
'content' => '',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'redefine_param' => 1
},
'bus_S' => {
'global_param' => 'Localparam',
'default' => '4',
'type' => 'Spin-button',
'content' => '1,256,1',
'info' => 'Number of wishbone slave interface',
'redefine_param' => 1
},
'bus_BTEw' => {
'redefine_param' => 1,
'info' => undef,
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '2 '
}
},
'module' => 'wishbone_bus',
'category' => 'Bus'
},
'timer0' => {
'category' => 'Timer',
'module_name' => 'timer',
'module' => 'timer',
'localparam' => {
'timer_CNTw' => {
'content' => '',
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '32 ',
'info' => undef,
'redefine_param' => 1
},
'timer_Dw' => {
'redefine_param' => 1,
'info' => undef,
'global_param' => 'Localparam',
'default' => '32',
'type' => 'Fixed',
'content' => ''
},
'timer_PRESCALER_WIDTH' => {
'redefine_param' => 1,
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
 
 
',
'global_param' => 'Localparam',
'default' => '8',
'type' => 'Spin-button',
'content' => '1,32,1'
},
'timer_SELw' => {
'global_param' => 'Localparam',
'type' => 'Fixed',
'default' => '4',
'content' => '',
'redefine_param' => 1,
'info' => undef
},
'timer_TAGw' => {
'content' => '',
'default' => '3',
'type' => 'Fixed',
'global_param' => 'Localparam',
'info' => undef,
'redefine_param' => 1
},
'timer_Aw' => {
'content' => '',
'type' => 'Fixed',
'default' => '3',
'global_param' => 'Localparam',
'info' => undef,
'redefine_param' => 1
}
},
'instance' => 'timer'
}
'info' => '',
'content' => '"NONE","ENABLED"'
}
},
'category' => 'Processor',
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'intfc_name' => 'plug:enable[0]',
'intfc_port' => 'enable_i',
'type' => 'input'
}
},
'instance' => 'cpu',
'module_name' => 'mor1k'
}
},
'ports' => {
'ram_jtag_to_wb' => {
'type' => 'input',
'intfc_name' => 'socket:jtag_to_wb[0]',
'intfc_port' => 'jwb_i',
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0'
},
'uart_wb_to_jtag' => {
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'jwb_o',
'type' => 'output',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'source_clk_in' => {
'range' => '',
'intfc_name' => 'plug:clk[0]',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_port' => 'clk_i'
},
'ram_wb_to_jtag' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'ram_WB2Jw-1 : 0',
'type' => 'output',
'range' => 'ram_WB2Jw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_o'
},
'uart_RxD_din_sim' => {
'intfc_port' => 'RxD_din_sim',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'range' => '7:0 '
},
'source_reset_in' => {
'intfc_name' => 'plug:reset[0]',
'range' => '',
'intfc_port' => 'reset_i',
'instance_name' => 'clk_source0',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'range' => 'uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input'
},
'uart_RxD_ready_sim' => {
'type' => 'output',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_ready_sim',
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => ''
'type' => 'output',
'intfc_port' => 'RxD_ready_sim'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input',
'intfc_port' => 'current_e_addr'
},
'ni_chan_in' => {
'instance_name' => 'ni_master0',
'intfc_port' => 'chan_in',
'type' => 'input',
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'ni_chan_out' => {
'instance_name' => 'ni_master0',
'range' => 'smartflit_chanel_t',
'type' => 'output',
'intfc_port' => 'chan_out',
'type' => 'output',
'intfc_name' => 'socket:ni[0]'
'intfc_name' => 'socket:ni[0]',
'range' => 'smartflit_chanel_t'
},
'cpu_cpu_en' => {
'instance_name' => 'mor1kx0',
'range' => '',
'intfc_port' => 'enable_i',
'type' => 'input',
'intfc_name' => 'plug:enable[0]'
},
'uart_RxD_din_sim' => {
'type' => 'input',
'intfc_name' => 'socket:RxD_sim[0]',
'intfc_port' => 'RxD_din_sim',
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart0'
},
'ni_current_r_addr' => {
'range' => 'ni_RAw-1 : 0',
'intfc_name' => 'socket:ni[0]',
'instance_name' => 'ni_master0',
'range' => 'ni_RAw-1 : 0',
'intfc_port' => 'current_r_addr',
'intfc_name' => 'socket:ni[0]',
'type' => 'input'
},
'uart_jtag_to_wb' => {
'intfc_name' => 'socket:jtag_to_wb[0]',
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i'
},
'uart_RxD_wr_sim' => {
'range' => '',
'intfc_name' => 'socket:RxD_sim[0]',
'type' => 'input',
'intfc_port' => 'RxD_wr_sim',
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0'
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'RxD_wr_sim'
},
'ni_current_e_addr' => {
'intfc_name' => 'socket:ni[0]',
'type' => 'input',
'intfc_port' => 'current_e_addr',
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0'
},
'source_clk_in' => {
'intfc_port' => 'clk_i',
'range' => '',
'instance_name' => 'clk_source0',
'type' => 'input',
'intfc_name' => 'plug:clk[0]'
},
'ni_chan_in' => {
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0',
'intfc_port' => 'chan_in',
'intfc_name' => 'socket:ni[0]',
'uart_wb_to_jtag' => {
'intfc_port' => 'jwb_o',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
},
'cpu_cpu_en' => {
'intfc_name' => 'plug:enable[0]',
'range' => '',
'instance_name' => 'mor1kx0',
'intfc_port' => 'enable_i',
'type' => 'input'
},
'source_reset_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
'type' => 'input'
}
},
'interface' => {
'plug:enable[0]' => {
'ports' => {
'cpu_cpu_en' => {
'range' => '',
'instance_name' => 'mor1kx0',
'intfc_port' => 'enable_i',
'type' => 'input'
}
}
},
'socket:RxD_sim[0]' => {
'ports' => {
'uart_RxD_wr_sim' => {
'intfc_port' => 'RxD_wr_sim',
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'input'
},
'uart_RxD_din_sim' => {
'range' => '7:0 ',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'RxD_din_sim',
'type' => 'input'
},
'uart_RxD_ready_sim' => {
'intfc_port' => 'RxD_ready_sim',
'range' => '',
'instance_name' => 'ProNoC_jtag_uart0',
'type' => 'output'
}
}
},
'socket:jtag_to_wb[0]' => {
'ports' => {
'uart_jtag_to_wb' => {
'type' => 'input',
'instance_name' => 'ProNoC_jtag_uart0',
'range' => 'uart_J2WBw-1 : 0',
'intfc_port' => 'jwb_i'
},
'ram_wb_to_jtag' => {
'type' => 'output',
'instance_name' => 'single_port_ram0',
'range' => 'ram_WB2Jw-1 : 0',
'intfc_port' => 'jwb_o'
},
'ram_jtag_to_wb' => {
'range' => 'ram_J2WBw-1 : 0',
'instance_name' => 'single_port_ram0',
'intfc_port' => 'jwb_i',
'type' => 'input'
},
'uart_wb_to_jtag' => {
'type' => 'output',
'range' => 'uart_WB2Jw-1 : 0',
'instance_name' => 'ProNoC_jtag_uart0',
'intfc_port' => 'jwb_o'
}
}
},
'plug:clk[0]' => {
'ports' => {
'source_clk_in' => {
'instance_name' => 'clk_source0',
'range' => '',
'intfc_port' => 'clk_i',
'type' => 'input'
}
}
},
'socket:ni[0]' => {
'ports' => {
'ni_chan_in' => {
'type' => 'input',
'intfc_port' => 'chan_in',
'range' => 'smartflit_chanel_t',
'instance_name' => 'ni_master0'
},
'ni_current_e_addr' => {
'intfc_port' => 'current_e_addr',
'range' => 'ni_EAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input'
},
'ni_chan_out' => {
'instance_name' => 'ni_master0',
'range' => 'smartflit_chanel_t',
'intfc_port' => 'chan_out',
'type' => 'output'
},
'ni_current_r_addr' => {
'intfc_port' => 'current_r_addr',
'range' => 'ni_RAw-1 : 0',
'instance_name' => 'ni_master0',
'type' => 'input'
}
}
},
'plug:reset[0]' => {
'ports' => {
'source_reset_in' => {
'type' => 'input',
'range' => '',
'instance_name' => 'clk_source0',
'intfc_port' => 'reset_i'
}
}
}
}
'ram_jtag_to_wb' => {
'intfc_port' => 'jwb_i',
'instance_name' => 'single_port_ram0',
'type' => 'input',
'range' => 'ram_J2WBw-1 : 0',
'intfc_name' => 'socket:jtag_to_wb[0]'
}
}
}, 'ip_gen' ),
'modules' => {},
'ROM0' => {
'start' => 0,
'end' => 49152
},
'device_win_adj' => {
'ha' => '0',
'va' => '0'
},
'global_param' => {
'CORE_ID' => 3,
'SW_LOC' => '/home/alireza/work/git/hca_git/mpsoc_work/SOC/mor1k_tile/sw'
},
'clk_source0' => {
'version' => 1
},
'graph_save' => {},
'mor1kx0' => {
'version' => 26
},
'wishbone_bus0' => {
'version' => 1
},
'MEM0' => {
'width' => '14',
'percent' => 75
},
'timer0' => {
'version' => 12
},
'single_port_ram0' => {
'version' => 39
},
'soc_name' => 'mor1k_tile',
'tile_diagram' => {
'show_clk' => 0,
'show_reset' => 0,
'show_unused' => 1
},
'noc_param' => {},
'hdl_files_ticked' => undef,
'parameters_order' => {
'current_module_param' => [
'FPGA_VENDOR',
'M',
'S',
'Dw',
'Aw',
'SELw',
'TAGw',
'CTIw',
'BTEw',
'OPTION_OPERAND_WIDTH',
'IRQ_NUM',
'OPTION_DCACHE_SNOOP',
'FEATURE_INSTRUCTIONCACHE',
'FEATURE_DATACACHE',
'FEATURE_IMMU',
'FEATURE_DMMU',
'FEATURE_MULTIPLIER',
'FEATURE_DIVIDER',
'OPTION_SHIFTER',
'WB_Aw',
'BYTE_WR_EN',
'JTAG_CONNECT',
'JTAG_INDEX',
'CORE_NUM',
'WB_Byte_Aw',
'BURST_MODE',
'MEM_CONTENT_FILE_NAME',
'INITIAL_EN',
'INIT_FILE_PATH',
'JDw',
'JAw',
'JSTATUSw',
'JINDEXw',
'J2WBw',
'WB2Jw',
'JTAG_CHAIN',
'MAX_TRANSACTION_WIDTH',
'MAX_BURST_SIZE',
'S_Aw',
'M_Aw',
'CRC_EN',
'RAw',
'EAw',
'HDATA_PRECAPw',
'CNTw',
'PRESCALER_WIDTH',
'BUFF_Aw',
'INCLUDE_SIM_PRINTF'
]
},
'JTAG' => {
'M_CHAIN' => '0'
},
'hdl_files_ticked' => undef,
'MEM0' => {
'percent' => 75,
'width' => '14'
},
'ProNoC_jtag_uart0' => {
'version' => 11
},
'Unset-intfc' => {},
'RAM0' => {
'end' => 65536,
'start' => 49152
},
'ni_master0' => {
'version' => 84
},
'instance_order' => [
'clk_source0',
'wishbone_bus0',
'mor1kx0',
'single_port_ram0',
'ni_master0',
'timer0',
'ProNoC_jtag_uart0'
],
'clk_source0' => {
'version' => 1
}
}
}, 'soc' );

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