URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/rtl/src_noc
- from Rev 54 to Rev 55
- ↔ Reverse comparison
Rev 54 → Rev 55
/mesh_torus.v
File deleted
mesh_torus.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: flit_buffer.v
===================================================================
--- flit_buffer.v (revision 54)
+++ flit_buffer.v (nonexistent)
@@ -1,1252 +0,0 @@
-`timescale 1ns/1ps
-
-/**********************************************************************
-** File: flit_buffer.v
-**
-** Copyright (C) 2014-2017 Alireza Monemi
-**
-** This file is part of ProNoC
-**
-** ProNoC ( stands for Prototype Network-on-chip) is free software:
-** you can redistribute it and/or modify it under the terms of the GNU
-** Lesser General Public License as published by the Free Software Foundation,
-** either version 2 of the License, or (at your option) any later version.
-**
-** ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-** Public License for more details.
-**
-** You should have received a copy of the GNU Lesser General Public
-** License along with ProNoC. If not, see = B-1);
- assign vc_not_empty [i] = (depth[i] > 0);
-
-
-`ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
-`else
- always @ (posedge clk or posedge reset)begin
-`endif
- if (reset) begin
- rd_ptr [i] <= {Bw{1'b0}};
- wr_ptr [i] <= {Bw{1'b0}};
- depth [i] <= {DEPTHw{1'b0}};
- end
- else begin
- if (wr[i] ) wr_ptr[i] <= wr_ptr [i]+ 1'h1;
- if (rd[i] ) rd_ptr [i]<= rd_ptr [i]+ 1'h1;
- if (wr[i] & ~rd[i]) depth [i]<= depth[i] + 1'h1;
- else if (~wr[i] & rd[i]) depth [i]<= depth[i] - 1'h1;
- end//else
- end//always
-
-
-//synthesis translate_off
-//synopsys translate_off
-
- always @(posedge clk) begin
- if(~reset)begin
- if (wr[i] && (depth[i] == B [DEPTHw-1 : 0]) && !rd[i])begin
- $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,B);
- $finish;
- end
- /* verilator lint_off WIDTH */
- if (rd[i] && (depth[i] == {DEPTHw{1'b0}} && SSA_EN !="YES" ))begin
- $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
- $finish;
- end
- if (rd[i] && !wr[i] && (depth[i] == {DEPTHw{1'b0}} && SSA_EN =="YES" ))begin
- $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
- $finish;
- end
- /* verilator lint_on WIDTH */
- end//~reset
- //if (wr_en) $display($time, " %h is written on fifo ",din);
- end//always
-//synopsys translate_on
-//synthesis translate_on
- end//for
-
-
-
- end else begin :no_pow2 //pow2
-
-
-
-
-
- /*****************
- Buffer width is not power of 2
- ******************/
-
-
-
-
-
- //pointers
- reg [BVw- 1 : 0] rd_ptr [V-1 :0];
- reg [BVw- 1 : 0] wr_ptr [V-1 :0];
-
- // memory address
- wire [BVw- 1 : 0] wr_addr;
- wire [BVw- 1 : 0] rd_addr;
-
- //pointer array
- wire [BVwV- 1 : 0] wr_addr_all;
- wire [BVwV- 1 : 0] rd_addr_all;
-
- for(i=0;i 0);
-
- /* verilator lint_off WIDTH */
-`ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
-`else
- always @ (posedge clk or posedge reset)begin
-`endif
- if (reset) begin
-
- rd_ptr [i] <= (B*i);
- wr_ptr [i] <= (B*i);
- depth [i] <= {DEPTHw{1'b0}};
- end
- else begin
- if (wr[i] ) wr_ptr[i] <=(wr_ptr[i]==(B*(i+1))-1)? (B*i) : wr_ptr [i]+ 1'h1;
- if (rd[i] ) rd_ptr[i] <=(rd_ptr[i]==(B*(i+1))-1)? (B*i) : rd_ptr [i]+ 1'h1;
- if (wr[i] & ~rd[i]) depth [i]<=depth[i] + 1'h1;
- else if (~wr[i] & rd[i]) depth [i]<= depth[i] - 1'h1;
- end//else
- end//always
- /* verilator lint_on WIDTH */
-
-//synthesis translate_off
-//synopsys translate_off
-
- always @(posedge clk) begin
- if(~reset)begin
- if (wr[i] && (depth[i] == B[DEPTHw-1 : 0]) && !rd[i]) begin
- $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,B);
- $finish;
- end
- /* verilator lint_off WIDTH */
- if (rd[i] && (depth[i] == {DEPTHw{1'b0}} && SSA_EN !="YES" )) begin
- $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
- $finish;
- end
- if (rd[i] && !wr[i] && (depth[i] == {DEPTHw{1'b0}} && SSA_EN =="YES" )) begin
- $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
- $finish;
- end
- /* verilator lint_on WIDTH */
-
- //if (wr_en) $display($time, " %h is written on fifo ",din);
- end//~reset
- end//always
-
-//synopsys translate_on
-//synthesis translate_on
-
-
-
- end//FOR
-
-
- onehot_mux_1D #(
- .W(BVw),
- .N(V)
- )
- wr_mux
- (
- .in(wr_addr_all),
- .out(wr_addr),
- .sel(vc_num_wr)
- );
-
- onehot_mux_1D #(
- .W(BVw),
- .N(V)
- )
- rd_mux
- (
- .in(rd_addr_all),
- .out(rd_addr),
- .sel(vc_num_rd)
- );
-
- fifo_ram_mem_size #(
- .DATA_WIDTH (RAM_DATA_WIDTH),
- .MEM_SIZE (BV ),
- .SSA_EN(SSA_EN)
- )
- the_queue
- (
- .wr_data (fifo_ram_din),
- .wr_addr (wr_addr),
- .rd_addr (rd_addr),
- .wr_en (wr_en),
- .rd_en (rd_en),
- .clk (clk),
- .rd_data (fifo_ram_dout)
- );
-
-
-
-
-
-
- end
- endgenerate
-
-
-
-
-
-
-//synthesis translate_off
-//synopsys translate_off
-generate
-if(DEBUG_EN) begin :dbg
- always @(posedge clk) begin
- if(~reset)begin
- if(wr_en && vc_num_wr == {V{1'b0}})begin
- $display("%t: ERROR: Attempt to write when no wr VC is asserted: %m",$time);
- $finish;
- end
- if(rd_en && vc_num_rd == {V{1'b0}})begin
- $display("%t: ERROR: Attempt to read when no rd VC is asserted: %m",$time);
- $finish;
- end
- end
- end
-end
-endgenerate
-//synopsys translate_on
-//synthesis translate_on
-
-endmodule
-
-
-
-/****************************
-
- fifo_ram
-
-*****************************/
-
-
-
-module fifo_ram #(
- parameter DATA_WIDTH = 32,
- parameter ADDR_WIDTH = 8,
- parameter SSA_EN="YES" // "YES" , "NO"
- )
- (
- wr_data,
- wr_addr,
- rd_addr,
- wr_en,
- rd_en,
- clk,
- rd_data
- );
-
-
- input [DATA_WIDTH-1 : 0] wr_data;
- input [ADDR_WIDTH-1 : 0] wr_addr;
- input [ADDR_WIDTH-1 : 0] rd_addr;
- input wr_en;
- input rd_en;
- input clk;
- output [DATA_WIDTH-1 : 0] rd_data;
-
-
-
- reg [DATA_WIDTH-1:0] memory_rd_data;
- // memory
- reg [DATA_WIDTH-1:0] queue [2**ADDR_WIDTH-1:0] /* synthesis ramstyle = "no_rw_check , M9K" */;
- always @(posedge clk ) begin
- if (wr_en)
- queue[wr_addr] <= wr_data;
- if (rd_en)
- memory_rd_data <= queue[rd_addr];
- end
-
-
-
-
-
-
-
- generate
- /* verilator lint_off WIDTH */
- if(SSA_EN =="YES") begin :predict
- /* verilator lint_on WIDTH */
- //add bypass
- reg [DATA_WIDTH-1:0] bypass_reg;
- reg rd_en_delayed;
- always @(posedge clk ) begin
- bypass_reg <=wr_data;
- rd_en_delayed <=rd_en;
- end
-
- assign rd_data = (rd_en_delayed)? memory_rd_data : bypass_reg;
-
-
-
- end else begin : no_predict
- assign rd_data = memory_rd_data;
- end
- endgenerate
-endmodule
-
-
-
-/*********************
-*
-* fifo_ram_mem_size
-*
-**********************/
-
-
-module fifo_ram_mem_size #(
- parameter DATA_WIDTH = 32,
- parameter MEM_SIZE = 200,
- parameter SSA_EN = "YES" // "YES" , "NO"
- )
- (
- wr_data,
- wr_addr,
- rd_addr,
- wr_en,
- rd_en,
- clk,
- rd_data
- );
-
-
- function integer log2;
- input integer number; begin
- log2=(number <=1) ? 1: 0;
- while(2**log22) begin :mwb2
- wire [MUX_SEL_WIDTH-1 : 0] mux_sel;
- wire [DEPTH_DATA_WIDTH-1 : 0] depth_2;
- wire empty;
- wire out_sel ;
- if(DATA_WIDTH>1) begin :wb1
- wire [MAX_DEPTH-2 : 0] mux_in [DATA_WIDTH-1 :0];
- wire [DATA_WIDTH-1 : 0] mux_out;
- reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0];
-
- for(i=0;i= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
- assign empty = depth == {DEPTH_DATA_WIDTH{1'b0}};
- assign recieve_more_than_0 = ~ empty;
- assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} || depth== 1 );
- assign out_sel = (recieve_more_than_1) ? 1'b1 : 1'b0;
- assign out_ld = (depth !=0 )? rd_en : wr_en;
- assign depth_2 = depth - 2;
- assign mux_sel = depth_2[MUX_SEL_WIDTH-1 : 0] ;
-
- end else if ( MAX_DEPTH == 2) begin :mw2
-
- reg [DATA_WIDTH-1 : 0] register;
-
-
- always @(posedge clk ) begin
- if(wr_en) register <= din;
- end //always
-
- assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0];
- assign nearly_full = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
- assign out_ld = (depth !=0 )? rd_en : wr_en;
- assign recieve_more_than_0 = (depth != {DEPTH_DATA_WIDTH{1'b0}});
- assign recieve_more_than_1 = ~( depth == 0 || depth== 1 );
- assign dout_next = (recieve_more_than_1) ? register : din;
-
-
- end else begin :mw1 // MAX_DEPTH == 1
- assign out_ld = wr_en;
- assign dout_next = din;
- assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0];
- assign nearly_full= 1'b1;
- assign recieve_more_than_0 = full;
- assign recieve_more_than_1 = 1'b0;
- end
-
-
-
- endgenerate
-
-
-
-
- `ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
- `else
- always @ (posedge clk or posedge reset)begin
- `endif
- if (reset) begin
- depth <= {DEPTH_DATA_WIDTH{1'b0}};
- end else begin
- if (wr_en & ~rd_en) depth <= depth + 1'h1;
- else if (~wr_en & rd_en) depth <= depth - 1'h1;
- end
- end//always
-
-
- `ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
- `else
- always @ (posedge clk or posedge reset)begin
- `endif
- if (reset) begin
- dout <= {DATA_WIDTH{1'b0}};
- end else begin
- if (out_ld) dout <= dout_next;
- end
- end//always
-
-//synthesis translate_off
-//synopsys translate_off
- always @(posedge clk)
- begin
- if(~reset)begin
- if (wr_en & ~rd_en & full) begin
- $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
- $finish;
- end
- /* verilator lint_off WIDTH */
- if (rd_en & !recieve_more_than_0 & IGNORE_SAME_LOC_RD_WR_WARNING == "NO") begin
- $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
- $finish;
- end
- if (rd_en & ~wr_en & !recieve_more_than_0 & (IGNORE_SAME_LOC_RD_WR_WARNING == "YES")) begin
- $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
- $finish;
- end
- /* verilator lint_on WIDTH */
- end //~reset
- end // always @ (posedge clk)
-
-//synopsys translate_on
-//synthesis translate_on
-
-
-
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-/*********************
-
- fwft_fifo_with_output_clear
- each individual output bit has
- its own clear signal
-
-**********************/
-
-
-
-
-
-module fwft_fifo_with_output_clear #(
- parameter DATA_WIDTH = 2,
- parameter MAX_DEPTH = 2,
- parameter IGNORE_SAME_LOC_RD_WR_WARNING="NO" // "YES" , "NO"
- )
- (
- din, // Data in
- wr_en, // Write enable
- rd_en, // Read the next word
- dout, // Data out
- full,
- nearly_full,
- recieve_more_than_0,
- recieve_more_than_1,
- reset,
- clk,
- clear
-
- );
-
- input [DATA_WIDTH-1:0] din;
- input wr_en;
- input rd_en;
- output reg [DATA_WIDTH-1:0] dout;
- output full;
- output nearly_full;
- output recieve_more_than_0;
- output recieve_more_than_1;
- input reset;
- input clk;
- input [DATA_WIDTH-1:0] clear;
-
- function integer log2;
- input integer number; begin
- log2=(number <=1) ? 1: 0;
- while(2**log22) begin :mwb2
- wire [MUX_SEL_WIDTH-1 : 0] mux_sel;
- wire [DEPTH_DATA_WIDTH-1 : 0] depth_2;
- wire empty;
- wire out_sel ;
- if(DATA_WIDTH>1) begin :wb1
- wire [MAX_DEPTH-2 : 0] mux_in [DATA_WIDTH-1 :0];
- wire [DATA_WIDTH-1 : 0] mux_out;
- reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0];
-
- for(i=0;i= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
- assign empty = depth == {DEPTH_DATA_WIDTH{1'b0}};
- assign recieve_more_than_0 = ~ empty;
- assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} || depth== 1 );
- assign out_sel = (recieve_more_than_1) ? 1'b1 : 1'b0;
- assign out_ld = (depth !=0 )? rd_en : wr_en;
- assign depth_2 = depth-2'd2;
- assign mux_sel = depth_2[MUX_SEL_WIDTH-1 : 0] ;
-
- end else if ( MAX_DEPTH == 2) begin :mw2
-
- reg [DATA_WIDTH-1 : 0] register;
-
- always @(posedge clk ) begin
- if(wr_en) register <= din;
- end //always
-
- assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0];
- assign nearly_full = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
- assign out_ld = (depth !=0 )? rd_en : wr_en;
- assign recieve_more_than_0 = (depth != {DEPTH_DATA_WIDTH{1'b0}});
- assign recieve_more_than_1 = ~( depth == 0 || depth== 1 );
- assign dout_next = (recieve_more_than_1) ? register : din;
-
- end else begin :mw1 // MAX_DEPTH == 1
- assign out_ld = wr_en;
- assign dout_next = din;
- assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0];
- assign nearly_full= 1'b1;
- assign recieve_more_than_0 = full;
- assign recieve_more_than_1 = 1'b0;
- end
-endgenerate
-
-`ifdef SYNC_RESET_MODE
- always @ (posedge clk )begin
-`else
- always @ (posedge clk or posedge reset)begin
-`endif
- if (reset) begin
- depth <= {DEPTH_DATA_WIDTH{1'b0}};
- end else begin
- if (wr_en & ~rd_en) depth <= depth + 1'h1;
- else if (~wr_en & rd_en) depth <= depth - 1'h1;
- end
- end//always
-
- generate
- for(i=0;i= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
- assign empty = depth == {DEPTH_DATA_WIDTH{1'b0}};
- assign recieve_more_than_0 = ~ empty;
- assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} || depth== 1 );
-
-
-
-
-//synthesis translate_off
-//synopsys translate_off
- always @(posedge clk)
- begin
- if(~reset)begin
- if (wr_en & ~rd_en & full) begin
- $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
- $finish;
- end
- /* verilator lint_off WIDTH */
- if (rd_en & !recieve_more_than_0 & IGNORE_SAME_LOC_RD_WR_WARNING == "NO") begin
- $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
- $finish;
- end
- if (rd_en & ~wr_en & !recieve_more_than_0 & (IGNORE_SAME_LOC_RD_WR_WARNING == "YES")) begin
- $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
- $finish;
- end
- /* verilator lint_on WIDTH */
- end //~reset
- end // always @ (posedge clk)
-
-//synopsys translate_on
-//synthesis translate_on
-
-
-
-
-endmodule
-
-
-
-
-
-
-
-
-
-/**********************************
-
- bram_based_fifo
-
-*********************************/
-
-
-module bram_based_fifo #(
- parameter Dw = 72,//data_width
- parameter B = 10// buffer num
-)(
- din,
- wr_en,
- rd_en,
- dout,
- full,
- nearly_full,
- empty,
- reset,
- clk
-);
-
-
- function integer log2;
- input integer number; begin
- log2=(number <=1) ? 1: 0;
- while(2**log2=Bint2; // B-1
-assign empty = depth == {DEPTHw{1'b0}};
-
-//synthesis translate_off
-//synopsys translate_off
-always @(posedge clk)
-begin
- if(~reset)begin
- if (wr_en && depth == B[DEPTHw-1 : 0] && !rd_en) begin
- $display(" %t: ERROR: Attempt to write to full FIFO: %m",$time);
- $finish;
- end
- if (rd_en && depth == {DEPTHw{1'b0}}) begin
- $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
- $finish;
- end
- end//~reset
-end
-//synopsys translate_on
-//synthesis translate_on
-
-endmodule // fifo
-
-
flit_buffer.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: combined_vc_sw_alloc.v
===================================================================
--- combined_vc_sw_alloc.v (revision 54)
+++ combined_vc_sw_alloc.v (nonexistent)
@@ -1,287 +0,0 @@
-`timescale 1ns/1ps
-/**********************************************************************
-** File: combined_vc_sw_alloc.v
-**
-** Copyright (C) 2014-2017 Alireza Monemi
-**
-** This file is part of ProNoC
-**
-** ProNoC ( stands for Prototype Network-on-chip) is free software:
-** you can redistribute it and/or modify it under the terms of the GNU
-** Lesser General Public License as published by the Free Software Foundation,
-** either version 2 of the License, or (at your option) any later version.
-**
-** ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-** Public License for more details.
-**
-** You should have received a copy of the GNU Lesser General Public
-** License along with ProNoC. If not, see
combined_vc_sw_alloc.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: comb_nonspec.v
===================================================================
--- comb_nonspec.v (revision 54)
+++ comb_nonspec.v (nonexistent)
@@ -1,970 +0,0 @@
-`timescale 1ns/1ps
-
-/**********************************************************************
-** File: comb-nonspec.v
-**
-** Copyright (C) 2014-2017 Alireza Monemi
-**
-** This file is part of ProNoC
-**
-** ProNoC ( stands for Prototype Network-on-chip) is free software:
-** you can redistribute it and/or modify it under the terms of the GNU
-** Lesser General Public License as published by the Free Software Foundation,
-** either version 2 of the License, or (at your option) any later version.
-**
-** ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-** Public License for more details.
-**
-** You should have received a copy of the GNU Lesser General Public
-** License along with ProNoC. If not, see j) begin: hh
- assign ovc_allocated_all_gen[i][j] = cand_ovc_granted[j][i-V];
-
- end
- end else begin : slp
- assign ovc_allocated_all_gen[i][j] = cand_ovc_granted[j][i];
- end
- end//j
-
- assign ovc_allocated_all [i] = |ovc_allocated_all_gen[i];
-
- end//i
-
- endgenerate
-
-endmodule
-
-
-
-
-/**************************************************************
-*
-* comb_nonspec_v2
-*
-* first arbiter has been shifted after first multiplexer
-*
-*
-*********************************************************/
-
-
-
-module comb_nonspec_v2_allocator #(
- parameter V = 4,
- parameter P = 5,
- parameter FIRST_ARBITER_EXT_P_EN = 1,
- parameter SWA_ARBITER_TYPE = "WRRA",
- parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
- parameter SELF_LOOP_EN= "NO"
-
-)(
- //VC allocator
- //input
- dest_port_all, // from input port
- ovc_is_assigned_all, //
- masked_ovc_request_all,
- pck_is_single_flit_all,
-
- //output
- ovc_allocated_all,//to the output port
- granted_ovc_num_all, // to the input port
- ivc_num_getting_ovc_grant,
-
- //switch_alloc
- ivc_request_all,
- assigned_ovc_not_full_all,
- vc_weight_is_consumed_all,
- iport_weight_is_consumed_all,
-
- //output
- granted_dest_port_all,
- ivc_num_getting_sw_grant,
- nonspec_first_arbiter_granted_ivc_all,
- any_ivc_sw_request_granted_all,
- any_ovc_granted_in_outport_all,
- granted_dst_is_from_a_single_flit_pck,
-
- // global
- clk,
- reset
-
-);
-
-
- localparam
- P_1 = (SELF_LOOP_EN == "NO") ? P-1 :P,
- PV = V * P,
- VV = V * V,
- VP_1 = V * P_1,
- PP_1 = P_1 * P,
- PVV = PV * V,
- PVP_1 = PV * P_1;
-
-
-
-
- input [PVV-1 : 0] masked_ovc_request_all;
- input [PVP_1-1 : 0] dest_port_all;
- input [PV-1 : 0] ovc_is_assigned_all;
- input [PV-1 : 0] pck_is_single_flit_all;
- output [PV-1 : 0] ovc_allocated_all;
- output [PVV-1 : 0] granted_ovc_num_all;
- output [PV-1 : 0] ivc_num_getting_ovc_grant;
- input [PV-1 : 0] ivc_request_all;
- input [PV-1 : 0] assigned_ovc_not_full_all;
- output [PP_1-1 : 0] granted_dest_port_all;
- output [PV-1 : 0] ivc_num_getting_sw_grant;
- output [P-1 : 0] any_ivc_sw_request_granted_all;
- output [P-1 : 0] any_ovc_granted_in_outport_all;
- output [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
- input clk,reset;
- input [PV-1 : 0] vc_weight_is_consumed_all;
- input [P-1 : 0] iport_weight_is_consumed_all;
-
- //internal wires switch allocator
- wire [PV-1 : 0] first_arbiter_granted_ivc_all;
- wire [PV-1 : 0] ivc_request_masked_all;
- wire [P-1 : 0] any_cand_ovc_exsit;
- output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-
- assign nonspec_first_arbiter_granted_ivc_all = first_arbiter_granted_ivc_all;
-
- //nonspeculative switch allocator
- nonspec_sw_alloc #(
- .V(V),
- .P(P),
- .FIRST_ARBITER_EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
- .SWA_ARBITER_TYPE(SWA_ARBITER_TYPE),
- .MIN_PCK_SIZE(MIN_PCK_SIZE)
- )
- nonspeculative_sw_allocator
- (
-
- .ivc_granted_all (ivc_num_getting_sw_grant),
- .ivc_request_masked_all (ivc_request_masked_all),
- .pck_is_single_flit_all(pck_is_single_flit_all),
- .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
- .dest_port_all (dest_port_all),
- .granted_dest_port_all (granted_dest_port_all),
- .first_arbiter_granted_ivc_all (first_arbiter_granted_ivc_all),
- //.first_arbiter_granted_port_all (first_arbiter_granted_port_all),
- .any_ivc_granted_all (any_ivc_sw_request_granted_all),
- .any_ovc_granted_all (any_ovc_granted_in_outport_all),
- .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
- .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
- .clk (clk),
- .reset (reset)
-
- );
-
- wire [V-1 : 0] masked_non_assigned_request [PV-1 : 0] ;
- wire [PV-1 : 0] masked_assigned_request;
- wire [PV-1 : 0] assigned_ovc_request_all;
- wire [VV-1 : 0] masked_non_assigned_request_per_port [P-1 : 0] ;
- wire [V-1 : 0] first_arbiter_granted_ivc_per_port[P-1 : 0] ;
- wire [V-1 : 0] candidate_ovc_local_num [P-1 : 0] ;
- wire [V-1 : 0] first_arbiter_ovc_granted [P-1:0];
- wire [P_1-1 : 0] granted_dest_port_per_port [P-1 : 0];
- wire [VP_1-1 : 0] cand_ovc_granted [P-1 : 0];
- wire [P_1-1 : 0] ovc_allocated_all_gen [PV-1 : 0];
- wire [V-1 : 0] granted_ovc_local_num_per_port [P-1 : 0];
- wire [V-1 : 0] ivc_local_num_getting_ovc_grant[P-1 : 0];
- wire [V : 0] summ_in [PV-1 : 0];
-
-
- assign assigned_ovc_request_all = ivc_request_all & ovc_is_assigned_all;
-
- genvar i,j;
- generate
-
- // IVC loop
- for(i=0;i< PV;i=i+1) begin :total_vc_loop
-
- // mask unavailable ovc from requests
- assign masked_non_assigned_request [i] = masked_ovc_request_all [(i+1)*V-1 : i*V ];
- assign masked_assigned_request [i] = assigned_ovc_not_full_all[i] & assigned_ovc_request_all[i];
-
- // summing assigned and non-assigned VC requests
- assign summ_in[i] ={masked_non_assigned_request [i],masked_assigned_request [i]};
- assign ivc_request_masked_all[i] = | summ_in[i];
-
- end//for
-
-
- for(i=0;i< P;i=i+1) begin :port_loop3
- for(j=0;j< V;j=j+1) begin :vc_loop
- //merge masked_candidate_ovc in each port
- assign masked_non_assigned_request_per_port[i][(j+1)*V-1 : j*V] = masked_non_assigned_request [i*V+j];
- end//for j
-
- assign first_arbiter_granted_ivc_per_port[i]=first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V];
-
- assign granted_dest_port_per_port[i]=granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
-
-
- onehot_mux_1D #(
- .W (V),
- .N (V)
- )
- multiplexer2
- (
- .in (masked_non_assigned_request_per_port [i]),
- .out (candidate_ovc_local_num [i]),
- .sel (first_arbiter_granted_ivc_per_port [i])
-
- );
-
-
- assign any_cand_ovc_exsit[i] = | candidate_ovc_local_num [i];
-
- //first level arbiter to candidate only one OVC
- arbiter #(
- .ARBITER_WIDTH (V)
- )
- first_arbiter
- (
- .clk (clk),
- .reset (reset),
- .request (candidate_ovc_local_num[i]),
- .grant (first_arbiter_ovc_granted[i]),
- .any_grant ( )
- );
-
-
- //demultiplexer
- one_hot_demux #(
- .IN_WIDTH (V),
- .SEL_WIDTH (P_1)
- )
- demux1
- (
- .demux_sel (granted_dest_port_per_port [i]),//selectore
- .demux_in (first_arbiter_ovc_granted[i]),//repeated
- .demux_out (cand_ovc_granted [i])
- );
-
-
- assign granted_ovc_local_num_per_port [i]=(any_ivc_sw_request_granted_all[i] )? first_arbiter_ovc_granted[i] : {V{1'b0}};
- assign ivc_local_num_getting_ovc_grant [i]= (any_ivc_sw_request_granted_all[i] & any_cand_ovc_exsit[i])? first_arbiter_granted_ivc_per_port [i] : {V{1'b0}};
- assign ivc_num_getting_ovc_grant [(i+1)*V-1 : i*V] = ivc_local_num_getting_ovc_grant[i];
- for(j=0;jj) begin: hh
- assign ovc_allocated_all_gen[i][j] = cand_ovc_granted[j][i-V];
-
- end
- end//j
-
- assign ovc_allocated_all [i] = |ovc_allocated_all_gen[i];
-
- end//i
-
- endgenerate
-
-
-endmodule
-
-
-/********************************************
-*
-* nonspeculative switch allocator
-*
-******************************************/
-
-module nonspec_sw_alloc #(
- parameter V = 4,
- parameter P = 5,
- parameter FIRST_ARBITER_EXT_P_EN = 1,
- parameter SWA_ARBITER_TYPE = "WRRA",
- parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
- parameter SELF_LOOP_EN="NO"
-
-)(
-
- ivc_granted_all,
- ivc_request_masked_all,
- pck_is_single_flit_all,
- granted_dst_is_from_a_single_flit_pck,
- dest_port_all,
- granted_dest_port_all,
- first_arbiter_granted_ivc_all,
- //first_arbiter_granted_port_all,
- any_ivc_granted_all,
- any_ovc_granted_all,
- vc_weight_is_consumed_all,
- iport_weight_is_consumed_all,
- clk,
- reset
-
-);
-
- localparam
- P_1 = (SELF_LOOP_EN== "NO") ? P-1 : P,
- PV = V * P,
- VP_1 = V * P_1,
- PP_1 = P_1 * P,
- PVP_1 = PV * P_1,
- PP = P*P;
-
-
- output [PV-1 : 0] ivc_granted_all;
- output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
- input [PV-1 : 0] ivc_request_masked_all;
- input [PV-1 : 0] pck_is_single_flit_all;
- input [PVP_1-1 : 0] dest_port_all;
- output [PP_1-1 : 0] granted_dest_port_all;
- output [PV-1 : 0] first_arbiter_granted_ivc_all;
- //output [PP_1-1 : 0] first_arbiter_granted_port_all;
- output [P-1 : 0] any_ivc_granted_all; //any ivc is granted in input port [i]
- output [P-1 : 0] any_ovc_granted_all; //any ovc is granted in output port [i]
- input clk, reset;
- input [PV-1 : 0] vc_weight_is_consumed_all;
- input [P-1: 0] iport_weight_is_consumed_all;
-
- //separte input per port
- wire [V-1 : 0] ivc_granted [P-1 : 0];
- wire [V-1 : 0] pck_is_single_flit [P-1 : 0];
- wire [VP_1-1 : 0] dest_port_ivc [P-1 : 0];
- wire [P_1-1 : 0] granted_dest_port [P-1 : 0];
- wire [P_1-1 : 0] single_flit_granted_dst [P-1 : 0];
- wire [PP-1 : 0] single_flit_granted_dst_all;
-
- // internal wires
- wire [V-1 : 0] ivc_masked [P-1 : 0];//output of mask and
- wire [V-1 : 0] first_arbiter_grant [P-1 : 0];//output of first arbiter
- wire [P-1 : 0] single_flit_pck_local_grant;
- wire [P_1-1 : 0] dest_port [P-1 : 0];//output of multiplexer
- wire [P_1-1 : 0] second_arbiter_request [P-1 : 0];
- wire [P_1-1 : 0] second_arbiter_grant [P-1 : 0];
- wire [P_1-1 : 0] second_arbiter_weight_consumed [P-1 : 0];
- wire [V-1 : 0] vc_weight_is_consumed [P-1 : 0];
- wire [P-1 :0] winner_weight_consumed;
-
- genvar i,j;
- generate
-
- for(i=0;i< P;i=i+1) begin :port_loop
- //assign in/out to the port based wires
- //output
- assign ivc_granted_all [(i+1)*V-1 : i*V] = ivc_granted [i];
- assign granted_dest_port_all [(i+1)*P_1-1 : i*P_1] = granted_dest_port[i];
- assign first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]= first_arbiter_grant[i];
- //input
- assign ivc_masked[i] = ivc_request_masked_all [(i+1)*V-1 : i*V];
-
- assign dest_port_ivc[i] = dest_port_all [(i+1)*VP_1-1 : i*VP_1];
- assign vc_weight_is_consumed[i] = vc_weight_is_consumed_all [(i+1)*V-1 : i*V];
-
- //first level arbiter
- swa_input_port_arbiter #(
- .ARBITER_WIDTH(V),
- .EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
- .ARBITER_TYPE(SWA_ARBITER_TYPE)
- )
- input_arbiter
- (
- .ext_pr_en_i(any_ivc_granted_all[i]),
- .request(ivc_masked [i]),
- .grant(first_arbiter_grant[i]),
- .any_grant( ),
- .clk(clk),
- .reset(reset),
- .vc_weight_is_consumed(vc_weight_is_consumed[i]),
- .winner_weight_consumed(winner_weight_consumed[i])
- );
-
-
-
- //destination port multiplexer
- onehot_mux_1D #(
- .W (P_1),
- .N (V)
- )
- multiplexer
- (
- .in (dest_port_ivc [i]),
- .out (dest_port [i]),
- .sel(first_arbiter_grant[i])
-
- );
- if(MIN_PCK_SIZE == 1) begin :single_flit_supported
- //single_flit req multiplexer
- assign pck_is_single_flit[i] = pck_is_single_flit_all [(i+1)*V-1 : i*V];
- onehot_mux_1D #(
- .W (1),
- .N (V)
- )
- multiplexer2
- (
- .in (pck_is_single_flit [i]),
- .out (single_flit_pck_local_grant[i]),
- .sel (first_arbiter_grant[i])
-
- );
-
- assign single_flit_granted_dst[i] = (single_flit_pck_local_grant[i])? granted_dest_port[i] : {P_1{1'b0}};
-
- if (SELF_LOOP_EN == "NO") begin :nslp
- add_sw_loc_one_hot #(
- .P(P),
- .SW_LOC(i)
- )
- add_sw_loc
- (
- .destport_in(single_flit_granted_dst[i]),
- .destport_out(single_flit_granted_dst_all[(i+1)*P-1 : i*P])
- );
- end else begin :slp
- assign single_flit_granted_dst_all[(i+1)*P-1 : i*P] = single_flit_granted_dst[i];
- end
-
- end else begin : single_flit_notsupported
- assign single_flit_pck_local_grant[i] = 1'bx;
- assign single_flit_granted_dst[i] = {P_1{1'bx}};
- assign single_flit_granted_dst_all[(i+1)*P-1 : i*P]={P{1'b0}};
- end
- //second arbiter input/output generate
-
-
- for(j=0;jj)begin: hh
- assign second_arbiter_request[i][j] = dest_port [j][i-1] ;
- //assign second_arbiter_weight_consumed[i][j] =winner_weight_consumed[j];
- assign second_arbiter_weight_consumed[i][j] =iport_weight_is_consumed_all[j];
- assign granted_dest_port[j][i-1] = second_arbiter_grant [i][j] ;
- end
- //if(i==j) wires are left disconnected
- end else begin :slp
- assign second_arbiter_request[i][j] = dest_port[j][i];
- assign second_arbiter_weight_consumed[i][j] =iport_weight_is_consumed_all[j] ;
- assign granted_dest_port[j][i] = second_arbiter_grant [i][j] ;
- end
- end
-
-
- //second level arbiter
- swa_output_port_arbiter #(
- .ARBITER_WIDTH(P_1),
- .ARBITER_TYPE(SWA_ARBITER_TYPE) // RRA, WRRA
- )
- output_arbiter
- (
- .weight_consumed(second_arbiter_weight_consumed[i]), // only used for WRRA
- .clk(clk),
- .reset(reset),
- .request(second_arbiter_request [i]),
- .grant(second_arbiter_grant [i]),
- .any_grant(any_ovc_granted_all [i])
- );
-
-
- //any ivc
- assign any_ivc_granted_all[i] = | granted_dest_port[i];
- assign ivc_granted[i] = (any_ivc_granted_all[i]) ? first_arbiter_grant[i] : {V{1'b0}};
-
-
- end//for
- endgenerate
-
-
- custom_or #(
- .IN_NUM(P),
- .OUT_WIDTH(P)
- )
- or_dst
- (
- .or_in(single_flit_granted_dst_all),
- .or_out(granted_dst_is_from_a_single_flit_pck)
- );
-
-endmodule
-
-
-
-/*******************
-* swa_input_port_arbiter
-*
-********************/
-
-
-module swa_input_port_arbiter #(
- parameter ARBITER_WIDTH =4,
- parameter EXT_P_EN = 1,
- parameter ARBITER_TYPE = "WRRA"// RRA, WRRA
-
-)(
- ext_pr_en_i, // it is used only if the EXT_P_EN is 1
- clk,
- reset,
- request,
- grant,
- any_grant,
- vc_weight_is_consumed, // only for WRRA
- winner_weight_consumed // only for WRRA
-);
-
-
-
-
-
- input ext_pr_en_i;
- input [ARBITER_WIDTH-1 : 0] request;
- output[ARBITER_WIDTH-1 : 0] grant;
- output any_grant;
- input clk;
- input reset;
- input [ARBITER_WIDTH-1 : 0] vc_weight_is_consumed;
- output winner_weight_consumed;
-
-
- generate
- /* verilator lint_off WIDTH */
- if(ARBITER_TYPE != "RRA") begin : wrra_m
- /* verilator lint_on WIDTH */
-
- // one hot mux
- onehot_mux_1D #(
- .W(1),
- .N(ARBITER_WIDTH)
- )
- mux
- (
- .in(vc_weight_is_consumed),
- .out(winner_weight_consumed),
- .sel(grant)
- );
-
- wire priority_en = (EXT_P_EN == 1) ? ext_pr_en_i & winner_weight_consumed : winner_weight_consumed;
-
- //round robin arbiter with external priority
-
- arbiter_priority_en #(
- .ARBITER_WIDTH(ARBITER_WIDTH)
- )
- rra
- (
- .request(request),
- .grant(grant),
- .any_grant(any_grant),
- .clk(clk),
- .reset(reset),
- .priority_en(priority_en)
- );
-
- end else begin : rra_m //RRA
- assign winner_weight_consumed = 1'bx;
- if(EXT_P_EN==1) begin : arbiter_ext_en
-
- arbiter_priority_en #(
- .ARBITER_WIDTH (ARBITER_WIDTH)
- )
- arb
- (
- .clk (clk),
- .reset (reset),
- .request (request),
- .grant (grant),
- .any_grant (any_grant ),
- .priority_en (ext_pr_en_i)
- );
-
- end else begin: first_lvl_arbiter_internal_en
-
- arbiter #(
- .ARBITER_WIDTH (ARBITER_WIDTH)
- )
- arb
- (
- .clk (clk),
- .reset (reset),
- .request (request),
- .grant (grant),
- .any_grant (any_grant )
- );
-
- end//else
-
- end
- endgenerate
-
-endmodule
-
-
-
-
-/*******************
-* swa_output_port_arbiter
-*
-********************/
-
-
-module swa_output_port_arbiter #(
- parameter ARBITER_WIDTH =4,
- parameter ARBITER_TYPE = "WRRA" // RRA, WRRA
-
-
-)(
- weight_consumed, // only used for WRRA
- clk,
- reset,
- request,
- grant,
- any_grant
-);
-
-
-
- input [ARBITER_WIDTH-1 : 0] request;
- output [ARBITER_WIDTH-1 : 0] grant;
- output any_grant;
- input clk;
- input reset;
- input [ARBITER_WIDTH-1 : 0] weight_consumed;
-
-
-
- generate
- /* verilator lint_off WIDTH */
- if(ARBITER_TYPE == "WRRA") begin : wrra_mine
- /* verilator lint_on WIDTH */
- // second level wrra priority is only changed if the granted request weight is consumed
- wire pr_en;
-
- onehot_mux_1D #(
- .W(1),
- .N(ARBITER_WIDTH)
- )
- multiplexer
- (
- .in(weight_consumed),
- .out(pr_en),
- .sel(grant)
-
- );
-
-
- arbiter_priority_en #(
- .ARBITER_WIDTH (ARBITER_WIDTH)
- )
- arb
- (
- .clk (clk),
- .reset (reset),
- .request (request),
- .grant (grant),
- .any_grant (any_grant ),
- .priority_en (pr_en)
- );
-
-
- /* verilator lint_off WIDTH */
- end else if(ARBITER_TYPE == "WRRA_CLASSIC") begin : wrra_classic
- /* verilator lint_on WIDTH */
- // use classic WRRA. only for compasrion with propsoed wrra
-
- wire [ARBITER_WIDTH-1 : 0] masked_req= request & ~weight_consumed;
- wire sel = |masked_req;
- wire [ARBITER_WIDTH-1 : 0] mux_req = (sel==1'b1)? masked_req : request;
-
- arbiter #(
- .ARBITER_WIDTH (ARBITER_WIDTH )
- )
- arb
- (
- .clk (clk),
- .reset (reset),
- .request (mux_req),
- .grant (grant),
- .any_grant (any_grant )
- );
-
-
-
- end else begin : rra_m
-
- arbiter #(
- .ARBITER_WIDTH (ARBITER_WIDTH )
- )
- arb
- (
- .clk (clk),
- .reset (reset),
- .request (request),
- .grant (grant),
- .any_grant (any_grant )
- );
-
- end
- endgenerate
-endmodule
-
comb_nonspec.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: inout_ports.sv
===================================================================
--- inout_ports.sv (revision 54)
+++ inout_ports.sv (revision 55)
@@ -316,6 +316,7 @@
the_ssa
(
.ivc_info(ivc_info),
+ .ovc_info(ovc_info),
.flit_in_wr_all(flit_in_wr_all),
.flit_in_all(flit_in_all),
.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
Index: output_ports.sv
===================================================================
--- output_ports.sv (revision 54)
+++ output_ports.sv (revision 55)
@@ -112,6 +112,8 @@
input smart_ctrl_t smart_ctrl_in [P-1: 0];
input [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
+ wire [PVV-1 : 0] ssa_granted_ovc_num_all;
+
logic [PV-1 : 0] ovc_status;
logic [PV-1 : 0] ovc_status_next;
wire [PV-1 : 0] assigned_ovc_is_full_all;
@@ -196,7 +198,7 @@
wire [PV-1 : 0] non_smart_ovc_allocated_all;
generate
for(i=0;i
/pronoc_pkg.sv
62,7 → 62,7
/* verilator lint_off WIDTH */ |
localparam |
DISTw = (TOPOLOGY=="FATTREE" || TOPOLOGY=="TREE" ) ? log2(2*L+1): log2(NR+1), |
OVC_ALLOC_MODE= (B<=4 && SSA_EN=="NO")? 1'b1 : 1'b0; |
OVC_ALLOC_MODE= ((V==1 || B<=4) )? 1'b1 : 1'b0; |
/* verilator lint_on WIDTH */ |
|
// 0: The new ovc is allocated only if its not nearly full. Results in a simpler sw_mask_gen logic |
/router_two_stage.sv
551,6 → 551,55
*/ |
|
|
//TRACE_DUMP_PER is defined in pronoc_def file |
|
|
`ifdef TRACE_DUMP_PER_NoC |
pronoc_trace_dump #( |
.P(P), |
.TRACE_DUMP_PER("NOC"), //NOC, ROUTER, PORT |
.CYCLE_REPORT(0) // 1 : enable, 0 : disable |
|
)dump1 |
( |
.current_r_id(current_r_id), |
.chan_in(chan_in), |
.chan_out(chan_out), |
.clk(clk) |
); |
`endif |
`ifdef TRACE_DUMP_PER_ROUTER |
pronoc_trace_dump #( |
.P(P), |
.TRACE_DUMP_PER("ROUTER"), //NOC, ROUTER, PORT |
.CYCLE_REPORT(0) // 1 : enable, 0 : disable |
|
)dump2 |
( |
.current_r_id(current_r_id), |
.chan_in(chan_in), |
.chan_out(chan_out), |
.clk(clk) |
); |
`endif |
`ifdef TRACE_DUMP_PER_PORT |
pronoc_trace_dump #( |
.P(P), |
.TRACE_DUMP_PER("PORT"), //NOC, ROUTER, PORT |
.CYCLE_REPORT(0) // 1 : enable, 0 : disable |
|
)dump3 |
( |
.current_r_id(current_r_id), |
.chan_in(chan_in), |
.chan_out(chan_out), |
.clk(clk) |
); |
`endif |
|
|
|
|
//synopsys translate_on |
//synthesis translate_on |
|
559,6 → 608,8
|
|
|
|
|
module credit_release_gen |
import pronoc_pkg::*; |
#( |
600,3 → 651,108
|
endmodule |
|
|
|
|
//synthesis translate_off |
module pronoc_trace_dump |
import pronoc_pkg::*; |
#( |
parameter P = 6, |
parameter TRACE_DUMP_PER= "ROUTER", //NOC, ROUTER, PORT |
parameter CYCLE_REPORT=0 // 1 : enable, 0 : disable |
|
)( |
current_r_id, |
chan_in, |
chan_out, |
clk |
); |
|
input [31:0] current_r_id; |
input flit_chanel_t chan_in [P-1 : 0]; |
input flit_chanel_t chan_out [P-1 : 0]; |
input clk; |
|
pronoc_trace_dump_sub #( |
.P(P), |
.TRACE_DUMP_PER(TRACE_DUMP_PER), //NOC, ROUTER, PORT |
.DIRECTION("in"), // in,out |
.CYCLE_REPORT(CYCLE_REPORT) // 1 : enable, 0 : disable |
|
)dump_in |
( |
.current_r_id(current_r_id), |
.chan_in(chan_in), |
.clk(clk) |
); |
|
pronoc_trace_dump_sub #( |
.P(P), |
.TRACE_DUMP_PER(TRACE_DUMP_PER), //NOC, ROUTER, PORT |
.DIRECTION("out"), // in,out |
.CYCLE_REPORT(CYCLE_REPORT) // 1 : enable, 0 : disable |
|
)dump_out |
( |
.current_r_id(current_r_id), |
.chan_in(chan_out), |
.clk(clk) |
); |
endmodule |
|
module pronoc_trace_dump_sub |
import pronoc_pkg::*; |
#( |
parameter P = 6, |
parameter TRACE_DUMP_PER= "ROUTER", //NOC, ROUTER, PORT |
parameter DIRECTION="in", // in,out |
parameter CYCLE_REPORT=0 // 1 : enable, 0 : disable |
|
)( |
current_r_id, |
chan_in, |
clk |
); |
|
input [31:0] current_r_id; |
input flit_chanel_t chan_in [P-1 : 0]; |
input clk; |
|
integer out; |
string fname [P-1 : 0]; |
|
genvar p; |
generate |
for (p=0;p<P;p++)begin |
initial begin |
/* verilator lint_off WIDTH */ |
if(TRACE_DUMP_PER == "PORT" ) fname[p] = $sformatf("trace_dump_R%0d_P%0d.out",current_r_id,p); |
if(TRACE_DUMP_PER == "ROUTER") fname[p] = $sformatf("trace_dump_R%0d.out",current_r_id); |
if(TRACE_DUMP_PER == "NOC" ) fname[p] = $sformatf("trace_dump.out",current_r_id,p); |
/* verilator lint_on WIDTH */ |
out = $fopen(fname[p],"w"); |
$fclose(out); |
end |
|
|
always @(posedge clk) begin |
if(chan_in[p].flit_wr) begin |
out = $fopen(fname[p],"a"); |
if(CYCLE_REPORT) $fwrite(out,"%t:",$time); |
$fwrite(out, "Flit %s: Port %0d, Payload: %h\n",DIRECTION, p, chan_in[p].flit); |
$fclose(out); |
end |
if(chan_in[p].credit>0) begin |
out = $fopen(fname[p],"a"); |
if(CYCLE_REPORT) $fwrite(out,"%t:",$time); |
$fwrite(out, "credit %s:%h Port %0d\n",DIRECTION, chan_in[p].credit,p); |
$fclose(out); |
end |
end |
|
end |
endgenerate |
endmodule |
//synthesis translate_on |
|
/ss_allocator.sv
52,6 → 52,7
// assigned_ovc_num_all, |
// ovc_is_assigned_all, |
ivc_info, |
ovc_info, |
ssa_ctrl_o |
); |
|
88,6 → 89,7
|
input reset,clk; |
input ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; |
input ovc_info_t ovc_info [P-1 : 0][V-1 : 0]; |
output ssa_ctrl_t ssa_ctrl_o [P-1 : 0]; |
|
|
114,6 → 116,7
wire [PVDSTPw-1 : 0] dest_port_encoded_all; |
wire [PVV-1 : 0] assigned_ovc_num_all; |
wire [PV-1 : 0] ovc_is_assigned_all; |
wire [MAX_P-1 : 0] destport_one_hot [PV-1 : 0]; |
|
genvar i; |
// there is no ssa for local port in 5 and 3 port routers |
124,11 → 127,14
localparam SS_PORT = strieght_port (P,C_PORT); |
|
assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req; |
assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full; |
assign assigned_ovc_not_full_all[i] = ~ovc_info[SS_PORT][i%V].full; |
//assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full; |
|
assign dest_port_encoded_all [(i+1)*DSTPw-1 : i*DSTPw] = ivc_info[C_PORT][i%V].dest_port_encoded; |
assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[C_PORT][i%V].assigned_ovc_num; |
assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned; |
|
assign destport_one_hot[i] = ivc_info[C_PORT][i%V].destport_one_hot; |
|
|
if (SS_PORT == DISABLED)begin : no_prefrable |
184,6 → 190,7
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant_all[i]), |
.ivc_reset(ivc_reset_all[i]), |
.single_flit_pck(single_flit_pck_all[i]), |
.destport_one_hot(destport_one_hot[i]), |
.decreased_credit_in_ss_ovc(decreased_credit_in_ss_ovc[i]) |
//synthesis translate_off |
//synopsys translate_off |
265,6 → 272,7
ovc_allocated, |
decreased_credit_in_ss_ovc, |
single_flit_pck, |
destport_one_hot, |
ivc_reset |
//synthesis translate_off |
//synopsys translate_off |
296,6 → 304,7
input [DSTPw-1 : 0] destport_encoded;//exsited packet destination port |
input assigned_to_ssovc; |
input ovc_is_assigned; |
input [MAX_P-1 : 0] destport_one_hot; |
|
output reg [V-1 : 0] granted_ovc_num; |
output ivc_num_getting_sw_grant; |
339,6 → 348,7
|
|
wire condition_1_2_valid; |
wire [DAw-1 : 0] dest_e_addr_in; |
|
extract_header_flit_info #( |
.DATA_w(0) |
350,7 → 360,7
.class_o(), |
.destport_o(destport_in_encoded), |
.src_e_addr_o( ), |
.dest_e_addr_o( ), |
.dest_e_addr_o(dest_e_addr_in ), |
.vc_num_o(vc_num_in), |
.hdr_flit_wr_o( ), |
.hdr_flg_o(hdr_flg), |
369,13 → 379,9
//check destination port is ss |
wire ss_port_hdr_flit, ss_port_nonhdr_flit; |
|
ssa_check_destport #( |
.TOPOLOGY(TOPOLOGY), |
.ROUTE_TYPE(ROUTE_TYPE), |
ssa_check_destport #( |
.SW_LOC(SW_LOC), |
.P(P), |
.DEBUG_EN(DEBUG_EN), |
.DSTPw(DSTPw), |
.P(P), |
.SS_PORT(SS_PORT) |
) |
check_destport |
382,7 → 388,10
( |
.destport_encoded(destport_encoded), |
.destport_in_encoded(destport_in_encoded), |
.destport_one_hot(destport_one_hot), |
.ss_port_hdr_flit(ss_port_hdr_flit), |
.dest_e_addr_in(dest_e_addr_in), |
|
.ss_port_nonhdr_flit(ss_port_nonhdr_flit) |
//synthesis translate_off |
//synopsys translate_off |
446,19 → 455,20
|
|
|
module ssa_check_destport #( |
parameter TOPOLOGY = "MESH", |
parameter ROUTE_TYPE="DETERMINISTIC", |
module ssa_check_destport |
import pronoc_pkg::*; |
#( |
parameter SW_LOC = 0, |
parameter P=5, |
parameter DEBUG_EN = 0, |
parameter DSTPw = P-1, |
parameter P=5, |
parameter SS_PORT=0 |
)( |
destport_encoded, //non header flit dest port |
destport_in_encoded, // header flit packet dest port |
ss_port_hdr_flit, // asserted if the header incomming flit goes to ss port |
ss_port_nonhdr_flit // assert if the body or tail incomming flit goes to ss port |
ss_port_nonhdr_flit, // assert if the body or tail incomming flit goes to ss port |
dest_e_addr_in, |
destport_one_hot |
|
//synthesis translate_off |
//synopsys translate_off |
,clk, |
475,6 → 485,8
//synthesis translate_on |
|
input [DSTPw-1 : 0] destport_encoded, destport_in_encoded; |
input [MAX_P-1 : 0] destport_one_hot; // buffered flit destination port |
input [DAw-1 : 0] dest_e_addr_in; |
output ss_port_hdr_flit, ss_port_nonhdr_flit; |
|
generate |
494,7 → 506,7
.ss_port_nonhdr_flit(ss_port_nonhdr_flit) |
); |
/* verilator lint_off WIDTH */ |
end else if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "FMESH") begin : mesh |
end else if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" ) begin : mesh |
/* verilator lint_on WIDTH */ |
|
mesh_torus_ssa_check_destport #( |
520,6 → 532,61
//synthesis translate_on |
|
); |
/* verilator lint_off WIDTH */ |
end else if (TOPOLOGY == "FMESH") begin :fmesh |
/* verilator lint_on WIDTH */ |
localparam |
ELw = log2(T3), |
Pw = log2(P), |
PLw = (TOPOLOGY == "FMESH") ? Pw : ELw; |
|
wire [Pw-1 : 0] endp_p_in; |
wire [MAX_P-1 : 0] destport_one_hot_in; |
|
fmesh_endp_addr_decode #( |
.T1(T1), |
.T2(T2), |
.T3(T3), |
.EAw(EAw) |
) |
endp_addr_decode |
( |
.e_addr(dest_e_addr_in), |
.ex(), |
.ey(), |
.ep(endp_p_in), |
.valid() |
); |
|
destp_generator #( |
.TOPOLOGY(TOPOLOGY), |
.ROUTE_NAME(ROUTE_NAME), |
.ROUTE_TYPE(ROUTE_TYPE), |
.T1(T1), |
.NL(T3), |
.P(P), |
.DSTPw(DSTPw), |
.PLw(PLw), |
.PPSw(PPSw), |
.SELF_LOOP_EN (SELF_LOOP_EN), |
.SW_LOC(SW_LOC), |
.CAST_TYPE(CAST_TYPE) |
) |
decoder |
( |
.destport_one_hot (destport_one_hot_in), |
.dest_port_encoded(destport_in_encoded), |
.dest_port_out( ), |
.endp_localp_num(endp_p_in), |
.swap_port_presel(1'b0), |
.port_pre_sel({PPSw{1'b0}}), |
.odd_column(1'b0) |
); |
|
|
assign ss_port_nonhdr_flit = destport_one_hot [SS_PORT]; |
assign ss_port_hdr_flit = destport_one_hot_in [SS_PORT]; |
|
end else begin : line |
line_ring_ssa_check_destport #( |
.ROUTE_TYPE(ROUTE_TYPE), |
/traffic_gen_top.sv
4,7 → 4,7
import pronoc_pkg::*; |
#( |
parameter MAX_RATIO = 1000, |
parameter ENDP_ID = 10 |
parameter ENDP_ID = 100000 |
) |
( |
|