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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

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  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/script
    from Rev 16 to Rev 28
    ↔ Reverse comparison
  •

Rev 16 → Rev 28

/foo
foo Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: Makefile =================================================================== --- Makefile (revision 16) +++ Makefile (revision 28) @@ -1,26 +1,51 @@ -VERILATED_CPP = /usr/share/verilator/include/verilated.cpp -VERILATED_INC = -I/usr/share/verilator/include +# -*- Makefile -*- +#***************************************************************************** +# +# DESCRIPTION: Verilator Example: Makefile for inside object directory +# +# This is executed in the object directory, and called by ../Makefile +# +# Copyright 2003-2014 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# +#***************************************************************************** + +default: sim + MUDULB = Vnoc MUDULA = Vrouter MUDULC = Vtraffic -sim: - #Compile your test code - g++ -I. -L. $(VERILATED_INC) -o testbench testbench.cpp -l$(MUDULA) -l$(MUDULB) -l$(MUDULC) -Wall -O3 - - -lib: - #Create object files - g++ -c -I. $(VERILATED_INC) $(VERILATED_CPP) -O3 - g++ -c -I. $(VERILATED_INC) $(MUDULA).cpp $(MUDULA)__Syms.cpp -O3 - g++ -c -I. $(VERILATED_INC) $(MUDULB).cpp $(MUDULB)__Syms.cpp -O3 - g++ -c -I. $(VERILATED_INC) $(MUDULC).cpp $(MUDULC)__Syms.cpp -O3 - #Link object files into static library - ar rcs lib$(MUDULA).a $(MUDULA).o $(MUDULA)__Syms.o verilated.o - ar rcs lib$(MUDULB).a $(MUDULB).o $(MUDULB)__Syms.o - ar rcs lib$(MUDULC).a $(MUDULC).o $(MUDULC)__Syms.o - #Remove object files - rm *.o +include Vrouter.mk + +lib: + $(MAKE) -f $(MUDULA).mk + $(MAKE) -f $(MUDULB).mk + $(MAKE) -f $(MUDULC).mk + + +####################################################################### +# Compile flags + +CPPFLAGS += -DVL_DEBUG=1 +ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users +CPPFLAGS += -DVL_THREADED=1 +CPPFLAGS += -W -Werror -Wall +endif + +####################################################################### +# Linking final exe -- presumes have a sim_main.cpp + + +sim: testbench.o $(VK_GLOBAL_OBJS) $(MUDULB)__ALL.a $(MUDULA)__ALL.a $(MUDULC)__ALL.a + $(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o testbench $(LIBS) -Wall -O3 2>&1 | c++filt + +testbench.o: testbench.cpp $(MUDULA).h $(MUDULB).h $(MUDULC).h + clean: rm *.o *.a main + +
/parameter.sh
11,7 → 11,8
 
# NoC parameters:
V=2 # number of VC per port
P=5 # number of port per router
TOPOLOGY="MESH" #"MESH" or "TORUS"
P="(TOPOLOGY==\"RING\")? 3 : 5" # number of port per router
B=4 # buffer space :flit per VC
NX=8 # number of node in x axis
NY=8 # number of node in y axis
21,7 → 22,7
VC_REALLOCATION_TYPE="NONATOMIC" # "ATOMIC" or "NONATOMIC"
COMBINATION_TYPE="COMB_NONSPEC" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC"
FIRST_ARBITER_EXT_P_EN=0
TOPOLOGY="MESH" #"MESH" or "TORUS"
ROUTE_NAME="XY" # Routing algorithm
# mesh : "XY" , "WEST_FIRST" , "NORTH_LAST" , "NEGETIVE_FIRST" , "DUATO"
# torus: "TRANC_XY" , "TRANC_WEST_FIRST", "TRANC_NORTH_LAST", "TRANC_NEGETIVE_FIRST", "TRANC_DUATO"
28,10 → 29,12
CLASS_SETTING="{CVw{1'b1}}"
SSA_EN="NO"
ADD_PIPREG_AFTER_CROSSBAR=0
ADD_PIPREG_BEFORE_CROSSBAR=0
#simulation parameters:
C0_p=100 # the percentage of injected packets with class 0
C1_p=0
85,7 → 88,8
generate_parameter_v (){
printf " \`ifdef INCLUDE_PARAM \n\n" >> parameter.v
printf " parameter V=$V;\n" >> parameter.v
printf " parameter V=$V;\n" >> parameter.v
printf " parameter TOPOLOGY=\"$TOPOLOGY\";\n" >> parameter.v
printf " parameter P=$P;\n" >> parameter.v
printf " parameter B=$B;\n" >> parameter.v
printf " parameter NX=$NX;\n" >> parameter.v
96,7 → 100,7
printf " parameter VC_REALLOCATION_TYPE=\"$VC_REALLOCATION_TYPE\";\n" >> parameter.v
printf " parameter COMBINATION_TYPE=\"$COMBINATION_TYPE\";\n" >> parameter.v
printf " parameter FIRST_ARBITER_EXT_P_EN=$FIRST_ARBITER_EXT_P_EN;\n" >> parameter.v
printf " parameter TOPOLOGY=\"$TOPOLOGY\";\n" >> parameter.v
printf " parameter ROUTE_NAME=\"$ROUTE_NAME\";\n" >> parameter.v
printf " parameter CONGESTION_INDEX=$CONGESTION_INDEX;\n" >> parameter.v
printf " parameter C0_p=$C0_p;\n" >> parameter.v
122,10 → 126,10
printf " parameter AVC_ATOMIC_EN= $AVC_ATOMIC_EN;\n">> parameter.v
printf " parameter AVG_LATENCY_METRIC= \"$AVG_LATENCY_METRIC\";\n">> parameter.v
printf " parameter ADD_PIPREG_AFTER_CROSSBAR= $ADD_PIPREG_AFTER_CROSSBAR;\n" >> parameter.v
printf " parameter ADD_PIPREG_BEFORE_CROSSBAR= $ADD_PIPREG_BEFORE_CROSSBAR;\n" >> parameter.v
printf " parameter CVw=(C==0)? V : C * V;\n" >> parameter.v
printf " parameter [CVw-1: 0] CLASS_SETTING = $CLASS_SETTING;\n">> parameter.v
printf " parameter [V-1 : 0] ESCAP_VC_MASK=$ESCAP_VC_MASK;\n" >> parameter.v
printf " parameter [V-1 : 0] ESCAP_VC_MASK=$ESCAP_VC_MASK;\n" >> parameter.v
printf " parameter SSA_EN= \"$SSA_EN\";\n">> parameter.v
printf " \n\n \`endif " >> parameter.v
170,10 → 174,10
printf "\t #define STND_DEV_EN $STND_DEV_EN\n">> parameter.h
printf "\t #define AVG_LATENCY_METRIC \"$AVG_LATENCY_METRIC\"\n">> parameter.h
printf "\t #define ADD_PIPREG_AFTER_CROSSBAR $ADD_PIPREG_AFTER_CROSSBAR\n" >> parameter.h
printf "\t #define ADD_PIPREG_BEFORE_CROSSBAR $ADD_PIPREG_BEFORE_CROSSBAR\n" >> parameter.h
printf "\t #define CVw (C==0)? V : C * V\n" >> parameter.h
printf "\t #define CLASS_SETTING \"$CLASS_SETTING\"\n">> parameter.h
printf "\t #define ESCAP_VC_MASK $ESCAP_VC_MASK\n">> parameter.h
printf "\t #define ESCAP_VC_MASK $ESCAP_VC_MASK\n">> parameter.h
printf "\t #define SSA_EN \"$SSA_EN\"\n" >> parameter.h
printf " \n\n #endif " >> parameter.h
}
/verilator_2D_mesh.sh
115,7 → 115,6
printf " parameter ROUTE_TYPE = (ROUTE_NAME == \"XY\" || ROUTE_NAME == \"TRANC_XY\" )? \"DETERMINISTIC\" : \n" >> parameter.v
printf " (ROUTE_NAME == \"DUATO\" || ROUTE_NAME == \"TRANC_DUATO\" )? \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\"; \n" >> parameter.v
printf " parameter ADD_PIPREG_AFTER_CROSSBAR= $ADD_PIPREG_AFTER_CROSSBAR;\n" >> parameter.v
printf " parameter ADD_PIPREG_BEFORE_CROSSBAR= $ADD_PIPREG_BEFORE_CROSSBAR;\n" >> parameter.v
printf " parameter CVw=(C==0)? V : C * V;\n" >> parameter.v
printf " parameter [CVw-1: 0] CLASS_SETTING = $CLASS_SETTING;\n">> parameter.v
printf " parameter [V-1 : 0] ESCAP_VC_MASK=$ESCAP_VC_MASK;\n" >> parameter.v
156,7 → 155,6
printf "\t #define PACKET_SIZE $PACKET_SIZE\n" >> parameter.h
printf "\t #define DEBUG_EN $DEBUG_EN \n" >> parameter.h
printf "\t #define ADD_PIPREG_AFTER_CROSSBAR $ADD_PIPREG_AFTER_CROSSBAR\n" >> parameter.h
printf "\t #define ADD_PIPREG_BEFORE_CROSSBAR $ADD_PIPREG_BEFORE_CROSSBAR\n" >> parameter.h
printf "\t #define CVw (C==0)? V : C * V\n" >> parameter.h
printf "\t #define CLASS_SETTING \"$CLASS_SETTING\"\n">> parameter.h
printf "\t #define ESCAP_VC_MASK $ESCAP_VC_MASK\n">> parameter.h
/verilator_compile_hw.sh
33,9 → 33,9
cd processed_rtl
 
verilator --cc router_verilator.v --profile-cfuncs --prefix "Vrouter" -O3
verilator --cc noc_connection.sv --prefix "Vnoc" -O3
verilator --cc --profile-cfuncs traffic_gen_verilator.v --prefix "Vtraffic" -O3
verilator --cc router_verilator.v --profile-cfuncs --prefix "Vrouter" -O3 -CFLAGS -O3
verilator --cc noc_connection.sv --prefix "Vnoc" -O3 -CFLAGS -O3
verilator --cc --profile-cfuncs traffic_gen_verilator.v --prefix "Vtraffic" -O3 -CFLAGS -O3
 
 
cp $script_path/Makefile obj_dir/
/verilator_multiple/verilator_ssa.sh
0,0 → 1,304
#!/bin/sh
set -e
# Any subsequent commands which fail will cause the shell script to exit immediately
 
my_dir="$(dirname "$0")"
source "$my_dir/../parameter.sh"
 
 
cd ..
script_path=$(pwd)
path=$script_path/..
comp_path=$path/../mpsoc_work/verilator
work_path=$comp_path/work
bin_path=$work_path/bin
multiple_path=$work_path/ssa4
data_path=$multiple_path/data
plot_path=$multiple_path/plot
src_c_path=$path/src_c
plot_c_path=$src_c_path/plot
 
rm -Rf $multiple_path
mkdir -p $data_path
mkdir -p $plot_path
 
#cp $path/src_c/plot/plot $multiple_path/plot_bin
 
 
 
V=4 # number of VC per port
B=5 # buffer space :flit per VC
NX=8 # number of node in x axis
NY=8 # number of node in y axis
C=4 # number of flit class
COMBINATION_TYPE="COMB_NONSPEC" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC"
FIRST_ARBITER_EXT_P_EN=0
ROUTE_NAME="XY"
CLASS_SETTING="16'b111111111111111"
#simulation parameters:
C0_p=25 # the percentage of injected packets with class 0
C1_p=25
C2_p=25
C3_p=25
# Simulation parameters:
#Hotspot Traffic setting
HOTSPOT_PERCENTAGE=3 #maximum 20
HOTSOPT_NUM=4 #maximum 5
HOTSPOT_CORE_1=$(CORE_NUM 2 2)
HOTSPOT_CORE_2=$(CORE_NUM 2 6)
HOTSPOT_CORE_3=$(CORE_NUM 6 2)
HOTSPOT_CORE_4=$(CORE_NUM 6 6)
MAX_PCK_NUM=256000
MAX_SIM_CLKs=100000
MAX_PCK_SIZ=10 # maximum flit number in a single packet
ESCAP_VC_MASK="4'b0001" # mask scape vc
DEBUG_EN=1
CONGESTION_INDEX=3 # 0: packets are routed to the ports with more available VCs
# 1: packets are routed to the ports with more available credits
# 2: packets are routed to the ports connected to the routers with less active ivc requests
# 3: packets are routed to the ports connected to the routers with less active ivc requests that are not granted
 
 
 
 
#
AVC_ATOMIC_EN=0
STND_DEV_EN=0 # 1: generate standard devision
TIMSTMP_FIFO_NUM=8
 
 
 
generate_plot_command(){
 
rm -f plot_command.h
 
cat > plot_command.h << EOF
#ifndef PLOT_COMMAND_H
#define PLOT_COMMAND_H
 
char * commandsForGnuplot[] = {
"set terminal postscript eps enhanced color font 'Helvetica,15'",
"set output 'temp.eps' ",
"set style line 1 lc rgb \"red\" lt 1 lw 2 pt 4 ps 1.5",
"set style line 2 lc rgb \"blue\" lt 1 lw 2 pt 6 ps 1.5",
"set style line 3 lc rgb \"green\" lt 1 lw 2 pt 10 ps 1.5",
"set style line 4 lc rgb '#8B008B' lt 1 lw 2 pt 14 ps 1.5",//darkmagenta
"set style line 5 lc rgb '#B8860B' lt 1 lw 2 pt 2 ps 1.5", //darkgoldenrod
"set style line 6 lc rgb \"gold\" lt 1 lw 2 pt 3 ps 1.5",
"set style line 7 lc rgb '#FF8C00' lt 1 lw 2 pt 10 ps 1.5",//darkorange
"set style line 8 lc rgb \"black\" lt 1 lw 2 pt 1 ps 1.5",
"set style line 9 lc rgb \"spring-green\" lt 1 lw 2 pt 8 ps 1.5",
"set style line 10 lc rgb \"yellow4\" lt 1 lw 2 pt 0 ps 1.5",
"set yrange [0:45]",
"set xrange [0:]",
0
};
 
#endif
 
EOF
 
mv -f plot_command.h $plot_c_path/plot_command.h
cd $plot_c_path
make
cp $plot_c_path/plot $multiple_path/plot_bin
cd $script_path
 
}
 
 
 
 
################
#
# regenerate_NoC
#
################
regenerate_NoC() {
generate_parameter_v
mv -f parameter.v ../src_verilator/
#verilate the NoC and make the library files
#################################################################3
./verilator_compile_hw.sh
 
# compile the testbench file
generate_parameter_h
mv -f parameter.h ../src_verilator/
 
./verilator_compile_sw.sh
cp $bin_path/testbench $multiple_path/$testbench_name
}
 
 
################
#
# merg_files
#
################
merg_files(){
if [ $STND_DEV_EN -eq 1 ]
then
 
target="_std"
else
target="_all"
 
fi
 
data_file=$data_path/${plot_name}${target}".txt"
plot_file=$plot_path/${plot_name}${target}".eps"
printf "#name:"$CURVE_NAME"\n" >> $data_file
cat ${testbench_name}${target}".txt" >> $data_file
printf "\n\n" >> $data_file
./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left"
if [ $C -gt 1 ]
then
data_file=$data_path/$plot_name"_c0.txt"
plot_file=$plot_path/$plot_name"_c0.eps"
printf "#name:"$CURVE_NAME"\n" >> $data_file
cat $testbench_name"_c0.txt" >> $data_file
printf "\n\n" >> $data_file
./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left"
data_file=$data_path/$plot_name"_c1.txt"
plot_file=$plot_path/$plot_name"_c1.eps"
printf "#name:"$CURVE_NAME"\n" >> $data_file
cat $testbench_name"_c1.txt" >> $data_file
printf "\n\n" >> $data_file
./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left"
fi
rm $testbench_name*
}
 
gen_testbench_name(){
testbench_name=$routename"_"$SSA_EN
}
 
gen_plot_name(){
plot_name=$routename"_"$TRAFFIC"_"$PACKET_SIZE
}
 
 
 
 
 
 
################
#
# run_sim
#
################
run_sim(){
 
for SSA_EN in "YES" "NO"
do
gen_testbench_name
regenerate_NoC
done
 
 
 
cd $multiple_path
for SSA_EN in "YES" "NO"
do
gen_testbench_name
CMD="./$testbench_name $testbench_name"
command $CMD &
done
# wait for all simulation to be done
wait
# merge the results in one file
VC_REALLOCATION_TYPE="NONATOMIC"
for SSA_EN in "YES" "NO"
do
gen_testbench_name
gen_plot_name
CURVE_NAME=$SSA_EN
merg_files
done # ROUTE_NAME
 
cd $script_path
}
 
generate_plot_command
 
 
 
 
for PACKET_SIZE in 4 # 6
do
for TRAFFIC in "RANDOM" # "BIT_REVERSE" "BIT_COMPLEMENT" "RANDOM" "HOTSPOT" "TRANSPOSE1" "TORNADO" #"CUSTOM"
do
run_sim
done
done #PACKET_SIZE
verilator_multiple/verilator_ssa.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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