OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

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    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/script
    from Rev 34 to Rev 38
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Rev 34 → Rev 38

verilator_multiple/verilator_sw_vc_comb.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilator_multiple/verilator_ssa.sh =================================================================== --- verilator_multiple/verilator_ssa.sh (revision 34) +++ verilator_multiple/verilator_ssa.sh (nonexistent) @@ -1,304 +0,0 @@ -#!/bin/sh -set -e -# Any subsequent commands which fail will cause the shell script to exit immediately - -my_dir="$(dirname "$0")" -source "$my_dir/../parameter.sh" - - -cd .. -script_path=$(pwd) -path=$script_path/.. -comp_path=$path/../mpsoc_work/verilator -work_path=$comp_path/work -bin_path=$work_path/bin -multiple_path=$work_path/ssa4 -data_path=$multiple_path/data -plot_path=$multiple_path/plot -src_c_path=$path/src_c -plot_c_path=$src_c_path/plot - -rm -Rf $multiple_path -mkdir -p $data_path -mkdir -p $plot_path - -#cp $path/src_c/plot/plot $multiple_path/plot_bin - - - - V=4 # number of VC per port - B=5 # buffer space :flit per VC - NX=8 # number of node in x axis - NY=8 # number of node in y axis - C=4 # number of flit class - COMBINATION_TYPE="COMB_NONSPEC" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC" - FIRST_ARBITER_EXT_P_EN=0 - ROUTE_NAME="XY" - CLASS_SETTING="16'b111111111111111" - -#simulation parameters: - C0_p=25 # the percentage of injected packets with class 0 - C1_p=25 - C2_p=25 - C3_p=25 - - - - # Simulation parameters: - - #Hotspot Traffic setting - HOTSPOT_PERCENTAGE=3 #maximum 20 - HOTSOPT_NUM=4 #maximum 5 - HOTSPOT_CORE_1=$(CORE_NUM 2 2) - HOTSPOT_CORE_2=$(CORE_NUM 2 6) - HOTSPOT_CORE_3=$(CORE_NUM 6 2) - HOTSPOT_CORE_4=$(CORE_NUM 6 6) - - - - - - MAX_PCK_NUM=256000 - MAX_SIM_CLKs=100000 - MAX_PCK_SIZ=10 # maximum flit number in a single packet - - - - - ESCAP_VC_MASK="4'b0001" # mask scape vc - DEBUG_EN=1 - - CONGESTION_INDEX=3 # 0: packets are routed to the ports with more available VCs - # 1: packets are routed to the ports with more available credits - # 2: packets are routed to the ports connected to the routers with less active ivc requests - # 3: packets are routed to the ports connected to the routers with less active ivc requests that are not granted - - - - - - -# - - AVC_ATOMIC_EN=0 - STND_DEV_EN=0 # 1: generate standard devision - TIMSTMP_FIFO_NUM=8 - - - - -generate_plot_command(){ - -rm -f plot_command.h - -cat > plot_command.h << EOF -#ifndef PLOT_COMMAND_H - #define PLOT_COMMAND_H - -char * commandsForGnuplot[] = { - "set terminal postscript eps enhanced color font 'Helvetica,15'", - "set output 'temp.eps' ", - "set style line 1 lc rgb \"red\" lt 1 lw 2 pt 4 ps 1.5", - "set style line 2 lc rgb \"blue\" lt 1 lw 2 pt 6 ps 1.5", - "set style line 3 lc rgb \"green\" lt 1 lw 2 pt 10 ps 1.5", - "set style line 4 lc rgb '#8B008B' lt 1 lw 2 pt 14 ps 1.5",//darkmagenta - "set style line 5 lc rgb '#B8860B' lt 1 lw 2 pt 2 ps 1.5", //darkgoldenrod - "set style line 6 lc rgb \"gold\" lt 1 lw 2 pt 3 ps 1.5", - "set style line 7 lc rgb '#FF8C00' lt 1 lw 2 pt 10 ps 1.5",//darkorange - "set style line 8 lc rgb \"black\" lt 1 lw 2 pt 1 ps 1.5", - "set style line 9 lc rgb \"spring-green\" lt 1 lw 2 pt 8 ps 1.5", - "set style line 10 lc rgb \"yellow4\" lt 1 lw 2 pt 0 ps 1.5", - "set yrange [0:45]", - "set xrange [0:]", - - 0 -}; - -#endif - -EOF - - mv -f plot_command.h $plot_c_path/plot_command.h - cd $plot_c_path - make - cp $plot_c_path/plot $multiple_path/plot_bin - cd $script_path - -} - - - - -################ -# -# regenerate_NoC -# -################ - -regenerate_NoC() { - generate_parameter_v - mv -f parameter.v ../src_verilator/ - - #verilate the NoC and make the library files -#################################################################3 - ./verilator_compile_hw.sh - - # compile the testbench file - generate_parameter_h - mv -f parameter.h ../src_verilator/ - - ./verilator_compile_sw.sh - - - cp $bin_path/testbench $multiple_path/$testbench_name -} - - -################ -# -# merg_files -# -################ - - -merg_files(){ - if [ $STND_DEV_EN -eq 1 ] - then - - target="_std" - else - target="_all" - - fi - - data_file=$data_path/${plot_name}${target}".txt" - plot_file=$plot_path/${plot_name}${target}".eps" - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat ${testbench_name}${target}".txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - - - if [ $C -gt 1 ] - then - - data_file=$data_path/$plot_name"_c0.txt" - plot_file=$plot_path/$plot_name"_c0.eps" - - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_c0.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - data_file=$data_path/$plot_name"_c1.txt" - plot_file=$plot_path/$plot_name"_c1.eps" - - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_c1.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - fi - - - rm $testbench_name* - -} - -gen_testbench_name(){ - testbench_name=$routename"_"$SSA_EN - -} - -gen_plot_name(){ - plot_name=$routename"_"$TRAFFIC"_"$PACKET_SIZE - -} - - - - - - - - -################ -# -# run_sim -# -################ -run_sim(){ - - for SSA_EN in "YES" "NO" - do - - gen_testbench_name - regenerate_NoC - done - - - - - - cd $multiple_path - - for SSA_EN in "YES" "NO" - do - - gen_testbench_name - CMD="./$testbench_name $testbench_name" - - command $CMD & - done - - - # wait for all simulation to be done - wait - - - - # merge the results in one file - VC_REALLOCATION_TYPE="NONATOMIC" - - for SSA_EN in "YES" "NO" - do - - - gen_testbench_name - gen_plot_name - CURVE_NAME=$SSA_EN - merg_files - done # ROUTE_NAME - - - cd $script_path - -} - - -generate_plot_command - - - - - - - for PACKET_SIZE in 4 # 6 - do - for TRAFFIC in "RANDOM" # "BIT_REVERSE" "BIT_COMPLEMENT" "RANDOM" "HOTSPOT" "TRANSPOSE1" "TORNADO" #"CUSTOM" - do - - - run_sim - - - done -done #PACKET_SIZE -
verilator_multiple/verilator_ssa.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilator_multiple/verilator_route_mesh.sh =================================================================== --- verilator_multiple/verilator_route_mesh.sh (revision 34) +++ verilator_multiple/verilator_route_mesh.sh (nonexistent) @@ -1,319 +0,0 @@ -#!/bin/sh -set -e -# Any subsequent commands which fail will cause the shell script to exit immediately - -my_dir="$(dirname "$0")" -source "$my_dir/../parameter.sh" - - -cd .. -script_path=$(pwd) -path=$script_path/.. -comp_path=$path/../adaptive_work/verilator -work_path=$comp_path/work -bin_path=$work_path/bin -multiple_path=$work_path/mesh_2d_route -data_path=$multiple_path/data -plot_path=$multiple_path/plot -src_c_path=$path/src_c - -rm -Rf $multiple_path -mkdir -p $data_path -mkdir -p $plot_path -cp $path/src_c/plot/plot $multiple_path/plot_bin - - - - V=2 # number of VC per port - B=4 # buffer space :flit per VC - NX=8 # number of node in x axis - NY=8 # number of node in y axis - C=1 # number of flit class - COMBINATION_TYPE="COMB_SPEC1" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC" - FIRST_ARBITER_EXT_P_EN=1 - TOPOLOGY="MESH" #"MESH" or "TORUS" - CLASS_SETTING="4'b1111" # no class. packets can be sent to any availbale OVC - - -#simulation parameters: - C0_p=100 # the percentage of injected packets with class 0 - C1_p=50 - C2_p=0 - C3_p=0 - - - - # Simulation parameters: - - #Hotspot Traffic setting - HOTSPOT_PERCENTAGE=3 #maximum 20 - HOTSOPT_NUM=4 #maximum 5 - HOTSPOT_CORE_1=$(CORE_NUM 2 2) - HOTSPOT_CORE_2=$(CORE_NUM 2 6) - HOTSPOT_CORE_3=$(CORE_NUM 6 2) - HOTSPOT_CORE_4=$(CORE_NUM 6 6) - - - - - - MAX_PCK_NUM=128000 - MAX_SIM_CLKs=100000 - MAX_PCK_SIZ=10 # maximum flit number in a single packet - TIMSTMP_FIFO_NUM=64 - - - - ESCAP_VC_MASK="2'b01" # mask scape vc - DEBUG_EN=1 - - CONGESTION_INDEX=3 # 0: packets are routed to the ports with more available VCs - # 1: packets are routed to the ports with more available credits - # 2: packets are routed to the ports connected to the routers with less active ivc requests - # 3: packets are routed to the ports connected to the routers with less active ivc requests that are not granted - - CONGw=2 # congestion data width which is passed between two neighbouring routers - - - - -# - - AVC_ATOMIC_EN=0 - STND_DEV_EN=0 # 1: generate standard devision - - - - - - -################ -# -# regenerate_NoC -# -################ - -regenerate_NoC() { - generate_parameter_v - mv -f parameter.v ../src_verilator/ - - #verilate the NoC and make the library files -#################################################################3 - ./verilator_compile_hw.sh - - # compile the testbench file - generate_parameter_h - mv -f parameter.h ../src_verilator/ - - ./verilator_compile_sw.sh - - - cp $bin_path/testbench $multiple_path/$testbench_name -} - -routename="NULL" -################ -# -# merg_files -# -################ - - -merg_files(){ - - data_file=$data_path/$plot_name"_all.txt" - plot_file=$plot_path/$plot_name"_all.eps" - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_all.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - - - if [ $C -gt 1 ] - then - - data_file=$data_path/$plot_name"_c0.txt" - plot_file=$plot_path/$plot_name"_c0.eps" - - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_c0.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - data_file=$data_path/$plot_name"_c1.txt" - plot_file=$plot_path/$plot_name"_c1.eps" - - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_c1.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - fi - - - rm $testbench_name* - -} - -gen_testbench_name(){ - testbench_name=$routename"_"$TRAFFIC"_"$PACKET_SIZE - -} - -gen_plot_name(){ - plot_name="CONG"$CONGESTION_INDEX$"_"$TRAFFIC"_"$PACKET_SIZE - -} - - -route_setting(){ - case $routename in - 'DUATO_XY_A') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="XY" - VC_REALLOCATION_TYPE="ATOMIC" - AVC_ATOMIC_EN=1 - echo "DUATO_XY_A" - ;; - 'DUATO_XY_H') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="XY" - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=1 - echo "DUATO_XY_H" - - ;; - 'DUATO_XY_F') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="XY" - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=0 - echo "DUATO_XY_F" - ;; - 'DUATO_NL_A') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="NORTH_LAST" - VC_REALLOCATION_TYPE="ATOMIC" - AVC_ATOMIC_EN=1 - echo "DUATO_NL_A" - ;; - 'DUATO_NL_H') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="NORTH_LAST" - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=1 - echo "DUATO_NL_H" - - ;; - 'DUATO_NL_F') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="NORTH_LAST" - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=0 - echo "DUATO_NL_F" - ;; - - - *) - ROUTE_NAME=$routename - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=0 - echo $ROUTE_NAME - ;; - - -esac -} - - - - - - -################ -# -# run_sim -# -################ -run_sim(){ - - for routename in "XY" "WEST_FIRST" "ODD_EVEN" "NEGETIVE_FIRST" "DUATO_XY_A" "DUATO_XY_H" "DUATO_XY_F" "DUATO_NL_A" "DUATO_NL_H" "DUATO_NL_F" - do - route_setting - gen_testbench_name - regenerate_NoC - done - - - - - - cd $multiple_path - - for routename in "XY" "WEST_FIRST" "ODD_EVEN" "NEGETIVE_FIRST" - do - route_setting - gen_testbench_name - CMD="./$testbench_name $testbench_name" - - command $CMD & - done - - - # wait for all simulation to be done - wait - - for routename in "DUATO_XY_A" "DUATO_XY_H" "DUATO_XY_F" "DUATO_NL_A" "DUATO_NL_H" "DUATO_NL_F" - do - route_setting - gen_testbench_name - CMD="./$testbench_name $testbench_name" - - command $CMD & - done - - - # wait for all simulation to be done - wait - - - # merge the results in one file - VC_REALLOCATION_TYPE="NONATOMIC" - - for routename in "XY" "WEST_FIRST" "ODD_EVEN" "NEGETIVE_FIRST" "DUATO_XY_A" "DUATO_XY_H" "DUATO_XY_F" "DUATO_NL_A" "DUATO_NL_H" "DUATO_NL_F" - do - - route_setting - gen_testbench_name - gen_plot_name - CURVE_NAME=$routename - merg_files - done # ROUTE_NAME - - - cd $script_path - -} - - - - for PACKET_SIZE in 2 3 4 6 - do - for TRAFFIC in "TRANSPOSE2" "TRANSPOSE1" "BIT_REVERSE" "BIT_COMPLEMENT" "RANDOM" "HOTSPOT" - do - for CONGESTION_INDEX in 1 #0 1 2 3 - do - - run_sim - - done - done -done #PACKET_SIZE -
verilator_multiple/verilator_route_mesh.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilator_multiple/ptonoc-vcsw.sh =================================================================== --- verilator_multiple/ptonoc-vcsw.sh (revision 34) +++ verilator_multiple/ptonoc-vcsw.sh (nonexistent) @@ -1,295 +0,0 @@ -#!/bin/sh -set -e -# Any subsequent commands which fail will cause the shell script to exit immediately - -my_dir="$(dirname "$0")" -source "$my_dir/../parameter.sh" - -# change default parameters - V=4 #if change u need to change CLASS_SETTING as well - FIRST_ARBITER_EXT_P_EN=0 - ROUTE_NAME="XY" - TRAFFIC="TRANSPOSE1" - DEBUG_EN=1 - STND_DEV_EN=0 - B=4 - VC_REALLOCATION_TYPE="NONATOMIC" - MAX_PCK_NUM=128000 - NX=4 # number of node in x axis - NY=4 # number of node in y axis - - - -cd .. -script_path=$(pwd) -path=$script_path/.. -comp_path=$path/../mpsoc_work/verilator -work_path=$comp_path/work -bin_path=$work_path/bin -multiple_path=$work_path/sw_vc_comb -data_path=$multiple_path/data -plot_path=$multiple_path/plot -src_c_path=$path/src_c -src_verilator_path=$path/src_verilator -plot_c_path=$src_c_path/plot -rm -Rf $multiple_path -mkdir -p $data_path -mkdir -p $plot_path - - - - - - -CLASS_CONFIG=0 - - - - - -################ -# -# regenerate_NoC -# -################ - -regenerate_NoC() { - rm -f parameter.v - generate_parameter_v - mv -f parameter.v $src_verilator_path/ - cd $script_path - #verilate the NoC and make the library files - - ./verilator_compile_hw.sh - - # compile the testbench file - generate_parameter_h - mv -f parameter.h $src_verilator_path/ - - ./verilator_compile_sw.sh - - - cp $bin_path/testbench $multiple_path/$testbench_name -} - -############### -# set packet classes -# -############### - - -class_setting(){ - if [ $CLASS_CONFIG -eq 0 ] - then - C=1 - C0_p=100 - CLASS_SETTING="4'b1111" - elif [ $CLASS_CONFIG -eq 1 ] - then - C=$V - C0_p=$(expr 100 / $V ) - C1_p=$(expr 100 / $V ) - C2_p=$(expr 100 / $V ) - C3_p=$(expr 100 / $V ) - CLASS_SETTING="16'b1000010000100001" - - - elif [ $CLASS_CONFIG -eq 3 ] - then - C=2 - C0_p=50 - C1_p=50 - CLASS_SETTING="8'b11001111" - - elif [ $CLASS_CONFIG -eq 4 ] - then - C=2 - C0_p=50 - C1_p=50 - CLASS_SETTING="8'b11000011" - else - C=2 - C0_p=50 - C1_p=50 - - fi - -} - - -####################### -# -# generate_plot_command_h -####################### - -generate_plot_command(){ - -rm -f plot_command.h - -cat > plot_command.h << EOF -#ifndef PLOT_COMMAND_H - #define PLOT_COMMAND_H - -char * commandsForGnuplot[] = { - "set terminal postscript eps enhanced color font 'Helvetica,24'", - "set output 'temp.eps' ", - "set style line 1 lc rgb \"red\" lt 1 lw 2 pt 4 ps 1.5", - "set style line 2 lc rgb \"blue\" lt 1 lw 2 pt 6 ps 1.5", - "set style line 3 lc rgb \"green\" lt 1 lw 2 pt 10 ps 1.5", - "set style line 4 lc rgb '#8B008B' lt 1 lw 2 pt 14 ps 1.5",//darkmagenta - "set style line 5 lc rgb '#B8860B' lt 1 lw 2 pt 2 ps 1.5", //darkgoldenrod - "set style line 6 lc rgb \"gold\" lt 1 lw 2 pt 3 ps 1.5", - "set style line 7 lc rgb '#FF8C00' lt 1 lw 2 pt 10 ps 1.5",//darkorange - "set style line 8 lc rgb \"black\" lt 1 lw 2 pt 1 ps 1.5", - "set style line 9 lc rgb \"spring-green\" lt 1 lw 2 pt 8 ps 1.5", - "set style line 10 lc rgb \"yellow4\" lt 1 lw 2 pt 0 ps 1.5", - "set yrange [0:60]", - "set xrange [0:]", - 0 -}; - -#endif - -EOF - - mv -f plot_command.h $plot_c_path/plot_command.h - cd $plot_c_path - make - cp $plot_c_path/plot $multiple_path/plot_bin - cd $path -} - - - -############# -# plot_file -# -############ - -plot_file (){ - data_file=$data_path/$plot_name$ext".txt" - plot_file=$plot_path/$plot_name$ext".eps" - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name$ext".txt" >> $data_file - printf "\n\n" >> $data_file - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "left" -} - - -################ -# -# merg_files -# -################ - - -merg_files(){ - - ext="_all" - plot_file - - - if [ $STND_DEV_EN -eq 1 ] - then - ext="_std" - plot_file - fi - - if [ $CLASS_CONFIG -eq 3 ] - then - ext="_c0" - plot_file - - ext="_c1" - plot_file - - if [ $STND_DEV_EN -eq 1 ] - then - ext="_std0" - plot_file - - ext="_std1" - plot_file - fi - - - fi - - - rm $testbench_name* - -} - -gen_testbench_name(){ - testbench_name=$VC_REALLOCATION_TYPE"_"$COMBINATION_TYPE"_Config"$CLASS_CONFIG"_P"$PACKET_SIZE - -} - -gen_plot_name(){ - plot_name=$VC_REALLOCATION_TYPE"_Config"$CLASS_CONFIG"_P"$PACKET_SIZE - -} - -################ -# -# run_sim -# -################ -run_sim(){ - - for COMBINATION_TYPE in "BASELINE" "COMB_SPEC1" "COMB_SPEC2" "COMB_NONSPEC" - do - gen_testbench_name - regenerate_NoC - done - - cd $multiple_path - - for COMBINATION_TYPE in "BASELINE" "COMB_SPEC1" "COMB_SPEC2" "COMB_NONSPEC" - do - gen_testbench_name - CMD="./$testbench_name $testbench_name" - - command $CMD & - done - - # wait for all simulation to be done - wait - - # merge the results in one file - for COMBINATION_TYPE in "BASELINE" "COMB_SPEC1" "COMB_SPEC2" "COMB_NONSPEC" - do - gen_testbench_name - gen_plot_name - CURVE_NAME=$COMBINATION_TYPE - merg_files - done #COMBINATION_TYPE - - - - cd $script_path - -} - -############### -# main -############## - - -generate_plot_command - - for PACKET_SIZE in 2 4 - do - for CLASS_CONFIG in 4 - do - class_setting - run_sim - #teset - - - - - - done # CLASS_CONFIG -done #PACKET_SIZE -
verilator_multiple/ptonoc-vcsw.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilator_multiple/verilator_congestion_index.sh =================================================================== --- verilator_multiple/verilator_congestion_index.sh (revision 34) +++ verilator_multiple/verilator_congestion_index.sh (nonexistent) @@ -1,318 +0,0 @@ -#!/bin/sh -set -e -# Any subsequent commands which fail will cause the shell script to exit immediately - -my_dir="$(dirname "$0")" -source "$my_dir/../parameter.sh" - - -cd .. -script_path=$(pwd) -path=$script_path/.. -comp_path=$path/../mpsoc_work/verilator -work_path=$comp_path/work -bin_path=$work_path/bin -multiple_path=$work_path/congestion_index -data_path=$multiple_path/data -plot_path=$multiple_path/plot -src_c_path=$path/src_c - -rm -Rf $multiple_path -mkdir -p $data_path -mkdir -p $plot_path -cp $path/src_c/plot/plot $multiple_path/plot_bin - - - - V=4 # number of VC per port - B=4 # buffer space :flit per VC - NX=8 # number of node in x axis - NY=8 # number of node in y axis - C=2 # number of flit class - COMBINATION_TYPE="COMB_NONSPEC" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC" - FIRST_ARBITER_EXT_P_EN=1 - TOPOLOGY="MESH" #"MESH" or "TORUS" - CLASS_SETTING="8'b11000011" # There are total of two classes. each class use half of avb VCs - -#simulation parameters: - C0_p=50 # the percentage of injected packets with class 0 - C1_p=50 - C2_p=0 - C3_p=0 - - - - # Simulation parameters: - - #Hotspot Traffic setting - HOTSPOT_PERCENTAGE=3 #maximum 20 - HOTSOPT_NUM=4 #maximum 5 - HOTSPOT_CORE_1=$(CORE_NUM 2 2) - HOTSPOT_CORE_2=$(CORE_NUM 2 6) - HOTSPOT_CORE_3=$(CORE_NUM 6 2) - HOTSPOT_CORE_4=$(CORE_NUM 6 6) - - - - - - MAX_PCK_NUM=128000 - MAX_SIM_CLKs=100000 - MAX_PCK_SIZ=10 # maximum flit number in a single packet - TIMSTMP_FIFO_NUM=64 - - - - ESCAP_VC_MASK="4'b0101" # mask scape vc - DEBUG_EN=1 - - CONGESTION_INDEX=3 # 0: packets are routed to the ports with more available VCs - # 1: packets are routed to the ports with more available credits - # 2: packets are routed to the ports connected to the routers with less active ivc requests - # 3: packets are routed to the ports connected to the routers with less active ivc requests that are not granted - - - - - - -# - - AVC_ATOMIC_EN=0 - STND_DEV_EN=0 # 1: generate standard devision - - - - - - -################ -# -# regenerate_NoC -# -################ - -regenerate_NoC() { - generate_parameter_v - mv -f parameter.v ../src_verilator/ - - #verilate the NoC and make the library files -#################################################################3 - ./verilator_compile_hw.sh - - # compile the testbench file - generate_parameter_h - mv -f parameter.h ../src_verilator/ - - ./verilator_compile_sw.sh - - - cp $bin_path/testbench $multiple_path/$testbench_name -} - -routename="NULL" -################ -# -# merg_files -# -################ - - -merg_files(){ - - data_file=$data_path/$plot_name"_all.txt" - plot_file=$plot_path/$plot_name"_all.eps" - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_all.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - - - if [ $C -gt 1 ] - then - - data_file=$data_path/$plot_name"_c0.txt" - plot_file=$plot_path/$plot_name"_c0.eps" - - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_c0.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - data_file=$data_path/$plot_name"_c1.txt" - plot_file=$plot_path/$plot_name"_c1.eps" - - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_c1.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - fi - - - rm $testbench_name* - -} - -gen_testbench_name(){ - testbench_name=$routename"_"$TRAFFIC"_"$PACKET_SIZE - -} - -gen_plot_name(){ - plot_name="CONG"$CONGESTION_INDEX$"_"$TRAFFIC"_"$PACKET_SIZE - -} - - -route_setting(){ - case $routename in - 'DUATO_XY_A') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="XY" - VC_REALLOCATION_TYPE="ATOMIC" - AVC_ATOMIC_EN=1 - echo "DUATO_XY_A" - ;; - 'DUATO_XY_H') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="XY" - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=1 - echo "DUATO_XY_H" - - ;; - 'DUATO_XY_F') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="XY" - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=0 - echo "DUATO_XY_F" - ;; - 'DUATO_NL_A') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="NORTH_LAST" - VC_REALLOCATION_TYPE="ATOMIC" - AVC_ATOMIC_EN=1 - echo "DUATO_NL_A" - ;; - 'DUATO_NL_H') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="NORTH_LAST" - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=1 - echo "DUATO_NL_H" - - ;; - 'DUATO_NL_F') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="NORTH_LAST" - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=0 - echo "DUATO_NL_F" - ;; - - - *) - ROUTE_NAME=$routename - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=0 - echo $ROUTE_NAME - ;; - - -esac -} - - - - - - -################ -# -# run_sim -# -################ -run_sim(){ - - for routename in "XY" "WEST_FIRST" "ODD_EVEN" "NEGETIVE_FIRST" "DUATO_XY_A" "DUATO_XY_H" "DUATO_XY_F" "DUATO_NL_A" "DUATO_NL_H" "DUATO_NL_F" - do - route_setting - gen_testbench_name - regenerate_NoC - done - - - - - - cd $multiple_path - - for routename in "XY" "WEST_FIRST" "ODD_EVEN" "NEGETIVE_FIRST" - do - route_setting - gen_testbench_name - CMD="./$testbench_name $testbench_name" - - command $CMD & - done - - - # wait for all simulation to be done - wait - - for routename in "DUATO_XY_A" "DUATO_XY_H" "DUATO_XY_F" "DUATO_NL_A" "DUATO_NL_H" "DUATO_NL_F" - do - route_setting - gen_testbench_name - CMD="./$testbench_name $testbench_name" - - command $CMD & - done - - - # wait for all simulation to be done - wait - - - # merge the results in one file - VC_REALLOCATION_TYPE="NONATOMIC" - - for routename in "XY" "WEST_FIRST" "ODD_EVEN" "NEGETIVE_FIRST" "DUATO_XY_A" "DUATO_XY_H" "DUATO_XY_F" "DUATO_NL_A" "DUATO_NL_H" "DUATO_NL_F" - do - - route_setting - gen_testbench_name - gen_plot_name - CURVE_NAME=$routename - merg_files - done # ROUTE_NAME - - - cd $script_path - -} - - - - for PACKET_SIZE in 2 3 4 6 - do - for TRAFFIC in "TRANSPOSE2" - do - for CONGESTION_INDEX in 10 9 8 7 6 5 4 3 2 1 - do - - run_sim - - done - done -done #PACKET_SIZE -
verilator_multiple/verilator_congestion_index.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilator_multiple/pronoc/verilator_ssa.sh =================================================================== --- verilator_multiple/pronoc/verilator_ssa.sh (revision 34) +++ verilator_multiple/pronoc/verilator_ssa.sh (nonexistent) @@ -1,304 +0,0 @@ -#!/bin/sh -set -e -# Any subsequent commands which fail will cause the shell script to exit immediately - -my_dir="$(dirname "$0")" -source "$my_dir/../parameter.sh" - - -cd .. -script_path=$(pwd) -path=$script_path/.. -comp_path=$path/../mpsoc_work/verilator -work_path=$comp_path/work -bin_path=$work_path/bin -multiple_path=$work_path/ssa4 -data_path=$multiple_path/data -plot_path=$multiple_path/plot -src_c_path=$path/src_c -plot_c_path=$src_c_path/plot - -rm -Rf $multiple_path -mkdir -p $data_path -mkdir -p $plot_path - -#cp $path/src_c/plot/plot $multiple_path/plot_bin - - - - V=4 # number of VC per port - B=5 # buffer space :flit per VC - NX=8 # number of node in x axis - NY=8 # number of node in y axis - C=4 # number of flit class - COMBINATION_TYPE="COMB_NONSPEC" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC" - FIRST_ARBITER_EXT_P_EN=0 - ROUTE_NAME="XY" - CLASS_SETTING="16'b111111111111111" - -#simulation parameters: - C0_p=25 # the percentage of injected packets with class 0 - C1_p=25 - C2_p=25 - C3_p=25 - - - - # Simulation parameters: - - #Hotspot Traffic setting - HOTSPOT_PERCENTAGE=3 #maximum 20 - HOTSOPT_NUM=4 #maximum 5 - HOTSPOT_CORE_1=$(CORE_NUM 2 2) - HOTSPOT_CORE_2=$(CORE_NUM 2 6) - HOTSPOT_CORE_3=$(CORE_NUM 6 2) - HOTSPOT_CORE_4=$(CORE_NUM 6 6) - - - - - - MAX_PCK_NUM=256000 - MAX_SIM_CLKs=100000 - MAX_PCK_SIZ=10 # maximum flit number in a single packet - - - - - ESCAP_VC_MASK="4'b0001" # mask scape vc - DEBUG_EN=1 - - CONGESTION_INDEX=3 # 0: packets are routed to the ports with more available VCs - # 1: packets are routed to the ports with more available credits - # 2: packets are routed to the ports connected to the routers with less active ivc requests - # 3: packets are routed to the ports connected to the routers with less active ivc requests that are not granted - - - - - - -# - - AVC_ATOMIC_EN=0 - STND_DEV_EN=0 # 1: generate standard devision - TIMSTMP_FIFO_NUM=8 - - - - -generate_plot_command(){ - -rm -f plot_command.h - -cat > plot_command.h << EOF -#ifndef PLOT_COMMAND_H - #define PLOT_COMMAND_H - -char * commandsForGnuplot[] = { - "set terminal postscript eps enhanced color font 'Helvetica,15'", - "set output 'temp.eps' ", - "set style line 1 lc rgb \"red\" lt 1 lw 2 pt 4 ps 1.5", - "set style line 2 lc rgb \"blue\" lt 1 lw 2 pt 6 ps 1.5", - "set style line 3 lc rgb \"green\" lt 1 lw 2 pt 10 ps 1.5", - "set style line 4 lc rgb '#8B008B' lt 1 lw 2 pt 14 ps 1.5",//darkmagenta - "set style line 5 lc rgb '#B8860B' lt 1 lw 2 pt 2 ps 1.5", //darkgoldenrod - "set style line 6 lc rgb \"gold\" lt 1 lw 2 pt 3 ps 1.5", - "set style line 7 lc rgb '#FF8C00' lt 1 lw 2 pt 10 ps 1.5",//darkorange - "set style line 8 lc rgb \"black\" lt 1 lw 2 pt 1 ps 1.5", - "set style line 9 lc rgb \"spring-green\" lt 1 lw 2 pt 8 ps 1.5", - "set style line 10 lc rgb \"yellow4\" lt 1 lw 2 pt 0 ps 1.5", - "set yrange [0:45]", - "set xrange [0:]", - - 0 -}; - -#endif - -EOF - - mv -f plot_command.h $plot_c_path/plot_command.h - cd $plot_c_path - make - cp $plot_c_path/plot $multiple_path/plot_bin - cd $script_path - -} - - - - -################ -# -# regenerate_NoC -# -################ - -regenerate_NoC() { - generate_parameter_v - mv -f parameter.v ../src_verilator/ - - #verilate the NoC and make the library files -#################################################################3 - ./verilator_compile_hw.sh - - # compile the testbench file - generate_parameter_h - mv -f parameter.h ../src_verilator/ - - ./verilator_compile_sw.sh - - - cp $bin_path/testbench $multiple_path/$testbench_name -} - - -################ -# -# merg_files -# -################ - - -merg_files(){ - if [ $STND_DEV_EN -eq 1 ] - then - - target="_std" - else - target="_all" - - fi - - data_file=$data_path/${plot_name}${target}".txt" - plot_file=$plot_path/${plot_name}${target}".eps" - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat ${testbench_name}${target}".txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - - - if [ $C -gt 1 ] - then - - data_file=$data_path/$plot_name"_c0.txt" - plot_file=$plot_path/$plot_name"_c0.eps" - - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_c0.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - data_file=$data_path/$plot_name"_c1.txt" - plot_file=$plot_path/$plot_name"_c1.eps" - - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_c1.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "outside left" - - fi - - - rm $testbench_name* - -} - -gen_testbench_name(){ - testbench_name=$routename"_"$SSA_EN - -} - -gen_plot_name(){ - plot_name=$routename"_"$TRAFFIC"_"$PACKET_SIZE - -} - - - - - - - - -################ -# -# run_sim -# -################ -run_sim(){ - - for SSA_EN in "YES" "NO" - do - - gen_testbench_name - regenerate_NoC - done - - - - - - cd $multiple_path - - for SSA_EN in "YES" "NO" - do - - gen_testbench_name - CMD="./$testbench_name $testbench_name" - - command $CMD & - done - - - # wait for all simulation to be done - wait - - - - # merge the results in one file - VC_REALLOCATION_TYPE="NONATOMIC" - - for SSA_EN in "YES" "NO" - do - - - gen_testbench_name - gen_plot_name - CURVE_NAME=$SSA_EN - merg_files - done # ROUTE_NAME - - - cd $script_path - -} - - -generate_plot_command - - - - - - - for PACKET_SIZE in 4 # 6 - do - for TRAFFIC in "HOTSPOT" "RANDOM" "TORNADO" # "BIT_REVERSE" "BIT_COMPLEMENT" "RANDOM" "TRANSPOSE1" #"CUSTOM" - do - - - run_sim - - - done -done #PACKET_SIZE -
verilator_multiple/pronoc/verilator_ssa.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilator_multiple/pronoc/pronoc.sh =================================================================== --- verilator_multiple/pronoc/pronoc.sh (revision 34) +++ verilator_multiple/pronoc/pronoc.sh (nonexistent) @@ -1,425 +0,0 @@ -#!/bin/sh -#set -e -# Any subsequent commands which fail will cause the shell script to exit immediately - -#my_dir="$(dirname "$0")" -#source "$my_dir/../parameter.sh" - -cc=$(pwd) -PWDI=$cc -echo "$PWD " - -script_path=$PWDI/../.. -path=$script_path/.. -comp_path=$path/../mpsoc_work/verilator -work_path=$comp_path/work -bin_path=$work_path/bin -multiple_path=$work_path/pronoc -data_path=$multiple_path/data -plot_path=$multiple_path/plot -src_c_path=$path/src_c -src_noc_path=$path/src_noc -src_verilator_path=$path/src_verilator -plot_c_path=$src_c_path/plot - -source "$script_path/parameter.sh" - -rm -Rf $multiple_path -mkdir -p $data_path -mkdir -p $plot_path -cp $path/src_c/plot/plot $multiple_path/plot_bin - - -#commen parameter - V=2 # number of VC per port - NX=8 # number of node in x axis - NY=8 # number of node in y axis - CONGESTION_INDEX=3 - B=4 # buffer space :flit per VC - ESCAP_VC_MASK="2'b01" # mask scape vc - C=0 # number of flit class - COMBINATION_TYPE="COMB_NONSPEC" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC" - AVC_ATOMIC_EN=0 - FIRST_ARBITER_EXT_P_EN=0 - TOPOLOGY="MESH" #"MESH" or "TORUS" - CLASS_SETTING="4'b1111" #There are total of two classes. each class use half of avb VCs - -#simulation parameters: - C0_p=50 # the percentage of injected packets with class 0 - C1_p=50 - C2_p=0 - C3_p=0 - - - - # Simulation parameters: - - #Hotspot Traffic setting - HOTSPOT_PERCENTAGE=4 #maximum 20 - HOTSOPT_NUM=4 #maximum 5 - HOTSPOT_CORE_1=$(CORE_NUM 2 3) - HOTSPOT_CORE_2=$(CORE_NUM 4 6) - HOTSPOT_CORE_3=$(CORE_NUM 6 2) - HOTSPOT_CORE_4=$(CORE_NUM 6 6) - - - - - - MAX_PCK_NUM=200000 - MAX_SIM_CLKs=100000 - MAX_PCK_SIZ=10 # maximum flit number in a single packet - TIMSTMP_FIFO_NUM=16 - - PACKET_SIZE=4 - - - DEBUG_EN=0 - - - - - - - -# - - AVC_ATOMIC_EN=0 - STND_DEV_EN=0 # 1: generate standard devision - - - - - - - - -###################### -# -# verilator_compile_hw -# -###################### - -verilator_compile_hw(){ - - - - work_path=$comp_path/work - #echo "$work_path\n" - cd $script_path - mkdir -p $work_path/rtl_work - - cp split $work_path/split - - - cd $work_path - - # remove old files - rm -rf rtl_work/* - rm -rf processed_rtl/* - rm -rf processed_rtl/obj_dir/* - - - - echo "copy all verilog files in rtl_work folder" - find $src_noc_path -name \*.v -exec cp '{}' rtl_work/ \; - find $src_verilator_path -name \*.v -exec cp '{}' rtl_work/ \; - -#replace conventional - if [ "$routename" == "DUATO_ORG" ] - then - cp -f $PWDI/vc_alloc_request_gen.v rtl_work/vc_alloc_request_gen.v - - echo "$PWDI vc_alloc_request_gen.v have been replaced" - fi - - - echo "split all verilog modules in separate files" - ./split > foo - - find $src_verilator_path -name \*.sv -exec cp '{}' processed_rtl/ \; - - - cd processed_rtl - - verilator --cc router_verilator.v --profile-cfuncs --prefix "Vrouter" -O3 - verilator --cc noc_connection.sv --prefix "Vnoc" -O3 - verilator --cc --profile-cfuncs traffic_gen_verilator.v --prefix "Vtraffic" -O3 - - - cp $script_path/Makefile obj_dir/ - cd obj_dir - make lib -j 4 - cd $script_path - - -} - - - - -################ -# -# regenerate_NoC -# -################ - -regenerate_NoC() { - generate_parameter_v - mv -f parameter.v $src_verilator_path/ - - #verilate the NoC and make the library files -#################################################################3 - verilator_compile_hw - - # compile the testbench file - generate_parameter_h - mv -f parameter.h $src_verilator_path/ - - ./verilator_compile_sw.sh - - - cp $bin_path/testbench $multiple_path/$testbench_name -} - -routename="NULL" -################ -# -# merg_files -# -################ - - -merg_files(){ - - data_file=$data_path/$plot_name"_all.txt" - plot_file=$plot_path/$plot_name"_all.eps" - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_all.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "left" - - - - if [ $C -gt 1 ] - then - - data_file=$data_path/$plot_name"_c0.txt" - plot_file=$plot_path/$plot_name"_c0.eps" - - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_c0.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "left" - - data_file=$data_path/$plot_name"_c1.txt" - plot_file=$plot_path/$plot_name"_c1.eps" - - - printf "#name:"$CURVE_NAME"\n" >> $data_file - cat $testbench_name"_c1.txt" >> $data_file - printf "\n\n" >> $data_file - - ./plot_bin $data_file $plot_file "Injection ratio flits/node/clk" "Average latency clk" "left" - - fi - - - rm $testbench_name* - -} - - - - -####################### -# -# generate_plot_command_h -####################### - -generate_plot_command(){ - -rm -f plot_command.h - -cat > plot_command.h << EOF -#ifndef PLOT_COMMAND_H - #define PLOT_COMMAND_H - -char * commandsForGnuplot[] = { - "set terminal postscript eps enhanced color font 'Helvetica,15'", - "set output 'temp.eps' ", - "set style line 1 lc rgb \"red\" lt 1 lw 2 pt 4 ps 1.5", - "set style line 2 lc rgb \"blue\" lt 1 lw 2 pt 6 ps 1.5", - "set style line 3 lc rgb \"green\" lt 1 lw 2 pt 10 ps 1.5", - "set style line 4 lc rgb '#8B008B' lt 1 lw 2 pt 14 ps 1.5",//darkmagenta - "set style line 5 lc rgb '#B8860B' lt 1 lw 2 pt 2 ps 1.5", //darkgoldenrod - "set style line 6 lc rgb \"gold\" lt 1 lw 2 pt 3 ps 1.5", - "set style line 7 lc rgb '#FF8C00' lt 1 lw 2 pt 10 ps 1.5",//darkorange - "set style line 8 lc rgb \"black\" lt 1 lw 2 pt 1 ps 1.5", - "set style line 9 lc rgb \"spring-green\" lt 1 lw 2 pt 8 ps 1.5", - "set style line 10 lc rgb \"yellow4\" lt 1 lw 2 pt 0 ps 1.5", - "set yrange [0:80]", - "set xrange [0:]", - - 0 -}; - -#endif - -EOF - - mv -f plot_command.h $plot_c_path/plot_command.h - cd $plot_c_path - make - cp $plot_c_path/plot $multiple_path/plot_bin - cd $script_path - -} - - - -gen_testbench_name(){ - testbench_name="B"$B"_"$routename"_"$TRAFFIC"_"$PACKET_SIZE - -} - -gen_plot_name(){ - plot_name="B"$B"_"$TRAFFIC"_"$PACKET_SIZE - -} - - -route_setting(){ - case $routename in - - - - 'DUATO_ORG') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="XY" - VC_REALLOCATION_TYPE="ATOMIC" - AVC_ATOMIC_EN=1 - echo "DUATO_ORG" - ;; - 'DUATO_WPF') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="XY" - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=1 - echo "DUATO_WPF" - - ;; - 'DUATO_MINE') - ROUTE_NAME="DUATO" - ROUTE_SUBFUNC="XY" - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=0 - echo "DUATO_MINE" - ;; - - - - *) - ROUTE_NAME=$routename - VC_REALLOCATION_TYPE="NONATOMIC" - AVC_ATOMIC_EN=0 - echo $ROUTE_NAME - ;; - - -esac -} - - - - - - -################ -# -# run_sim -# -################ -run_sim(){ - - for routename in "DUATO_ORG" "DUATO_MINE" "DUATO_WPF" "XY" "WEST_FIRST" "ODD_EVEN" "NEGETIVE_FIRST" - do - route_setting - gen_testbench_name - regenerate_NoC - done - - - - - - cd $multiple_path - - for routename in "XY" "WEST_FIRST" "ODD_EVEN" "NEGETIVE_FIRST" - do - route_setting - gen_testbench_name - CMD="./$testbench_name $testbench_name" - - command $CMD & - done - - - # wait for all simulation to be done - wait - - for routename in "DUATO_ORG" "DUATO_MINE" "DUATO_WPF" - do - route_setting - gen_testbench_name - CMD="./$testbench_name $testbench_name" - - command $CMD & - done - - - # wait for all simulation to be done - wait - - - # merge the results in one file - VC_REALLOCATION_TYPE="NONATOMIC" - - for routename in "XY" "WEST_FIRST" "ODD_EVEN" "NEGETIVE_FIRST" "DUATO_ORG" "DUATO_MINE" "DUATO_WPF" - do - - route_setting - gen_testbench_name - gen_plot_name - CURVE_NAME=$routename - merg_files - done # ROUTE_NAME - - - cd $script_path - -} - -generate_plot_command - -for B in 8 -do - for PACKET_SIZE in 2 8 - do - for TRAFFIC in "TRANSPOSE2" "TRANSPOSE1" "BIT_REVERSE" "RANDOM" "HOTSPOT" - do - for CONGESTION_INDEX in 12 #0 1 2 3 - do - - run_sim - - done - done - done #PACKET_SIZE - -done -
verilator_multiple/pronoc/pronoc.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: model.tcl =================================================================== --- model.tcl (revision 34) +++ model.tcl (revision 38) @@ -116,7 +116,7 @@ set text "###################################################################" -#vsim -t ps work.testbench_noc +#vsim -t ps work.testbench_router vsim -t ps work.testbench_modelsim run 100 ms
/parameter.sh
12,7 → 12,7
# NoC parameters:
V=2 # number of VC per port
TOPOLOGY="MESH" #"MESH" or "TORUS"
P="(TOPOLOGY==\"RING\")? 3 : 5" # number of port per router
P="localparam P= (TOPOLOGY==\"RING\" || TOPOLOGY==\"LINE\")? 3 : 5" # number of port per router
B=4 # buffer space :flit per VC
NX=8 # number of node in x axis
NY=8 # number of node in y axis
30,8 → 30,9
CLASS_SETTING="{CVw{1'b1}}"
SSA_EN="NO"
SSA_EN="NO" # "YES","NO"
SWA_ARBITER_TYPE="RRA" # "RRA" ,"WRRA"
WEIGHTw=4
ADD_PIPREG_AFTER_CROSSBAR=0
129,7 → 130,9
printf " parameter CVw=(C==0)? V : C * V;\n" >> parameter.v
printf " parameter [CVw-1: 0] CLASS_SETTING = $CLASS_SETTING;\n">> parameter.v
printf " parameter [V-1 : 0] ESCAP_VC_MASK=$ESCAP_VC_MASK;\n" >> parameter.v
printf " parameter SSA_EN= \"$SSA_EN\";\n">> parameter.v
printf " parameter SSA_EN= \"$SSA_EN\";\n">> parameter.v
printf " parameter SWA_ARBITER_TYPE=\"$SWA_ARBITER_TYPE\";\n">> parameter.v
printf " parameter WEIGHTw=$WEIGHTw;\n">> parameter.v
printf " \n\n \`endif " >> parameter.v
150,10 → 153,10
printf "\t #define FIRST_ARBITER_EXT_P_EN $FIRST_ARBITER_EXT_P_EN\n" >> parameter.h
printf "\t #define TOPOLOGY \"$TOPOLOGY\"\n" >> parameter.h
printf "\t #define ROUTE_NAME \"$ROUTE_NAME\"\n" >> parameter.h
printf "\t #define C0_p $C0_p\n" >> parameter.h
printf "\t #define C1_p $C1_p\n" >> parameter.h
printf "\t #define C2_p $C2_p\n" >> parameter.h
printf "\t #define C3_p $C3_p\n" >> parameter.h
printf "\t #define C0_p $C0_p\n" >> parameter.h
printf "\t #define C1_p $C1_p\n" >> parameter.h
printf "\t #define C2_p $C2_p\n" >> parameter.h
printf "\t #define C3_p $C3_p\n" >> parameter.h
printf "\t #define TRAFFIC \"$TRAFFIC\"\n" >> parameter.h
printf "\t #define HOTSPOT_PERCENTAGE $HOTSPOT_PERCENTAGE\n" >> parameter.h
printf "\t #define HOTSOPT_NUM $HOTSOPT_NUM\n" >> parameter.h
172,12 → 175,14
printf "\t #define AVC_ATOMIC_EN $AVC_ATOMIC_EN\n" >> parameter.h
printf "\t #define CONGESTION_INDEX $CONGESTION_INDEX\n">>parameter.h
printf "\t #define STND_DEV_EN $STND_DEV_EN\n">> parameter.h
printf "\t #define AVG_LATENCY_METRIC \"$AVG_LATENCY_METRIC\"\n">> parameter.h
printf "\t #define ADD_PIPREG_AFTER_CROSSBAR $ADD_PIPREG_AFTER_CROSSBAR\n" >> parameter.h
printf "\t #define CVw (C==0)? V : C * V\n" >> parameter.h
printf "\t #define CLASS_SETTING \"$CLASS_SETTING\"\n">> parameter.h
printf "\t #define ESCAP_VC_MASK $ESCAP_VC_MASK\n">> parameter.h
printf "\t #define SSA_EN \"$SSA_EN\"\n" >> parameter.h
printf "\t #define AVG_LATENCY_METRIC \"$AVG_LATENCY_METRIC\"\n">> parameter.h
printf "\t #define ADD_PIPREG_AFTER_CROSSBAR $ADD_PIPREG_AFTER_CROSSBAR\n" >> parameter.h
printf "\t #define CVw (C==0)? V : C * V\n" >> parameter.h
printf "\t #define CLASS_SETTING \"$CLASS_SETTING\"\n">> parameter.h
printf "\t #define ESCAP_VC_MASK $ESCAP_VC_MASK\n">> parameter.h
printf "\t #define SSA_EN \"$SSA_EN\"\n" >> parameter.h
printf "\t #define SWA_ARBITER_TYPE \"$SWA_ARBITER_TYPE\"\n">> parameter.h
printf "\t #define WEIGHTw=$WEIGHTw\n">> parameter.h
printf " \n\n #endif " >> parameter.h
}
/run_modelsim
1,6 → 1,5
#!/bin/sh
#/home/alireza/modelsim/modeltech/bin/vsim -c -do model.tcl
#/home/alireza/modelsim/modeltech/bin/vsim -do model.tcl
#/home/alireza/altera/13.0sp1/modelsim_ase/bin/vsim -do model.tcl
/home/alireza/altera/modelsim_ase/bin/vsim -do model.tcl
 
/home/alireza/altera/13.0sp1/modelsim_ase/bin/vsim -do model.tcl
#/home/alireza/altera/modeltech/bin/vsim -do model.tcl
 
/transcript
4,114 → 4,160
###################################################################
###################################################################
##---- Specify variables
# /home/alireza/Mywork/mpsoc/script/..
# /home/alireza/Mywork/mpsoc/script/../src_noc
# /home/alireza/Mywork/mpsoc/script/../src_modelsim
# /home/alireza/Mywork/mpsoc/script/../../mpsoc_work/modelsim
# /home/alireza/Mywork/mpsoc/script/../../mpsoc_work/modelsim/work
# /home/alireza/Mywork/mpsoc/script/../src_noc/combined_vc_sw_alloc.v /home/alireza/Mywork/mpsoc/script/../src_noc/comb-spec1.v /home/alireza/Mywork/mpsoc/script/../src_noc/arbiter.v /home/alireza/Mywork/mpsoc/script/../src_noc/noc.v /home/alireza/Mywork/mpsoc/script/../src_noc/agent.v /home/alireza/Mywork/mpsoc/script/../src_noc/route_torus.v /home/alireza/Mywork/mpsoc/script/../src_noc/inout_ports.v /home/alireza/Mywork/mpsoc/script/../src_noc/router.v /home/alireza/Mywork/mpsoc/script/../src_noc/class_table.v /home/alireza/Mywork/mpsoc/script/../src_noc/vc_alloc_request_gen.v /home/alireza/Mywork/mpsoc/script/../src_noc/congestion_analyzer.v /home/alireza/Mywork/mpsoc/script/../src_noc/credit_count.v /home/alireza/Mywork/mpsoc/script/../src_noc/traffic_gen_old.v /home/alireza/Mywork/mpsoc/script/../src_noc/comb_spec2.v /home/alireza/Mywork/mpsoc/script/../src_noc/comb_nonspec.v /home/alireza/Mywork/mpsoc/script/../src_noc/routing.v /home/alireza/Mywork/mpsoc/script/../src_noc/crossbar.v /home/alireza/Mywork/mpsoc/script/../src_noc/main_comp.v /home/alireza/Mywork/mpsoc/script/../src_noc/traffic_gen.v /home/alireza/Mywork/mpsoc/script/../src_noc/baseline.v /home/alireza/Mywork/mpsoc/script/../src_noc/flit_buffer.v /home/alireza/Mywork/mpsoc/script/../src_noc/canonical_credit_count.v /home/alireza/Mywork/mpsoc/script/../src_noc/flit_buffer_vlsi.v /home/alireza/Mywork/mpsoc/script/../src_noc/input_ports.v /home/alireza/Mywork/mpsoc/script/../src_noc/route_mesh.v
# /home/alireza/Mywork/mpsoc/script/../src_modelsim/traffic_pattern.v /home/alireza/Mywork/mpsoc/script/../src_modelsim/testbench_modelsim.v /home/alireza/Mywork/mpsoc/script/../src_modelsim/random_num.v /home/alireza/Mywork/mpsoc/script/../src_modelsim/testbench_router.v /home/alireza/Mywork/mpsoc/script/../src_modelsim/random.v
# /home/alireza/mywork/mpsoc/script/..
# /home/alireza/mywork/mpsoc/script/../src_noc
# /home/alireza/mywork/mpsoc/script/../src_modelsim
# /home/alireza/mywork/mpsoc/script/../../mpsoc_work/modelsim
# /home/alireza/mywork/mpsoc/script/../../mpsoc_work/modelsim/work
# /home/alireza/mywork/mpsoc/script/../src_noc/crossbar.v /home/alireza/mywork/mpsoc/script/../src_noc/route_mesh.v /home/alireza/mywork/mpsoc/script/../src_noc/canonical_credit_count.v /home/alireza/mywork/mpsoc/script/../src_noc/traffic_gen.v /home/alireza/mywork/mpsoc/script/../src_noc/inout_ports.v /home/alireza/mywork/mpsoc/script/../src_noc/router.v /home/alireza/mywork/mpsoc/script/../src_noc/wrra.v /home/alireza/mywork/mpsoc/script/../src_noc/main_comp.v /home/alireza/mywork/mpsoc/script/../src_noc/ss_allocator.v /home/alireza/mywork/mpsoc/script/../src_noc/flit_buffer.v /home/alireza/mywork/mpsoc/script/../src_noc/credit_count.v /home/alireza/mywork/mpsoc/script/../src_noc/input_ports.v /home/alireza/mywork/mpsoc/script/../src_noc/congestion_analyzer.v /home/alireza/mywork/mpsoc/script/../src_noc/route_torus.v /home/alireza/mywork/mpsoc/script/../src_noc/class_table.v /home/alireza/mywork/mpsoc/script/../src_noc/noc.v /home/alireza/mywork/mpsoc/script/../src_noc/baseline.v /home/alireza/mywork/mpsoc/script/../src_noc/comb_nonspec.v /home/alireza/mywork/mpsoc/script/../src_noc/arbiter.v /home/alireza/mywork/mpsoc/script/../src_noc/comb_spec2.v /home/alireza/mywork/mpsoc/script/../src_noc/combined_vc_sw_alloc.v /home/alireza/mywork/mpsoc/script/../src_noc/vc_alloc_request_gen.v /home/alireza/mywork/mpsoc/script/../src_noc/routing.v /home/alireza/mywork/mpsoc/script/../src_noc/comb-spec1.v
# /home/alireza/mywork/mpsoc/script/../src_modelsim/traffic_pattern.v /home/alireza/mywork/mpsoc/script/../src_modelsim/random_num.v /home/alireza/mywork/mpsoc/script/../src_modelsim/testbench_router.v /home/alireza/mywork/mpsoc/script/../src_modelsim/testbench_modelsim.v /home/alireza/mywork/mpsoc/script/../src_modelsim/random.v
# reading modelsim.ini
# 1
# 0
###################################################################
##---- 1. Creating working library
# ** Warning: (vlib-34) Library already exists at "/home/alireza/Mywork/mpsoc/script/../../mpsoc_work/modelsim/work".
# ** Warning: (vlib-34) Library already exists at "/home/alireza/mywork/mpsoc/script/../../mpsoc_work/modelsim/work".
# Modifying modelsim.ini
###################################################################
##---- 3. Compile the Design
# 1444651849
# 1518690625
# 0
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module combined_vc_sw_alloc
# -- Compiling module crossbar
#
# Top level modules:
# combined_vc_sw_alloc
# crossbar
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module comb_spec1_allocator
# -- Compiling module spec_sw_alloc
# -- Compiling module sw_alloc_sub
# -- Compiling module xy_mesh_routing
# -- Compiling module west_first_routing
# -- Compiling module north_last_routing
# -- Compiling module negetive_first_routing
# -- Compiling module odd_even_routing
# -- Compiling module duato_mesh_routing
# -- Compiling module mesh_dir
#
# Top level modules:
# comb_spec1_allocator
# xy_mesh_routing
# west_first_routing
# north_last_routing
# negetive_first_routing
# odd_even_routing
# duato_mesh_routing
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module arbiter
# -- Compiling module arbiter_priority_en
# -- Compiling module my_one_hot_arbiter_priority_en
# -- Compiling module my_one_hot_arbiter
# -- Compiling module arbiter_2_one_hot
# -- Compiling module arbiter_3_one_hot
# -- Compiling module arbiter_4_one_hot
# -- Compiling module Dimitrakopoulos_arbiter_genvar
# -- Compiling module Dimitrakopoulos_arbiter
# -- Compiling module Dimitrakopoulos_arbiter_priority_en
# -- Compiling module tree_arbiter
# -- Compiling module Dimitrakopoulos_arbiter_ext_priority
# -- Compiling module my_one_hot_arbiter_ext_priority
# -- Compiling module arbiter_ext_priority
# -- Compiling module canonical_credit_counter
# -- Compiling module inport_module_can
# -- Compiling module sw_mask_gen_can
#
# Top level modules:
# arbiter_priority_en
# Dimitrakopoulos_arbiter_genvar
# tree_arbiter
# my_one_hot_arbiter_ext_priority
# arbiter_ext_priority
# canonical_credit_counter
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module noc
# -- Compiling module traffic_gen
# -- Compiling module injection_ratio_ctrl
# -- Compiling module packet_gen
# -- Compiling module distance_gen
#
# Top level modules:
# noc
# traffic_gen
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module agent
# -- Compiling module inout_ports
# -- Compiling module output_vc_status
#
# Top level modules:
# agent
# inout_ports
# output_vc_status
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module tranc_xy_routing
# -- Compiling module tranc_west_first_routing
# -- Compiling module tranc_north_last_routing
# -- Compiling module tranc_negetive_first_routing
# -- Compiling module tranc_duato_routing
# -- Compiling module tranc_dir
# -- Compiling module router
#
# Top level modules:
# tranc_xy_routing
# tranc_west_first_routing
# tranc_north_last_routing
# tranc_negetive_first_routing
# tranc_duato_routing
# router
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module inout_ports
# -- Compiling module wrra
# -- Compiling module rra_priority_lock
# -- Compiling module weight_counter
# -- Compiling module classic_weight_counter
# -- Compiling module weight_control
# -- Compiling module wrra_contention_gen
# -- Compiling module wrra_inputport_destports_sum
# -- Compiling module weights_update
# -- Compiling module weight_update_per_port
# -- Compiling module output_weight_latch
# -- Compiling module accumulator
#
# Top level modules:
# inout_ports
# wrra
# rra_priority_lock
# weight_control
# wrra_contention_gen
# weights_update
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module router
# -- Compiling module router_test
# -- Compiling module one_hot_mux
# -- Compiling module one_hot_demux
# -- Compiling module custom_or
# -- Compiling module outport_sum
# -- Compiling module bin_to_one_hot
# -- Compiling module one_hot_to_bin
# -- Compiling module binary_mux
# -- Compiling module set_bits_counter
# -- Compiling module check_single_bit_assertation
# -- Compiling module fast_minimum_number
# -- Compiling module parallel_counter
# -- Compiling module CS_GEN
# -- Compiling module PC_7_3
# -- Compiling module PC_15_4
# -- Compiling module PC_31_5
# -- Compiling module PC_63_6
# -- Compiling module PC_127_7
#
# Top level modules:
# router_test
# one_hot_demux
# custom_or
# outport_sum
# bin_to_one_hot
# one_hot_to_bin
# binary_mux
# set_bits_counter
# check_single_bit_assertation
# fast_minimum_number
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module class_ovc_table
# -- Compiling module vc_priority_based_dest_port
# -- Compiling module ss_allocator
# -- Compiling module ssa_per_vc
# -- Compiling module add_ss_port
#
# Top level modules:
# class_ovc_table
# vc_priority_based_dest_port
# ss_allocator
# add_ss_port
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module vc_alloc_request_gen_determinstic
# -- Compiling module vc_alloc_request_gen_adaptive
# -- Compiling module swap_port_presel_gen
# -- Compiling module adaptive_avb_ovc_mux
# -- Compiling module port_selector
# -- Compiling module vc_alloc_request_gen_adaptive_classic
# -- Compiling module portsel_classic
# -- Compiling module flit_buffer
# -- Compiling module fifo_ram
# -- Compiling module fifo_ram_mem_size
# -- Compiling module fwft_fifo
# -- Compiling module fwft_fifo_with_output_clear
# -- Compiling module fifo
#
# Top level modules:
# vc_alloc_request_gen_determinstic
# vc_alloc_request_gen_adaptive
# vc_alloc_request_gen_adaptive_classic
# flit_buffer
# fwft_fifo
# fwft_fifo_with_output_clear
# fifo
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module credit_counter
# -- Compiling module inport_module
# -- Compiling module sw_mask_gen
# -- Compiling module check_ovc
#
# Top level modules:
# credit_counter
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module input_ports
# -- Compiling module input_queue_per_port
# -- Compiling module flit_update
# -- Compiling module flit_update_dtrmn
# -- Compiling module flit_update_adaptive
# -- Compiling module extract_header_flit_info
#
# Top level modules:
# input_ports
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module port_presel_based_dst_ports_vc
# -- Compiling module port_presel_based_dst_ports_credit
# -- Compiling module port_presel_based_dst_routers_vc
134,36 → 180,96
# congestion_out_gen
# deadlock_detector
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module credit_counter
# -- Compiling module inport_module
# -- Compiling module sw_mask_gen
# -- Compiling module check_ovc
# -- Compiling module tranc_xy_routing
# -- Compiling module tranc_west_first_routing
# -- Compiling module tranc_north_last_routing
# -- Compiling module tranc_negetive_first_routing
# -- Compiling module tranc_duato_routing
# -- Compiling module tranc_dir
#
# Top level modules:
# credit_counter
# tranc_xy_routing
# tranc_west_first_routing
# tranc_north_last_routing
# tranc_negetive_first_routing
# tranc_duato_routing
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module traffic_gen_old
# -- Compiling module send_traffic
# -- Compiling module class_ovc_table
# -- Compiling module vc_priority_based_dest_port
#
# Top level modules:
# traffic_gen_old
# class_ovc_table
# vc_priority_based_dest_port
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module comb_spec2_allocator
# -- Compiling module spec_sw_alloc2
# -- Compiling module sw_alloc_sub2
# -- Compiling module spec_sw_alloc_sub2
# -- Compiling module noc
#
# Top level modules:
# comb_spec2_allocator
# noc
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module baseline_allocator
# -- Compiling module canonical_vc_alloc
# -- Compiling module spec_sw_alloc_can
#
# Top level modules:
# baseline_allocator
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module comb_nonspec_allocator
# -- Compiling module comb_nonspec_v2_allocator
# -- Compiling module nonspec_sw_alloc
# -- Compiling module swa_input_port_arbiter
# -- Compiling module swa_output_port_arbiter
#
# Top level modules:
# comb_nonspec_allocator
# comb_nonspec_v2_allocator
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module arbiter
# -- Compiling module arbiter_priority_en
# -- Compiling module my_one_hot_arbiter
# -- Compiling module arbiter_2_one_hot
# -- Compiling module arbiter_3_one_hot
# -- Compiling module arbiter_4_one_hot
# -- Compiling module my_one_hot_arbiter_priority_en
# -- Compiling module thermo_gen
# -- Compiling module thermo_arbiter
# -- Compiling module thermo_arbiter_priority_en
# -- Compiling module thermo_arbiter_ext_priority
# -- Compiling module tree_arbiter
# -- Compiling module my_one_hot_arbiter_ext_priority
# -- Compiling module arbiter_ext_priority
#
# Top level modules:
# arbiter_priority_en
# tree_arbiter
# my_one_hot_arbiter_ext_priority
# arbiter_ext_priority
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module comb_spec2_allocator
# -- Compiling module spec_sw_alloc2
# -- Compiling module sw_alloc_sub2
# -- Compiling module spec_sw_alloc_sub2
#
# Top level modules:
# comb_spec2_allocator
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module combined_vc_sw_alloc
#
# Top level modules:
# combined_vc_sw_alloc
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module vc_alloc_request_gen_determinstic
# -- Compiling module vc_alloc_request_gen_adaptive
# -- Compiling module swap_port_presel_gen
# -- Compiling module adaptive_avb_ovc_mux
# -- Compiling module port_selector
# -- Compiling module vc_alloc_request_gen_adaptive_classic
# -- Compiling module portsel_classic
#
# Top level modules:
# vc_alloc_request_gen_determinstic
# vc_alloc_request_gen_adaptive
# vc_alloc_request_gen_adaptive_classic
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module look_ahead_routing
# -- Compiling module deterministic_look_ahead_routing
# -- Compiling module adaptive_look_ahead_routing
174,118 → 280,35
# -- Compiling module add_sw_loc_one_hot
# -- Compiling module conventional_routing
# -- Compiling module ni_conventional_routing
# -- Compiling module tranc_ring_routing
# -- Compiling module xy_line_routing
#
# Top level modules:
# look_ahead_routing
# remove_sw_loc_one_hot
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module crossbar
# -- Compiling module comb_spec1_allocator
# -- Compiling module spec_sw_alloc
# -- Compiling module sw_alloc_sub
#
# Top level modules:
# crossbar
# comb_spec1_allocator
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module one_hot_mux
# -- Compiling module one_hot_demux
# -- Compiling module custom_or
# -- Compiling module outport_sum
# -- Compiling module bin_to_one_hot
# -- Compiling module one_hot_to_bin
# -- Compiling module binary_mux
# -- Compiling module set_bits_counter
# -- Compiling module check_single_bit_assertation
# -- Compiling module fast_minimum_number
# -- Compiling module parallel_counter
# -- Compiling module CS_GEN
# -- Compiling module PC_7_3
# -- Compiling module PC_15_4
# -- Compiling module PC_31_5
# -- Compiling module PC_63_6
# -- Compiling module PC_127_7
# -- Compiling module pck_class_in_gen
# -- Compiling module pck_dst_gen
# -- Compiling module two_dimention_pck_dst_gen
# -- Compiling module one_dimention_pck_dst_gen
#
# Top level modules:
# one_hot_demux
# custom_or
# outport_sum
# bin_to_one_hot
# one_hot_to_bin
# binary_mux
# set_bits_counter
# check_single_bit_assertation
# fast_minimum_number
# pck_class_in_gen
# pck_dst_gen
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module traffic_gen
# -- Compiling module injection_ratio_ctrl
# -- Compiling module packet_gen
# -- Compiling module distance_gen
# -- Compiling module output_vc_status
#
# Top level modules:
# traffic_gen
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module baseline_allocator
# -- Compiling module canonical_vc_alloc
# -- Compiling module spec_sw_alloc_can
# -- Compiling module testbench_router
#
# Top level modules:
# baseline_allocator
# testbench_router
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module flit_buffer
# -- Compiling module fifo_ram
# -- Compiling module fifo_ram_mem_size
# -- Compiling module fwft_fifo
# -- Compiling module fifo
#
# Top level modules:
# flit_buffer
# fwft_fifo
# fifo
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module canonical_credit_counter
# -- Compiling module inport_module_can
# -- Compiling module sw_mask_gen_can
#
# Top level modules:
# canonical_credit_counter
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module flit_buffer_vlsi
# -- Compiling module fifo_ram_diff_edge
# -- Compiling module fifo_ram_mem_size_diff_edge
#
# Top level modules:
# flit_buffer_vlsi
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module input_ports
# -- Compiling module input_queue_per_port
# -- Compiling module flit_update
# -- Compiling module flit_update_dtrmn
# -- Compiling module flit_update_adaptive
#
# Top level modules:
# input_ports
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module xy_mesh_routing
# -- Compiling module west_first_routing
# -- Compiling module north_last_routing
# -- Compiling module negetive_first_routing
# -- Compiling module odd_even_routing
# -- Compiling module duato_mesh_routing
# -- Compiling module mesh_dir
#
# Top level modules:
# xy_mesh_routing
# west_first_routing
# north_last_routing
# negetive_first_routing
# odd_even_routing
# duato_mesh_routing
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module pck_class_in_gen
# -- Compiling module pck_dst_gen
#
# Top level modules:
# pck_class_in_gen
# pck_dst_gen
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module testbench_modelsim
# -- Compiling module testbench_sub
#
292,12 → 315,6
# Top level modules:
# testbench_modelsim
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module testbench_router
#
# Top level modules:
# testbench_router
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module pseudo_hotspot_no_core
# -- Compiling module pseudo_hotspot
# -- Compiling module pseudo_random
309,7 → 326,7
# pseudo_hotspot_no_core
# pseudo_hotspot
# pseudo_random_gen
# 1444651849
# 1518690625
###################################################################
## END OF COMPILATION
###################################################################
331,50 → 348,52
# Loading work.ni_conventional_routing
# Loading work.conventional_routing
# Loading work.fifo
# Loading work.extract_header_flit_info
# Loading work.distance_gen
# Loading work.one_hot_to_bin
# Loading work.pck_class_in_gen
# Loading work.pseudo_random
# Loading work.pck_dst_gen
# Loading work.congestion_out_based_avb_ovc_not_granted_ivc
# Loading work.input_queue_per_port
# Loading work.look_ahead_routing
# Loading work.flit_update
# Loading work.credit_counter
# Loading work.port_pre_sel_gen
# Loading work.vc_alloc_request_gen_adaptive
# Loading work.vc_alloc_request_gen_determinstic
# Loading work.comb_nonspec_allocator
# Loading work.nonspec_sw_alloc
# Loading work.one_hot_mux
# Loading work.add_sw_loc_one_hot
# Loading work.arbiter
# Loading work.duato_mesh_routing
# Loading work.mesh_dir
# Loading work.pseudo_random
# Loading work.pseudo_random_no_core
# Loading work.parallel_counter
# Loading work.normalizer
# Loading work.adaptive_look_ahead_routing
# Loading work.xy_mesh_routing
# Loading work.one_hot_to_bin
# Loading work.two_dimention_pck_dst_gen
# Loading work.deterministic_look_ahead_routing
# Loading work.next_router_addr_predictor
# Loading work.flit_update_adaptive
# Loading work.next_router_inport_predictor
# Loading work.remove_receive_port_one_hot
# Loading work.bin_to_one_hot
# Loading work.flit_update_dtrmn
# Loading work.class_ovc_table
# Loading work.fwft_fifo
# Loading work.flit_buffer_vlsi
# Loading work.port_presel_based_dst_routers_vc
# Loading work.flit_buffer
# Loading work.inport_module
# Loading work.one_hot_demux
# Loading work.sw_mask_gen
# Loading work.parallel_counter
# Loading work.check_ovc
# Loading work.adaptive_avb_ovc_mux
# Loading work.port_selector
# Loading work.remove_sw_loc_one_hot
# Loading work.swap_port_presel_gen
# Loading work.swa_input_port_arbiter
# Loading work.swa_output_port_arbiter
# Loading work.my_one_hot_arbiter
# Loading work.fifo_ram
# Loading work.PC_15_4
# Loading work.CS_GEN
# Loading work.PC_7_3
# Loading work.fifo_ram_mem_size_diff_edge
# Loading work.PC_31_5
# Loading work.arbiter_priority_en
# Loading work.arbiter_2_one_hot
# Loading work.my_one_hot_arbiter_priority_en
# Loading work.arbiter_4_one_hot
# ** Warning: Design size of 61 instances exceeds ModelSim ALTERA recommended capacity.
# This may because you are loading cell libraries which are not recommended with
# the ModelSim Altera version. Expect performance to be adversely affected.
# Break key hit
# Simulation stop requested.
/verilator_compile_simulator.sh
16,7 → 16,7
rm -rf $work_path/bin/testbench
cp Makefile $obj_dir_path
cp $src_verilator_path/simulator.cpp $obj_dir_path/testbench.cpp
cp $src_verilator_path/simulator2.cpp $obj_dir_path/testbench.cpp
cp $src_verilator_path/parameter.h $obj_dir_path
cd $obj_dir_path
make sim

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