URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb
- from Rev 38 to Rev 48
- ↔ Reverse comparison
Rev 38 → Rev 48
/vjtag_wb.v
93,8 → 93,12
); |
|
|
`ifdef SYNC_RESET_MODE |
always @ (posedge clk )begin |
`else |
always @ (posedge clk or posedge reset)begin |
`endif |
|
always @(posedge clk or posedge reset) begin |
if(reset) begin |
wb_addr <= {AW{1'b0}}; |
wb_wr_data <= {DW{1'b0}}; |
232,10 → 236,12
assign data_out = shift_buffer; |
|
|
|
|
always @(posedge tck or posedge reset) |
begin |
`ifdef SYNC_RESET_MODE |
always @ (posedge tck )begin |
`else |
always @ (posedge tck or posedge reset)begin |
`endif |
|
if (reset)begin |
ir <= 3'b000; |
bypass_reg<=1'b0; |
283,9 → 289,13
|
reg wb_wr_addr2, wb_wr_data2, wb_rd_data2; |
reg wb_wr_addr3, wb_wr_data3, wb_rd_data3; |
|
`ifdef SYNC_RESET_MODE |
always @ (posedge clk )begin |
`else |
always @ (posedge clk or posedge reset)begin |
`endif |
|
always @(posedge clk or posedge reset) |
begin |
if( reset ) begin |
wb_wr_addr2<=1'b0; |
wb_wr_data2<=1'b0; |