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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/src_verilog/lib
    from Rev 38 to Rev 48
    ↔ Reverse comparison
  •

Rev 38 → Rev 48

/arbiter.v
208,8 → 208,12
);
always@(posedge clk or posedge reset) begin
`ifdef SYNC_RESET_MODE
always @ (posedge clk )begin
`else
always @ (posedge clk or posedge reset)begin
`endif
 
if(reset) begin
low_pr <= {ARBITER_BIN_WIDTH{1'b0}};
end else begin
352,8 → 356,13
.one_hot_code(grant),
.bin_code(grant_bcd)
);
always@(posedge clk or posedge reset) begin
 
`ifdef SYNC_RESET_MODE
always @ (posedge clk )begin
`else
always @ (posedge clk or posedge reset)begin
`endif
if(reset) begin
low_pr <= {ARBITER_BIN_WIDTH{1'b0}};
end else begin
445,23 → 454,26
);
 
assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
assign masked_request= request & pr;
assign any_grant=termo1[ARBITER_WIDTH-1];
assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
assign masked_request= request & pr;
assign any_grant=termo1[ARBITER_WIDTH-1];
 
always @(posedge clk or posedge reset)begin
if(reset) pr<= {ARBITER_WIDTH{1'b1}};
else begin
if(any_grant) pr<= edge_mask;
`ifdef SYNC_RESET_MODE
always @ (posedge clk )begin
`else
always @ (posedge clk or posedge reset)begin
`endif
if(reset) pr<= {ARBITER_WIDTH{1'b1}};
else begin
if(any_grant) pr<= edge_mask;
end
end
 
end
assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
assign grant= mux_out ^ edge_mask;
 
assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
assign grant= mux_out ^ edge_mask;
 
 
 
endmodule
518,7 → 530,13
assign masked_request= request & pr;
assign any_grant=termo1[ARBITER_WIDTH-1];
 
always @(posedge clk or posedge reset)begin
`ifdef SYNC_RESET_MODE
always @ (posedge clk )begin
`else
always @ (posedge clk or posedge reset)begin
`endif
 
if(reset) pr<= {ARBITER_WIDTH{1'b1}};
else begin
if(priority_en) pr<= edge_mask;
/generic_ram.v
54,8 → 54,10
q_b
);
 
/* verilator lint_off WIDTH */
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
 
/* verilator lint_on WIDTH */
input [(Dw-1):0] data_a, data_b;
input [(Aw-1):0] addr_a, addr_b;
input [BYTE_ENw-1 : 0] byteena_a, byteena_b;
63,8 → 65,9
output [(Dw-1):0] q_a, q_b;
generate
/* verilator lint_off WIDTH */
if ( BYTE_WR_EN == "NO") begin : no_byten
 
/* verilator lint_on WIDTH */
dual_port_ram #(
.Dw (Dw),
.Aw (Aw),
140,9 → 143,10
q
);
 
/* verilator lint_off WIDTH */
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
 
/* verilator lint_on WIDTH */
input [(Dw-1):0] data;
input [(Aw-1):0] addr;
input [BYTE_ENw-1 : 0] byteen;
150,8 → 154,9
output [(Dw-1):0] q;
generate
/* verilator lint_off WIDTH */
if ( BYTE_WR_EN == "NO") begin : no_byten
 
/* verilator lint_on WIDTH */
single_port_ram #(
.Dw (Dw),
249,7 → 254,9
 
// initial the memory if the file is defined
generate
/* verilator lint_off WIDTH */
if (INITIAL_EN == "YES") begin : init
/* verilator lint_on WIDTH */
initial $readmemh(INIT_FILE,ram);
end
endgenerate
328,7 → 335,9
 
// initial the memory if the file is defined
generate
/* verilator lint_off WIDTH */
if (INITIAL_EN == "YES") begin : init
/* verilator lint_on WIDTH */
initial $readmemh(INIT_FILE,ram);
end
endgenerate
388,7 → 397,9
 
// initial the memory if the file is defined
generate
/* verilator lint_off WIDTH */
if (INITIAL_EN == "YES") begin : init
/* verilator lint_on WIDTH */
initial $readmemh(INIT_FILE,ram);
end
endgenerate
/jtag_wb/vjtag_wb.v
93,8 → 93,12
);
`ifdef SYNC_RESET_MODE
always @ (posedge clk )begin
`else
always @ (posedge clk or posedge reset)begin
`endif
always @(posedge clk or posedge reset) begin
if(reset) begin
wb_addr <= {AW{1'b0}};
wb_wr_data <= {DW{1'b0}};
232,10 → 236,12
assign data_out = shift_buffer;
always @(posedge tck or posedge reset)
begin
`ifdef SYNC_RESET_MODE
always @ (posedge tck )begin
`else
always @ (posedge tck or posedge reset)begin
`endif
 
if (reset)begin
ir <= 3'b000;
bypass_reg<=1'b0;
283,9 → 289,13
reg wb_wr_addr2, wb_wr_data2, wb_rd_data2;
reg wb_wr_addr3, wb_wr_data3, wb_rd_data3;
 
`ifdef SYNC_RESET_MODE
always @ (posedge clk )begin
`else
always @ (posedge clk or posedge reset)begin
`endif
always @(posedge clk or posedge reset)
begin
if( reset ) begin
wb_wr_addr2<=1'b0;
wb_wr_data2<=1'b0;
/wb_single_port_ram.v
36,7 → 36,7
parameter Aw=10, //RAM address width
parameter BYTE_WR_EN= "YES",//"YES","NO"
parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC"
parameter JTAG_CONNECT= "JTAG_WB",//"DISABLED", "JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
parameter JTAG_CONNECT= "ALTERA_JTAG_WB",//"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
parameter JTAG_INDEX= 0,
parameter INITIAL_EN= "NO",
parameter MEM_CONTENT_FILE_NAME= "ram0",// ram initial file name
192,7 → 192,7
parameter Aw=10, //RAM address width
parameter BYTE_WR_EN= "YES",//"YES","NO"
parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC"
parameter JTAG_CONNECT= "JTAG_WB",//"DISABLED", "JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
parameter JTAG_CONNECT= "ALTERA_JTAG_WB",//"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
parameter JTAG_INDEX= 0,
parameter INITIAL_EN= "NO",
parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file
207,7 → 207,9
we_a,
q_a
);
/* verilator lint_off WIDTH */
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
/* verilator lint_on WIDTH */
input clk,reset;
input [Dw-1 : 0] data_a;
252,12 → 254,15
 
generate
/* verilator lint_off WIDTH */
if(FPGA_VENDOR=="ALTERA")begin:altera_fpga
/* verilator lint_on WIDTH */
localparam RAM_TAG_STRING=i2s(JTAG_INDEX);
localparam RAM_ID =(JTAG_CONNECT== "ALTERA_IMCE") ? {"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=",RAM_TAG_STRING}
: {"ENABLE_RUNTIME_MOD=NO"};
 
if(JTAG_CONNECT== "JTAG_WB")begin:dual_ram
/* verilator lint_off WIDTH */
if(JTAG_CONNECT== "ALTERA_JTAG_WB")begin:dual_ram
/* verilator lint_on WIDTH */
// aletra dual port ram
altsyncram #(
.operation_mode("BIDIR_DUAL_PORT"),
351,10 → 356,10
 
end
end
 
/* verilator lint_off WIDTH */
else if(FPGA_VENDOR=="GENERIC")begin:generic_ram
if(JTAG_CONNECT== "JTAG_WB")begin:dual_ram
if(JTAG_CONNECT== "ALTERA_JTAG_WB")begin:dual_ram
/* verilator lint_on WIDTH */
 
generic_dual_port_ram #(
.Dw(Dw),
405,9 → 410,9
end//jtag_wb
end //Generic
 
 
if(JTAG_CONNECT == "JTAG_WB")begin:jtag_wb
 
/* verilator lint_off WIDTH */
if(JTAG_CONNECT == "ALTERA_JTAG_WB")begin:jtag_wb
/* verilator lint_on WIDTH */
reg jtag_ack;
wire jtag_we_o, jtag_stb_o;
 
/wishbone_bus.v
479,7 → 479,12
 
assign comreq = |(grant & request);
 
always @ (posedge clk or posedge reset) begin
`ifdef SYNC_RESET_MODE
always @ (posedge clk )begin
`else
always @ (posedge clk or posedge reset)begin
`endif
if (reset) begin
grant_registered <= {M{1'b0}};
end else begin

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