URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/sw
- from Rev 38 to Rev 48
- ↔ Reverse comparison
Rev 38 → Rev 48
/README
35,7 → 35,7
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If the memory core and jtag_wb are connected to the same wishbone bus, you can program the memory using |
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sh program.sh |
bash program.sh |
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/jtag_intfc.sh
1,4 → 1,4
#!/bin/sh |
#!/bin/bash |
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HARDWARE_NAME="DE-SoC *" |
DEVICE_NAME="@2*" |
/program.sh
1,7 → 1,6
#!/bin/bash |
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#!/bin/sh |
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#JTAG_INTFC="$PRONOC_WORK/toolchain/bin/JTAG_INTFC" |
source ./jtag_intfc.sh |
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24,7 → 23,7
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#programe the memory |
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sh write_memory.sh |
bash write_memory.sh |
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#Enable the cpu |
/ram_test.h
5,7 → 5,7
/* ss */ |
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/* programer */ |
/* programmer */ |
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/* ram */ |
/write_memory.sh
1,4 → 1,4
#!/bin/sh |
#!/bin/bash |
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#JTAG_INTFC="$PRONOC_WORK/toolchain/bin/JTAG_INTFC" |
source ./jtag_intfc.sh |