URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_c/jtag/test_rtl
- from Rev 38 to Rev 48
- ↔ Reverse comparison
Rev 38 → Rev 48
/jtag_ram_test/src_verilog/lib/arbiter.v
208,8 → 208,12
); |
|
|
|
always@(posedge clk or posedge reset) begin |
`ifdef SYNC_RESET_MODE |
always @ (posedge clk )begin |
`else |
always @ (posedge clk or posedge reset)begin |
`endif |
|
if(reset) begin |
low_pr <= {ARBITER_BIN_WIDTH{1'b0}}; |
end else begin |
352,8 → 356,13
.one_hot_code(grant), |
.bin_code(grant_bcd) |
); |
|
always@(posedge clk or posedge reset) begin |
|
`ifdef SYNC_RESET_MODE |
always @ (posedge clk )begin |
`else |
always @ (posedge clk or posedge reset)begin |
`endif |
|
if(reset) begin |
low_pr <= {ARBITER_BIN_WIDTH{1'b0}}; |
end else begin |
445,23 → 454,26
); |
|
|
assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1; |
assign masked_request= request & pr; |
assign any_grant=termo1[ARBITER_WIDTH-1]; |
assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1; |
assign masked_request= request & pr; |
assign any_grant=termo1[ARBITER_WIDTH-1]; |
|
always @(posedge clk or posedge reset)begin |
if(reset) pr<= {ARBITER_WIDTH{1'b1}}; |
else begin |
if(any_grant) pr<= edge_mask; |
`ifdef SYNC_RESET_MODE |
always @ (posedge clk )begin |
`else |
always @ (posedge clk or posedge reset)begin |
`endif |
if(reset) pr<= {ARBITER_WIDTH{1'b1}}; |
else begin |
if(any_grant) pr<= edge_mask; |
end |
end |
|
end |
assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0}; |
assign grant= mux_out ^ edge_mask; |
|
assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0}; |
assign grant= mux_out ^ edge_mask; |
|
|
|
endmodule |
|
|
518,7 → 530,13
assign masked_request= request & pr; |
assign any_grant=termo1[ARBITER_WIDTH-1]; |
|
always @(posedge clk or posedge reset)begin |
`ifdef SYNC_RESET_MODE |
always @ (posedge clk )begin |
`else |
always @ (posedge clk or posedge reset)begin |
`endif |
|
|
if(reset) pr<= {ARBITER_WIDTH{1'b1}}; |
else begin |
if(priority_en) pr<= edge_mask; |
/jtag_ram_test/src_verilog/lib/generic_ram.v
54,8 → 54,10
q_b |
); |
|
/* verilator lint_off WIDTH */ |
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1; |
|
/* verilator lint_on WIDTH */ |
|
input [(Dw-1):0] data_a, data_b; |
input [(Aw-1):0] addr_a, addr_b; |
input [BYTE_ENw-1 : 0] byteena_a, byteena_b; |
63,8 → 65,9
output [(Dw-1):0] q_a, q_b; |
|
generate |
/* verilator lint_off WIDTH */ |
if ( BYTE_WR_EN == "NO") begin : no_byten |
|
/* verilator lint_on WIDTH */ |
dual_port_ram #( |
.Dw (Dw), |
.Aw (Aw), |
140,9 → 143,10
q |
|
); |
|
/* verilator lint_off WIDTH */ |
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1; |
|
/* verilator lint_on WIDTH */ |
|
input [(Dw-1):0] data; |
input [(Aw-1):0] addr; |
input [BYTE_ENw-1 : 0] byteen; |
150,8 → 154,9
output [(Dw-1):0] q; |
|
generate |
/* verilator lint_off WIDTH */ |
if ( BYTE_WR_EN == "NO") begin : no_byten |
|
/* verilator lint_on WIDTH */ |
|
single_port_ram #( |
.Dw (Dw), |
249,7 → 254,9
|
// initial the memory if the file is defined |
generate |
/* verilator lint_off WIDTH */ |
if (INITIAL_EN == "YES") begin : init |
/* verilator lint_on WIDTH */ |
initial $readmemh(INIT_FILE,ram); |
end |
endgenerate |
328,7 → 335,9
|
// initial the memory if the file is defined |
generate |
/* verilator lint_off WIDTH */ |
if (INITIAL_EN == "YES") begin : init |
/* verilator lint_on WIDTH */ |
initial $readmemh(INIT_FILE,ram); |
end |
endgenerate |
388,7 → 397,9
|
// initial the memory if the file is defined |
generate |
/* verilator lint_off WIDTH */ |
if (INITIAL_EN == "YES") begin : init |
/* verilator lint_on WIDTH */ |
initial $readmemh(INIT_FILE,ram); |
end |
endgenerate |
/jtag_ram_test/src_verilog/lib/jtag_wb/vjtag_wb.v
93,8 → 93,12
); |
|
|
`ifdef SYNC_RESET_MODE |
always @ (posedge clk )begin |
`else |
always @ (posedge clk or posedge reset)begin |
`endif |
|
always @(posedge clk or posedge reset) begin |
if(reset) begin |
wb_addr <= {AW{1'b0}}; |
wb_wr_data <= {DW{1'b0}}; |
232,10 → 236,12
assign data_out = shift_buffer; |
|
|
|
|
always @(posedge tck or posedge reset) |
begin |
`ifdef SYNC_RESET_MODE |
always @ (posedge tck )begin |
`else |
always @ (posedge tck or posedge reset)begin |
`endif |
|
if (reset)begin |
ir <= 3'b000; |
bypass_reg<=1'b0; |
283,9 → 289,13
|
reg wb_wr_addr2, wb_wr_data2, wb_rd_data2; |
reg wb_wr_addr3, wb_wr_data3, wb_rd_data3; |
|
`ifdef SYNC_RESET_MODE |
always @ (posedge clk )begin |
`else |
always @ (posedge clk or posedge reset)begin |
`endif |
|
always @(posedge clk or posedge reset) |
begin |
if( reset ) begin |
wb_wr_addr2<=1'b0; |
wb_wr_data2<=1'b0; |
/jtag_ram_test/src_verilog/lib/wb_single_port_ram.v
36,7 → 36,7
parameter Aw=10, //RAM address width |
parameter BYTE_WR_EN= "YES",//"YES","NO" |
parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC" |
parameter JTAG_CONNECT= "JTAG_WB",//"DISABLED", "JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb |
parameter JTAG_CONNECT= "ALTERA_JTAG_WB",//"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb |
parameter JTAG_INDEX= 0, |
parameter INITIAL_EN= "NO", |
parameter MEM_CONTENT_FILE_NAME= "ram0",// ram initial file name |
192,7 → 192,7
parameter Aw=10, //RAM address width |
parameter BYTE_WR_EN= "YES",//"YES","NO" |
parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC" |
parameter JTAG_CONNECT= "JTAG_WB",//"DISABLED", "JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb |
parameter JTAG_CONNECT= "ALTERA_JTAG_WB",//"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb |
parameter JTAG_INDEX= 0, |
parameter INITIAL_EN= "NO", |
parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file |
207,7 → 207,9
we_a, |
q_a |
); |
/* verilator lint_off WIDTH */ |
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1; |
/* verilator lint_on WIDTH */ |
|
input clk,reset; |
input [Dw-1 : 0] data_a; |
252,12 → 254,15
|
|
generate |
/* verilator lint_off WIDTH */ |
if(FPGA_VENDOR=="ALTERA")begin:altera_fpga |
/* verilator lint_on WIDTH */ |
localparam RAM_TAG_STRING=i2s(JTAG_INDEX); |
localparam RAM_ID =(JTAG_CONNECT== "ALTERA_IMCE") ? {"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=",RAM_TAG_STRING} |
: {"ENABLE_RUNTIME_MOD=NO"}; |
|
if(JTAG_CONNECT== "JTAG_WB")begin:dual_ram |
/* verilator lint_off WIDTH */ |
if(JTAG_CONNECT== "ALTERA_JTAG_WB")begin:dual_ram |
/* verilator lint_on WIDTH */ |
// aletra dual port ram |
altsyncram #( |
.operation_mode("BIDIR_DUAL_PORT"), |
351,10 → 356,10
|
end |
end |
|
/* verilator lint_off WIDTH */ |
else if(FPGA_VENDOR=="GENERIC")begin:generic_ram |
if(JTAG_CONNECT== "JTAG_WB")begin:dual_ram |
|
if(JTAG_CONNECT== "ALTERA_JTAG_WB")begin:dual_ram |
/* verilator lint_on WIDTH */ |
|
generic_dual_port_ram #( |
.Dw(Dw), |
405,9 → 410,9
end//jtag_wb |
end //Generic |
|
|
if(JTAG_CONNECT == "JTAG_WB")begin:jtag_wb |
|
/* verilator lint_off WIDTH */ |
if(JTAG_CONNECT == "ALTERA_JTAG_WB")begin:jtag_wb |
/* verilator lint_on WIDTH */ |
reg jtag_ack; |
wire jtag_we_o, jtag_stb_o; |
|
/jtag_ram_test/src_verilog/lib/wishbone_bus.v
479,7 → 479,12
|
assign comreq = |(grant & request); |
|
always @ (posedge clk or posedge reset) begin |
`ifdef SYNC_RESET_MODE |
always @ (posedge clk )begin |
`else |
always @ (posedge clk or posedge reset)begin |
`endif |
|
if (reset) begin |
grant_registered <= {M{1'b0}}; |
end else begin |
/jtag_ram_test/src_verilog/ram_test.v
57,13 → 57,13
end |
endfunction //i2s |
|
localparam programer_DW=32; |
localparam programer_AW=32; |
localparam programer_S_Aw= 7; |
localparam programer_M_Aw= 32; |
localparam programer_TAGw= 3; |
localparam programer_SELw= 4; |
localparam programer_VJTAG_INDEX=CORE_ID; |
localparam programmer_DW=32; |
localparam programmer_AW=32; |
localparam programmer_S_Aw= 7; |
localparam programmer_M_Aw= 32; |
localparam programmer_TAGw= 3; |
localparam programmer_SELw= 4; |
localparam programmer_VJTAG_INDEX=CORE_ID; |
|
localparam ram_BYTE_WR_EN="YES"; |
localparam ram_FPGA_VENDOR="ALTERA"; |
103,17 → 103,17
wire ss_socket_clk_0_clk_o; |
wire ss_socket_reset_0_reset_o; |
|
wire programer_plug_clk_0_clk_i; |
wire programer_plug_wb_master_0_ack_i; |
wire [ programer_M_Aw-1 : 0 ] programer_plug_wb_master_0_adr_o; |
wire [ programer_TAGw-1 : 0 ] programer_plug_wb_master_0_cti_o; |
wire programer_plug_wb_master_0_cyc_o; |
wire [ programer_DW-1 : 0 ] programer_plug_wb_master_0_dat_i; |
wire [ programer_DW-1 : 0 ] programer_plug_wb_master_0_dat_o; |
wire [ programer_SELw-1 : 0 ] programer_plug_wb_master_0_sel_o; |
wire programer_plug_wb_master_0_stb_o; |
wire programer_plug_wb_master_0_we_o; |
wire programer_plug_reset_0_reset_i; |
wire programmer_plug_clk_0_clk_i; |
wire programmer_plug_wb_master_0_ack_i; |
wire [ programmer_M_Aw-1 : 0 ] programmer_plug_wb_master_0_adr_o; |
wire [ programmer_TAGw-1 : 0 ] programmer_plug_wb_master_0_cti_o; |
wire programmer_plug_wb_master_0_cyc_o; |
wire [ programmer_DW-1 : 0 ] programmer_plug_wb_master_0_dat_i; |
wire [ programmer_DW-1 : 0 ] programmer_plug_wb_master_0_dat_o; |
wire [ programmer_SELw-1 : 0 ] programmer_plug_wb_master_0_sel_o; |
wire programmer_plug_wb_master_0_stb_o; |
wire programmer_plug_wb_master_0_we_o; |
wire programmer_plug_reset_0_reset_i; |
|
wire ram_plug_clk_0_clk_i; |
wire ram_plug_reset_0_reset_i; |
201,25 → 201,25
.reset_out(ss_socket_reset_0_reset_o) |
); |
vjtag_wb #( |
.DW(programer_DW), |
.AW(programer_AW), |
.S_Aw(programer_S_Aw), |
.M_Aw(programer_M_Aw), |
.TAGw(programer_TAGw), |
.SELw(programer_SELw), |
.VJTAG_INDEX(programer_VJTAG_INDEX) |
) programer ( |
.clk(programer_plug_clk_0_clk_i), |
.m_ack_i(programer_plug_wb_master_0_ack_i), |
.m_addr_o(programer_plug_wb_master_0_adr_o), |
.m_cti_o(programer_plug_wb_master_0_cti_o), |
.m_cyc_o(programer_plug_wb_master_0_cyc_o), |
.m_dat_i(programer_plug_wb_master_0_dat_i), |
.m_dat_o(programer_plug_wb_master_0_dat_o), |
.m_sel_o(programer_plug_wb_master_0_sel_o), |
.m_stb_o(programer_plug_wb_master_0_stb_o), |
.m_we_o(programer_plug_wb_master_0_we_o), |
.reset(programer_plug_reset_0_reset_i), |
.DW(programmer_DW), |
.AW(programmer_AW), |
.S_Aw(programmer_S_Aw), |
.M_Aw(programmer_M_Aw), |
.TAGw(programmer_TAGw), |
.SELw(programmer_SELw), |
.VJTAG_INDEX(programmer_VJTAG_INDEX) |
) programmer ( |
.clk(programmer_plug_clk_0_clk_i), |
.m_ack_i(programmer_plug_wb_master_0_ack_i), |
.m_addr_o(programmer_plug_wb_master_0_adr_o), |
.m_cti_o(programmer_plug_wb_master_0_cti_o), |
.m_cyc_o(programmer_plug_wb_master_0_cyc_o), |
.m_dat_i(programmer_plug_wb_master_0_dat_i), |
.m_dat_o(programmer_plug_wb_master_0_dat_o), |
.m_sel_o(programmer_plug_wb_master_0_sel_o), |
.m_stb_o(programmer_plug_wb_master_0_stb_o), |
.m_we_o(programmer_plug_wb_master_0_we_o), |
.reset(programmer_plug_reset_0_reset_i), |
.status_i() |
); |
wb_single_port_ram #( |
252,8 → 252,13
.sa_sel_i(ram_plug_wb_slave_0_sel_i), |
.sa_stb_i(ram_plug_wb_slave_0_stb_i), |
.sa_tag_i(ram_plug_wb_slave_0_tag_i), |
.sa_we_i(ram_plug_wb_slave_0_we_i) |
.sa_we_i(ram_plug_wb_slave_0_we_i), |
.jtag_to_wb ( ), |
.wb_to_jtag ( ) |
|
); |
|
|
wishbone_bus #( |
.M(bus_M), |
.S(bus_S), |
293,22 → 298,24
.s_sel_one_hot(bus_socket_wb_addr_map_0_sel_one_hot), |
.s_stb_o_all(bus_socket_wb_slave_array_stb_o), |
.s_tag_o_all(bus_socket_wb_slave_array_tag_o), |
.s_we_o_all(bus_socket_wb_slave_array_we_o) |
.s_we_o_all(bus_socket_wb_slave_array_we_o), |
.snoop_adr_o(), |
.snoop_en_o() |
); |
|
|
|
assign programer_plug_clk_0_clk_i = ss_socket_clk_0_clk_o; |
assign programer_plug_wb_master_0_ack_i = bus_socket_wb_master_0_ack_o; |
assign bus_socket_wb_master_0_adr_i = programer_plug_wb_master_0_adr_o; |
assign bus_socket_wb_master_0_cti_i = programer_plug_wb_master_0_cti_o; |
assign bus_socket_wb_master_0_cyc_i = programer_plug_wb_master_0_cyc_o; |
assign programer_plug_wb_master_0_dat_i = bus_socket_wb_master_0_dat_o[programer_DW-1 : 0]; |
assign bus_socket_wb_master_0_dat_i = programer_plug_wb_master_0_dat_o; |
assign bus_socket_wb_master_0_sel_i = programer_plug_wb_master_0_sel_o; |
assign bus_socket_wb_master_0_stb_i = programer_plug_wb_master_0_stb_o; |
assign bus_socket_wb_master_0_we_i = programer_plug_wb_master_0_we_o; |
assign programer_plug_reset_0_reset_i = ss_socket_reset_0_reset_o; |
assign programmer_plug_clk_0_clk_i = ss_socket_clk_0_clk_o; |
assign programmer_plug_wb_master_0_ack_i = bus_socket_wb_master_0_ack_o; |
assign bus_socket_wb_master_0_adr_i = programmer_plug_wb_master_0_adr_o; |
assign bus_socket_wb_master_0_cti_i = programmer_plug_wb_master_0_cti_o; |
assign bus_socket_wb_master_0_cyc_i = programmer_plug_wb_master_0_cyc_o; |
assign programmer_plug_wb_master_0_dat_i = bus_socket_wb_master_0_dat_o[programmer_DW-1 : 0]; |
assign bus_socket_wb_master_0_dat_i = programmer_plug_wb_master_0_dat_o; |
assign bus_socket_wb_master_0_sel_i = programmer_plug_wb_master_0_sel_o; |
assign bus_socket_wb_master_0_stb_i = programmer_plug_wb_master_0_stb_o; |
assign bus_socket_wb_master_0_we_i = programmer_plug_wb_master_0_we_o; |
assign programmer_plug_reset_0_reset_i = ss_socket_reset_0_reset_o; |
|
|
assign ram_plug_clk_0_clk_i = ss_socket_clk_0_clk_o; |
/jtag_ram_test/src_verilog/ram_test_top.v
58,13 → 58,13
end |
endfunction //i2s |
|
localparam programer_DW=32; |
localparam programer_AW=32; |
localparam programer_S_Aw= 7; |
localparam programer_M_Aw= 32; |
localparam programer_TAGw= 3; |
localparam programer_SELw= 4; |
localparam programer_VJTAG_INDEX=CORE_ID; |
localparam programmer_DW=32; |
localparam programmer_AW=32; |
localparam programmer_S_Aw= 7; |
localparam programmer_M_Aw= 32; |
localparam programmer_TAGw= 3; |
localparam programmer_SELw= 4; |
localparam programmer_VJTAG_INDEX=CORE_ID; |
|
localparam ram_BYTE_WR_EN="YES"; |
localparam ram_FPGA_VENDOR="ALTERA"; |
/jtag_ram_test/sw/README
35,7 → 35,7
|
If the memory core and jtag_wb are connected to the same wishbone bus, you can program the memory using |
|
sh program.sh |
bash program.sh |
|
|
|
/jtag_ram_test/sw/jtag_intfc.sh
1,4 → 1,4
#!/bin/sh |
#!/bin/bash |
|
HARDWARE_NAME="DE-SoC *" |
DEVICE_NAME="@2*" |
/jtag_ram_test/sw/program.sh
1,7 → 1,6
#!/bin/bash |
|
#!/bin/sh |
|
|
#JTAG_INTFC="$PRONOC_WORK/toolchain/bin/JTAG_INTFC" |
source ./jtag_intfc.sh |
|
24,7 → 23,7
|
#programe the memory |
|
sh write_memory.sh |
bash write_memory.sh |
|
|
#Enable the cpu |
/jtag_ram_test/sw/ram_test.h
5,7 → 5,7
/* ss */ |
|
|
/* programer */ |
/* programmer */ |
|
|
/* ram */ |
/jtag_ram_test/sw/write_memory.sh
1,4 → 1,4
#!/bin/sh |
#!/bin/bash |
|
#JTAG_INTFC="$PRONOC_WORK/toolchain/bin/JTAG_INTFC" |
source ./jtag_intfc.sh |
/jtag_sim_pattern/Makefile
0,0 → 1,2
all: |
gcc main.c -o main |
/jtag_sim_pattern/jtag_sim_input.v
0,0 → 1,42
`ifdef INCLUDE_SIM_INPUT |
/* |
parameter SIM_ACTION = "((1,1,7,3),(0,2,010000007f,24),(0,2,0200000006,24),(0,2,04000000ff,24))"; |
SIM_ACTION: |
((time,type,value,length), |
(time,type,value,length), |
... |
(time,type,value,length)) |
where: |
time: A 32-bit value in milliseconds that represents the start time of the shift |
relative to the completion of the previous shift. |
type: A 4-bit value that determines whether the shift is a DR shift or an |
IR shift. |
value: The data associated with the shift. For IR shifts, it is a 32-bit value. |
For DR shifts, the length is determined by length. |
length: A 32-bit value that specifies the length of the data being shifted. |
This value should be equal to SLD_NODE_IR_WIDTH; otherwise, the value |
field may be padded or truncated. 0 is invalid. |
|
SLD_SIM_TOTAL_LENGTH: |
The total number of bits to be shifted in either an IR shift or a DR shift. This |
value should be equal to the sum of all the length values specified in the SLD_SIM_ACTION string |
|
SIM_N_SCAN: |
Specifies the number of shifts in the simulation model |
|
example: |
select index 7f |
$jseq drshift -state IDLE -hex 36 7f00000001 (0,2, 010000007f,24) |
I:6,D:32:FFFFFFF,D:32:FFFFFFFF to jtag |
|
$jseq drshift -state IDLE -hex 36 0600000002 (0,2, 0200000006,24) |
$jseq drshift -state IDLE -hex 36 ff00000004 (0,2, 04000000ff,24) |
|
parameter SIM_ACTION = "((1,1,7,3),(0,2,ff,20),(0,1,6,3),(0,2,ffffffff,20),(0,2,1,20),(0,2,2,20),(0,2,3,20),(0,2,4,20))"; |
parameter SIM_N_SCAN=8; |
parameter SIM_LENGTH=198; |
*/ |
parameter SIM_ACTION = "((1,1,7,3),(0,2,010000007f,24),(0,2,0200000001,24),(0,2,0400000003,24),(0,2,0400000002,24),(0,2,0200000000,24),(0,2,0100000000,24),(0,2,0200000004,24),(0,2,0400000001,24),(0,2,0200000007,24),(0,2,0400000000,24),(0,2,0200000006,24),(0,2,04cccccccc,24),(0,2,04aaaaaaaa,24),(0,2,0455555555,24),(0,2,0478563412,24),(0,2,04ccbbaaff,24),(0,2,0400000000,24),(0,2,0412121212,24),(0,2,04cccccccc,24),(0,2,04aaaaaaaa,24),(0,2,0455555555,24),(0,2,0478563412,24),(0,2,04ccbbaaff,24),(0,2,0400000000,24),(0,2,0412121212,24),(0,2,04cccccccc,24),(0,2,04aaaaaaaa,24),(0,2,0455555555,24),(0,2,0478563412,24),(0,2,04ccbbaaff,24),(0,2,0400000000,24),(0,2,0412121212,24),(0,2,0200000005,24),(0,2,0400000000,24),(0,2,0400000001,24),(0,2,0400000002,24),(0,2,0400000003,24),(0,2,0400000004,24),(0,2,0400000005,24),(0,2,0400000006,24),(0,2,0400000007,24),(0,2,0400000008,24),(0,2,0400000009,24),(0,2,040000000a,24),(0,2,040000000b,24),(0,2,040000000c,24),(0,2,040000000d,24),(0,2,040000000e,24),(0,2,040000000f,24),(0,2,0400000010,24),(0,2,0400000011,24),(0,2,0400000012,24),(0,2,0400000013,24),(0,2,0400000014,24),(0,2,0400000015,24),(0,2,0400000000,24),(0,2,0400000001,24),(0,2,0200000004,24),(0,2,0400000000,24),(0,2,010000007f,24),(0,2,0200000001,24),(0,2,0400000000,24),(0,2,0200000000,24))"; |
parameter SIM_N_SCAN=64; |
parameter SIM_LENGTH=2271; |
`endif |
/jtag_sim_pattern/main
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svn:mime-type = application/octet-stream
jtag_sim_pattern/main
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
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Index: jtag_sim_pattern/main.c
===================================================================
--- jtag_sim_pattern/main.c (nonexistent)
+++ jtag_sim_pattern/main.c (revision 48)
@@ -0,0 +1,102 @@
+#include
+#include
+#include
+#include
+
+
+void jtag_reorder ( char * string_in, char *string_out ) {
+
+ int size = strlen(string_in);
+ int i;
+ for (i=0;i