Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

jtag_quartus_stp/jtag_quartus_stp.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: jtag_quartus_stp/pipe.c =================================================================== --- jtag_quartus_stp/pipe.c (nonexistent) +++ jtag_quartus_stp/pipe.c (revision 38) @@ -0,0 +1,117 @@ +/* + Copyright (C) Andrew Tridgell 1996 + Copyright (C) Paul Mackerras 1996 + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +/* + Utilities used in rsync + + tridge, June 1996 + */ + +#ifndef _PIPE_H_ +#define _PIPE_H_ + +#include +#include +#include + +#define STDIN_FILENO 0 +#define STDOUT_FILENO 1 + +pid_t do_fork(void); + +void exit_cleanup(int value) { + exit(value); +} + +/* this is taken from CVS */ +int piped_child(char **command,int *f_in,int *f_out) +{ + int pid; + int to_child_pipe[2]; + int from_child_pipe[2]; + + if (pipe(to_child_pipe) < 0 || + pipe(from_child_pipe) < 0) { + fprintf(stderr,"pipe: %s\n",strerror(errno)); + exit_cleanup(1); + } + + + pid = do_fork(); + if (pid < 0) { + fprintf(stderr,"fork: %s\n",strerror(errno)); + exit_cleanup(1); + } + + if (pid == 0) + { + if (dup2(to_child_pipe[0], STDIN_FILENO) < 0 || + close(to_child_pipe[1]) < 0 || + close(from_child_pipe[0]) < 0 || + dup2(from_child_pipe[1], STDOUT_FILENO) < 0) { + fprintf(stderr,"Failed to dup/close : %s\n",strerror(errno)); + exit_cleanup(1); + } + if (to_child_pipe[0] != STDIN_FILENO) close(to_child_pipe[0]); + if (from_child_pipe[1] != STDOUT_FILENO) close(from_child_pipe[1]); + execvp(command[0], command); + fprintf(stderr,"Failed to exec %s : %s\n", + command[0],strerror(errno)); + exit_cleanup(1); + } + + if (close(from_child_pipe[1]) < 0 || + close(to_child_pipe[0]) < 0) { + fprintf(stderr,"Failed to close : %s\n",strerror(errno)); + exit_cleanup(1); + } + + *f_in = from_child_pipe[0]; + *f_out = to_child_pipe[1]; + + return pid; +} + + +static pid_t all_pids[10]; +static int num_pids; + +/* fork and record the pid of the child */ +pid_t do_fork(void) +{ + pid_t newpid = fork(); + + if (newpid) { + all_pids[num_pids++] = newpid; + } + return newpid; +} + +/* kill all children + +void kill_all(int sig) +{ + int i; + for (i=0;i +#include +#include +#include +#include + +#include "pipe.c" + + + + + + + +#define DEBUG_JTAG + +int index_num = 127; + + + + + + + + + +#define DEFAULT_TM4HOST "DE-SoC *" +#define DEFAULT_TMNUM 2 + + + + +FILE *to_stp, *from_stp; + + + +int hexcut( char * hexstring, unsigned * val, int words ){ + size_t count = 0; + int start; + + if (*(hexstring+1)=='x' || *(hexstring+1)=='X') hexstring+=2; + int size=strlen(hexstring); + int hexnum= (size%8)? (size/8)+1 : size/8; + for(count = 0; count < words; count++) val[count]=0; + + for(count = 1; count <= hexnum; count++) { + start=(count*8>size)? 0 : size-count*8; + + sscanf(hexstring+start, "%08x", &val[count-1]); + *(hexstring+start)=0; + } + + // printf("size=%d, hexnum=%u\n",size,hexnum); + + + return hexnum; +} + + +void hexgen( char * hexstring, unsigned * val, int words ){ + size_t count = 0; + sprintf(hexstring,"0x"); + for(count = 0; count < words; count++) { + if(count == 0) sprintf((hexstring+2),"%x",val[words-count-1]); + else sprintf(hexstring,"%08x",val[words-count-1]); + hexstring+=strlen(hexstring); + } + + // return hexnum; +} + +void hextostring( char * hexstring, unsigned * val, int words ){ + size_t count = 0; + //sprintf(hexstring,"0x"); + for(count = 0; count < words; count++) { + if(count == 0) sprintf((hexstring),"%x",val[words-count-1]); + else sprintf(hexstring,"%08x",val[words-count-1]); + hexstring+=strlen(hexstring); + } + + // return hexnum; +} + + +int jtag_init(char *hrdname, char *dvicname ) { + + /* Create a quartus_stp process, and get the list of ports */ + + int f_to_stp, f_from_stp; + char buf[1024]; + char *command[] = {"quartus_stp", "-s", 0}; + + if(from_stp != (FILE *) NULL) { + fclose(from_stp); + fclose(to_stp); + } + + piped_child(command, &f_from_stp, &f_to_stp); + + from_stp = fdopen(f_from_stp, "r"); + to_stp = fdopen(f_to_stp, "w"); + + if(from_stp == (FILE *) NULL || to_stp == (FILE *) NULL) { + fprintf(stderr, "jtag_init: can't communicate with quartus_stp process\n"); + fclose(from_stp); + fclose(to_stp); + from_stp = (FILE *) NULL; + to_stp = (FILE *) NULL; + return(1); + } + + + + while(1) { + fgets(buf, sizeof(buf), from_stp); + if(strstr(buf, "ERROR") != NULL) { + printf("\tERROR\n"); + printf("'%s'\n", buf); + exit(1); + } + + + + if(!strcmp(buf, "\n")) + break; + if(feof(from_stp)) { + fprintf(stderr, "saw eof from quartus_stp\n"); + exit(1); + } + + if(ferror(from_stp)) { + fprintf(stderr, "saw error from quartus_stp\n"); + exit(1); + } + } + + fprintf(to_stp, "foreach name [get_hardware_names] {\n"); + fprintf(to_stp, " puts $name\n"); + fprintf(to_stp, " if { [string match \"*%s*\" $name] } {\n", hrdname); + fprintf(to_stp, " set hardware_name $name\n"); + fprintf(to_stp, " }\n"); + fprintf(to_stp, "}\n"); + fprintf(to_stp, "puts \"\\nhardware_name is $hardware_name\";\n"); + fprintf(to_stp, "foreach name [get_device_names -hardware_name $hardware_name] {\n"); + fprintf(to_stp, " if { [string match \"*%s*\" $name] } {\n",dvicname); + fprintf(to_stp, " set chip_name $name\n"); + fprintf(to_stp, " }\n"); + fprintf(to_stp, "}\n"); + fprintf(to_stp, "puts \"device_name is $chip_name\\n\";\n"); + fprintf(to_stp, "open_device -hardware_name $hardware_name -device_name $chip_name\n"); + + fflush(to_stp); + + while(1) { + fgets(buf, sizeof(buf), from_stp); + + if(strstr(buf, "ERROR") != NULL) { + printf("\tERROR\n"); + printf("'%s'\n", buf); + exit(1); + } + + if(!strcmp(buf, "\n")) + break; + if(feof(from_stp)) { + fprintf(stderr, "saw eof from quartus_stp\n"); + exit(1); + } + if(ferror(from_stp)) { + fprintf(stderr, "saw error from quartus_stp\n"); + exit(1); + } + } + return 0; + +} + + + + + + +void return_dr (unsigned *out) { + char buf[1024]; + char *ptr=buf; + fprintf(to_stp,"puts $data\n"); + fflush(to_stp); + fgets(buf, sizeof(buf), from_stp); + while(*ptr=='t' || *ptr=='c' || *ptr=='l' || *ptr=='>' || *ptr==' ' ) ptr++; + //printf("saw: '%s'\n", ptr); + *out= strtol(ptr,NULL,16); +} + +void return_dr_long (unsigned *out, int words) { + char buf[1024]; + char *ptr=buf; + fprintf(to_stp,"puts $data\n"); + fflush(to_stp); + fgets(buf, sizeof(buf), from_stp); + while(*ptr=='t' || *ptr=='c' || *ptr=='l' || *ptr=='>' || *ptr==' ' ) ptr++; + //printf("saw: '%s'\n", ptr); + hexcut( ptr, out, words ); +} + + +void jtag_vir(unsigned vir) { + fprintf(to_stp,"device_lock -timeout 10000\n"); + fprintf(to_stp,"device_virtual_ir_shift -instance_index %d -ir_value %x -no_captured_ir_value\n",index_num,vir); + fprintf(to_stp,"catch {device_unlock}\n"); +} + + +void jtag_vdr(unsigned sz, unsigned bits, unsigned *out) { + if (!out){ + fprintf(to_stp,"device_lock -timeout 10000\n"); + fprintf(to_stp,"device_virtual_dr_shift -dr_value %x -instance_index %d -length %d -no_captured_dr_value -value_in_hex\n",bits,index_num,sz); + fprintf(to_stp,"catch {device_unlock}\n"); + }else{ + fprintf(to_stp,"device_lock -timeout 10000\n"); + fprintf(to_stp,"set data [device_virtual_dr_shift -dr_value %x -instance_index %d -length %d -value_in_hex]\n",bits,index_num,sz); + fprintf(to_stp,"catch {device_unlock}\n"); + return_dr (out); + } +} + +void jtag_vdr_long(unsigned sz, unsigned * bits, unsigned *out, int words) { + char hexstring[1000]; + //printf("jtag_vdr_long(unsigned %d, unsigned %s, unsigned %s, int %d)",sz,bits,out,words ); + hextostring( hexstring, bits, words ); + + if (!out){ + fprintf(to_stp,"device_lock -timeout 10000\n"); + fprintf(to_stp,"device_virtual_dr_shift -dr_value %s -instance_index %d -length %d -no_captured_dr_value -value_in_hex\n",hexstring,index_num,sz); + //printf("device_virtual_dr_shift -dr_value %s -instance_index %d -length %d -no_captured_dr_value -value_in_hex\n",hexstring,index_num,sz); + fprintf(to_stp,"catch {device_unlock}\n"); + }else{ + fprintf(to_stp,"device_lock -timeout 10000\n"); + fprintf(to_stp,"set data [device_virtual_dr_shift -dr_value %s -instance_index %d -length %d -value_in_hex]\n",hexstring,index_num,sz); + fprintf(to_stp,"catch {device_unlock}\n"); + return_dr_long (out,words); + } + +} + + +void closeport(){ + fprintf(to_stp,"catch {device_unlock}\n"); + fprintf(to_stp,"catch {close_device}\n"); + fflush(to_stp); +} + + + +void vdr_large (unsigned sz, char * string, char *out){ + int words= (sz%32)? (sz/32)+1 : sz/32; + unsigned val[64],val_o[64]; + printf("data=%s\n",string); + hexcut(string, val, words ); + + + if( out == 0) { + jtag_vdr_long(sz,val,0,words); + return; + } + jtag_vdr_long(sz,val,val_o,words); + + hexgen( out, val_o, words ); + + + +} + +void turn_on_led(){ + unsigned out; + //fprintf(to_stp, "device_lock -timeout 10000\n"); + //fprintf(to_stp,"device_virtual_ir_shift -instance_index 127 -ir_value 1 -no_captured_ir_value\n"); + jtag_vir(1); + //fprintf(to_stp,"catch {device_unlock}\n"); + //fprintf(to_stp,"device_virtual_dr_shift -dr_value 3 -instance_index 127 -length 2 -no_captured_dr_value -value_in_hex\n"); + char string[100]="0"; + vdr_large(2, string, NULL); + //fprintf(to_stp, "device_lock -timeout 10000\n"); + //fprintf(to_stp,"device_virtual_ir_shift -instance_index 127 -ir_value 0 -no_captured_ir_value\n"); + jtag_vir(0); + //printf("outs= %d \n",out); + //fprintf(to_stp,"catch {device_unlock}\n"); + fflush(to_stp); + //run(); + +} + + +void turn_off_led(){ + unsigned out; +/* + fprintf(to_stp, "device_lock -timeout 10000\n"); + fprintf(to_stp,"device_virtual_ir_shift -instance_index 127 -ir_value 1 -no_captured_ir_value\n"); + fprintf(to_stp,"device_virtual_dr_shift -dr_value 3 -instance_index 127 -length 2 -no_captured_dr_value -value_in_hex\n"); + fprintf(to_stp,"device_virtual_dr_shift -dr_value 2 -instance_index 127 -length 2 -no_captured_dr_value -value_in_hex\n"); + fprintf(to_stp,"device_virtual_ir_shift -instance_index 127 -ir_value 0 -no_captured_ir_value\n"); + fprintf(to_stp,"catch {device_unlock}\n"); + +*/ + //run(); + + char string[100]="3"; + jtag_vir(1); + //vdr_large(2, string, NULL); + jtag_vdr(2,3,NULL); + jtag_vir(0); + //printf("outs= %d \n",out); + + fflush(to_stp); +} + + + + + +int main(){ + int c=0; + jtag_init("DE-SoC *","@2*"); // fpr DE10-nano + while (c==0 || c== 1){ + printf("Enter 1: to on, 0: to off, else to quit:\n"); + scanf ("%d",&c); + if(c==0){printf("\toff\n"); turn_off_led();} + else if (c== 1){printf("\ton\n"); turn_on_led();} + else break; + + } + + closeport(); + fclose(from_stp); + fclose(to_stp); + from_stp = (FILE *) NULL; + to_stp = (FILE *) NULL; + + return 0; + + + +} + + + + Index: jtag_quartus_stp/test.tcl =================================================================== --- jtag_quartus_stp/test.tcl (nonexistent) +++ jtag_quartus_stp/test.tcl (revision 38) @@ -0,0 +1,85 @@ +#quartus_stp -t +#This portion of the script is derived from some of the examples from Altera +global usbblaster_name +global test_device +# List all available programming hardwares, and select the USBBlaster. +# (Note: this example assumes only one USBBlaster connected.) +# Programming Hardwares: +foreach hardware_name [get_hardware_names] { + puts $hardware_name + if { [string match "DE-SoC *" $hardware_name] } { + set usbblaster_name $hardware_name + } +} + + +puts "\nSelect JTAG chain connected to $usbblaster_name.\n"; + +# List all devices on the chain, and select the first device on the chain. +#Devices on the JTAG chain: + + +foreach device_name [get_device_names -hardware_name $usbblaster_name] { + puts $device_name + if { [string match "@2*" $device_name] } { + set test_device $device_name + } +} +puts "\nSelect device: $test_device.\n"; + +# Open device +proc openport {} { + global usbblaster_name + global test_device + open_device -hardware_name $usbblaster_name -device_name $test_device +} + +# Close device. Just used if communication error occurs +proc closeport { } { + catch {device_unlock} + catch {close_device} +} + + + +openport +device_lock -timeout 10000 + +device_virtual_ir_shift -instance_index 127 -ir_value 1 -no_captured_ir_value +device_virtual_dr_shift -dr_value 3 -instance_index 127 -length 2 -no_captured_dr_value -value_in_hex +device_virtual_dr_shift -dr_value 2 -instance_index 127 -length 2 -no_captured_dr_value -value_in_hex +device_virtual_ir_shift -instance_index 127 -ir_value 0 -no_captured_ir_value +catch {device_unlock} + +after 1000 + +device_lock -timeout 10000 +device_virtual_ir_shift -instance_index 127 -ir_value 1 -no_captured_ir_value +device_virtual_dr_shift -dr_value 3 -instance_index 127 -length 2 -no_captured_dr_value -value_in_hex +device_virtual_dr_shift -dr_value 0 -instance_index 127 -length 2 -no_captured_dr_value -value_in_hex +device_virtual_ir_shift -instance_index 127 -ir_value 0 -no_captured_ir_value +catch {device_unlock} + +after 1000 + +device_lock -timeout 10000 +device_virtual_ir_shift -instance_index 127 -ir_value 1 -no_captured_ir_value +device_virtual_dr_shift -dr_value 3 -instance_index 127 -length 2 -no_captured_dr_value -value_in_hex +set data [device_virtual_dr_shift -dr_value 2 -instance_index 127 -length 2 -value_in_hex] +puts $data +device_virtual_ir_shift -instance_index 127 -ir_value 0 -no_captured_ir_value +catch {device_unlock} + +after 1000 + +closeport + + + + + + + + + + Index: test_rtl/jtag_led_test/c5_pin_model_dump.txt =================================================================== --- test_rtl/jtag_led_test/c5_pin_model_dump.txt (nonexistent) +++ test_rtl/jtag_led_test/c5_pin_model_dump.txt (revision 38) @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2 +io_4iomodule_c5_index: 54gpio_index: 465 +io_4iomodule_c5_index: 33gpio_index: 6 +io_4iomodule_c5_index: 51gpio_index: 461 +io_4iomodule_c5_index: 27gpio_index: 10 +io_4iomodule_c5_index: 57gpio_index: 457 +io_4iomodule_c5_index: 34gpio_index: 14 +io_4iomodule_c5_index: 28gpio_index: 453 +io_4iomodule_c5_index: 26gpio_index: 19 +io_4iomodule_c5_index: 47gpio_index: 449 +io_4iomodule_c5_index: 29gpio_index: 22 +io_4iomodule_c5_index: 3gpio_index: 445 +io_4iomodule_c5_index: 16gpio_index: 27 +io_4iomodule_c5_index: 6gpio_index: 441 +io_4iomodule_c5_index: 50gpio_index: 30 +io_4iomodule_c5_index: 35gpio_index: 437 +io_4iomodule_c5_index: 7gpio_index: 35 +io_4iomodule_c5_index: 53gpio_index: 433 +io_4iomodule_c5_index: 12gpio_index: 38 +io_4iomodule_c5_index: 1gpio_index: 429 +io_4iomodule_c5_index: 22gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 425 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 30gpio_index: 421 +io_4iomodule_c5_index: 2gpio_index: 51 +io_4iomodule_c5_index: 31gpio_index: 417 +io_4iomodule_c5_index: 39gpio_index: 54 +io_4iomodule_c5_index: 18gpio_index: 413 +io_4iomodule_c5_index: 10gpio_index: 59 +io_4iomodule_c5_index: 42gpio_index: 409 +io_4iomodule_c5_index: 5gpio_index: 62 +io_4iomodule_c5_index: 24gpio_index: 405 +io_4iomodule_c5_index: 37gpio_index: 67 +io_4iomodule_c5_index: 13gpio_index: 401 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 44gpio_index: 397 +io_4iomodule_c5_index: 38gpio_index: 75 +io_4iomodule_c5_index: 52gpio_index: 393 +io_4iomodule_c5_index: 32gpio_index: 78 +io_4iomodule_c5_index: 56gpio_index: 389 +io_4iomodule_a_index: 13gpio_index: 385 +io_4iomodule_c5_index: 4gpio_index: 83 +io_4iomodule_c5_index: 23gpio_index: 86 +io_4iomodule_a_index: 15gpio_index: 381 +io_4iomodule_a_index: 8gpio_index: 377 +io_4iomodule_c5_index: 46gpio_index: 91 +io_4iomodule_a_index: 5gpio_index: 373 +io_4iomodule_a_index: 11gpio_index: 369 +io_4iomodule_c5_index: 41gpio_index: 94 +io_4iomodule_a_index: 3gpio_index: 365 +io_4iomodule_c5_index: 25gpio_index: 99 +io_4iomodule_a_index: 7gpio_index: 361 +io_4iomodule_c5_index: 9gpio_index: 102 +io_4iomodule_a_index: 0gpio_index: 357 +io_4iomodule_c5_index: 14gpio_index: 107 +io_4iomodule_a_index: 12gpio_index: 353 +io_4iomodule_c5_index: 45gpio_index: 110 +io_4iomodule_c5_index: 17gpio_index: 115 +io_4iomodule_a_index: 4gpio_index: 349 +io_4iomodule_c5_index: 36gpio_index: 118 +io_4iomodule_a_index: 10gpio_index: 345 +io_4iomodule_a_index: 16gpio_index: 341 +io_4iomodule_c5_index: 15gpio_index: 123 +io_4iomodule_a_index: 14gpio_index: 337 +io_4iomodule_c5_index: 43gpio_index: 126 +io_4iomodule_c5_index: 19gpio_index: 131 +io_4iomodule_a_index: 1gpio_index: 333 +io_4iomodule_c5_index: 59gpio_index: 134 +io_4iomodule_a_index: 2gpio_index: 329 +io_4iomodule_a_index: 9gpio_index: 325 +io_4iomodule_c5_index: 48gpio_index: 139 +io_4iomodule_a_index: 6gpio_index: 321 +io_4iomodule_a_index: 17gpio_index: 317 +io_4iomodule_c5_index: 40gpio_index: 142 +io_4iomodule_c5_index: 11gpio_index: 147 +io_4iomodule_c5_index: 58gpio_index: 150 +io_4iomodule_c5_index: 21gpio_index: 155 +io_4iomodule_c5_index: 49gpio_index: 158 +io_4iomodule_h_c5_index: 0gpio_index: 161 +io_4iomodule_h_c5_index: 6gpio_index: 165 +io_4iomodule_h_c5_index: 10gpio_index: 169 +io_4iomodule_h_c5_index: 3gpio_index: 173 +io_4iomodule_h_c5_index: 8gpio_index: 176 +io_4iomodule_h_c5_index: 11gpio_index: 180 +io_4iomodule_h_c5_index: 7gpio_index: 184 +io_4iomodule_h_c5_index: 5gpio_index: 188 +io_4iomodule_h_c5_index: 1gpio_index: 192 +io_4iomodule_h_c5_index: 2gpio_index: 196 +io_4iomodule_h_c5_index: 9gpio_index: 200 +io_4iomodule_h_c5_index: 4gpio_index: 204 +io_4iomodule_h_index: 15gpio_index: 208 +io_4iomodule_h_index: 1gpio_index: 212 +io_4iomodule_h_index: 3gpio_index: 216 +io_4iomodule_h_index: 2gpio_index: 220 +io_4iomodule_h_index: 11gpio_index: 224 +io_4iomodule_vref_h_index: 1gpio_index: 228 +io_4iomodule_h_index: 20gpio_index: 231 +io_4iomodule_h_index: 8gpio_index: 235 +io_4iomodule_h_index: 6gpio_index: 239 +io_4iomodule_h_index: 10gpio_index: 243 +io_4iomodule_h_index: 23gpio_index: 247 +io_4iomodule_h_index: 7gpio_index: 251 +io_4iomodule_h_index: 22gpio_index: 255 +io_4iomodule_h_index: 5gpio_index: 259 +io_4iomodule_h_index: 24gpio_index: 263 +io_4iomodule_h_index: 0gpio_index: 267 +io_4iomodule_h_index: 13gpio_index: 271 +io_4iomodule_h_index: 21gpio_index: 275 +io_4iomodule_h_index: 16gpio_index: 279 +io_4iomodule_vref_h_index: 0gpio_index: 283 +io_4iomodule_h_index: 12gpio_index: 286 +io_4iomodule_h_index: 4gpio_index: 290 +io_4iomodule_h_index: 19gpio_index: 294 +io_4iomodule_h_index: 18gpio_index: 298 +io_4iomodule_h_index: 17gpio_index: 302 +io_4iomodule_h_index: 25gpio_index: 306 +io_4iomodule_h_index: 14gpio_index: 310 +io_4iomodule_h_index: 9gpio_index: 314 Index: test_rtl/jtag_led_test/src/top.v =================================================================== --- test_rtl/jtag_led_test/src/top.v (nonexistent) +++ test_rtl/jtag_led_test/src/top.v (revision 38) @@ -0,0 +1,125 @@ +module top ( + LED +); + output [6:0] LED; + + wire [1:0] jtag_out; + + jtag_control_port #( + .VJTAG_INDEX(127), + .DW(2) + ) + uut + ( + .jtag_out(jtag_out) + ); + + assign LED[0]=jtag_out[0]; + assign LED[1]=jtag_out[1]; + + +endmodule + + + + + +module jtag_control_port #( + parameter VJTAG_INDEX=127, + parameter DW=2 + +)( + jtag_out +); + + + output [DW-1 : 0] jtag_out; + + + + //vjtag vjtag signals declaration + wire [2:0] ir_out , ir_in; + wire tdo, tck, tdi; + wire cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir; + + + vjtag #( + .VJTAG_INDEX(VJTAG_INDEX) + ) + vjtag_inst ( + .ir_out ( ir_out ), + .tdo ( tdo ), + .ir_in ( ir_in ), + .tck ( tck ), + .tdi ( tdi ), + .virtual_state_cdr ( cdr ), + .virtual_state_cir ( cir ), + .virtual_state_e1dr ( e1dr ), + .virtual_state_e2dr ( e2dr ), + .virtual_state_pdr ( pdr ), + .virtual_state_sdr ( sdr ), + .virtual_state_udr ( udr ), + .virtual_state_uir ( uir ) + ); + + + // IR states + + + + reg [2:0] ir; + reg bypass_reg; + reg [DW-1 : 0] shift_buffer,shift_buffer_next; + reg cdr_delayed,sdr_delayed; + reg [DW-1 : 0] status,status_next; + + assign jtag_out = status ; + /* + always @(negedge tck) + begin + // Delay the CDR signal by one half clock cycle + cdr_delayed = cdr; + sdr_delayed = sdr; + end + */ + + assign ir_out = ir_in; // Just pass the IR out + assign tdo = (ir == 3'b000) ? bypass_reg : shift_buffer[0]; + + + + + + always @(posedge tck ) + begin + if( uir ) ir <= ir_in; // Capture the instruction provided + bypass_reg <= tdi; + shift_buffer<=shift_buffer_next; + status<=status_next; + + end + +generate + if(DW==1)begin :DW1 + always @ (*)begin + shift_buffer_next=shift_buffer; + status_next = status; + if( sdr ) shift_buffer_next= tdi; //,shift_buffer[DW-1:1]};// shift buffer + if((ir == 3'b001) & cdr ) shift_buffer_next = status; + if((ir == 3'b001) & udr ) status_next = shift_buffer; + end + end + else begin :DWB + always @ (*)begin + shift_buffer_next=shift_buffer; + status_next = status; + if( sdr ) shift_buffer_next= {tdi, shift_buffer[DW-1:1]};// shift buffer + if((ir == 3'b001) & cdr ) shift_buffer_next = status; + if((ir == 3'b001) & udr ) status_next = shift_buffer; + end + + end +endgenerate + + +endmodule Index: test_rtl/jtag_led_test/src/vjtag.v =================================================================== --- test_rtl/jtag_led_test/src/vjtag.v (nonexistent) +++ test_rtl/jtag_led_test/src/vjtag.v (revision 38) @@ -0,0 +1,184 @@ +// megafunction wizard: %Virtual JTAG% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: sld_virtual_jtag + +// ============================================================ +// File Name: vjtag.v +// Megafunction Name(s): +// sld_virtual_jtag +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module vjtag #( + parameter VJTAG_INDEX=126 + +)( + ir_out, + tdo, + ir_in, + tck, + tdi, + virtual_state_cdr, + virtual_state_cir, + virtual_state_e1dr, + virtual_state_e2dr, + virtual_state_pdr, + virtual_state_sdr, + virtual_state_udr, + virtual_state_uir); + + input [2:0] ir_out; + input tdo; + output [2:0] ir_in; + output tck; + output tdi; + output virtual_state_cdr; + output virtual_state_cir; + output virtual_state_e1dr; + output virtual_state_e2dr; + output virtual_state_pdr; + output virtual_state_sdr; + output virtual_state_udr; + output virtual_state_uir; + + wire sub_wire0; + wire sub_wire1; + wire [2:0] sub_wire2; + wire sub_wire3; + wire sub_wire4; + wire sub_wire5; + wire sub_wire6; + wire sub_wire7; + wire sub_wire8; + wire sub_wire9; + wire sub_wire10; + wire virtual_state_cir = sub_wire0; + wire virtual_state_pdr = sub_wire1; + wire [2:0] ir_in = sub_wire2[2:0]; + wire tdi = sub_wire3; + wire virtual_state_udr = sub_wire4; + wire tck = sub_wire5; + wire virtual_state_e1dr = sub_wire6; + wire virtual_state_uir = sub_wire7; + wire virtual_state_cdr = sub_wire8; + wire virtual_state_e2dr = sub_wire9; + wire virtual_state_sdr = sub_wire10; + + sld_virtual_jtag sld_virtual_jtag_component ( + .ir_out (ir_out), + .tdo (tdo), + .virtual_state_cir (sub_wire0), + .virtual_state_pdr (sub_wire1), + .ir_in (sub_wire2), + .tdi (sub_wire3), + .virtual_state_udr (sub_wire4), + .tck (sub_wire5), + .virtual_state_e1dr (sub_wire6), + .virtual_state_uir (sub_wire7), + .virtual_state_cdr (sub_wire8), + .virtual_state_e2dr (sub_wire9), + .virtual_state_sdr (sub_wire10) + // synopsys translate_off + , + .jtag_state_cdr (), + .jtag_state_cir (), + .jtag_state_e1dr (), + .jtag_state_e1ir (), + .jtag_state_e2dr (), + .jtag_state_e2ir (), + .jtag_state_pdr (), + .jtag_state_pir (), + .jtag_state_rti (), + .jtag_state_sdr (), + .jtag_state_sdrs (), + .jtag_state_sir (), + .jtag_state_sirs (), + .jtag_state_tlr (), + .jtag_state_udr (), + .jtag_state_uir (), + .tms () + // synopsys translate_on + ); + defparam + sld_virtual_jtag_component.sld_auto_instance_index = "NO", + sld_virtual_jtag_component.sld_instance_index = VJTAG_INDEX, + sld_virtual_jtag_component.sld_ir_width = 3, + sld_virtual_jtag_component.sld_sim_action = "((0,1,7,3),(0,2,ff,20),(0,1,6,3),(0,2,ffffffff,20),(0,2,1,20),(0,2,2,20),(0,2,3,20),(0,2,4,20))", + sld_virtual_jtag_component.sld_sim_n_scan = 8, + sld_virtual_jtag_component.sld_sim_total_length = 198; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: show_jtag_state STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO" +// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "126" +// Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "3" +// Retrieval info: CONSTANT: SLD_SIM_ACTION STRING "((0,1,7,3),(0,2,ff,20),(0,1,6,3),(0,2,ffffffff,20),(0,2,1,20),(0,2,2,20),(0,2,3,20),(0,2,4,20))" +// Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "8" +// Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "198" +// Retrieval info: USED_PORT: ir_in 0 0 3 0 OUTPUT NODEFVAL "ir_in[2..0]" +// Retrieval info: USED_PORT: ir_out 0 0 3 0 INPUT NODEFVAL "ir_out[2..0]" +// Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck" +// Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi" +// Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo" +// Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr" +// Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir" +// Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr" +// Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr" +// Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr" +// Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr" +// Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr" +// Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir" +// Retrieval info: CONNECT: @ir_out 0 0 3 0 ir_out 0 0 3 0 +// Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0 +// Retrieval info: CONNECT: ir_in 0 0 3 0 @ir_in 0 0 3 0 +// Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0 +// Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf

test_rtl/jtag_led_test/src/vjtag.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: test_rtl/jtag_led_test/top.qpf =================================================================== --- test_rtl/jtag_led_test/top.qpf (nonexistent) +++ test_rtl/jtag_led_test/top.qpf (revision 38) @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 16:17:05 January 01, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "16:17:05 January 01, 2018" + +# Revisions + +PROJECT_REVISION = "top" Index: test_rtl/jtag_led_test/top.qsf =================================================================== --- test_rtl/jtag_led_test/top.qsf (nonexistent) +++ test_rtl/jtag_led_test/top.qsf (revision 38) @@ -0,0 +1,493 @@ +# Generated using ProNoC +#============================================================ +# Build by Terasic V1.0.0 +#============================================================ + +# Device setting for DE10-nano VB2 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2 +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:08:14 OCTOBER 14, 2016" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA + + + +#============================================================ +# ADC +#============================================================ + +#============================================================ +# ARDUINO +#============================================================ + +#============================================================ +# FPGA +#============================================================ + +#============================================================ +# GPIO +#============================================================ + +#============================================================ +# HDMI +#============================================================ + +#============================================================ +# HPS +#============================================================ + +#============================================================ +# KEY +#============================================================ + +#============================================================ +# LED +#============================================================ + +#============================================================ +# SW +#============================================================ + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + + +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO +set_location_assignment PIN_AG13 -to ARDUINO_IO[0] +set_location_assignment PIN_AF13 -to ARDUINO_IO[1] +set_location_assignment PIN_AG10 -to ARDUINO_IO[2] +set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +set_location_assignment PIN_U14 -to ARDUINO_IO[4] +set_location_assignment PIN_U13 -to ARDUINO_IO[5] +set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +set_location_assignment PIN_AG11 -to ARDUINO_IO[15] +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 +set_location_assignment PIN_V12 -to GPIO_0[0] +set_location_assignment PIN_E8 -to GPIO_0[1] +set_location_assignment PIN_W12 -to GPIO_0[2] +set_location_assignment PIN_D11 -to GPIO_0[3] +set_location_assignment PIN_D8 -to GPIO_0[4] +set_location_assignment PIN_AH13 -to GPIO_0[5] +set_location_assignment PIN_AF7 -to GPIO_0[6] +set_location_assignment PIN_AH14 -to GPIO_0[7] +set_location_assignment PIN_AF4 -to GPIO_0[8] +set_location_assignment PIN_AH3 -to GPIO_0[9] +set_location_assignment PIN_AD5 -to GPIO_0[10] +set_location_assignment PIN_AG14 -to GPIO_0[11] +set_location_assignment PIN_AE23 -to GPIO_0[12] +set_location_assignment PIN_AE6 -to GPIO_0[13] +set_location_assignment PIN_AD23 -to GPIO_0[14] +set_location_assignment PIN_AE24 -to GPIO_0[15] +set_location_assignment PIN_D12 -to GPIO_0[16] +set_location_assignment PIN_AD20 -to GPIO_0[17] +set_location_assignment PIN_C12 -to GPIO_0[18] +set_location_assignment PIN_AD17 -to GPIO_0[19] +set_location_assignment PIN_AC23 -to GPIO_0[20] +set_location_assignment PIN_AC22 -to GPIO_0[21] +set_location_assignment PIN_Y19 -to GPIO_0[22] +set_location_assignment PIN_AB23 -to GPIO_0[23] +set_location_assignment PIN_AA19 -to GPIO_0[24] +set_location_assignment PIN_W11 -to GPIO_0[25] +set_location_assignment PIN_AA18 -to GPIO_0[26] +set_location_assignment PIN_W14 -to GPIO_0[27] +set_location_assignment PIN_Y18 -to GPIO_0[28] +set_location_assignment PIN_Y17 -to GPIO_0[29] +set_location_assignment PIN_AB25 -to GPIO_0[30] +set_location_assignment PIN_AB26 -to GPIO_0[31] +set_location_assignment PIN_Y11 -to GPIO_0[32] +set_location_assignment PIN_AA26 -to GPIO_0[33] +set_location_assignment PIN_AA13 -to GPIO_0[34] +set_location_assignment PIN_AA11 -to GPIO_0[35] +set_location_assignment PIN_Y15 -to GPIO_1[0] +set_location_assignment PIN_AC24 -to GPIO_1[1] +set_location_assignment PIN_AA15 -to GPIO_1[2] +set_location_assignment PIN_AD26 -to GPIO_1[3] +set_location_assignment PIN_AG28 -to GPIO_1[4] +set_location_assignment PIN_AF28 -to GPIO_1[5] +set_location_assignment PIN_AE25 -to GPIO_1[6] +set_location_assignment PIN_AF27 -to GPIO_1[7] +set_location_assignment PIN_AG26 -to GPIO_1[8] +set_location_assignment PIN_AH27 -to GPIO_1[9] +set_location_assignment PIN_AG25 -to GPIO_1[10] +set_location_assignment PIN_AH26 -to GPIO_1[11] +set_location_assignment PIN_AH24 -to GPIO_1[12] +set_location_assignment PIN_AF25 -to GPIO_1[13] +set_location_assignment PIN_AG23 -to GPIO_1[14] +set_location_assignment PIN_AF23 -to GPIO_1[15] +set_location_assignment PIN_AG24 -to GPIO_1[16] +set_location_assignment PIN_AH22 -to GPIO_1[17] +set_location_assignment PIN_AH21 -to GPIO_1[18] +set_location_assignment PIN_AG21 -to GPIO_1[19] +set_location_assignment PIN_AH23 -to GPIO_1[20] +set_location_assignment PIN_AA20 -to GPIO_1[21] +set_location_assignment PIN_AF22 -to GPIO_1[22] +set_location_assignment PIN_AE22 -to GPIO_1[23] +set_location_assignment PIN_AG20 -to GPIO_1[24] +set_location_assignment PIN_AF21 -to GPIO_1[25] +set_location_assignment PIN_AG19 -to GPIO_1[26] +set_location_assignment PIN_AH19 -to GPIO_1[27] +set_location_assignment PIN_AG18 -to GPIO_1[28] +set_location_assignment PIN_AH18 -to GPIO_1[29] +set_location_assignment PIN_AF18 -to GPIO_1[30] +set_location_assignment PIN_AF20 -to GPIO_1[31] +set_location_assignment PIN_AG15 -to GPIO_1[32] +set_location_assignment PIN_AE20 -to GPIO_1[33] +set_location_assignment PIN_AE19 -to GPIO_1[34] +set_location_assignment PIN_AE17 -to GPIO_1[35] +set_location_assignment PIN_U10 -to HDMI_I2C_SCL +set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +set_location_assignment PIN_T13 -to HDMI_I2S +set_location_assignment PIN_T11 -to HDMI_LRCLK +set_location_assignment PIN_U11 -to HDMI_MCLK +set_location_assignment PIN_T12 -to HDMI_SCLK +set_location_assignment PIN_AG5 -to HDMI_TX_CLK +set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +set_location_assignment PIN_W8 -to HDMI_TX_D[2] +set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +set_location_assignment PIN_AD19 -to HDMI_TX_DE +set_location_assignment PIN_T8 -to HDMI_TX_HS +set_location_assignment PIN_AF11 -to HDMI_TX_INT +set_location_assignment PIN_V13 -to HDMI_TX_VS + +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + + +set_global_assignment -name SDC_FILE DE10_Nano_golden_top.sdc + + + +set_global_assignment -name TOP_LEVEL_ENTITY top + set_global_assignment -name VERILOG_FILE ./src/top.v + set_global_assignment -name VERILOG_FILE ./src/vjtag.v + + +set_global_assignment -name VERILOG_FILE top.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: test_rtl/jtag_led_test/top.qws =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: test_rtl/jtag_led_test/top.qws =================================================================== --- test_rtl/jtag_led_test/top.qws (nonexistent) +++ test_rtl/jtag_led_test/top.qws (revision 38)

test_rtl/jtag_led_test/top.qws Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: test_rtl/jtag_ram_test/c5_pin_model_dump.txt =================================================================== --- test_rtl/jtag_ram_test/c5_pin_model_dump.txt (nonexistent) +++ test_rtl/jtag_ram_test/c5_pin_model_dump.txt (revision 38) @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2 +io_4iomodule_c5_index: 54gpio_index: 465 +io_4iomodule_c5_index: 33gpio_index: 6 +io_4iomodule_c5_index: 51gpio_index: 461 +io_4iomodule_c5_index: 27gpio_index: 10 +io_4iomodule_c5_index: 57gpio_index: 457 +io_4iomodule_c5_index: 34gpio_index: 14 +io_4iomodule_c5_index: 28gpio_index: 453 +io_4iomodule_c5_index: 26gpio_index: 19 +io_4iomodule_c5_index: 47gpio_index: 449 +io_4iomodule_c5_index: 29gpio_index: 22 +io_4iomodule_c5_index: 3gpio_index: 445 +io_4iomodule_c5_index: 16gpio_index: 27 +io_4iomodule_c5_index: 6gpio_index: 441 +io_4iomodule_c5_index: 50gpio_index: 30 +io_4iomodule_c5_index: 35gpio_index: 437 +io_4iomodule_c5_index: 7gpio_index: 35 +io_4iomodule_c5_index: 53gpio_index: 433 +io_4iomodule_c5_index: 12gpio_index: 38 +io_4iomodule_c5_index: 1gpio_index: 429 +io_4iomodule_c5_index: 22gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 425 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 30gpio_index: 421 +io_4iomodule_c5_index: 2gpio_index: 51 +io_4iomodule_c5_index: 31gpio_index: 417 +io_4iomodule_c5_index: 39gpio_index: 54 +io_4iomodule_c5_index: 18gpio_index: 413 +io_4iomodule_c5_index: 10gpio_index: 59 +io_4iomodule_c5_index: 42gpio_index: 409 +io_4iomodule_c5_index: 5gpio_index: 62 +io_4iomodule_c5_index: 24gpio_index: 405 +io_4iomodule_c5_index: 37gpio_index: 67 +io_4iomodule_c5_index: 13gpio_index: 401 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 44gpio_index: 397 +io_4iomodule_c5_index: 38gpio_index: 75 +io_4iomodule_c5_index: 52gpio_index: 393 +io_4iomodule_c5_index: 32gpio_index: 78 +io_4iomodule_c5_index: 56gpio_index: 389 +io_4iomodule_a_index: 13gpio_index: 385 +io_4iomodule_c5_index: 4gpio_index: 83 +io_4iomodule_c5_index: 23gpio_index: 86 +io_4iomodule_a_index: 15gpio_index: 381 +io_4iomodule_a_index: 8gpio_index: 377 +io_4iomodule_c5_index: 46gpio_index: 91 +io_4iomodule_a_index: 5gpio_index: 373 +io_4iomodule_a_index: 11gpio_index: 369 +io_4iomodule_c5_index: 41gpio_index: 94 +io_4iomodule_a_index: 3gpio_index: 365 +io_4iomodule_c5_index: 25gpio_index: 99 +io_4iomodule_a_index: 7gpio_index: 361 +io_4iomodule_c5_index: 9gpio_index: 102 +io_4iomodule_a_index: 0gpio_index: 357 +io_4iomodule_c5_index: 14gpio_index: 107 +io_4iomodule_a_index: 12gpio_index: 353 +io_4iomodule_c5_index: 45gpio_index: 110 +io_4iomodule_c5_index: 17gpio_index: 115 +io_4iomodule_a_index: 4gpio_index: 349 +io_4iomodule_c5_index: 36gpio_index: 118 +io_4iomodule_a_index: 10gpio_index: 345 +io_4iomodule_a_index: 16gpio_index: 341 +io_4iomodule_c5_index: 15gpio_index: 123 +io_4iomodule_a_index: 14gpio_index: 337 +io_4iomodule_c5_index: 43gpio_index: 126 +io_4iomodule_c5_index: 19gpio_index: 131 +io_4iomodule_a_index: 1gpio_index: 333 +io_4iomodule_c5_index: 59gpio_index: 134 +io_4iomodule_a_index: 2gpio_index: 329 +io_4iomodule_a_index: 9gpio_index: 325 +io_4iomodule_c5_index: 48gpio_index: 139 +io_4iomodule_a_index: 6gpio_index: 321 +io_4iomodule_a_index: 17gpio_index: 317 +io_4iomodule_c5_index: 40gpio_index: 142 +io_4iomodule_c5_index: 11gpio_index: 147 +io_4iomodule_c5_index: 58gpio_index: 150 +io_4iomodule_c5_index: 21gpio_index: 155 +io_4iomodule_c5_index: 49gpio_index: 158 +io_4iomodule_h_c5_index: 0gpio_index: 161 +io_4iomodule_h_c5_index: 6gpio_index: 165 +io_4iomodule_h_c5_index: 10gpio_index: 169 +io_4iomodule_h_c5_index: 3gpio_index: 173 +io_4iomodule_h_c5_index: 8gpio_index: 176 +io_4iomodule_h_c5_index: 11gpio_index: 180 +io_4iomodule_h_c5_index: 7gpio_index: 184 +io_4iomodule_h_c5_index: 5gpio_index: 188 +io_4iomodule_h_c5_index: 1gpio_index: 192 +io_4iomodule_h_c5_index: 2gpio_index: 196 +io_4iomodule_h_c5_index: 9gpio_index: 200 +io_4iomodule_h_c5_index: 4gpio_index: 204 +io_4iomodule_h_index: 15gpio_index: 208 +io_4iomodule_h_index: 1gpio_index: 212 +io_4iomodule_h_index: 3gpio_index: 216 +io_4iomodule_h_index: 2gpio_index: 220 +io_4iomodule_h_index: 11gpio_index: 224 +io_4iomodule_vref_h_index: 1gpio_index: 228 +io_4iomodule_h_index: 20gpio_index: 231 +io_4iomodule_h_index: 8gpio_index: 235 +io_4iomodule_h_index: 6gpio_index: 239 +io_4iomodule_h_index: 10gpio_index: 243 +io_4iomodule_h_index: 23gpio_index: 247 +io_4iomodule_h_index: 7gpio_index: 251 +io_4iomodule_h_index: 22gpio_index: 255 +io_4iomodule_h_index: 5gpio_index: 259 +io_4iomodule_h_index: 24gpio_index: 263 +io_4iomodule_h_index: 0gpio_index: 267 +io_4iomodule_h_index: 13gpio_index: 271 +io_4iomodule_h_index: 21gpio_index: 275 +io_4iomodule_h_index: 16gpio_index: 279 +io_4iomodule_vref_h_index: 0gpio_index: 283 +io_4iomodule_h_index: 12gpio_index: 286 +io_4iomodule_h_index: 4gpio_index: 290 +io_4iomodule_h_index: 19gpio_index: 294 +io_4iomodule_h_index: 18gpio_index: 298 +io_4iomodule_h_index: 17gpio_index: 302 +io_4iomodule_h_index: 25gpio_index: 306 +io_4iomodule_h_index: 14gpio_index: 310 +io_4iomodule_h_index: 9gpio_index: 314 Index: test_rtl/jtag_ram_test/ram_test.qpf =================================================================== --- test_rtl/jtag_ram_test/ram_test.qpf (nonexistent) +++ test_rtl/jtag_ram_test/ram_test.qpf (revision 38) @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +# Date created = 17:14:14 January 06, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.1" +DATE = "17:14:14 January 06, 2018" + +# Revisions + +PROJECT_REVISION = "ram_test" Index: test_rtl/jtag_ram_test/ram_test.qsf =================================================================== --- test_rtl/jtag_ram_test/ram_test.qsf (nonexistent) +++ test_rtl/jtag_ram_test/ram_test.qsf (revision 38) @@ -0,0 +1,504 @@ +# Generated using ProNoC +#============================================================ +# Build by Terasic V1.0.0 +#============================================================ + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name TOP_LEVEL_ENTITY "DE10_Nano_golden_top" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2 +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:08:14 OCTOBER 14, 2016" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA + + + +#============================================================ +# ADC +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + +#============================================================ +# ARDUINO +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N + +#============================================================ +# FPGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 + +#============================================================ +# GPIO +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] + +#============================================================ +# HDMI +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS + +#============================================================ +# HPS +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + + +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO +set_location_assignment PIN_AG13 -to ARDUINO_IO[0] +set_location_assignment PIN_AF13 -to ARDUINO_IO[1] +set_location_assignment PIN_AG10 -to ARDUINO_IO[2] +set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +set_location_assignment PIN_U14 -to ARDUINO_IO[4] +set_location_assignment PIN_U13 -to ARDUINO_IO[5] +set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +set_location_assignment PIN_AG11 -to ARDUINO_IO[15] +set_location_assignment PIN_AH7 -to ARDUINO_RESET_N +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 +set_location_assignment PIN_V12 -to GPIO_0[0] +set_location_assignment PIN_E8 -to GPIO_0[1] +set_location_assignment PIN_W12 -to GPIO_0[2] +set_location_assignment PIN_D11 -to GPIO_0[3] +set_location_assignment PIN_D8 -to GPIO_0[4] +set_location_assignment PIN_AH13 -to GPIO_0[5] +set_location_assignment PIN_AF7 -to GPIO_0[6] +set_location_assignment PIN_AH14 -to GPIO_0[7] +set_location_assignment PIN_AF4 -to GPIO_0[8] +set_location_assignment PIN_AH3 -to GPIO_0[9] +set_location_assignment PIN_AD5 -to GPIO_0[10] +set_location_assignment PIN_AG14 -to GPIO_0[11] +set_location_assignment PIN_AE23 -to GPIO_0[12] +set_location_assignment PIN_AE6 -to GPIO_0[13] +set_location_assignment PIN_AD23 -to GPIO_0[14] +set_location_assignment PIN_AE24 -to GPIO_0[15] +set_location_assignment PIN_D12 -to GPIO_0[16] +set_location_assignment PIN_AD20 -to GPIO_0[17] +set_location_assignment PIN_C12 -to GPIO_0[18] +set_location_assignment PIN_AD17 -to GPIO_0[19] +set_location_assignment PIN_AC23 -to GPIO_0[20] +set_location_assignment PIN_AC22 -to GPIO_0[21] +set_location_assignment PIN_Y19 -to GPIO_0[22] +set_location_assignment PIN_AB23 -to GPIO_0[23] +set_location_assignment PIN_AA19 -to GPIO_0[24] +set_location_assignment PIN_W11 -to GPIO_0[25] +set_location_assignment PIN_AA18 -to GPIO_0[26] +set_location_assignment PIN_W14 -to GPIO_0[27] +set_location_assignment PIN_Y18 -to GPIO_0[28] +set_location_assignment PIN_Y17 -to GPIO_0[29] +set_location_assignment PIN_AB25 -to GPIO_0[30] +set_location_assignment PIN_AB26 -to GPIO_0[31] +set_location_assignment PIN_Y11 -to GPIO_0[32] +set_location_assignment PIN_AA26 -to GPIO_0[33] +set_location_assignment PIN_AA13 -to GPIO_0[34] +set_location_assignment PIN_AA11 -to GPIO_0[35] +set_location_assignment PIN_Y15 -to GPIO_1[0] +set_location_assignment PIN_AC24 -to GPIO_1[1] +set_location_assignment PIN_AA15 -to GPIO_1[2] +set_location_assignment PIN_AD26 -to GPIO_1[3] +set_location_assignment PIN_AG28 -to GPIO_1[4] +set_location_assignment PIN_AF28 -to GPIO_1[5] +set_location_assignment PIN_AE25 -to GPIO_1[6] +set_location_assignment PIN_AF27 -to GPIO_1[7] +set_location_assignment PIN_AG26 -to GPIO_1[8] +set_location_assignment PIN_AH27 -to GPIO_1[9] +set_location_assignment PIN_AG25 -to GPIO_1[10] +set_location_assignment PIN_AH26 -to GPIO_1[11] +set_location_assignment PIN_AH24 -to GPIO_1[12] +set_location_assignment PIN_AF25 -to GPIO_1[13] +set_location_assignment PIN_AG23 -to GPIO_1[14] +set_location_assignment PIN_AF23 -to GPIO_1[15] +set_location_assignment PIN_AG24 -to GPIO_1[16] +set_location_assignment PIN_AH22 -to GPIO_1[17] +set_location_assignment PIN_AH21 -to GPIO_1[18] +set_location_assignment PIN_AG21 -to GPIO_1[19] +set_location_assignment PIN_AH23 -to GPIO_1[20] +set_location_assignment PIN_AA20 -to GPIO_1[21] +set_location_assignment PIN_AF22 -to GPIO_1[22] +set_location_assignment PIN_AE22 -to GPIO_1[23] +set_location_assignment PIN_AG20 -to GPIO_1[24] +set_location_assignment PIN_AF21 -to GPIO_1[25] +set_location_assignment PIN_AG19 -to GPIO_1[26] +set_location_assignment PIN_AH19 -to GPIO_1[27] +set_location_assignment PIN_AG18 -to GPIO_1[28] +set_location_assignment PIN_AH18 -to GPIO_1[29] +set_location_assignment PIN_AF18 -to GPIO_1[30] +set_location_assignment PIN_AF20 -to GPIO_1[31] +set_location_assignment PIN_AG15 -to GPIO_1[32] +set_location_assignment PIN_AE20 -to GPIO_1[33] +set_location_assignment PIN_AE19 -to GPIO_1[34] +set_location_assignment PIN_AE17 -to GPIO_1[35] +set_location_assignment PIN_U10 -to HDMI_I2C_SCL +set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +set_location_assignment PIN_T13 -to HDMI_I2S +set_location_assignment PIN_T11 -to HDMI_LRCLK +set_location_assignment PIN_U11 -to HDMI_MCLK +set_location_assignment PIN_T12 -to HDMI_SCLK +set_location_assignment PIN_AG5 -to HDMI_TX_CLK +set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +set_location_assignment PIN_W8 -to HDMI_TX_D[2] +set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +set_location_assignment PIN_AD19 -to HDMI_TX_DE +set_location_assignment PIN_T8 -to HDMI_TX_HS +set_location_assignment PIN_AF11 -to HDMI_TX_INT +set_location_assignment PIN_V13 -to HDMI_TX_VS + +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + +set_global_assignment -name SDC_FILE DE10_Nano_golden_top.sdc +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + + + set_global_assignment -name TOP_LEVEL_ENTITY Top + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/ram_test.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/ram_test_top.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/Top.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/wb_bram_ctrl.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/main_comp.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/wb_single_port_ram.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/clk_source.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/generic_ram.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/altera_reset_synchronizer.v + set_global_assignment -name SYSTEMVERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/byte_enabled_generic_ram.sv + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/wishbone_bus.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/arbiter.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/jtag_wb/jtag_system_en.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/jtag_wb/jtag_source_probe.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/jtag_wb/vjtag.v + set_global_assignment -name VERILOG_FILE /home/alireza/mywork/mpsoc_work/SOC/ram_test/src_verilog/lib/jtag_wb/vjtag_wb.v Index: test_rtl/jtag_ram_test/src_verilog/Top.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/Top.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/Top.v (revision 38) @@ -0,0 +1,37 @@ + +/********************************************************************** +** File: Top.v +** +** Copyright (C) 2014-2018 Alireza Monemi +** +** This file is part of ProNoC 1.7.0 +** +** ProNoC ( stands for Prototype Network-on-chip) is free software: +** you can redistribute it and/or modify it under the terms of the GNU +** Lesser General Public License as published by the Free Software Foundation, +** either version 2 of the License, or (at your option) any later version. +** +** ProNoC is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with ProNoC. If not, see . +******************************************************************************/ + +module Top ( + FPGA_CLK1_50, + KEY +); + input FPGA_CLK1_50; + input [1 : 0] KEY; + + + ram_test_top uut( + .ss_clk_in( FPGA_CLK1_50 ), + .ss_reset_in(~ KEY [ 0]) + ); + + +endmodule Index: test_rtl/jtag_ram_test/src_verilog/lib/altera_reset_synchronizer.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/lib/altera_reset_synchronizer.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/lib/altera_reset_synchronizer.v (revision 38) @@ -0,0 +1,87 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2013/02/11 $ +// $Author: swbranch $ + +// ----------------------------------------------- +// Reset Synchronizer +// ----------------------------------------------- +`timescale 1 ns / 1 ns + +module altera_reset_synchronizer +#( + parameter ASYNC_RESET = 1, + parameter DEPTH = 2 +) +( + input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, + + input clk, + output reset_out +); + + // ----------------------------------------------- + // Synchronizer register chain. We cannot reuse the + // standard synchronizer in this implementation + // because our timing constraints are different. + // + // Instead of cutting the timing path to the d-input + // on the first flop we need to cut the aclr input. + // + // We omit the "preserve" attribute on the final + // output register, so that the synthesis tool can + // duplicate it where needed. + // ----------------------------------------------- + (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; + reg altera_reset_synchronizer_int_chain_out; + + generate if (ASYNC_RESET) begin + + // ----------------------------------------------- + // Assert asynchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk or posedge reset_in) begin + if (reset_in) begin + altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; + altera_reset_synchronizer_int_chain_out <= 1'b1; + end + else begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end else begin + + // ----------------------------------------------- + // Assert synchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk) begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end + endgenerate + +endmodule + Index: test_rtl/jtag_ram_test/src_verilog/lib/arbiter.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/lib/arbiter.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/lib/arbiter.v (revision 38) @@ -0,0 +1,877 @@ + `timescale 1ns/1ps +/********************************************************************** +** File: arbiter.v +** +** Copyright (C) 2014-2017 Alireza Monemi +** +** This file is part of ProNoC +** +** ProNoC ( stands for Prototype Network-on-chip) is free software: +** you can redistribute it and/or modify it under the terms of the GNU +** Lesser General Public License as published by the Free Software Foundation, +** either version 2 of the License, or (at your option) any later version. +** +** ProNoC is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with ProNoC. If not, see . +** +** +** +** Description: +** This file contains several Fixed prority and round robin +** arbiters +** +******************************************************************************/ + + +/***************************************** +* +* general round robin arbiter +* +* +******************************************/ + +module arbiter #( + parameter ARBITER_WIDTH =8 + +) +( + clk, + reset, + request, + grant, + any_grant +); + + + input [ARBITER_WIDTH-1 : 0] request; + output [ARBITER_WIDTH-1 : 0] grant; + output any_grant; + input clk; + input reset; + + + + generate + if(ARBITER_WIDTH==1) begin: w1 + assign grant= request; + assign any_grant =request; + end else if(ARBITER_WIDTH<=4) begin: w4 + //my own arbiter + my_one_hot_arbiter #( + .ARBITER_WIDTH (ARBITER_WIDTH) + ) + one_hot_arb + ( + .clk (clk), + .reset (reset), + .request (request), + .grant (grant), + .any_grant (any_grant) + ); + + end else begin : wb4 + + thermo_arbiter #( + .ARBITER_WIDTH (ARBITER_WIDTH) + ) + one_hot_arb + ( + .clk (clk), + .reset (reset), + .request (request), + .grant (grant), + .any_grant (any_grant) + ); + end + endgenerate +endmodule + +/***************************************** +* +* arbiter_priority_en +* RRA with external priority enable signal +* +******************************************/ + +module arbiter_priority_en #( + parameter ARBITER_WIDTH =8 + +) +( + clk, + reset, + request, + grant, + any_grant, + priority_en +); + + + + + input [ARBITER_WIDTH-1 : 0] request; + output [ARBITER_WIDTH-1 : 0] grant; + output any_grant; + input clk; + input reset; + input priority_en; + + + generate + if(ARBITER_WIDTH==1) begin: w1 + assign grant= request; + assign any_grant =request; + end else if(ARBITER_WIDTH<=4) begin: w4 + //my own arbiter + my_one_hot_arbiter_priority_en #( + .ARBITER_WIDTH (ARBITER_WIDTH) + ) + one_hot_arb + ( + .clk (clk), + .reset (reset), + .request (request), + .grant (grant), + .any_grant (any_grant), + .priority_en (priority_en) + + ); + + end else begin :wb4 + + thermo_arbiter_priority_en #( + .ARBITER_WIDTH (ARBITER_WIDTH) + ) + one_hot_arb + ( + .clk (clk), + .reset (reset), + .request (request), + .grant (grant), + .any_grant (any_grant), + .priority_en (priority_en) + ); + end +endgenerate +endmodule + + + +/****************************************************** +* my_one_hot_arbiter +* RRA with binary-coded priority register. Binary-coded +* Priority results in less area cost and CPD for arbire +* width of 4 and smaller only. +* +******************************************************/ + + + +module my_one_hot_arbiter #( + parameter ARBITER_WIDTH =4 + + +) +( + input [ARBITER_WIDTH-1 : 0] request, + output [ARBITER_WIDTH-1 : 0] grant, + output any_grant, + input clk, + input reset +); + + function integer log2; + input integer number; begin + log2=(number <=1) ? 1: 0; + while(2**log2. +** +** +** Description: +** Generic single dual port ram +** +** +*******************************************************************/ + +`timescale 1ns / 1ps + + +/******************** +* generic_dual_port_ram +********************/ + +module generic_dual_port_ram #( + parameter Dw=8, + parameter Aw=6, + parameter BYTE_WR_EN= "YES",//"YES","NO" + parameter INITIAL_EN= "NO", + parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format +) +( + data_a, + data_b, + addr_a, + addr_b, + byteena_a, + byteena_b, + we_a, + we_b, + clk, + q_a, + q_b +); + +localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1; + + input [(Dw-1):0] data_a, data_b; + input [(Aw-1):0] addr_a, addr_b; + input [BYTE_ENw-1 : 0] byteena_a, byteena_b; + input we_a, we_b, clk; + output [(Dw-1):0] q_a, q_b; + +generate +if ( BYTE_WR_EN == "NO") begin : no_byten + + dual_port_ram #( + .Dw (Dw), + .Aw (Aw), + .INITIAL_EN(INITIAL_EN), + .INIT_FILE(INIT_FILE) + ) + the_ram + ( + .data_a (data_a), + .data_b (data_b), + .addr_a (addr_a), + .addr_b (addr_b), + .we_a (we_a), + .we_b (we_b), + .clk (clk), + .q_a (q_a), + .q_b (q_b) + ); + +end else begin : byten + + byte_enabled_true_dual_port_ram #( + .BYTE_WIDTH(8), + .ADDRESS_WIDTH(Aw), + .BYTES(Dw/8), + .INITIAL_EN(INITIAL_EN), + .INIT_FILE(INIT_FILE) + + ) + the_ram + ( + .addr1 (addr_a), + .addr2 (addr_b), + .be1 (byteena_a), + .be2 (byteena_b), + .data_in1 (data_a), + .data_in2 (data_b), + .we1 (we_a), + .we2 (we_b), + .clk (clk), + .data_out1 (q_a), + .data_out2 (q_b) + ); + end +endgenerate + +endmodule + + + + + + +/******************** +* generic_single_port_ram +********************/ + + + +module generic_single_port_ram #( + parameter Dw=8, + parameter Aw=6, + parameter BYTE_WR_EN= "YES",//"YES","NO" + parameter INITIAL_EN= "NO", + parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format +) +( + data, + addr, + byteen, + we, + clk, + q + +); + + localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1; + + input [(Dw-1):0] data; + input [(Aw-1):0] addr; + input [BYTE_ENw-1 : 0] byteen; + input we, clk; + output [(Dw-1):0] q; + +generate +if ( BYTE_WR_EN == "NO") begin : no_byten + + + single_port_ram #( + .Dw (Dw), + .Aw (Aw), + .INITIAL_EN(INITIAL_EN), + .INIT_FILE(INIT_FILE) + ) + the_ram + ( + .data (data), + .addr (addr), + .we (we), + .clk (clk), + .q (q) + ); + +end else begin : byten + + byte_enabled_single_port_ram #( + .BYTE_WIDTH(8), + .ADDRESS_WIDTH(Aw), + .BYTES(Dw/8), + .INITIAL_EN(INITIAL_EN), + .INIT_FILE(INIT_FILE) + + ) + the_ram + ( + .addr (addr), + .be (byteen), + .data_in(data), + .we (we), + .clk (clk), + .data_out(q) + ); +end +endgenerate + +endmodule + + + + + + + + + + + + + + + + + +/******************* + + dual_port_ram + +********************/ + + +// Quartus II Verilog Template +// True Dual Port RAM with single clock + + +module dual_port_ram +#( + parameter Dw=8, + parameter Aw=6, + parameter INITIAL_EN= "NO", + parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file +) +( + data_a, + data_b, + addr_a, + addr_b, + we_a, + we_b, + clk, + q_a, + q_b +); + + + input [(Dw-1):0] data_a, data_b; + input [(Aw-1):0] addr_a, addr_b; + input we_a, we_b, clk; + output reg [(Dw-1):0] q_a, q_b; + + // Declare the RAM variable + reg [Dw-1:0] ram[2**Aw-1:0]; + + // initial the memory if the file is defined + generate + if (INITIAL_EN == "YES") begin : init + initial $readmemh(INIT_FILE,ram); + end + endgenerate + + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + else + begin + q_a <= ram[addr_a]; + end + end + + // Port B + always @ (posedge clk) + begin + if (we_b) + begin + ram[addr_b] <= data_b; + q_b <= data_b; + end + else + begin + q_b <= ram[addr_b]; + end + end + + + +endmodule + + + +/**************** +*simple_dual_port_ram +* +*****************/ + + + +// Quartus II Verilog Template +// Simple Dual Port RAM with separate read/write addresses and +// single read/write clock + +module simple_dual_port_ram #( + parameter Dw=8, + parameter Aw=6, + parameter INITIAL_EN= "NO", + parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format +) +( + data, + read_addr, + write_addr, + we, + clk, + q +); + + input [Dw-1 :0] data; + input [Aw-1 :0] read_addr; + input [Aw-1 :0] write_addr; + input we; + input clk; + output reg [Dw-1 :0] q; + + + // Declare the RAM variable + reg [Dw-1:0] ram [2**Aw-1:0]; + + // initial the memory if the file is defined + generate + if (INITIAL_EN == "YES") begin : init + initial $readmemh(INIT_FILE,ram); + end + endgenerate + + always @ (posedge clk) + begin + // Write + if (we) + ram[write_addr] <= data; + + // Read (if read_addr == write_addr, return OLD data). To return + // NEW data, use = (blocking write) rather than <= (non-blocking write) + // in the write assignment. NOTE: NEW data may require extra bypass + // logic around the RAM. + q <= ram[read_addr]; + end + +endmodule + + + + + + + +/***************************** + + single_port_ram + + +*****************************/ + +// Quartus II Verilog Template +// Single port RAM with single read/write address + +module single_port_ram #( + parameter Dw=8, + parameter Aw=6, + parameter INITIAL_EN= "NO", + parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format +) +( + data, + addr, + we, + clk, + q +); + + input [(Dw-1):0] data; + input [(Aw-1):0] addr; + input we, clk; + output [(Dw-1):0] q; + + // Declare the RAM variable + reg [Dw-1:0] ram[2**Aw-1:0]; + + // initial the memory if the file is defined + generate + if (INITIAL_EN == "YES") begin : init + initial $readmemh(INIT_FILE,ram); + end + endgenerate + + // Variable to hold the registered read address + reg [Aw-1:0] addr_reg; + + always @ (posedge clk) + begin + // Write + if (we) + ram[addr] <= data; + addr_reg <= addr; + end + + // Continuous assignment implies read returns NEW data. + // This is the natural behavior of the TriMatrix memory + // blocks in Single Port mode. + assign q = ram[addr_reg]; + +endmodule + + + + Index: test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/jtag_source_probe.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/jtag_source_probe.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/jtag_source_probe.v (revision 38) @@ -0,0 +1,155 @@ + +/********************************************************************** +** File: jtag_source_probe.v +** +** +** Copyright (C) 2014-2017 Alireza Monemi +** +** This file is part of ProNoC +** +** ProNoC ( stands for Prototype Network-on-chip) is free software: +** you can redistribute it and/or modify it under the terms of the GNU +** Lesser General Public License as published by the Free Software Foundation, +** either version 2 of the License, or (at your option) any later version. +** +** ProNoC is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with ProNoC. If not, see . +** +** +** Description: +** Jtag source probe which can be read/write using host PC +** C-based software located in src_c/jtag +** . +** +*******************************************************************/ + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +module jtag_source_probe #( + parameter VJTAG_INDEX=127, + parameter Dw=2 //probe/probe width in bits + +)( + source, + probe +); + + + input [Dw-1 :0] probe; + output reg [Dw-1 :0] source; + + + + //vjtag vjtag signals declaration + wire [2:0] ir_out , ir_in; + wire tdo, tck, tdi; + wire cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir; + + + vjtag #( + .VJTAG_INDEX(VJTAG_INDEX) + ) + vjtag_inst ( + .ir_out ( ir_out ), + .tdo ( tdo ), + .ir_in ( ir_in ), + .tck ( tck ), + .tdi ( tdi ), + .virtual_state_cdr ( cdr ), + .virtual_state_cir ( cir ), + .virtual_state_e1dr ( e1dr ), + .virtual_state_e2dr ( e2dr ), + .virtual_state_pdr ( pdr ), + .virtual_state_sdr ( sdr ), + .virtual_state_udr ( udr ), + .virtual_state_uir ( uir ) + ); + + + // IR states + + + + reg [2:0] ir; + reg bypass_reg; + reg [Dw-1 : 0] shift_buffer,shift_buffer_next; + reg cdr_delayed,sdr_delayed; + reg [Dw-1 : 0] source_next;//,status_next; + + localparam BYPAS_ST= 3'b000, + SOURCE_ST=3'b001, + PROBE_ST =3'b010; + + + + assign ir_out = ir_in; // Just pass the IR out + assign tdo = (ir == BYPAS_ST) ? bypass_reg : shift_buffer[0]; + + + + + + always @(posedge tck ) + begin + if( uir ) ir <= ir_in; // Capture the instruction provided + bypass_reg <= tdi; + shift_buffer<=shift_buffer_next; + source<=source_next; + + end + +generate + if(Dw==1)begin :DW1 + always @ (*)begin + shift_buffer_next=shift_buffer; + source_next = source; + if( sdr ) shift_buffer_next= tdi; //,shift_buffer[DW-1:1]};// shift buffer + case(ir) + SOURCE_ST:begin + if (cdr ) shift_buffer_next = source; + if (udr ) source_next = shift_buffer; + end + PROBE_ST:begin + if (cdr ) shift_buffer_next = probe; + end + default begin + shift_buffer_next=shift_buffer; + source_next = source; + end + endcase + + end + end + else begin :DWB + always @ (*)begin + shift_buffer_next=shift_buffer; + source_next = source; + if( sdr ) shift_buffer_next= {tdi, shift_buffer[Dw-1:1]};// shift buffer + case(ir) + SOURCE_ST:begin + if (cdr ) shift_buffer_next = source; + if (udr ) source_next = shift_buffer ; + end + PROBE_ST:begin + if (cdr ) shift_buffer_next = probe; + end + default begin + shift_buffer_next=shift_buffer; + source_next = source; + end + endcase + end + + end +endgenerate + + +endmodule +

test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/jtag_source_probe.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/jtag_system_en.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/jtag_system_en.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/jtag_system_en.v (revision 38) @@ -0,0 +1,163 @@ +/********************************************************************** +** File: jtag_system_en.v +** +** +** Copyright (C) 2014-2017 Alireza Monemi +** +** This file is part of ProNoC +** +** ProNoC ( stands for Prototype Network-on-chip) is free software: +** you can redistribute it and/or modify it under the terms of the GNU +** Lesser General Public License as published by the Free Software Foundation, +** either version 2 of the License, or (at your option) any later version. +** +** ProNoC is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with ProNoC. If not, see . +** +** +** Description: +** each system single core or many core must have one jtag_system_en module in order +** to allow mmeory programming. +** This module has two output ports which can be programed using jtag interface: +** cpu_en: which can enable/disable the cpu cores. This port must be connected to all +** cpus enable port in order tio deactiavte them during memory programming +** system_reset: This pin must be ored by sytem global reset pin. The jtag memory +** programmer will reset the system before and after perogramming the memories. +** +*******************************************************************/ + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + + +module jtag_system_en ( + cpu_en, + system_reset + +); + output cpu_en, system_reset; + wire [1 : 0] jtag_out; + + jtag_control_port #( + .VJTAG_INDEX(127), + .DW(2) + + )enable( + .jtag_out(jtag_out) + ); + + assign system_reset=jtag_out[0]; + assign cpu_en=~jtag_out[1]; + +endmodule + + + +module jtag_control_port #( + parameter VJTAG_INDEX=127, + parameter DW=2 + +)( + jtag_out +); + + + output [DW-1 : 0] jtag_out; + + + + //vjtag vjtag signals declaration + wire [2:0] ir_out , ir_in; + wire tdo, tck, tdi; + wire cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir; + + + vjtag #( + .VJTAG_INDEX(VJTAG_INDEX) + ) + vjtag_inst ( + .ir_out ( ir_out ), + .tdo ( tdo ), + .ir_in ( ir_in ), + .tck ( tck ), + .tdi ( tdi ), + .virtual_state_cdr ( cdr ), + .virtual_state_cir ( cir ), + .virtual_state_e1dr ( e1dr ), + .virtual_state_e2dr ( e2dr ), + .virtual_state_pdr ( pdr ), + .virtual_state_sdr ( sdr ), + .virtual_state_udr ( udr ), + .virtual_state_uir ( uir ) + ); + + + // IR states + + + + reg [2:0] ir; + reg bypass_reg; + reg [DW-1 : 0] shift_buffer,shift_buffer_next; + reg cdr_delayed,sdr_delayed; + reg [DW-1 : 0] status,status_next; + + assign jtag_out = status ; + /* + always @(negedge tck) + begin + // Delay the CDR signal by one half clock cycle + cdr_delayed = cdr; + sdr_delayed = sdr; + end + */ + + assign ir_out = ir_in; // Just pass the IR out + assign tdo = (ir == 3'b000) ? bypass_reg : shift_buffer[0]; + + + + + + always @(posedge tck ) + begin + if( uir ) ir <= ir_in; // Capture the instruction provided + bypass_reg <= tdi; + shift_buffer<=shift_buffer_next; + status<=status_next; + + end + +generate + if(DW==1)begin :DW1 + always @ (*)begin + shift_buffer_next=shift_buffer; + status_next = status; + if( sdr ) shift_buffer_next= tdi; //,shift_buffer[DW-1:1]};// shift buffer + if((ir == 3'b001) & cdr ) shift_buffer_next = status; + if((ir == 3'b001) & udr ) status_next = shift_buffer; + end + end + else begin :DWB + always @ (*)begin + shift_buffer_next=shift_buffer; + status_next = status; + if( sdr ) shift_buffer_next= {tdi, shift_buffer[DW-1:1]};// shift buffer + if((ir == 3'b001) & cdr ) shift_buffer_next = status; + if((ir == 3'b001) & udr ) status_next = shift_buffer; + end + + end +endgenerate + + +endmodule + +

test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/jtag_system_en.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/vjtag.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/vjtag.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/vjtag.v (revision 38) @@ -0,0 +1,184 @@ +// megafunction wizard: %Virtual JTAG% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: sld_virtual_jtag + +// ============================================================ +// File Name: vjtag.v +// Megafunction Name(s): +// sld_virtual_jtag +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module vjtag #( + parameter VJTAG_INDEX=126 + +)( + ir_out, + tdo, + ir_in, + tck, + tdi, + virtual_state_cdr, + virtual_state_cir, + virtual_state_e1dr, + virtual_state_e2dr, + virtual_state_pdr, + virtual_state_sdr, + virtual_state_udr, + virtual_state_uir); + + input [2:0] ir_out; + input tdo; + output [2:0] ir_in; + output tck; + output tdi; + output virtual_state_cdr; + output virtual_state_cir; + output virtual_state_e1dr; + output virtual_state_e2dr; + output virtual_state_pdr; + output virtual_state_sdr; + output virtual_state_udr; + output virtual_state_uir; + + wire sub_wire0; + wire sub_wire1; + wire [2:0] sub_wire2; + wire sub_wire3; + wire sub_wire4; + wire sub_wire5; + wire sub_wire6; + wire sub_wire7; + wire sub_wire8; + wire sub_wire9; + wire sub_wire10; + wire virtual_state_cir = sub_wire0; + wire virtual_state_pdr = sub_wire1; + wire [2:0] ir_in = sub_wire2[2:0]; + wire tdi = sub_wire3; + wire virtual_state_udr = sub_wire4; + wire tck = sub_wire5; + wire virtual_state_e1dr = sub_wire6; + wire virtual_state_uir = sub_wire7; + wire virtual_state_cdr = sub_wire8; + wire virtual_state_e2dr = sub_wire9; + wire virtual_state_sdr = sub_wire10; + + sld_virtual_jtag sld_virtual_jtag_component ( + .ir_out (ir_out), + .tdo (tdo), + .virtual_state_cir (sub_wire0), + .virtual_state_pdr (sub_wire1), + .ir_in (sub_wire2), + .tdi (sub_wire3), + .virtual_state_udr (sub_wire4), + .tck (sub_wire5), + .virtual_state_e1dr (sub_wire6), + .virtual_state_uir (sub_wire7), + .virtual_state_cdr (sub_wire8), + .virtual_state_e2dr (sub_wire9), + .virtual_state_sdr (sub_wire10) + // synopsys translate_off + , + .jtag_state_cdr (), + .jtag_state_cir (), + .jtag_state_e1dr (), + .jtag_state_e1ir (), + .jtag_state_e2dr (), + .jtag_state_e2ir (), + .jtag_state_pdr (), + .jtag_state_pir (), + .jtag_state_rti (), + .jtag_state_sdr (), + .jtag_state_sdrs (), + .jtag_state_sir (), + .jtag_state_sirs (), + .jtag_state_tlr (), + .jtag_state_udr (), + .jtag_state_uir (), + .tms () + // synopsys translate_on + ); + defparam + sld_virtual_jtag_component.sld_auto_instance_index = "NO", + sld_virtual_jtag_component.sld_instance_index = VJTAG_INDEX, + sld_virtual_jtag_component.sld_ir_width = 3, + sld_virtual_jtag_component.sld_sim_action = "((0,1,7,3),(0,2,ff,20),(0,1,6,3),(0,2,ffffffff,20),(0,2,1,20),(0,2,2,20),(0,2,3,20),(0,2,4,20))", + sld_virtual_jtag_component.sld_sim_n_scan = 8, + sld_virtual_jtag_component.sld_sim_total_length = 198; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: show_jtag_state STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO" +// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "126" +// Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "3" +// Retrieval info: CONSTANT: SLD_SIM_ACTION STRING "((0,1,7,3),(0,2,ff,20),(0,1,6,3),(0,2,ffffffff,20),(0,2,1,20),(0,2,2,20),(0,2,3,20),(0,2,4,20))" +// Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "8" +// Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "198" +// Retrieval info: USED_PORT: ir_in 0 0 3 0 OUTPUT NODEFVAL "ir_in[2..0]" +// Retrieval info: USED_PORT: ir_out 0 0 3 0 INPUT NODEFVAL "ir_out[2..0]" +// Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck" +// Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi" +// Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo" +// Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr" +// Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir" +// Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr" +// Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr" +// Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr" +// Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr" +// Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr" +// Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir" +// Retrieval info: CONNECT: @ir_out 0 0 3 0 ir_out 0 0 3 0 +// Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0 +// Retrieval info: CONNECT: ir_in 0 0 3 0 @ir_in 0 0 3 0 +// Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0 +// Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0 +// Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf

test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/vjtag.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/vjtag_wb.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/vjtag_wb.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/vjtag_wb.v (revision 38) @@ -0,0 +1,323 @@ +module vjtag_wb #( + parameter VJTAG_INDEX=126, + parameter DW=32, + parameter AW=32, + parameter SW=32, + + //wishbone port parameters + parameter S_Aw = 7, + parameter M_Aw = 32, + parameter TAGw = 3, + parameter SELw = 4 + + +)( + clk, + reset, + status_i, + + //wishbone master interface signals + m_sel_o, + m_dat_o, + m_addr_o, + m_cti_o, + m_stb_o, + m_cyc_o, + m_we_o, + m_dat_i, + m_ack_i + +); + + //IO declaration + input reset,clk; + input [SW-1 : 0] status_i; + + //wishbone master interface signals + output [SELw-1 : 0] m_sel_o; + output [DW-1 : 0] m_dat_o; + output [M_Aw-1 : 0] m_addr_o; + output [TAGw-1 : 0] m_cti_o; + output m_stb_o; + output m_cyc_o; + output m_we_o; + input [DW-1 : 0] m_dat_i; + input m_ack_i; + + + localparam STATE_NUM=3, + IDEAL =1, + WB_WR_DATA=2, + WB_RD_DATA=4; + + reg [STATE_NUM-1 : 0] ps,ns; + + wire [DW-1 :0] data_out, data_in; + wire wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en; + reg wr_mem_en, rd_mem_en, wb_cap_rd; + + reg [AW-1 : 0] wb_addr,wb_addr_next; + reg [DW-1 : 0] wb_wr_data,wb_rd_data; + reg wb_addr_inc; + + + assign m_cti_o = 3'b000; + assign m_sel_o = 4'b1111; + assign m_cyc_o = m_stb_o; + assign m_stb_o = wr_mem_en | rd_mem_en; + assign m_we_o = wr_mem_en; + assign m_dat_o = wb_wr_data; + assign m_addr_o = wb_addr; + assign data_in = wb_rd_data; +//vjtag vjtag signals declaration + + +localparam VJ_DW= (DW > AW)? DW : AW; + + + vjtag_ctrl #( + .DW(VJ_DW), + .VJTAG_INDEX(VJTAG_INDEX), + .STW(SW) + ) + vjtag_ctrl_inst + ( + .clk(clk), + .reset(reset), + .data_out(data_out), + .data_in(data_in), + .wb_wr_addr_en(wb_wr_addr_en), + .wb_wr_data_en(wb_wr_data_en), + .wb_rd_data_en(wb_rd_data_en), + .status_i(status_i) + ); + + + + always @(posedge clk or posedge reset) begin + if(reset) begin + wb_addr <= {AW{1'b0}}; + wb_wr_data <= {DW{1'b0}}; + ps <= IDEAL; + end else begin + wb_addr <= wb_addr_next; + ps <= ns; + if(wb_wr_data_en) wb_wr_data <= data_out; + if(wb_cap_rd) wb_rd_data <= m_dat_i; + end + end + + + always @(*)begin + wb_addr_next= wb_addr; + if(wb_wr_addr_en) wb_addr_next = data_out [AW-1 : 0]; + else if (wb_addr_inc) wb_addr_next = wb_addr +1'b1; + end + + + + always @(*)begin + ns=ps; + wr_mem_en =1'b0; + rd_mem_en =1'b0; + wb_addr_inc=1'b0; + wb_cap_rd=1'b0; + case(ps) + IDEAL : begin + if(wb_wr_data_en) ns= WB_WR_DATA; + if(wb_rd_data_en) ns= WB_RD_DATA; + end + WB_WR_DATA: begin + wr_mem_en =1'b1; + if(m_ack_i) begin + ns=IDEAL; + wb_addr_inc=1'b1; + end + end + WB_RD_DATA: begin + rd_mem_en =1'b1; + if(m_ack_i) begin + wb_cap_rd=1'b1; + ns=IDEAL; + //wb_addr_inc=1'b1; + end + end + endcase + end + + //assign led={wb_addr[7:0], wb_wr_data[7:0]}; + +endmodule + + + + +module vjtag_ctrl #( + parameter DW=32, + parameter STW=2, // status width <= DW + parameter VJTAG_INDEX=126 + +)( + clk, + reset, + data_out, + data_in, + status_i, + wb_wr_addr_en, + wb_wr_data_en, + wb_rd_data_en +); + +//IO declaration + input reset,clk; + output [DW-1 :0] data_out; + input [DW-1 :0] data_in; + input [STW-1 :0] status_i; + output wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en; + + +//vjtag vjtag signals declaration + wire [2:0] ir_out , ir_in; + wire tdo, tck, tdi; + wire cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir; + + + vjtag #( + .VJTAG_INDEX(VJTAG_INDEX) + ) + vjtag_inst ( + .ir_out ( ir_out ), + .tdo ( tdo ), + .ir_in ( ir_in ), + .tck ( tck ), + .tdi ( tdi ), + .virtual_state_cdr ( cdr ), + .virtual_state_cir ( cir ), + .virtual_state_e1dr ( e1dr ), + .virtual_state_e2dr ( e2dr ), + .virtual_state_pdr ( pdr ), + .virtual_state_sdr ( sdr ), + .virtual_state_udr ( udr ), + .virtual_state_uir ( uir ) + ); + + + // IR states + localparam [2:0] UPDATE_WB_ADDR = 3'b111, + UPDATE_WB_WR_DATA = 3'b110, + UPDATE_WB_RD_DATA = 3'b101, + RD_STATUS =3'b100, + BYPASS = 3'b000; + + + // internal registers + reg [2:0] ir; + reg bypass_reg; + reg [DW-1 : 0] shift_buffer,shift_buffer_next; + reg cdr_delayed,sdr_delayed; + + + + /* + always @(negedge tck) + begin + // Delay the CDR signal by one half clock cycle + cdr_delayed = cdr; + sdr_delayed = sdr; + end + */ + + assign ir_out = ir_in; // Just pass the IR out + assign tdo = (ir == BYPASS) ? bypass_reg : shift_buffer[0]; + assign data_out = shift_buffer; + + + + + always @(posedge tck or posedge reset) + begin + if (reset)begin + ir <= 3'b000; + bypass_reg<=1'b0; + shift_buffer<={DW{1'b0}}; + + end else begin + if( uir ) ir <= ir_in; // Capture the instruction provided + bypass_reg <= tdi; + shift_buffer<=shift_buffer_next; + + end + end + + + + always @ (*)begin + shift_buffer_next=shift_buffer; + + if( sdr ) shift_buffer_next={tdi,shift_buffer[DW-1:1]};// shift buffer + case(ir) + RD_STATUS:begin + if( cdr ) shift_buffer_next[STW-1 : 0] = status_i; + end + default: begin + if( cdr ) shift_buffer_next = data_in; + end + endcase + end + + + + reg wb_wr_addr1, wb_wr_data1, wb_rd_data1; + //always @(posedge tck or posedge reset) + always @(*) + begin + //if( reset ) begin + // wb_wr_addr1<=1'b0; + // wb_wr_data1<=1'b0; + //end else begin + wb_wr_addr1=(ir== UPDATE_WB_ADDR || ir== UPDATE_WB_RD_DATA) & udr; + wb_wr_data1=(ir== UPDATE_WB_WR_DATA && udr ); + wb_rd_data1=(ir==UPDATE_WB_RD_DATA && cdr); + //end + end + + reg wb_wr_addr2, wb_wr_data2, wb_rd_data2; + reg wb_wr_addr3, wb_wr_data3, wb_rd_data3; + + always @(posedge clk or posedge reset) + begin + if( reset ) begin + wb_wr_addr2<=1'b0; + wb_wr_data2<=1'b0; + wb_wr_addr3<=1'b0; + wb_wr_data3<=1'b0; + wb_rd_data2<=1'b0; + wb_rd_data3<=1'b0; + end else begin + wb_wr_addr2<=wb_wr_addr1; + wb_wr_data2<=wb_wr_data1; + wb_wr_addr3<=wb_wr_addr2; + wb_wr_data3<=wb_wr_data2; + wb_rd_data2<=wb_rd_data1; + wb_rd_data3<=wb_rd_data2; + end + end + + assign wb_wr_addr_en =(wb_wr_addr2 & ~wb_wr_addr3); + assign wb_wr_data_en =(wb_wr_data2 & ~wb_wr_data3); + assign wb_rd_data_en =(wb_rd_data2 & ~wb_rd_data3); +endmodule + + + + + + + + + + + + + +

test_rtl/jtag_ram_test/src_verilog/lib/jtag_wb/vjtag_wb.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: test_rtl/jtag_ram_test/src_verilog/lib/main_comp.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/lib/main_comp.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/lib/main_comp.v (revision 38) @@ -0,0 +1,807 @@ + `timescale 1ns/1ps + + +/********************************************************************** +** File: main_comp.v +** +** Copyright (C) 2014-2017 Alireza Monemi +** +** This file is part of ProNoC +** +** ProNoC ( stands for Prototype Network-on-chip) is free software: +** you can redistribute it and/or modify it under the terms of the GNU +** Lesser General Public License as published by the Free Software Foundation, +** either version 2 of the License, or (at your option) any later version. +** +** ProNoC is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with ProNoC. If not, see . +** +** +** Description: +** This file contains several general RTL modules such as +** different types of multiplexors, converters and counters ... +** +**************************************************************/ + + + + + + + +/********************************* + + + + multiplexer + + + +********************************/ + +module one_hot_mux #( + parameter IN_WIDTH = 20, + parameter SEL_WIDTH = 5, + parameter OUT_WIDTH = IN_WIDTH/SEL_WIDTH + + ) + ( + input [IN_WIDTH-1 :0] mux_in, + output[OUT_WIDTH-1 :0] mux_out, + input[SEL_WIDTH-1 :0] sel + + ); + + wire [IN_WIDTH-1 :0] mask; + wire [IN_WIDTH-1 :0] masked_mux_in; + wire [SEL_WIDTH-1:0] mux_out_gen [OUT_WIDTH-1:0]; + + genvar i,j; + + //first selector masking + generate // first_mask = {sel[0],sel[0],sel[0],....,sel[n],sel[n],sel[n]} + for(i=0; i=CMP_VAL*(j+1))begin : if1 + assign gen[i][j] = in_sep[j][i-CMP_VAL]; + end + else if( i< CMP_VAL*(j+1) && i>= (CMP_VAL*j)) begin :if2 + assign gen[i][j] = in_sep[IN_NUM-1][i]; + end + else begin :els + assign gen[i][j] = in_sep[j][i]; + end + end// for i + end// for j + for(i=0;i1)? log2(ONE_HOT_WIDTH):1 +) +( + input [ONE_HOT_WIDTH-1 : 0] one_hot_code, + output [BIN_WIDTH-1 : 0] bin_code + +); + + + function integer log2; + input integer number; begin + log2=(number <=1) ? 1: 0; + while(2**log21)begin :if1 + for(i=0; i1)? log2(IN_NUM): 1; + + + input [IN_WIDTH-1 :0] mux_in; + output [OUT_WIDTH-1 :0] mux_out; + input [SEL_WIDTH_BIN-1 :0] sel; + genvar i; + + + generate + if(IN_NUM>1) begin :if1 + wire [OUT_WIDTH-1 :0] mux_in_2d [IN_NUM -1 :0]; + for (i=0; i< IN_NUM; i=i+1) begin : loop + assign mux_in_2d[i] =mux_in[((i+1)*OUT_WIDTH)-1 : i*OUT_WIDTH]; + end + assign mux_out = mux_in_2d[sel]; + end else begin :els + assign mux_out = mux_in; + end + endgenerate + +endmodule + + +/****************************** + + set_bits_counter + +*******************************/ + + +module set_bits_counter #( + parameter IN_WIDTH =120, + parameter OUT_WIDTH = log2(IN_WIDTH+1) + ) + ( + input [IN_WIDTH-1 : 0] in, + output [OUT_WIDTH-1 : 0] out + +); + + function integer log2; + input integer number; begin + log2=(number <=1) ? 1: 0; + while(2**log21) + for(i=0; ij) begin :if1 assign comp_array [i][j] = ~ comp_array [j][i-1]; end + else begin :els assign comp_array [i] [j] = numbers[i]<= numbers[j+1]; end + end//for j + assign min_out[i]= & comp_array[i]; + end//for i + end//else + endgenerate + +endmodule + + +/******************************************** + + Carry-based reduction parallel counter + + +********************************************/ +module parallel_counter #( + parameter IN_WIDTH =120 // max 127 +) +( + in, + out +); + + + + function integer log2; + input integer number; begin + log2=(number <=1) ? 1: 0; + while(2**log2 IN_WIDTH ) begin :w1 + assign pc_in = {{(PCIw-IN_WIDTH){1'b0}},in}; + end else begin:els + assign pc_in=in; + end // if + + if(PCIw == 7) begin :w7 + + PC_7_3 pc ( + .in(pc_in), + .out(pc_out) + ); + + end else if(PCIw == 15) begin :w15 + PC_15_4 pc ( + .in(pc_in), + .out(pc_out) + ); + + end else if(PCIw == 31) begin :w31 + PC_31_5 pc ( + .in(pc_in), + .out(pc_out) + ); + end else if(PCIw == 63) begin :w63 + PC_63_6 pc ( + .in(pc_in), + .out(pc_out) + ); + + end else begin :w127 + PC_127_7 pc ( + .in(pc_in), + .out(pc_out) + ); + end + + endgenerate + + assign out = pc_out[OUT_WIDTH-1 : 0]; + +endmodule + + + +//carry-sum generation blocks +module CS_GEN ( + in, + abc, + s +); + input [6 : 0] in; + output s; + output [2 : 0] abc; + + wire a,b,c,s; + wire [3 : 0] in1; + wire [2 : 0] in2; + wire [2 : 0] j1; + wire [1 : 0] j2; + + assign {in2,in1} = in; + assign j1= in1[3]+in1[2]+in1[1]+in1[0]; + assign j2= in2[2]+in2[1]+in2[0]; + + //s is asserted when both in1 and in2 have odd number of ones. + assign s = j1[0] ^ j2[0]; + // a is asserted when there are at least two ones in in1 (i.e., j1 >= 2); + assign a = (j1 > 3'd1); + + //b is asserted when there are at least two ones in in2 (i.e., j2 >= 2); + assign b = (j2 > 2'd1); + + // C is asserted when when j1 equals 4 or when s is asserted + assign c = (j1==4) | (j1[0] & j2[0]); + + assign abc = {a,b,c}; +endmodule + +/************************* + + (7,3) parallel counter + +*************************/ + +module PC_7_3 ( + in, + out + +); + input [6 : 0] in; + output [2 : 0] out; + + wire [2 : 0] abc; + + CS_GEN cs( + .in(in), + .abc(abc), + .s(out[0]) + ); + + assign out[2:1] = abc[2]+abc[1]+abc[0]; + + + + +endmodule + +/************************* + + (15,4) parallel counter + +*************************/ + +module PC_15_4 ( + in, + out + +); + input [14 : 0] in; + output [3 : 0] out; + + wire [2:0] abc0,abc1; + wire s0,s1,b2; + + CS_GEN cs0( + .in (in [6 : 0]), + .abc (abc0), + .s (s0) + ); + + CS_GEN cs1( + .in (in [13 : 7]), + .abc (abc1), + .s (s1) + ); + + assign {b2,out[0]} =in [14] + s0 +s1; + + PC_7_3 pc_sub( + .in({abc0,abc1,b2}), + .out(out[3:1]) + ); + + + + +endmodule + + +// (31,5) parallel counter +module PC_31_5 ( + in, + out + +); + localparam CS_NUM = 5; + + input [30 : 0] in; + output [4 : 0] out; + + + wire [CS_NUM-1 : 0] s; + wire [(CS_NUM*7)-1 : 0] cs_in; + wire [14 : 0] pc_15_in; + + assign cs_in ={s[3:0] ,in }; + + genvar i; + generate + for (i=0;i. +** +** +** Description: +** memory wishbone bus interface controller +** +** +*******************************************************************/ + + + +`timescale 1ns/1ps + +module wb_bram_ctrl #( + parameter Dw=32, //RAM data_width in bits + parameter Aw=10, //RAM address width + + // wishbon bus param + parameter BURST_MODE = "DISABLED", // "DISABLED" , "ENABLED" wisbone bus burst mode + parameter SELw = Dw/8, + parameter CTIw = 3, + parameter BTEw = 2 +)( + clk, + reset, + + //wishbone bus interface + sa_dat_i, + sa_sel_i, + sa_addr_i, + sa_cti_i, + sa_bte_i, + sa_stb_i, + sa_cyc_i, + sa_we_i, + sa_dat_o, + sa_ack_o, + sa_err_o, + sa_rty_o, + + // BRAM interface + d, + addr, + we, + q + + +); + + input clk; + input reset; + + // BRAM interface + output [Dw-1 : 0] d; + output [Aw-1 : 0] addr; + output we; + input [Dw-1 : 0] q; + +// Wishbone bus interface + input [Dw-1 : 0] sa_dat_i; + input [SELw-1 : 0] sa_sel_i; + input [Aw-1 : 0] sa_addr_i; + + input sa_stb_i; + input sa_cyc_i; + input sa_we_i; + input [CTIw-1 : 0] sa_cti_i; + input [BTEw-1 : 0] sa_bte_i; + + + output [Dw-1 : 0] sa_dat_o; + output sa_ack_o; + output sa_err_o; + output sa_rty_o; + + wire sa_ack; + + + // 3'b100 is reserved in wb4 interface. It is used for ni + // wire sa_ack_ni_burst = sa_stb_i ; //the ack is registerd inside the master in burst mode + // assign sa_ack_o = (sa_cti_i == 3'b100 ) ? sa_ack_ni_burst: sa_ack; + + assign sa_ack_o = sa_ack; + + generate if (BURST_MODE== "ENABLED") begin : burst_wb + + wb_burst_bram_ctrl #( + .Dw(Dw), + .Aw(Aw), + .SELw(SELw), + .CTIw(CTIw), + .BTEw(BTEw) + ) + bram_ctrl + ( + .clk(clk), + .reset(reset), + .d(d), + .addr(addr), + .we(we), + .q(q), + .sa_dat_i(sa_dat_i), + .sa_sel_i(sa_sel_i), + .sa_addr_i(sa_addr_i), + .sa_stb_i(sa_stb_i), + .sa_cyc_i(sa_cyc_i), + .sa_we_i(sa_we_i), + .sa_cti_i(sa_cti_i), + .sa_bte_i(sa_bte_i), + .sa_dat_o(sa_dat_o), + .sa_ack_o(sa_ack), + .sa_err_o(sa_err_o), + .sa_rty_o(sa_rty_o) + ); + + end else begin : no_burst + + + assign sa_dat_o = q; + assign d = sa_dat_i ; + assign addr = sa_addr_i; + assign we = sa_stb_i & sa_we_i; + assign sa_err_o = 1'b0; + assign sa_rty_o = 1'b0; + + reg ack; + assign sa_ack = ack; + + always @(posedge clk ) begin + if(reset) begin + ack <= 1'b0; + end else begin + ack <= (~sa_ack_o) & sa_stb_i; + end + end + + end + endgenerate + +endmodule + + + + + + + + + +module wb_burst_bram_ctrl #( + + parameter Dw=32, //RAM data_width in bits + parameter Aw=10, //RAM address width + + // wishbon bus param + parameter SELw = Dw/8, + parameter CTIw = 3, + parameter BTEw = 2 + +)( + clk, + reset, + + //wishbone bus interface + sa_dat_i, + sa_sel_i, + sa_addr_i, + sa_cti_i, + sa_bte_i, + sa_stb_i, + sa_cyc_i, + sa_we_i, + sa_dat_o, + sa_ack_o, + sa_err_o, + sa_rty_o, + + // BRAM interface + d, + addr, + we, + q + + +); + + `define UDLY 1 + + input clk; + input reset; + + // BRAM interface + output [Dw-1 : 0] d; + output [Aw-1 : 0] addr; + output we; + input [Dw-1 : 0] q; + + + + // Wishbone bus interface + input [Dw-1 : 0] sa_dat_i; + input [SELw-1 : 0] sa_sel_i; + input [Aw-1 : 0] sa_addr_i; + + input sa_stb_i; + input sa_cyc_i; + input sa_we_i; + input [CTIw-1 : 0] sa_cti_i; + input [BTEw-1 : 0] sa_bte_i; + + + output reg [Dw-1 : 0] sa_dat_o; + output reg sa_ack_o; + output reg sa_err_o; + output reg sa_rty_o; + + + + //Burst Type Extension for Incrementing and Decrementing bursts + localparam [1:0] + LINEAR = 2'b00, + FOUR_BEAT =2'b01, + EIGHT_BEAT=2'b10, + SIXTEEN_BEAT =2'b11; + + + + + + + localparam [2:0] ST_IDLE = 3'b000, + ST_BURST = 3'b001, + ST_END = 3'b010, + ST_SUBRD = 3'b100, + ST_SUB = 3'b101, + ST_SUBWR = 3'b110; + + + + + /*---------------------------------------------------------------------- + Internal Nets and Registers + ----------------------------------------------------------------------*/ + wire [Dw-1:0] data; // Data read from RAM + reg write_enable; // RAM write enable + reg [Dw-1:0] write_data, write_data_d; // RAM write data + reg [Aw+1:0] pmi_address, pmi_address_nxt; + reg [Aw+1:0] adr_linear_incr,adr_4_beat,adr_8_beat,adr_16_beat; + + reg [Aw-1:0] read_address, write_address; + reg sa_ack_o_nxt; + reg [Dw-1:0] read_data; + // reg read_enable; + reg raw_hazard, raw_hazard_nxt; + reg [Dw-1:0] sa_dat_i_d; + reg [3:0] sa_sel_i_d; + reg delayed_write; + + wire [Aw+1 : 0] addr_init = {sa_addr_i,2'b00}; + /*---------------------------------------------------------------------- + State Machine + ----------------------------------------------------------------------*/ + reg [2:0] state, state_nxt; + + always @(*) + case (state) + ST_IDLE: + if (sa_stb_i && sa_cyc_i && (sa_ack_o == 1'b0)) + if(sa_cti_i ==3'b100) + state_nxt = ST_IDLE; + else if ((sa_cti_i == 3'b000) || (sa_cti_i == 3'b111) ) + state_nxt = ST_END; + else + if (sa_we_i && (sa_sel_i != 4'b1111)) + state_nxt = ST_SUBRD; + else + state_nxt = ST_BURST; + else + state_nxt = state; + + ST_BURST: + if (sa_cti_i == 3'b111) + state_nxt = ST_IDLE; + else + state_nxt = state; + + ST_SUBRD: + state_nxt = ST_SUB; + + ST_SUB: + if (sa_cti_i == 3'b111) + state_nxt = ST_SUBWR; + else + state_nxt = state; + + default: + state_nxt = ST_IDLE; + endcase + + /*---------------------------------------------------------------------- + + ----------------------------------------------------------------------*/ + always @(*) + if ((state == ST_SUB) && (read_address == write_address)) + raw_hazard_nxt = 1'b1; + else + raw_hazard_nxt = 1'b0; + + /*---------------------------------------------------------------------- + Set up read to EBR + ----------------------------------------------------------------------*/ + always @(*) + begin + /* + if ((sa_we_i == 1'b0) + || (sa_we_i + && (((state == ST_IDLE) && ((sa_cti_i == 3'b000) || (sa_cti_i == 3'b111) || (sa_sel_i != 4'b1111))) + || (state == ST_SUBRD) + || ((state == ST_SUB) && (raw_hazard_nxt == 1'b0))))) + read_enable = 1'b1; + else + read_enable = 1'b0; + */ + read_data = raw_hazard ? write_data_d : data; + end + + /*---------------------------------------------------------------------- + Set up write to EBR + ----------------------------------------------------------------------*/ + always @(*) + begin + if ((sa_we_i + && (// Word Burst Write (first write in a sequence) + ((state == ST_IDLE) + && sa_cyc_i && sa_stb_i && (sa_cti_i != 3'b000) && (sa_cti_i !=3'b100) && (sa_cti_i != 3'b111) && (sa_sel_i == 4'b1111)) + // Single Write + || (state == ST_END) + // Burst Write (all writes beyond first write) + || (state == ST_BURST))) + // Sub-Word Burst Write + || ((state == ST_SUB) || (state == ST_SUBWR))) + write_enable = 1'b1; + else + write_enable = 1'b0; + + if ((state == ST_SUBRD) || (state == ST_SUB) || (state == ST_SUBWR)) + delayed_write = 1'b1; + else + delayed_write = 1'b0; + + write_data[7:0] = (delayed_write + ? (sa_sel_i_d[0] ? sa_dat_i_d[7:0] : read_data[7:0]) + : (sa_sel_i[0] ? sa_dat_i[7:0] : data[7:0])); + write_data[15:8] = (delayed_write + ? (sa_sel_i_d[1] ? sa_dat_i_d[15:8] : read_data[15:8]) + : (sa_sel_i[1] ? sa_dat_i[15:8] : data[15:8])); + write_data[23:16] = (delayed_write + ? (sa_sel_i_d[2] ? sa_dat_i_d[23:16] : read_data[23:16]) + : (sa_sel_i[2] ? sa_dat_i[23:16] : data[23:16])); + write_data[31:24] = (delayed_write + ? (sa_sel_i_d[3] ? sa_dat_i_d[31:24] : read_data[31:24]) + : (sa_sel_i[3] ? sa_dat_i[31:24] : data[31:24])); + end + + + /*---------------------------------------------------------------------- + Set up address to EBR + ----------------------------------------------------------------------*/ + always @(*) begin + if (// First address of any access is obtained from Wishbone signals + (state == ST_IDLE) + // Read for a Sub-Word Wishbone Burst Write + || (state == ST_SUB)) read_address = sa_addr_i; + else read_address = pmi_address[Aw+1:2]; + + if ((state == ST_SUB) || (state == ST_SUBWR)) write_address = pmi_address[Aw+1:2]; + else write_address = sa_addr_i; + + // Keep track of first address and subsequently increment it by 4 + // bytes on a burst read + if (sa_we_i) begin + //pmi_address_nxt = sa_addr_i[Aw+1:0]; + adr_linear_incr= addr_init; + adr_4_beat= addr_init; + adr_8_beat= addr_init; + adr_16_beat=addr_init; + end else + if (state == ST_IDLE) + if ((sa_sel_i == 4'b1000) || (sa_sel_i == 4'b0100) || (sa_sel_i == 4'b0010) || (sa_sel_i == 4'b0001))begin + //pmi_address_nxt = sa_addr_i[Aw+1:0] + 1'b1; + adr_linear_incr= addr_init + 1'b1; + adr_4_beat= {addr_init[Aw+1 :4], addr_init[3:0] + 1'b1}; + adr_8_beat= {addr_init[Aw+1 :5], addr_init[4:0] + 1'b1}; + adr_16_beat={addr_init[Aw+1 :6], addr_init[5:0] + 1'b1}; + end else if ((sa_sel_i == 4'b1100) || (sa_sel_i == 4'b0011))begin + //pmi_address_nxt = {(sa_addr_i[Aw+1:1] + 1'b1), 1'b0}; + adr_linear_incr= {(addr_init[Aw+1:1] + 1'b1), 1'b0}; + adr_4_beat= {addr_init[Aw+1 :4], {addr_init[3:1] +1'b1},1'b0}; + adr_8_beat= {addr_init[Aw+1 :5], {addr_init[4:1] +1'b1},1'b0}; + adr_16_beat={addr_init[Aw+1 :6], {addr_init[5:1] +1'b1},1'b0}; + end else begin + //pmi_address_nxt = {(sa_addr_i[Aw+1:2] + 1'b1), 2'b00}; + adr_linear_incr= {(addr_init[Aw+1:2] + 1'b1), 2'b00}; + adr_4_beat= {addr_init[Aw+1 :4], {addr_init[3:2] +1'b1},2'b00}; + adr_8_beat= {addr_init[Aw+1 :5], {addr_init[4:2] +1'b1},2'b00}; + adr_16_beat={addr_init[Aw+1 :6], {addr_init[5:2] +1'b1},2'b00}; + end + else + if ((sa_sel_i == 4'b1000) || (sa_sel_i == 4'b0100) || (sa_sel_i == 4'b0010) || (sa_sel_i == 4'b0001))begin + //pmi_address_nxt_linear_incr = pmi_address + 1'b1; + adr_linear_incr= pmi_address + 1'b1; + adr_4_beat= {pmi_address[Aw+1 :4], pmi_address[3:0] + 1'b1}; + adr_8_beat= {pmi_address[Aw+1 :5], pmi_address[4:0] + 1'b1}; + adr_16_beat={pmi_address[Aw+1 :6], pmi_address[5:0] + 1'b1}; + end else if ((sa_sel_i == 4'b1100) || (sa_sel_i == 4'b0011)) begin + // pmi_address_nxt = {pmi_address[Aw+1:1] + 1'b1), 1'b0}; + adr_linear_incr= {(pmi_address[Aw+1:1] + 1'b1), 1'b0}; + adr_4_beat= {pmi_address[Aw+1 :4], {pmi_address[3:1] + 1'b1},1'b0}; + adr_8_beat= {pmi_address[Aw+1 :5], {pmi_address[4:1] + 1'b1},1'b0}; + adr_16_beat={pmi_address[Aw+1 :6], {pmi_address[5:1] + 1'b1},1'b0}; + end else begin + //pmi_address_nxt_linear_incr = {(pmi_address[Aw+1:2] + 1'b1), 2'b00}; + adr_linear_incr= {(pmi_address[Aw+1:2] + 1'b1), 2'b00}; + adr_4_beat= {pmi_address[Aw+1 :4], {pmi_address[3:2] +1'b1},2'b00}; + adr_8_beat= {pmi_address[Aw+1 :5], {pmi_address[4:2] +1'b1},2'b00}; + adr_16_beat={pmi_address[Aw+1 :6], {pmi_address[5:2] +1'b1},2'b00}; + end + end + + + + + always @(*)begin + case(sa_bte_i) + LINEAR: pmi_address_nxt = adr_linear_incr; + FOUR_BEAT: pmi_address_nxt = adr_4_beat; + EIGHT_BEAT: pmi_address_nxt = adr_8_beat; + SIXTEEN_BEAT:pmi_address_nxt = adr_16_beat; + endcase + end + + + /*---------------------------------------------------------------------- + Set up outgoing wishbone signals + ----------------------------------------------------------------------*/ + always @(*) + begin + if (((state == ST_IDLE) && sa_cyc_i && sa_stb_i && (sa_ack_o == 1'b0)) + || (state == ST_BURST) + || (state == ST_SUBRD) + || (state == ST_SUB)) + sa_ack_o_nxt = 1'b1; + else + sa_ack_o_nxt = 1'b0; + + sa_dat_o = data; + sa_rty_o = 1'b0; + sa_err_o = 1'b0; + end + + /*---------------------------------------------------------------------- + Sequential Logic + ----------------------------------------------------------------------*/ + always @(posedge clk) + if (reset) + begin + sa_ack_o <= #`UDLY 1'b0; + sa_dat_i_d <= #`UDLY 0; + sa_sel_i_d <= #`UDLY 0; + state <= #`UDLY ST_IDLE; + pmi_address <= #`UDLY 0; + write_data_d <= #`UDLY 0; + raw_hazard <= #`UDLY 0; + end + else + begin + sa_ack_o <= #`UDLY sa_ack_o_nxt; + sa_dat_i_d <= #`UDLY sa_dat_i; + sa_sel_i_d <= #`UDLY sa_sel_i; + state <= #`UDLY state_nxt; + pmi_address <= #`UDLY pmi_address_nxt; + write_data_d <= #`UDLY write_data; + raw_hazard <= #`UDLY raw_hazard_nxt; + end + + + + + + assign d = write_data; + assign addr=(write_enable)? write_address : read_address; + assign we = write_enable; + assign data= q; + + + +endmodule Index: test_rtl/jtag_ram_test/src_verilog/lib/wb_single_port_ram.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/lib/wb_single_port_ram.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/lib/wb_single_port_ram.v (revision 38) @@ -0,0 +1,464 @@ +/********************************************************************** +** File: wb_dual_port_ram.v +** +** +** Copyright (C) 2014-2017 Alireza Monemi +** +** This file is part of ProNoC +** +** ProNoC ( stands for Prototype Network-on-chip) is free software: +** you can redistribute it and/or modify it under the terms of the GNU +** Lesser General Public License as published by the Free Software Foundation, +** either version 2 of the License, or (at your option) any later version. +** +** ProNoC is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with ProNoC. If not, see . +** +** +** Description: +** wishbone based single port ram +** +** +*******************************************************************/ + + +`timescale 1ns / 1ps + + + +module wb_single_port_ram #( + parameter Dw=32, //RAM data_width in bits + parameter Aw=10, //RAM address width + parameter BYTE_WR_EN= "YES",//"YES","NO" + parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC" + parameter JTAG_CONNECT= "JTAG_WB",//"DISABLED", "JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb + parameter JTAG_INDEX= 0, + parameter INITIAL_EN= "NO", + parameter MEM_CONTENT_FILE_NAME= "ram0",// ram initial file name + parameter INIT_FILE_PATH = "path_to/sw", // The sw folder path. It will be used for finding initial file. The path will be rewriten by the top module. + // wishbon bus param + parameter BURST_MODE= "DISABLED", // "DISABLED" , "ENABLED" wisbone bus burst mode + parameter TAGw = 3, + parameter SELw = Dw/8, + parameter CTIw = 3, + parameter BTEw = 2 + + + ) + ( + clk, + reset, + + //wishbone bus interface + sa_dat_i, + sa_sel_i, + sa_addr_i, + sa_tag_i, + sa_cti_i, + sa_bte_i, + sa_stb_i, + sa_cyc_i, + sa_we_i, + sa_dat_o, + sa_ack_o, + sa_err_o, + sa_rty_o + + ); + + + + + input clk; + input reset; + + + + + //wishbone bus interface + input [Dw-1 : 0] sa_dat_i; + input [SELw-1 : 0] sa_sel_i; + input [Aw-1 : 0] sa_addr_i; + input [TAGw-1 : 0] sa_tag_i; + input sa_stb_i; + input sa_cyc_i; + input sa_we_i; + input [CTIw-1 : 0] sa_cti_i; + input [BTEw-1 : 0] sa_bte_i; + + output [Dw-1 : 0] sa_dat_o; + output sa_ack_o; + output sa_err_o; + output sa_rty_o; + + + wire [Dw-1 : 0] d; + wire [Aw-1 : 0] addr; + wire we; + wire [Dw-1 : 0] q; + + + + + localparam MEM_NAME = (FPGA_VENDOR== "ALTERA")? {MEM_CONTENT_FILE_NAME,".mif"} : + {MEM_CONTENT_FILE_NAME,".hex"}; //Generic + + + localparam INIT_FILE = {INIT_FILE_PATH,"/RAM/",MEM_NAME}; + + + wb_bram_ctrl #( + .Dw(Dw), + .Aw(Aw), + .BURST_MODE(BURST_MODE), + .SELw(SELw), + .CTIw(CTIw), + .BTEw(BTEw) + ) + ctrl + ( + .clk(clk), + .reset(reset), + .d(d), + .addr(addr), + .we(we), + .q(q), + .sa_dat_i(sa_dat_i), + .sa_sel_i(sa_sel_i), + .sa_addr_i(sa_addr_i), + .sa_stb_i(sa_stb_i), + .sa_cyc_i(sa_cyc_i), + .sa_we_i(sa_we_i), + .sa_cti_i(sa_cti_i), + .sa_bte_i(sa_bte_i), + .sa_dat_o(sa_dat_o), + .sa_ack_o(sa_ack_o), + .sa_err_o(sa_err_o), + .sa_rty_o(sa_rty_o) + ); + + + + + + single_port_ram_top #( + .Dw(Dw), + .Aw(Aw), + .BYTE_WR_EN(BYTE_WR_EN), + .FPGA_VENDOR(FPGA_VENDOR), + .JTAG_CONNECT(JTAG_CONNECT), + .JTAG_INDEX(JTAG_INDEX), + .INITIAL_EN(INITIAL_EN), + .INIT_FILE(INIT_FILE) + ) + ram_top + ( + .reset(reset), + .clk(clk), + .data_a(d), + .addr_a(addr), + .we_a(we), + .q_a(q), + .byteena_a(sa_sel_i) + ); + + +endmodule + + + + + + + + + + + + + + + + + + +module single_port_ram_top #( + parameter Dw=32, //RAM data_width in bits + parameter Aw=10, //RAM address width + parameter BYTE_WR_EN= "YES",//"YES","NO" + parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC" + parameter JTAG_CONNECT= "JTAG_WB",//"DISABLED", "JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb + parameter JTAG_INDEX= 0, + parameter INITIAL_EN= "NO", + parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file + + ) + ( + reset, + clk, + data_a, + addr_a, + byteena_a, + we_a, + q_a +); + localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1; + +input clk,reset; +input [Dw-1 : 0] data_a; +input [Aw-1 : 0] addr_a; +input we_a; +input [BYTE_ENw-1 : 0] byteena_a; +output [Dw-1 : 0] q_a; + + + + function [15:0]i2s; + input integer c; integer i; integer tmp; begin + tmp =0; + for (i=0; i<2; i=i+1'b1) begin + tmp = tmp + (((c % 10) + 6'd48) << i*8); + c = c/10; + end + i2s = tmp[15:0]; + end + endfunction //i2s + + function integer log2; + input integer number; begin + log2=0; + while(2**log2. +** +** +** Description: +** parametrizable wishbone bus +** +*******************************************************************/ + + + + + + + + +`timescale 10ns/1ns + + +module wishbone_bus #( + + parameter M = 4, //number of master port + parameter S = 4, //number of slave port + parameter Dw = 32, // maximum data width + parameter Aw = 32, // address width + parameter SELw = 2, + parameter TAGw = 3, //merged {tga,tgb,tgc} + parameter CTIw = 3, + parameter BTEw = 2 + + +) +( + //slaves interface + s_adr_o_all, + s_dat_o_all, + s_sel_o_all, + s_tag_o_all, + s_we_o_all, + s_cyc_o_all, + s_stb_o_all, + s_cti_o_all, + s_bte_o_all, + + s_dat_i_all, + s_ack_i_all, + s_err_i_all, + s_rty_i_all, + + + //masters interface + m_dat_o_all, + m_ack_o_all, + m_err_o_all, + m_rty_o_all, + + + m_adr_i_all, + m_dat_i_all, + m_sel_i_all, + m_tag_i_all, + m_we_i_all, + m_stb_i_all, + m_cyc_i_all, + m_cti_i_all, + m_bte_i_all, + + //address compar + m_grant_addr, + s_sel_one_hot, + + + //system signals + + clk, + reset + +); + + function integer log2; + input integer number; begin + log2=0; + while(2**log21)? log2(M):1, + Sw = (S>1)? log2(S):1, + CTIwM = CTIw * M, + BTEwM = BTEw * M; + + + + + + output [AwS-1 : 0] s_adr_o_all; + output [DwS-1 : 0] s_dat_o_all; + output [SELwS-1 : 0] s_sel_o_all; + output [TAGwS-1 : 0] s_tag_o_all; + output [S-1 : 0] s_we_o_all; + output [S-1 : 0] s_cyc_o_all; + output [S-1 : 0] s_stb_o_all; + output [CTIwS-1 : 0] s_cti_o_all; + output [BTEwS-1 : 0] s_bte_o_all; + + + input [DwS-1 : 0] s_dat_i_all; + input [S-1 : 0] s_ack_i_all; + input [S-1 : 0] s_err_i_all; + input [S-1 : 0] s_rty_i_all; + + + + + + //masters interface + output [DwM-1 : 0] m_dat_o_all; + output [M-1 : 0] m_ack_o_all; + output [M-1 : 0] m_err_o_all; + output [M-1 : 0] m_rty_o_all; + + + input [AwM-1 : 0] m_adr_i_all; + input [DwM-1 : 0] m_dat_i_all; + input [SELwM-1 : 0] m_sel_i_all; + input [TAGwM-1 : 0] m_tag_i_all; + input [M-1 : 0] m_we_i_all; + input [M-1 : 0] m_stb_i_all; + input [M-1 : 0] m_cyc_i_all; + input [CTIwM-1 : 0] m_cti_i_all; + input [BTEwM-1 : 0] m_bte_i_all; + + // + output [Aw-1 : 0] m_grant_addr; + input [S-1 : 0] s_sel_one_hot; + //system signals + + input clk, reset; + + + wire any_s_ack,any_s_err,any_s_rty; + wire m_grant_we,m_grant_stb,m_grant_cyc; + + wire [Dw-1 : 0] m_grant_dat,s_read_dat; + wire [SELw-1 : 0] m_grant_sel; + wire [BTEw-1 : 0] m_grant_bte; + wire [CTIw-1 : 0] m_grant_cti; + wire [TAGw-1 : 0] m_grant_tag; + + + wire [Sw-1 : 0] s_sel_bin; + wire [M-1 : 0] m_grant_onehot; + wire [Mw-1 : 0] m_grant_bin; + + wire [Aw-1 : 0] s_adr_o; + wire [Dw-1 : 0] s_dat_o; + wire [SELw-1 : 0] s_sel_o; + wire [BTEw-1 : 0] s_bte_o; + wire [CTIw-1 : 0] s_cti_o; + + wire [TAGw-1 : 0] s_tag_o; + wire s_we_o; + wire s_cyc_o; + wire [Dw-1 : 0] m_dat_o; + + + assign s_adr_o_all = {S{s_adr_o}}; + assign s_dat_o_all = {S{s_dat_o}}; + assign s_sel_o_all = {S{s_sel_o}}; + assign s_cti_o_all = {S{s_cti_o}}; + assign s_bte_o_all = {S{s_bte_o}}; + + assign s_tag_o_all = {S{s_tag_o}}; + assign s_we_o_all = {S{s_we_o}}; + assign s_cyc_o_all = {S{s_cyc_o}}; + assign m_dat_o_all= {M{m_dat_o}}; + + assign any_s_ack =| s_ack_i_all; + assign any_s_err =| s_err_i_all; + assign any_s_rty =| s_rty_i_all; + + assign s_adr_o = m_grant_addr; + assign s_dat_o = m_grant_dat; + assign s_sel_o = m_grant_sel; + assign s_bte_o = m_grant_bte; + assign s_cti_o = m_grant_cti; + assign s_tag_o = m_grant_tag; + assign s_we_o = m_grant_we; + assign s_cyc_o = m_grant_cyc; + assign s_stb_o_all = s_sel_one_hot & {S{m_grant_stb & m_grant_cyc}}; + + +//wire [ADDR_PERFIX-1 : 0] m_perfix_addr; +//assign m_perfix_addr = m_grant_addr[Aw-3 : Aw-ADDR_PERFIX-2]; + + +assign m_dat_o = s_read_dat; +assign m_ack_o_all = m_grant_onehot & {M{any_s_ack}}; +assign m_err_o_all = m_grant_onehot & {M{any_s_err}}; +assign m_rty_o_all = m_grant_onehot & {M{any_s_rty}}; + + + + +//convert one hot to bin + one_hot_to_bin #( + .ONE_HOT_WIDTH(S) + ) + s_sel_conv + ( + .one_hot_code(s_sel_one_hot), + .bin_code(s_sel_bin) + ); + + + + one_hot_to_bin #( + .ONE_HOT_WIDTH(M) + ) + m_grant_conv + ( + .one_hot_code (m_grant_onehot), + .bin_code (m_grant_bin) + ); + + + + //slave multiplexer + binary_mux #( + .IN_WIDTH (DwS), + .OUT_WIDTH (Dw) + ) + s_read_data_mux + ( + .mux_in (s_dat_i_all), + .mux_out (s_read_dat), + .sel (s_sel_bin) + + ); + + + //master ports multiplexers + + binary_mux #( + .IN_WIDTH (AwM), + .OUT_WIDTH (Aw) + ) + m_adr_mux + ( + .mux_in (m_adr_i_all), + .mux_out (m_grant_addr), + .sel (m_grant_bin) + + ); + + + + binary_mux #( + .IN_WIDTH (DwM), + .OUT_WIDTH (Dw) + ) + m_data_mux + ( + .mux_in (m_dat_i_all), + .mux_out (m_grant_dat), + .sel (m_grant_bin) + + ); + + + + binary_mux #( + .IN_WIDTH (SELwM), + .OUT_WIDTH (SELw) + ) + m_sel_mux + ( + .mux_in (m_sel_i_all), + .mux_out (m_grant_sel), + .sel (m_grant_bin) + + ); + + binary_mux #( + .IN_WIDTH (BTEwM), + .OUT_WIDTH (BTEw) + ) + m_bte_mux + ( + .mux_in (m_bte_i_all), + .mux_out (m_grant_bte), + .sel (m_grant_bin) + + ); + + binary_mux #( + .IN_WIDTH (CTIwM), + .OUT_WIDTH (CTIw) + ) + m_cti_mux + ( + .mux_in (m_cti_i_all), + .mux_out (m_grant_cti), + .sel (m_grant_bin) + + ); + + + binary_mux #( + .IN_WIDTH (TAGwM), + .OUT_WIDTH (TAGw) + ) + m_tag_mux + ( + .mux_in (m_tag_i_all), + .mux_out (m_grant_tag), + .sel (m_grant_bin) + + ); + + + binary_mux #( + .IN_WIDTH (M), + .OUT_WIDTH (1) + ) + m_we_mux + ( + .mux_in (m_we_i_all), + .mux_out (m_grant_we), + .sel (m_grant_bin) + + ); + + + /* + binary_mux #( + .IN_WIDTH (M), + .OUT_WIDTH (1) + ) + m_stb_mux + ( + .mux_in (m_stb_i_all), + .mux_out (m_grant_stb), + .sel (m_grant_bin) + + ); + + + + binary_mux #( + .IN_WIDTH (M), + .OUT_WIDTH (1) + ) + m_cyc_mux + ( + .mux_in (m_cyc_i_all), + .mux_out (m_grant_cyc), + .sel (m_grant_bin) + + ); + */ + // if m_grant_one_hot is zero the stb and cyc must not be asserted hence have to use one-hot mux + + + one_hot_mux #( + .IN_WIDTH(M), + .SEL_WIDTH(M), + .OUT_WIDTH(1) + ) + m_stb_mux + ( + .mux_in(m_stb_i_all), + .mux_out(m_grant_stb), + .sel(m_grant_onehot) + + ); + + + one_hot_mux #( + .IN_WIDTH(M), + .SEL_WIDTH(M), + .OUT_WIDTH(1) + ) + m_cyc_mux + ( + .mux_in(m_cyc_i_all), + .mux_out(m_grant_cyc), + .sel(m_grant_onehot) + + ); + + + + + +generate + if(M > 1) begin + // round roubin arbiter + bus_arbiter # ( + .M (M) + ) + arbiter + ( + .request (m_cyc_i_all), + .grant (m_grant_onehot), + .clk (clk), + .reset (reset) + ); + end else begin // if we have just one master there is no needs for arbitration + assign m_grant_onehot = m_cyc_i_all; + end +endgenerate + + + +endmodule + + + + +/************** + + bus_arbiter + +**************/ + +module bus_arbiter # ( + parameter M = 4 +) +( + request, + grant, + clk, + reset +); + + input [M-1 : 0] request; + output [M-1 : 0] grant; + input clk, reset; + + wire comreq; + wire [M-1 : 0] one_hot_arb_req, one_hot_arb_grant; + reg [M-1 : 0] grant_registered; + + assign one_hot_arb_req = request & {M{~comreq}}; + assign grant = grant_registered; + + assign comreq = |(grant & request); + + always @ (posedge clk or posedge reset) begin + if (reset) begin + grant_registered <= {M{1'b0}}; + end else begin + if(~comreq) grant_registered <= one_hot_arb_grant; + end + end//always + + + arbiter #( + .ARBITER_WIDTH (M ) + ) + the_combinational_arbiter + ( + .request (one_hot_arb_req), + .grant (one_hot_arb_grant), + .any_grant (), + .clk (clk), + .reset (reset) + ); + + + + +endmodule Index: test_rtl/jtag_ram_test/src_verilog/ram_test.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/ram_test.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/ram_test.v (revision 38) @@ -0,0 +1,366 @@ + +/************************************************************************** +** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE +** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification. +****************************************************************************/ + + +/********************************************************************** +** File: ram_test.v +** +** Copyright (C) 2014-2018 Alireza Monemi +** +** This file is part of ProNoC 1.7.0 +** +** ProNoC ( stands for Prototype Network-on-chip) is free software: +** you can redistribute it and/or modify it under the terms of the GNU +** Lesser General Public License as published by the Free Software Foundation, +** either version 2 of the License, or (at your option) any later version. +** +** ProNoC is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with ProNoC. If not, see . +******************************************************************************/ + +`timescale 1ns / 1ps +module ram_test #( + parameter CORE_ID=0, + parameter SW_LOC="/home/alireza/mywork/mpsoc_work/SOC/ram_test/sw" , + parameter ram_Dw=32 , + parameter ram_Aw=12 +)( + ss_clk_in, + ss_reset_in +); + + function integer log2; + input integer number; begin + log2=0; + while(2**log2= ram_WB0_BASE_ADDR) & (bus_socket_wb_addr_map_0_grant_addr <= ram_WB0_END_ADDR)); + endmodule + Index: test_rtl/jtag_ram_test/src_verilog/ram_test_top.v =================================================================== --- test_rtl/jtag_ram_test/src_verilog/ram_test_top.v (nonexistent) +++ test_rtl/jtag_ram_test/src_verilog/ram_test_top.v (revision 38) @@ -0,0 +1,128 @@ + +/************************************************************************** +** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE +** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification. +****************************************************************************/ + + +/********************************************************************** +** File: ram_test_top.v +** +** Copyright (C) 2014-2018 Alireza Monemi +** +** This file is part of ProNoC 1.7.0 +** +** ProNoC ( stands for Prototype Network-on-chip) is free software: +** you can redistribute it and/or modify it under the terms of the GNU +** Lesser General Public License as published by the Free Software Foundation, +** either version 2 of the License, or (at your option) any later version. +** +** ProNoC is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with ProNoC. If not, see . +******************************************************************************/ + +`timescale 1ns / 1ps + +module ram_test_top #( + parameter CORE_ID=0, + parameter SW_LOC="/home/alireza/mywork/mpsoc_work/SOC/ram_test/sw" , + parameter ram_Dw=32 , + parameter ram_Aw=12 +)( + ss_clk_in, + ss_reset_in +); + + function integer log2; + input integer number; begin + log2=0; + while(2**log2

test_rtl/jtag_ram_test/sw/RAM/ram0.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: test_rtl/jtag_ram_test/sw/RAM/ram0.hex =================================================================== --- test_rtl/jtag_ram_test/sw/RAM/ram0.hex (nonexistent) +++ test_rtl/jtag_ram_test/sw/RAM/ram0.hex (revision 38) @@ -0,0 +1,427 @@ +B8080050 +00000000 +B80802DC +00000000 +B80802EC +00000000 +00000000 +00000000 +B80802E4 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +31A006A8 +30400598 +30200EB8 +B9F400C0 +80000000 +B9F40290 +30A30000 +B8000000 +E06006A8 +3021FFE4 +F9E10000 +BC030014 +B8000040 +F86005A0 +99FC2000 +80000000 +E86005A0 +E8830000 +BE24FFEC +30630004 +B0000000 +30600000 +BC030010 +30A006A0 +99FC1800 +80000000 +30600001 +F06006A8 +E9E10000 +B60F0008 +3021001C +B0000000 +30600000 +3021FFE4 +F9E10000 +30A006A0 +30C006AC +BC03000C +99FC1800 +80000000 +E86006A4 +B0000000 +30800000 +BC030014 +30A006A4 +BC04000C +99FC2000 +80000000 +E9E10000 +B60F0008 +3021001C +2021FFEC +F9E10000 +20C006A8 +20E006A8 +06463800 +BC720014 +F8060000 +20C60004 +06463800 +BC92FFF4 +20C006A8 +20E006C8 +06463800 +BC720014 +F8060000 +20C60004 +06463800 +BC92FFF4 +B9F40104 +80000000 +B9F403D0 +80000000 +20C00000 +20E00000 +B9F40048 +20A00000 +32630000 +B9F403D8 +80000000 +B9F4007C +80000000 +C9E10000 +30730000 +B60F0008 +20210014 +BE050014 +30A5FFFF +80000000 +BE25FFFC +30A5FFFF +B60F0008 +80000000 +3021FFDC +F9E10000 +FA61001C +FAC10020 +B0009100 +32600004 +32C00001 +FAD30000 +B000004C +30A04B40 +B9F4FFBC +80000000 +F8130000 +B000004C +30A04B40 +B9F4FFA8 +80000000 +B800FFD8 +94700010 +A4630010 +BC23FFF8 +94608001 +B0002000 +A4630000 +BC230018 +10800800 +30600400 +90630001 +10841800 +10202000 +94710010 +B60F0008 +80000000 +94710010 +B60F0008 +80000000 +94700010 +A4630010 +BC23FFF8 +B60F0008 +80000000 +94700010 +A4630010 +BC23FFF8 +94608001 +B0002000 +A4630000 +BC230050 +10800800 +30600400 +90630001 +14C32000 +10203000 +10A40000 +30E00EC8 +16472003 +BCB20020 +15040000 +10862800 +E8650000 +30A50004 +16472803 +BE52FFF0 +D8644000 +94710010 +80000000 +B800FFFC +94710010 +B60F0008 +80000000 +B6110000 +80000000 +B6910000 +80000000 +B62E0000 +80000000 +3021FFE0 +10C00000 +FA61001C +F9E10000 +B9F40024 +12650000 +E8A0058C +E8650028 +BC03000C +99FC1800 +80000000 +B9F4FD4C +10B30000 +E860058C +3021FFC8 +FB410030 +FB610034 +F9E10000 +FA61001C +FAC10020 +FAE10024 +FB010028 +FB21002C +EB030048 +13650000 +BE180050 +13460000 +E8780004 +EB380088 +3263FFFF +BC53003C +64930402 +30640008 +12D81800 +BE060074 +12F92000 +BC1900C0 +E8770080 +1643D000 +BC1200EC +3273FFFF +32F7FFFC +AA53FFFF +BE32FFE8 +32D6FFFC +E9E10000 +EA61001C +EAC10020 +EAE10024 +EB010028 +EB21002C +EB410030 +EB610034 +B60F0008 +30210038 +E8B70000 +99FC3800 +80000000 +3273FFFF +32F7FFFC +AA53FFFF +BE12FFC0 +32D6FFFC +E8780004 +E8F60000 +3063FFFF +16439800 +BC120074 +F8160000 +BC07FFD4 +BE190058 +30800001 +E8790100 +44849C00 +84641800 +BC030044 +E8790104 +84641800 +BC23FFA4 +E8D70000 +99FC3800 +10BB0000 +B810FFA4 +3273FFFF +3273FFFF +AA53FFFF +BE12FF5C +3273FFFF +AA53FFFF +BE32FFF0 +3273FFFF +B800FF48 +99FC3800 +3273FFFF +B810FF78 +32F7FFFC +FA780004 +B800FF90 +E8780004 +E8F60000 +3063FFFF +16439800 +BC120054 +F8160000 +BC07FF00 +BC190038 +30800001 +E8790100 +44849C00 +84641800 +BC030024 +E8790104 +84641800 +BC230030 +E8D70000 +99FC3800 +10BB0000 +B810FED0 +3273FFFF +99FC3800 +3273FFFF +B810FEC4 +32F7FFFC +FA780004 +B800FFB0 +E8B70000 +99FC3800 +3273FFFF +B810FEA8 +32F7FFFC +E860057C +3021FFE0 +FA61001C +F9E10000 +3260057C +AA43FFFF +BC120018 +99FC1800 +3273FFFC +E8730000 +AA43FFFF +BC32FFF0 +E9E10000 +EA61001C +B60F0008 +30210020 +3021FFF8 +D9E00800 +B9F4FB88 +80000000 +B9F4FFB0 +80000000 +C9E00800 +B60F0008 +30210008 +3021FFF8 +D9E00800 +B9F4FB08 +80000000 +C9E00800 +B60F0008 +30210008 +FFFFFFFF +00000000 +FFFFFFFF +00000000 +000005AC +43000000 +00000000 +00000000 +00000000 +00000588 +00000001 +000005AC +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000590 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +FF000000 Index: test_rtl/jtag_ram_test/sw/RAM/ram0.mif =================================================================== --- test_rtl/jtag_ram_test/sw/RAM/ram0.mif (nonexistent) +++ test_rtl/jtag_ram_test/sw/RAM/ram0.mif (revision 38) @@ -0,0 +1,361 @@ +-- Copyright (C) 2013 Alireza Monemi + +WIDTH=32; +DEPTH=4096; +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 00000000 : B8080050; + 00000001 : 00000000; + 00000002 : B80802DC; + 00000003 : 00000000; + 00000004 : B80802EC; + [00000005..00000007] : 00000000; + 00000008 : B80802E4; + [00000009..00000013] : 00000000; + 00000014 : 31A006A8; + 00000015 : 30400598; + 00000016 : 30200EB8; + 00000017 : B9F400C0; + 00000018 : 80000000; + 00000019 : B9F40290; + 0000001A : 30A30000; + 0000001B : B8000000; + 0000001C : E06006A8; + 0000001D : 3021FFE4; + 0000001E : F9E10000; + 0000001F : BC030014; + 00000020 : B8000040; + 00000021 : F86005A0; + 00000022 : 99FC2000; + 00000023 : 80000000; + 00000024 : E86005A0; + 00000025 : E8830000; + 00000026 : BE24FFEC; + 00000027 : 30630004; + 00000028 : B0000000; + 00000029 : 30600000; + 0000002A : BC030010; + 0000002B : 30A006A0; + 0000002C : 99FC1800; + 0000002D : 80000000; + 0000002E : 30600001; + 0000002F : F06006A8; + 00000030 : E9E10000; + 00000031 : B60F0008; + 00000032 : 3021001C; + 00000033 : B0000000; + 00000034 : 30600000; + 00000035 : 3021FFE4; + 00000036 : F9E10000; + 00000037 : 30A006A0; + 00000038 : 30C006AC; + 00000039 : BC03000C; + 0000003A : 99FC1800; + 0000003B : 80000000; + 0000003C : E86006A4; + 0000003D : B0000000; + 0000003E : 30800000; + 0000003F : BC030014; + 00000040 : 30A006A4; + 00000041 : BC04000C; + 00000042 : 99FC2000; + 00000043 : 80000000; + 00000044 : E9E10000; + 00000045 : B60F0008; + 00000046 : 3021001C; + 00000047 : 2021FFEC; + 00000048 : F9E10000; + 00000049 : 20C006A8; + 0000004A : 20E006A8; + 0000004B : 06463800; + 0000004C : BC720014; + 0000004D : F8060000; + 0000004E : 20C60004; + 0000004F : 06463800; + 00000050 : BC92FFF4; + 00000051 : 20C006A8; + 00000052 : 20E006C8; + 00000053 : 06463800; + 00000054 : BC720014; + 00000055 : F8060000; + 00000056 : 20C60004; + 00000057 : 06463800; + 00000058 : BC92FFF4; + 00000059 : B9F40104; + 0000005A : 80000000; + 0000005B : B9F403D0; + 0000005C : 80000000; + 0000005D : 20C00000; + 0000005E : 20E00000; + 0000005F : B9F40048; + 00000060 : 20A00000; + 00000061 : 32630000; + 00000062 : B9F403D8; + 00000063 : 80000000; + 00000064 : B9F4007C; + 00000065 : 80000000; + 00000066 : C9E10000; + 00000067 : 30730000; + 00000068 : B60F0008; + 00000069 : 20210014; + 0000006A : BE050014; + 0000006B : 30A5FFFF; + 0000006C : 80000000; + 0000006D : BE25FFFC; + 0000006E : 30A5FFFF; + 0000006F : B60F0008; + 00000070 : 80000000; + 00000071 : 3021FFDC; + 00000072 : F9E10000; + 00000073 : FA61001C; + 00000074 : FAC10020; + 00000075 : B0009100; + 00000076 : 32600004; + 00000077 : 32C00001; + 00000078 : FAD30000; + 00000079 : B000004C; + 0000007A : 30A04B40; + 0000007B : B9F4FFBC; + 0000007C : 80000000; + 0000007D : F8130000; + 0000007E : B000004C; + 0000007F : 30A04B40; + 00000080 : B9F4FFA8; + 00000081 : 80000000; + 00000082 : B800FFD8; + 00000083 : 94700010; + 00000084 : A4630010; + 00000085 : BC23FFF8; + 00000086 : 94608001; + 00000087 : B0002000; + 00000088 : A4630000; + 00000089 : BC230018; + 0000008A : 10800800; + 0000008B : 30600400; + 0000008C : 90630001; + 0000008D : 10841800; + 0000008E : 10202000; + 0000008F : 94710010; + 00000090 : B60F0008; + 00000091 : 80000000; + 00000092 : 94710010; + 00000093 : B60F0008; + 00000094 : 80000000; + 00000095 : 94700010; + 00000096 : A4630010; + 00000097 : BC23FFF8; + 00000098 : B60F0008; + 00000099 : 80000000; + 0000009A : 94700010; + 0000009B : A4630010; + 0000009C : BC23FFF8; + 0000009D : 94608001; + 0000009E : B0002000; + 0000009F : A4630000; + 000000A0 : BC230050; + 000000A1 : 10800800; + 000000A2 : 30600400; + 000000A3 : 90630001; + 000000A4 : 14C32000; + 000000A5 : 10203000; + 000000A6 : 10A40000; + 000000A7 : 30E00EC8; + 000000A8 : 16472003; + 000000A9 : BCB20020; + 000000AA : 15040000; + 000000AB : 10862800; + 000000AC : E8650000; + 000000AD : 30A50004; + 000000AE : 16472803; + 000000AF : BE52FFF0; + 000000B0 : D8644000; + 000000B1 : 94710010; + 000000B2 : 80000000; + 000000B3 : B800FFFC; + 000000B4 : 94710010; + 000000B5 : B60F0008; + 000000B6 : 80000000; + 000000B7 : B6110000; + 000000B8 : 80000000; + 000000B9 : B6910000; + 000000BA : 80000000; + 000000BB : B62E0000; + 000000BC : 80000000; + 000000BD : 3021FFE0; + 000000BE : 10C00000; + 000000BF : FA61001C; + 000000C0 : F9E10000; + 000000C1 : B9F40024; + 000000C2 : 12650000; + 000000C3 : E8A0058C; + 000000C4 : E8650028; + 000000C5 : BC03000C; + 000000C6 : 99FC1800; + 000000C7 : 80000000; + 000000C8 : B9F4FD4C; + 000000C9 : 10B30000; + 000000CA : E860058C; + 000000CB : 3021FFC8; + 000000CC : FB410030; + 000000CD : FB610034; + 000000CE : F9E10000; + 000000CF : FA61001C; + 000000D0 : FAC10020; + 000000D1 : FAE10024; + 000000D2 : FB010028; + 000000D3 : FB21002C; + 000000D4 : EB030048; + 000000D5 : 13650000; + 000000D6 : BE180050; + 000000D7 : 13460000; + 000000D8 : E8780004; + 000000D9 : EB380088; + 000000DA : 3263FFFF; + 000000DB : BC53003C; + 000000DC : 64930402; + 000000DD : 30640008; + 000000DE : 12D81800; + 000000DF : BE060074; + 000000E0 : 12F92000; + 000000E1 : BC1900C0; + 000000E2 : E8770080; + 000000E3 : 1643D000; + 000000E4 : BC1200EC; + 000000E5 : 3273FFFF; + 000000E6 : 32F7FFFC; + 000000E7 : AA53FFFF; + 000000E8 : BE32FFE8; + 000000E9 : 32D6FFFC; + 000000EA : E9E10000; + 000000EB : EA61001C; + 000000EC : EAC10020; + 000000ED : EAE10024; + 000000EE : EB010028; + 000000EF : EB21002C; + 000000F0 : EB410030; + 000000F1 : EB610034; + 000000F2 : B60F0008; + 000000F3 : 30210038; + 000000F4 : E8B70000; + 000000F5 : 99FC3800; + 000000F6 : 80000000; + 000000F7 : 3273FFFF; + 000000F8 : 32F7FFFC; + 000000F9 : AA53FFFF; + 000000FA : BE12FFC0; + 000000FB : 32D6FFFC; + 000000FC : E8780004; + 000000FD : E8F60000; + 000000FE : 3063FFFF; + 000000FF : 16439800; + 00000100 : BC120074; + 00000101 : F8160000; + 00000102 : BC07FFD4; + 00000103 : BE190058; + 00000104 : 30800001; + 00000105 : E8790100; + 00000106 : 44849C00; + 00000107 : 84641800; + 00000108 : BC030044; + 00000109 : E8790104; + 0000010A : 84641800; + 0000010B : BC23FFA4; + 0000010C : E8D70000; + 0000010D : 99FC3800; + 0000010E : 10BB0000; + 0000010F : B810FFA4; + 00000110 : 3273FFFF; + 00000111 : 3273FFFF; + 00000112 : AA53FFFF; + 00000113 : BE12FF5C; + 00000114 : 3273FFFF; + 00000115 : AA53FFFF; + 00000116 : BE32FFF0; + 00000117 : 3273FFFF; + 00000118 : B800FF48; + 00000119 : 99FC3800; + 0000011A : 3273FFFF; + 0000011B : B810FF78; + 0000011C : 32F7FFFC; + 0000011D : FA780004; + 0000011E : B800FF90; + 0000011F : E8780004; + 00000120 : E8F60000; + 00000121 : 3063FFFF; + 00000122 : 16439800; + 00000123 : BC120054; + 00000124 : F8160000; + 00000125 : BC07FF00; + 00000126 : BC190038; + 00000127 : 30800001; + 00000128 : E8790100; + 00000129 : 44849C00; + 0000012A : 84641800; + 0000012B : BC030024; + 0000012C : E8790104; + 0000012D : 84641800; + 0000012E : BC230030; + 0000012F : E8D70000; + 00000130 : 99FC3800; + 00000131 : 10BB0000; + 00000132 : B810FED0; + 00000133 : 3273FFFF; + 00000134 : 99FC3800; + 00000135 : 3273FFFF; + 00000136 : B810FEC4; + 00000137 : 32F7FFFC; + 00000138 : FA780004; + 00000139 : B800FFB0; + 0000013A : E8B70000; + 0000013B : 99FC3800; + 0000013C : 3273FFFF; + 0000013D : B810FEA8; + 0000013E : 32F7FFFC; + 0000013F : E860057C; + 00000140 : 3021FFE0; + 00000141 : FA61001C; + 00000142 : F9E10000; + 00000143 : 3260057C; + 00000144 : AA43FFFF; + 00000145 : BC120018; + 00000146 : 99FC1800; + 00000147 : 3273FFFC; + 00000148 : E8730000; + 00000149 : AA43FFFF; + 0000014A : BC32FFF0; + 0000014B : E9E10000; + 0000014C : EA61001C; + 0000014D : B60F0008; + 0000014E : 30210020; + 0000014F : 3021FFF8; + 00000150 : D9E00800; + 00000151 : B9F4FB88; + 00000152 : 80000000; + 00000153 : B9F4FFB0; + 00000154 : 80000000; + 00000155 : C9E00800; + 00000156 : B60F0008; + 00000157 : 30210008; + 00000158 : 3021FFF8; + 00000159 : D9E00800; + 0000015A : B9F4FB08; + 0000015B : 80000000; + 0000015C : C9E00800; + 0000015D : B60F0008; + 0000015E : 30210008; + 0000015F : FFFFFFFF; + 00000160 : 00000000; + 00000161 : FFFFFFFF; + 00000162 : 00000000; + 00000163 : 000005AC; + 00000164 : 43000000; + [00000165..00000167] : 00000000; + 00000168 : 00000588; + 00000169 : 00000001; + 0000016A : 000005AC; + [0000016B..00000172] : 00000000; + 00000173 : 00000590; + [00000174..00000FFF] : 00000000; +END; \ No newline at end of file Index: test_rtl/jtag_ram_test/sw/README =================================================================== --- test_rtl/jtag_ram_test/sw/README (nonexistent) +++ test_rtl/jtag_ram_test/sw/README (revision 38) @@ -0,0 +1,72 @@ + + +/************************************************************************** +** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE +** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification. +****************************************************************************/ + + + +/********************************************************************** +** File: readme +** +** Copyright (C) 2014-2018 Alireza Monemi +** +** This file is part of ProNoC 1.7.0 +** +** ProNoC ( stands for Prototype Network-on-chip) is free software: +** you can redistribute it and/or modify it under the terms of the GNU +** Lesser General Public License as published by the Free Software Foundation, +** either version 2 of the License, or (at your option) any later version. +** +** ProNoC is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with ProNoC. If not, see . +******************************************************************************/ + + +*********************** +** Program the memories +*********************** + +If the memory core and jtag_wb are connected to the same wishbone bus, you can program the memory using + + sh program.sh + + + +*************************** +** soc parameters +*************************** + + parameter CORE_ID=0, + parameter SW_LOC="/home/alireza/mywork/mpsoc_work/SOC/ram_test/sw" , + parameter ram_Dw=32 , + parameter ram_Aw=12 + +**************************** +** wishbone bus(es) info +**************************** + #slave interfaces: + #instance name, interface name, connected to, base address, boundray address + ram, wb, bus, 0x00000000, 0x00003fff + + + #master interfaces: + #instance name, interface name, connected to + programer, wbm, bus + + +**************************** +** Jtag to wishbone interface (jtag_wb) info: +**************************** + + #instance name, instance name, VJTAG_INDEX + programer, bus, CORE_ID + + + Index: test_rtl/jtag_ram_test/sw/jtag_intfc.sh =================================================================== --- test_rtl/jtag_ram_test/sw/jtag_intfc.sh (nonexistent) +++ test_rtl/jtag_ram_test/sw/jtag_intfc.sh (revision 38) @@ -0,0 +1,5 @@ +#!/bin/sh + +HARDWARE_NAME="DE-SoC *" +DEVICE_NAME="@2*" +JTAG_INTFC="$PRONOC_WORK/toolchain/bin/jtag_quartus_stp -a $HARDWARE_NAME -b $DEVICE_NAME" Index: test_rtl/jtag_ram_test/sw/main.c =================================================================== --- test_rtl/jtag_ram_test/sw/main.c (nonexistent) +++ test_rtl/jtag_ram_test/sw/main.c (revision 38) @@ -0,0 +1,25 @@ + +#include "ram_test.h" + + +// a simple delay function +void delay ( unsigned int num ){ + + while (num>0){ + num--; + nop(); // asm volatile ("nop"); + } + return; + +} + +int main(){ + while(1){ + + + + } + +return 0; +} + Index: test_rtl/jtag_ram_test/sw/program.sh =================================================================== --- test_rtl/jtag_ram_test/sw/program.sh (nonexistent) +++ test_rtl/jtag_ram_test/sw/program.sh (revision 38) @@ -0,0 +1,34 @@ + +#!/bin/sh + + +#JTAG_INTFC="$PRONOC_WORK/toolchain/bin/JTAG_INTFC" +source ./jtag_intfc.sh + +#reset and disable cpus, then release the reset but keep the cpus disabled + +$JTAG_INTFC -n 127 -d "I:1,D:2:3,D:2:2,I:0" + +# jtag instruction +# 0: bypass +# 1: getting data +# jtag data : +# bit 0 is reset +# bit 1 is disable +# I:1 set jtag_enable in active mode +# D:2:3 load jtag_enable data register with 0x3 reset=1 disable=1 +# D:2:2 load jtag_enable data register with 0x2 reset=0 disable=1 +# I:0 set jtag_enable in bypass mode + + + +#programe the memory + + sh write_memory.sh + + +#Enable the cpu +$JTAG_INTFC -n 127 -d "I:1,D:2:0,I:0" +# I:1 set jtag_enable in active mode +# D:2:0 load jtag_enable data register with 0x0 reset=0 disable=0 +# I:0 set jtag_enable in bypass mode Index: test_rtl/jtag_ram_test/sw/ram_test.h =================================================================== --- test_rtl/jtag_ram_test/sw/ram_test.h (nonexistent) +++ test_rtl/jtag_ram_test/sw/ram_test.h (revision 38) @@ -0,0 +1,15 @@ +#ifndef RAM_TEST_SYSTEM_H + #define RAM_TEST_SYSTEM_H + + + /* ss */ + + + /* programer */ + + + /* ram */ + + + /* bus */ + #endif Index: test_rtl/jtag_ram_test/sw/write_memory.sh =================================================================== --- test_rtl/jtag_ram_test/sw/write_memory.sh (nonexistent) +++ test_rtl/jtag_ram_test/sw/write_memory.sh (revision 38) @@ -0,0 +1,6 @@ +#!/bin/sh + +#JTAG_INTFC="$PRONOC_WORK/toolchain/bin/JTAG_INTFC" +source ./jtag_intfc.sh + + $JTAG_INTFC -n 0 -s "0x00000000" -e "0x0000ffff" -i "./RAM/ram0.bin" -c \ No newline at end of file