URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_processor/aeMB/verilog/src
- from Rev 16 to Rev 48
- ↔ Reverse comparison
Rev 16 → Rev 48
/aeMB2_iche.v.bak
File deleted
\ No newline at end of file
aeMB2_iche.v.bak
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB2_sim.v.bak
===================================================================
--- aeMB2_sim.v.bak (revision 16)
+++ aeMB2_sim.v.bak (nonexistent)
@@ -1,329 +0,0 @@
-/* $Id: aeMB2_sim.v,v 1.2 2007-12-29 00:31:48 sybreon Exp $
-**
-** AEMB2 SIMULATION WRAPPER
-** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
-**
-** This file is part of AEMB.
-**
-** AEMB is free software: you can redistribute it and/or modify it
-** under the terms of the GNU Lesser General Public License as
-** published by the Free Software Foundation, either version 3 of the
-** License, or (at your option) any later version.
-**
-** AEMB is distributed in the hope that it will be useful, but WITHOUT
-** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-** Public License for more details.
-**
-** You should have received a copy of the GNU Lesser General Public
-** License along with AEMB. If not, see
aeMB2_sim.v.bak
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB2_iwbif.v.bak
===================================================================
--- aeMB2_iwbif.v.bak (revision 16)
+++ aeMB2_iwbif.v.bak (nonexistent)
@@ -1,164 +0,0 @@
-/* $Id: aeMB2_iwbif.v,v 1.5 2008-04-27 19:52:31 sybreon Exp $
-**
-** AEMB2 EDK 6.2 COMPATIBLE CORE
-** Copyright (C) 2004-2008 Shawn Tan
-**
-** This file is part of AEMB.
-**
-** AEMB is free software: you can redistribute it and/or modify it
-** under the terms of the GNU Lesser General Public License as
-** published by the Free Software Foundation, either version 3 of the
-** License, or (at your option) any later version.
-**
-** AEMB is distributed in the hope that it will be useful, but WITHOUT
-** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-** Public License for more details.
-**
-** You should have received a copy of the GNU Lesser General Public
-** License along with AEMB. If not, see
aeMB2_iwbif.v.bak
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB2_sim.v
===================================================================
--- aeMB2_sim.v (revision 16)
+++ aeMB2_sim.v (revision 48)
@@ -122,10 +122,10 @@
always @(posedge sim.clk_i) if (sim.ena_i) begin
$write ("\n", ($stime/10));
- $writeh (" T", sim.pha_i);
- $writeh(" PC=", iwb_adr);
+ $write (" T", sim.pha_i);
+ $write(" PC=", iwb_adr);
- $writeh ("\t| ");
+ $write ("\t| ");
case (sim.rOPC_IF)
6'o00: if (sim.rRD_IF == 0) $write(" "); else $write("ADD");
@@ -252,8 +252,8 @@
endcase // case (sim.rOPC_IF)
case (sim.rOPC_IF[3])
- 1'b1: $writeh("\t r",sim.rRD_IF,", r",sim.rRA_IF,", h",sim.rIMM_IF);
- 1'b0: $writeh("\t r",sim.rRD_IF,", r",sim.rRA_IF,", r",sim.rRB_IF," ");
+ 1'b1: $write("\t r",sim.rRD_IF,", r",sim.rRA_IF,", h",sim.rIMM_IF);
+ 1'b0: $write("\t r",sim.rRD_IF,", r",sim.rRA_IF,", r",sim.rRB_IF," ");
endcase // case (sim.rOPC_IF[3])
if (sim.bpcu.fHZD)
@@ -261,12 +261,12 @@
// ALU
$write("\t|");
- $writeh(" A=",sim.rOPA_OF);
- $writeh(" B=",sim.rOPB_OF);
- $writeh(" C=",sim.rOPX_OF);
- $writeh(" M=",sim.rOPM_OF);
+ $write(" A=",sim.rOPA_OF);
+ $write(" B=",sim.rOPB_OF);
+ $write(" C=",sim.rOPX_OF);
+ $write(" M=",sim.rOPM_OF);
- $writeh(" MSR=", wMSR," ");
+ $write(" MSR=", wMSR," ");
case (sim.rALU_OF)
3'o0: $write(" ADD");
@@ -279,9 +279,9 @@
// MA
$write ("\t| ");
if (sim.dwb_stb_o)
- $writeh("@",sim.rRES_EX);
+ $write("@",sim.rRES_EX);
else
- $writeh("=",sim.rRES_EX);
+ $write("=",sim.rRES_EX);
case (sim.rBRA)
@@ -297,11 +297,11 @@
if (|sim.rRD_MA) begin
case (sim.rOPD_MA)
2'o2: begin
- if (sim.rSEL_MA != 4'h0) $writeh("R",sim.rRD_MA,"=RAM(",sim.regf.rREGD,")");
- if (sim.rSEL_MA == 4'h0) $writeh("R",sim.rRD_MA,"=FSL(",sim.regf.rREGD,")");
+ if (sim.rSEL_MA != 4'h0) $write("R",sim.rRD_MA,"=RAM(",sim.regf.rREGD,")");
+ if (sim.rSEL_MA == 4'h0) $write("R",sim.rRD_MA,"=FSL(",sim.regf.rREGD,")");
end
- 2'o1: $writeh("R",sim.rRD_MA,"=LNK(",sim.regf.rREGD,")");
- 2'o0: $writeh("R",sim.rRD_MA,"=ALU(",sim.regf.rREGD,")");
+ 2'o1: $write("R",sim.rRD_MA,"=LNK(",sim.regf.rREGD,")");
+ 2'o0: $write("R",sim.rRD_MA,"=ALU(",sim.regf.rREGD,")");
endcase // case (sim.rOPD_MA)
end
@@ -308,7 +308,7 @@
/*
// STORE
if (dwb_stb_o & dwb_wre_o) begin
- $writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
+ $write("RAM(", dwb_adr ,")=", dwb_dat_o);
case (dwb_sel_o)
4'hF: $write(":L");
4'h3,4'hC: $write(":W");
@@ -326,4 +326,4 @@
/* $Log: not supported by cvs2svn $*/
/* Revision 1.1 2007/12/18 18:54:36 sybreon*/
/* Partitioned simulation model.*/
-/* */
\ No newline at end of file
+/* */
/aeMB_sim.v
111,8 → 111,8
if (cpu.gena) begin |
|
$write ("\n", ($stime/10)); |
$writeh (" PC=", iwb_adr ); |
$writeh ("\t"); |
$write (" PC=", iwb_adr ); |
$write ("\t"); |
|
case (wBRA) |
2'b00: $write(" "); |
246,8 → 246,8
endcase // case (cpu.rOPC) |
|
case (cpu.rOPC[3]) |
1'b1: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM); |
1'b0: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB," "); |
1'b1: $write("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM); |
1'b0: $write("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB," "); |
endcase // case (cpu.rOPC[3]) |
|
|
265,10 → 265,10
3'o5: $write(" BSF"); |
default: $write(" XXX"); |
endcase // case (cpu.rMXALU) |
$writeh("=h",cpu.xecu.xRESULT); |
$write("=h",cpu.xecu.xRESULT); |
|
// WRITEBACK |
$writeh("\tSR=", wMSR," "); |
$write("\tSR=", wMSR," "); |
|
if (cpu.regf.fRDWE) begin |
case (cpu.rMXDST) |
276,8 → 276,8
if (dwb_stb_o) $writeh("R",cpu.rRW,"=RAM(h",cpu.regf.xWDAT,")"); |
if (fsl_stb_o) $writeh("R",cpu.rRW,"=FSL(h",cpu.regf.xWDAT,")"); |
end |
2'o1: $writeh("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")"); |
2'o0: $writeh("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")"); |
2'o1: $write("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")"); |
2'o0: $write("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")"); |
endcase // case (cpu.rMXDST) |
end |
|
306,4 → 306,4
Revision 1.1 2007/12/23 20:40:45 sybreon |
Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. |
|
*/ |
*/ |