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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_processor/aeMB/verilog
    from Rev 16 to Rev 17
    ↔ Reverse comparison
  •

Rev 16 → Rev 17

/aemb.v
6,10 → 6,11
dwb_sel_o,
dwb_stb_o,
dwb_tag_o,
dwb_wre_o,
dwb_wre_o,
dwb_cti_o,
dwb_bte_o,
dwb_ack_i,
dwb_dat_i,
dwb_dat_i,
dwb_err_i,
dwb_rty_i,
18,10 → 19,13
iwb_sel_o,
iwb_stb_o,
iwb_tag_o,
iwb_wre_o,
iwb_wre_o,
iwb_dat_o,
iwb_cti_o,
iwb_bte_o,
iwb_ack_i,
iwb_dat_i,
iwb_dat_o,
iwb_err_i,
iwb_rty_i,
53,7 → 57,11
output [3:0] dwb_sel_o;
output dwb_stb_o;
output [2:0] dwb_tag_o;
output dwb_wre_o;
output dwb_wre_o;
output [2:0] dwb_cti_o;
output [1:0] dwb_bte_o;
input dwb_ack_i;
input [31:0] dwb_dat_i;
68,12 → 76,17
output iwb_wre_o;
input iwb_ack_i;
input [31:0] iwb_dat_i;
output[31:0] iwb_dat_o;
output[31:0] iwb_dat_o;
output [2:0] iwb_cti_o;
output [1:0] iwb_bte_o;
input clk;
input sys_ena_i;
input sys_int_i;
input reset;
wire i_tag,d_tag;
// not used but added to prevent warning
input dwb_err_i, dwb_rty_i, iwb_err_i, iwb_rty_i;
 
99,7 → 112,7
.xwb_cyc_o() , // xwb_cyc_o
.xwb_adr_o() , // [AEMB_XWB-1:2] xwb_adr_o
.iwb_wre_o(iwb_wre_o) , // iwb_wre_o
.iwb_tag_o() , // iwb_tag_o
.iwb_tag_o(i_tag) , // iwb_tag_o
.iwb_stb_o(iwb_stb_o) , // iwb_stb_o
.iwb_sel_o(iwb_sel_o) , // [3:0] iwb_sel_o
.iwb_cyc_o(iwb_cyc_o) , // iwb_cyc_o
106,7 → 119,7
.iwb_adr_o(iwb_adr_o[29:0]) , // [AEMB_IWB-1:2] iwb_adr_o
.dwb_wre_o(dwb_wre_o) , // dwb_wre_o
.dwb_tag_o() , // dwb_tag_o
.dwb_tag_o(d_tag) , // dwb_tag_o
.dwb_stb_o(dwb_stb_o) , // dwb_stb_o
.dwb_sel_o(dwb_sel_o) , // [3:0] dwb_sel_o
.dwb_dat_o(dwb_dat_o) , // [31:0] dwb_dat_o
127,10 → 140,17
);
 
assign iwb_dat_o = 0;
assign iwb_tag_o = 3'b000; // clasic wishbone without burst
assign dwb_tag_o = 3'b000; // clasic wishbone without burst
assign iwb_adr_o[31:30] = 2'b00;
assign dwb_adr_o[31:30] = 2'b00;
// I have no idea which tag (a,b or c) is used in aemb. I assume it is address tag (taga)
assign iwb_tag_o = {i_tag,2'b00};
assign dwb_tag_o = {d_tag,2'b00};
assign iwb_adr_o[31:30] = 2'b00;
assign dwb_adr_o[31:30] = 2'b00;
assign dwb_cti_o = 3'd0;
assign dwb_bte_o = 2'd0;
assign iwb_cti_o = 3'd0;
assign iwb_bte_o = 2'd0;
 
endmodule

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