URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_processor/aeMB
- from Rev 19 to Rev 25
- ↔ Reverse comparison
Rev 19 → Rev 25
/sw/Makefile
1,4 → 1,4
all: |
cd compile; ./gccrom ../main.c; |
cd compile; cp ram.mif ../ram00.mif; |
cd compile; sh gccrom ../main.c; |
cd compile; cp ram.mif ../ram${CORE_ID}.mif; cp ram.bin ../ram${CORE_ID}.bin; |
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/sw/compile/gccrom
5,10 → 5,11
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# Compile using C pre-processor |
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ELFFILE="rom" |
XILFLAGS="-mtune=v5.00 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul" |
CXXFLAGS="-O1" |
LNKFLAGS="-Wl,-defsym -Wl,_STACK_SIZE=0x400 -Wl,-defsym -Wl,_HEAP_SIZE=0x400" |
LNKFLAGS="-Wl,-defsym -Wl,_STACK_SIZE=${STACK_SIZE} -Wl,-defsym -Wl,_HEAP_SIZE=${HEAP_SIZE}" |
LIBFLAGS="" |
INCFLAGS="-Icc/" |
RAMSIZE="3FFF" #for aeMB ramwith of 12 |
33,9 → 34,11
$TOOLCHAIN/aemb/bin/mb-objcopy -O ihex $ELFFILE $ELFFILE.ihex && \ |
#echo "copy2ihex=$?" && \ |
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# Generate a MIF file from the IHEX file |
$TOOLCHAIN/ihex2mif/ihex2mif -f $ELFFILE.ihex -e $RAMSIZE -o ram.mif && \ |
# Generate a MIF & BIN files from the IHEX file |
$TOOLCHAIN/bin/ihex2mif -f $ELFFILE.ihex -e $RAMSIZE -o ram.mif && \ |
echo "ihex2mif=$?" |
$TOOLCHAIN/bin/ihex2bin -i $ELFFILE.ihex -o ram.bin && \ |
echo "ihex2bin=$?" |
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# echo the checksum |
#MD5=$(sha1sum $ELFFILE | cut -c1-32) && \ |