URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_processor/lm32/verilog/src
- from Rev 19 to Rev 25
- ↔ Reverse comparison
Rev 19 → Rev 25
/lm32.v
14,6 → 14,7
clk_i, |
rst_i, |
interrupt, |
en_i, |
// Instruction Wishbone master |
I_DAT_I, |
I_ACK_I, |
50,7 → 51,13
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input clk_i; // Clock |
input rst_i; // Reset |
input en_i; |
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wire reset; |
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assign reset = rst_i | ~ en_i; |
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//`ifdef CFG_INTERRUPTS_ENABLED |
input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins |
//`endif |
136,7 → 143,7
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lm32_top the_lm32_top( |
.clk_i(clk_i), |
.rst_i(rst_i), |
.rst_i(reset ), |
.interrupt_n(~interrupt), |
.I_DAT_I(I_DAT_I), |
.I_ACK_I(I_ACK_I), |
176,3 → 183,4
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endmodule |
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