URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_processor/mor1kx-3.1/rtl/verilog
- from Rev 38 to Rev 42
- ↔ Reverse comparison
Rev 38 → Rev 42
/mor1kx-defines.v
1,3 → 1,4
`timescale 1ns/1ps |
/* **************************************************************************** |
This Source Code Form is subject to the terms of the |
Open Hardware Description License, v. 1.0. If a copy |
/mor1kx_cache_lru.v
82,6 → 82,7
// .lru_pre (lru_pre[NUMWAYS-1:0]), |
// .lru_post (lru_post[NUMWAYS-1:0])); |
|
`timescale 1ns/1ps |
|
module mor1kx_cache_lru(/*AUTOARG*/ |
// Outputs |
/mor1kx_simple_dpram_sclk.v
11,6 → 11,7
Copyright (C) 2012 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
|
******************************************************************************/ |
`timescale 1ns/1ps |
|
module mor1kx_simple_dpram_sclk |
#( |
/mor1kx_true_dpram_sclk.v
9,7 → 9,7
Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
|
******************************************************************************/ |
|
`timescale 1ns/1ps |
module mor1kx_true_dpram_sclk |
#( |
parameter ADDR_WIDTH = 32, |