URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_processor/mor1kx-3.1/sw
- from Rev 45 to Rev 48
- ↔ Reverse comparison
Rev 45 → Rev 48
/Makefile
1,11 → 1,17
SOURCE_LIB = |
include SOURCE_LIB |
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include march_flags.mak |
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HDR_SOURCE_DIR=mor1kx |
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TOOLCHAIN=$(PRONOC_WORK)/toolchain/or1k-elf |
IHEX2MIF =$(PRONOC_WORK)/toolchain/bin/ihex2mif |
IHEX2BIN =$(PRONOC_WORK)/toolchain/bin/ihex2bin |
BIN2HEX =$(PRONOC_WORK)/toolchain/bin/bin2str |
IHEX2MIF=$(PRONOC_WORK)/toolchain/bin/ihex2mif |
IHEX2BIN=$(PRONOC_WORK)/toolchain/bin/ihex2bin |
BIN2HEX=$(PRONOC_WORK)/toolchain/bin/bin2str |
BIN2MIF=$(PRONOC_WORK)/toolchain/bin/bin2mif |
BIN2MEM=$(PRONOC_WORK)/toolchain/bin/bin2mem |
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OR32_TOOL_PREFIX=${TOOLCHAIN}/bin/or1k-elf- |
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OR32_LD=$(OR32_TOOL_PREFIX)ld |
18,7 → 24,7
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LIBRARIES = -L${OR32_LIB1} -L. -L./$(HDR_SOURCE_DIR) -lorlib -lgcc |
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MARCH_FLAGS ?=-msoft-mul -msoft-div -msoft-float |
#MARCH_FLAGS ?=-msoft-mul -msoft-div -msoft-float |
CFLAGS ?= -g -nostdlib -O2 $(MARCH_FLAGS) |
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LDFLAGS ?= -Tlink.ld -e 256 |
26,7 → 32,7
#RAMSIZE=3FFF |
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# Sources to go into the liborpsoc.a support library |
COMPILE_SRCS=$(HDR_SOURCE_DIR)/exceptions.c $(HDR_SOURCE_DIR)/int.c $(HDR_SOURCE_DIR)/mmu.S $(HDR_SOURCE_DIR)/$(HDR_SOURCE_DIR)-utils.c $(HDR_SOURCE_DIR)/cache.S |
COMPILE_SRCS=$(HDR_SOURCE_DIR)/exceptions.c $(HDR_SOURCE_DIR)/int.c $(HDR_SOURCE_DIR)/mmu.S $(HDR_SOURCE_DIR)/$(HDR_SOURCE_DIR)-utils.c $(HDR_SOURCE_DIR)/cache.S $(SOURCE_LIB) |
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all: image.ihex |
58,8 → 64,10
$(OR32_OBJCOPY) -O ihex image image.ihex |
# Generate a MIF & BIN files from the IHEX file |
# $(IHEX2MIF) -f image.ihex -e $(RAMSIZE) -o RAM/ram0.mif |
$(IHEX2MIF) -f image.ihex -o RAM/ram0.mif |
# $(IHEX2MIF) -f image.ihex -o RAM/ram0.mif |
$(IHEX2BIN) -i image.ihex -o RAM/ram0.bin |
$(BIN2MIF) -f RAM/ram0.bin -o RAM/ram0.mif -w 32 |
$(BIN2MEM) -f RAM/ram0.bin -o RAM/ram0.mem -w 32 |
$(BIN2HEX) -f RAM/ram0.bin -h |
rm *.o *.a |
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/custom
--- link.ld (revision 45)
+++ link.ld (revision 48)
@@ -2,13 +2,10 @@
SEARCH_DIR(.)
__DYNAMIC = 0;
-MEMORY
-{
- vectors : ORIGIN = 0, LENGTH = 0x1000
- ram : ORIGIN = 0x1000, LENGTH = (8M - 0x1000)
-}
+INCLUDE linkvar.ld;
+
/* Stack information variables */
_min_stack = 0x2000; /* 8K - minimum stack space to reserve */
@@ -18,9 +15,9 @@
.vectors :
{
*(.vectors)
- } > vectors
+ } > rom
- .text : {
+ .text 0x1000 : {
_stext = .;
*(.text)
_etext = .;
@@ -37,12 +34,15 @@
*(.lit)
*(.shdata)
_endtext = .;
- } > ram
+ } > rom
.rodata : {
+ _srodata = .;
*(.rodata);
*(.rodata.*)
- } > ram
+ . = ALIGN(0x10);
+ _erodata = .;
+ } > rom
.shbss :
{
@@ -58,8 +58,9 @@
_sdata = .;
*(.data)
edata = .;
+ . = ALIGN(0x4);
_edata = .;
- } > ram
+ } > ram AT > rom /* "> ram" is the VMA, "> rom" is the LMA */
.bss :
{
/linkvar.ld
0,0 → 1,10
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/* Rom information variables */ |
_Rom_start = 0x0; |
_Rom_end = 0xc000; |
_Rom_size = 0xc000; /* 48 K B- Rom space */ |
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_Ram_start = 0xc000; |
_Ram_end = 0x10000; |
_Ram_size = 0x4000; /* 16 K B- Ram space */ |
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/march_flags.mak
0,0 → 1,19
MARCH_MULTIPLIER=${FEATURE_MULTIPLIER} |
MARCH_DIVIDER=${FEATURE_DIVIDER} |
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ifeq (${MARCH_MULTIPLIER},"NONE") |
MARCH_MUL_FLG=-msoft-mul |
else |
MARCH_MUL_FLG=-mhard-mul |
endif |
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ifeq (${MARCH_DIVIDER},"NONE") |
MARCH_DIV_FLG=-msoft-div |
else |
MARCH_DIV_FLG=-mhard-div |
endif |
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MARCH_FLAGS ?=${MARCH_MUL_FLG} ${MARCH_DIV_FLG} -msoft-float |
/mor1kx/crt0.S
217,7 → 217,8
CLEAR_GPR(r4) |
/* nop to reset cycle counter */ |
l.nop NOP_CNT_RESET |
OR1K_DELAYED_NOP(OR1K_INST(l.jal main)) |
/*initial_global_data then call main*/ |
OR1K_DELAYED_NOP(OR1K_INST(l.jal __main)) |
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/* If program exits, call exit routine */ |
/* Save r11 */ |
/mor1kx/int.c
88,4 → 88,17
// Clear all pending interrupts in the PICSR |
mtspr(SPR_PICSR, 0); |
} |
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/mor1kx/mor1kx-utils.c
1,6 → 1,9
#include "spr-defs.h" |
#include "board.h" // For timer rate (IN_CLK, TICKS_PER_SEC) |
#include <or1k-support-defs.h> |
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extern int main(); |
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/* For writing into SPR. */ |
void |
mtspr(unsigned long spr, unsigned long value) |
112,3 → 115,16
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} |
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extern char _erodata, _sdata, _edata, _bstart, _bend; |
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void __main (void){ //initial_global_data |
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char *src = &_erodata; //start of Data section in Rom |
char *dst = &_sdata; |
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/* ROM has data at end of rodata; copy it. */ |
while (dst < &_edata) { |
*dst++ = *src++; |
} |
main(); //call the main function |
} |
/mor1kx/system.h
75,4 → 75,29
/* Wait for 10ms, assumes CLK_HZ is 100, which it usually is. |
Will be slightly inaccurate!*/ |
void cpu_sleep_10ms(void); |
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void __main (void); //initial_global_data |
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/****************** |
* General inttrupt functions for all CPUs added to ProNoC |
*******************/ |
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#define general_int_init int_init |
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//#define general_int_add int_add |
inline int general_int_add(unsigned long vect, void (* handler), void *arg){ |
return int_add(vect, handler,arg); |
} |
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#define general_int_enable int_enable |
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#define general_cpu_int_en cpu_enable_user_interrupts |
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