URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_processor/mor1kx-3.1
- from Rev 38 to Rev 42
- ↔ Reverse comparison
Rev 38 → Rev 42
/rtl/mor1k.v
1,5 → 1,11
`timescale 1ns/1ps |
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module mor1k #( |
parameter OPTION_DCACHE_SNOOP = "ENABLED",// "NONE","ENABLED" |
parameter FEATURE_INSTRUCTIONCACHE ="ENABLED",// "NONE","ENABLED" |
parameter FEATURE_DATACACHE ="ENABLED",// "NONE","ENABLED" |
parameter FEATURE_IMMU ="ENABLED",// "NONE","ENABLED" |
parameter FEATURE_DMMU="ENABLED",// "NONE","ENABLED" |
parameter OPTION_OPERAND_WIDTH=32, |
parameter IRQ_NUM=32 |
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8,6 → 14,11
clk, |
rst, |
cpu_en, |
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//snoop_interface |
snoop_adr_i, |
snoop_en_i, |
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// Wishbone interface |
iwbm_adr_o, |
44,6 → 55,10
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input clk; |
input rst; |
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input [31:0] snoop_adr_i; |
input snoop_en_i; |
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// Wishbone interface |
output [31:0] iwbm_adr_o; |
88,28 → 103,34
// wire du_stall_o, |
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wire [31:0] dadr_o,iadr_o; |
wire [31:0] snoop_adr_i_byte; |
assign iwbm_adr_o= {2'b00,iadr_o[31:2]}; |
assign dwbm_adr_o= {2'b00,dadr_o[31:2]}; |
assign snoop_adr_i_byte= {snoop_adr_i[29:0],2'b00}; |
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mor1kx #( |
.OPTION_DCACHE_SNOOP(OPTION_DCACHE_SNOOP), |
.FEATURE_DEBUGUNIT("ENABLED"), |
.FEATURE_CMOV("ENABLED"), |
.FEATURE_INSTRUCTIONCACHE("ENABLED"), |
.FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE), |
.OPTION_ICACHE_BLOCK_WIDTH(5), |
.OPTION_ICACHE_SET_WIDTH(8), |
.OPTION_ICACHE_WAYS(2), |
.OPTION_ICACHE_LIMIT_WIDTH(32), |
.FEATURE_IMMU("ENABLED"), |
.FEATURE_DATACACHE("ENABLED"), |
.FEATURE_IMMU(FEATURE_IMMU), |
.FEATURE_DATACACHE(FEATURE_DATACACHE), |
.OPTION_DCACHE_BLOCK_WIDTH(5), |
.OPTION_DCACHE_SET_WIDTH(8), |
.OPTION_DCACHE_WAYS(2), |
.OPTION_DCACHE_LIMIT_WIDTH(31), |
.FEATURE_DMMU("ENABLED"), |
.FEATURE_DMMU(FEATURE_DMMU), |
.OPTION_PIC_TRIGGER("LATCHED_LEVEL"), |
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.IBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"), |
.DBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"), |
180,8 → 201,8
.multicore_coreid_i (32'd0), |
.multicore_numcores_i (32'd0), |
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.snoop_adr_i (32'd0), |
.snoop_en_i (1'b0), |
.snoop_adr_i (snoop_adr_i_byte), |
.snoop_en_i (snoop_en_i), |
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.du_addr_i(du_addr_i), |
.du_stb_i(du_stb_i), |
/rtl/verilog/mor1kx-defines.v
1,3 → 1,4
`timescale 1ns/1ps |
/* **************************************************************************** |
This Source Code Form is subject to the terms of the |
Open Hardware Description License, v. 1.0. If a copy |
/rtl/verilog/mor1kx_cache_lru.v
82,6 → 82,7
// .lru_pre (lru_pre[NUMWAYS-1:0]), |
// .lru_post (lru_post[NUMWAYS-1:0])); |
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`timescale 1ns/1ps |
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module mor1kx_cache_lru(/*AUTOARG*/ |
// Outputs |
/rtl/verilog/mor1kx_simple_dpram_sclk.v
11,6 → 11,7
Copyright (C) 2012 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
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******************************************************************************/ |
`timescale 1ns/1ps |
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module mor1kx_simple_dpram_sclk |
#( |
/rtl/verilog/mor1kx_true_dpram_sclk.v
9,7 → 9,7
Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
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******************************************************************************/ |
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`timescale 1ns/1ps |
module mor1kx_true_dpram_sclk |
#( |
parameter ADDR_WIDTH = 32, |