URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_processor/mor1kx-3.1
- from Rev 42 to Rev 45
- ↔ Reverse comparison
Rev 42 → Rev 45
/sw/Makefile
23,7 → 23,7
|
LDFLAGS ?= -Tlink.ld -e 256 |
|
RAMSIZE=3FFF |
#RAMSIZE=3FFF |
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# Sources to go into the liborpsoc.a support library |
COMPILE_SRCS=$(HDR_SOURCE_DIR)/exceptions.c $(HDR_SOURCE_DIR)/int.c $(HDR_SOURCE_DIR)/mmu.S $(HDR_SOURCE_DIR)/$(HDR_SOURCE_DIR)-utils.c $(HDR_SOURCE_DIR)/cache.S |
57,7 → 57,8
mkdir -p ./RAM |
$(OR32_OBJCOPY) -O ihex image image.ihex |
# Generate a MIF & BIN files from the IHEX file |
$(IHEX2MIF) -f image.ihex -e $(RAMSIZE) -o RAM/ram0.mif |
# $(IHEX2MIF) -f image.ihex -e $(RAMSIZE) -o RAM/ram0.mif |
$(IHEX2MIF) -f image.ihex -o RAM/ram0.mif |
$(IHEX2BIN) -i image.ihex -o RAM/ram0.bin |
$(BIN2HEX) -f RAM/ram0.bin -h |
rm *.o *.a |