URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_processor
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/program_memories.sh
0,0 → 1,4
#!/bin/sh |
cd program |
quartus_stp -t prog.tcl |
cd .. |
program_memories.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/verilog/aemb.v
===================================================================
--- aeMB/verilog/aemb.v (revision 16)
+++ aeMB/verilog/aemb.v (revision 17)
@@ -6,10 +6,11 @@
dwb_sel_o,
dwb_stb_o,
dwb_tag_o,
- dwb_wre_o,
+ dwb_wre_o,
+ dwb_cti_o,
+ dwb_bte_o,
dwb_ack_i,
- dwb_dat_i,
-
+ dwb_dat_i,
dwb_err_i,
dwb_rty_i,
@@ -18,10 +19,13 @@
iwb_sel_o,
iwb_stb_o,
iwb_tag_o,
- iwb_wre_o,
+ iwb_wre_o,
+ iwb_dat_o,
+ iwb_cti_o,
+ iwb_bte_o,
iwb_ack_i,
iwb_dat_i,
- iwb_dat_o,
+
iwb_err_i,
iwb_rty_i,
@@ -53,7 +57,11 @@
output [3:0] dwb_sel_o;
output dwb_stb_o;
output [2:0] dwb_tag_o;
- output dwb_wre_o;
+ output dwb_wre_o;
+ output [2:0] dwb_cti_o;
+ output [1:0] dwb_bte_o;
+
+
input dwb_ack_i;
input [31:0] dwb_dat_i;
@@ -68,12 +76,17 @@
output iwb_wre_o;
input iwb_ack_i;
input [31:0] iwb_dat_i;
- output[31:0] iwb_dat_o;
+ output[31:0] iwb_dat_o;
+ output [2:0] iwb_cti_o;
+ output [1:0] iwb_bte_o;
+
input clk;
input sys_ena_i;
input sys_int_i;
input reset;
+ wire i_tag,d_tag;
+
// not used but added to prevent warning
input dwb_err_i, dwb_rty_i, iwb_err_i, iwb_rty_i;
@@ -99,7 +112,7 @@
.xwb_cyc_o() , // xwb_cyc_o
.xwb_adr_o() , // [AEMB_XWB-1:2] xwb_adr_o
.iwb_wre_o(iwb_wre_o) , // iwb_wre_o
- .iwb_tag_o() , // iwb_tag_o
+ .iwb_tag_o(i_tag) , // iwb_tag_o
.iwb_stb_o(iwb_stb_o) , // iwb_stb_o
.iwb_sel_o(iwb_sel_o) , // [3:0] iwb_sel_o
.iwb_cyc_o(iwb_cyc_o) , // iwb_cyc_o
@@ -106,7 +119,7 @@
.iwb_adr_o(iwb_adr_o[29:0]) , // [AEMB_IWB-1:2] iwb_adr_o
.dwb_wre_o(dwb_wre_o) , // dwb_wre_o
- .dwb_tag_o() , // dwb_tag_o
+ .dwb_tag_o(d_tag) , // dwb_tag_o
.dwb_stb_o(dwb_stb_o) , // dwb_stb_o
.dwb_sel_o(dwb_sel_o) , // [3:0] dwb_sel_o
.dwb_dat_o(dwb_dat_o) , // [31:0] dwb_dat_o
@@ -127,10 +140,17 @@
);
assign iwb_dat_o = 0;
- assign iwb_tag_o = 3'b000; // clasic wishbone without burst
- assign dwb_tag_o = 3'b000; // clasic wishbone without burst
- assign iwb_adr_o[31:30] = 2'b00;
- assign dwb_adr_o[31:30] = 2'b00;
+ // I have no idea which tag (a,b or c) is used in aemb. I assume it is address tag (taga)
+ assign iwb_tag_o = {i_tag,2'b00};
+ assign dwb_tag_o = {d_tag,2'b00};
+ assign iwb_adr_o[31:30] = 2'b00;
+ assign dwb_adr_o[31:30] = 2'b00;
+ assign dwb_cti_o = 3'd0;
+ assign dwb_bte_o = 2'd0;
+ assign iwb_cti_o = 3'd0;
+ assign iwb_bte_o = 2'd0;
+
+
endmodule
/aeMB/sw/aemb/msr.hh
0,0 → 1,171
/* $Id: msr.hh,v 1.9 2008-04-28 20:29:15 sybreon Exp $ |
** |
** AEMB2 HI-PERFORMANCE CPU |
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net> |
** |
** This file is part of AEMB. |
** |
** AEMB is free software: you can redistribute it and/or modify it |
** under the terms of the GNU General Public License as published by |
** the Free Software Foundation, either version 3 of the License, or |
** (at your option) any later version. |
** |
** AEMB is distributed in the hope that it will be useful, but WITHOUT |
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
** License for more details. |
** |
** You should have received a copy of the GNU General Public License |
** along with AEMB. If not, see <http://www.gnu.org/licenses/>. |
*/ |
|
/** |
Basic MSR functions |
@file msr.hh |
|
These functions provide read/write access to the Machine Status |
Register. It also contains the bit definitions of the register. |
*/ |
|
#ifndef _AEMB_MSR_HH |
#define _AEMB_MSR_HH |
|
// STANDARD BITS |
#define AEMB_MSR_BE (1 << 0) ///< Buslock Enable |
#define AEMB_MSR_IE (1 << 1) ///< Interrupt Enable |
#define AEMB_MSR_C (1 << 2) ///< Arithmetic Carry |
#define AEMB_MSR_BIP (1 << 3) ///< Break in Progress |
#define AEMB_MSR_EE (1 << 8) ///< Exception Enable |
#define AEMB_MSR_EIP (1 << 9) ///< Exception in Progress |
|
#define AEMB_MSR_ITE (1 << 5) ///< Instruction Cache Enable |
#define AEMB_MSR_DZ (1 << 6) ///< Division by Zero |
#define AEMB_MSR_DTE (1 << 7) ///< Data Cache Enable |
|
// CUSTOM BITS |
#define AEMB_MSR_MTX (1 << 4) ///< Hardware Mutex |
#define AEMB_MSR_PHA (1 << 29) ///< Hardware Thread Phase |
#define AEMB_MSR_HTX (1 << 30) ///< Hardware Threads Extension |
#define AEMB_MSR_CC (1 << 31) ///< Carry Copy |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
/** |
Read the value of the MSR register |
@return register contents |
*/ |
|
inline int aembGetMSR() |
{ |
int rmsr; |
asm volatile ("mfs %0, rmsr":"=r"(rmsr)); |
return rmsr; |
} |
|
/** |
Write a value to the MSR register |
@param rmsr value to write |
*/ |
|
inline void aembPutMSR(int rmsr) |
{ |
asm volatile ("mts rmsr, %0"::"r"(rmsr)); |
} |
|
/** |
Read and clear the MSR |
@param rmsk clear mask |
@return msr value |
*/ |
|
inline int aembClrMSR(const short rmsk) |
{ |
int tmp; |
//asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(rmsk):"memory"); |
return tmp; |
} |
|
/** |
Read and set the MSR |
@param rmsk set mask |
@return msr value |
*/ |
|
inline int aembSetMSR(const short rmsk) |
{ |
int tmp; |
//asm volatile ("msrset %0, %1":"=r"(tmp):"K"(rmsk):"memory"); |
return tmp; |
} |
|
/** Enable global interrupts */ |
inline int aembEnableInterrupts() |
{ |
int msr; |
asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_IE)); |
return msr; |
} |
|
/** Disable global interrupts */ |
inline int aembDisableInterrupts() |
{ |
int msr; |
asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_IE)); |
return msr; |
} |
|
/** Enable global exception */ |
inline int aembEnableException() |
{ |
int msr; |
asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_EE)); |
return msr; |
} |
|
/** Disable global exception */ |
inline int aembDisableException() |
{ |
int msr; |
asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_EE)); |
return msr; |
} |
|
/** Enable data caches */ |
inline int aembEnableDataTag() |
{ |
int msr; |
asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE)); |
return msr; |
} |
|
/** Disable data caches */ |
inline int aembDisableDataTag() |
{ |
int msr; |
asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE)); |
return msr; |
} |
|
/** Enable inst caches */ |
inline int aembEnableInstTag() |
{ |
int msr; |
asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE)); |
return msr; |
} |
|
/** Disable inst caches */ |
inline int aembDisableInstTag() |
{ |
int msr; |
asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE)); |
return msr; |
} |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif |
aeMB/sw/aemb/msr.hh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/aemb/stdio.hh
===================================================================
--- aeMB/sw/aemb/stdio.hh (nonexistent)
+++ aeMB/sw/aemb/stdio.hh (revision 17)
@@ -0,0 +1,77 @@
+/* $Id: stdio.hh,v 1.5 2008-04-28 20:29:15 sybreon Exp $
+**
+** AEMB2 HI-PERFORMANCE CPU
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU General Public License as published by
+** the Free Software Foundation, either version 3 of the License, or
+** (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+** License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with AEMB. If not, see .
+*/
+
+/**
+ Basic standard I/O functions
+ @file stdio.hh
+
+ These functions provide function prototypes for outbyte/inbyte
+ which are required by the linker during compile time. These
+ functions can be defined anywhere else in code but should not be
+ inlined.
+ */
+
+#ifndef _AEMB_STDIO_HH
+#define _AEMB_STDIO_HH
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ /**
+ Default stdout prototype.
+ @param c char
+
+ This is used to output characters to LCD or UART.
+ */
+
+ void outbyte(char c);
+
+ /**
+ Default stdin prototype.
+ @return char
+
+ This is used to read characters in from UART or keyboard.
+ */
+
+ char inbyte();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*
+ $Log: not supported by cvs2svn $
+ Revision 1.4 2008/04/27 16:33:42 sybreon
+ License change to GPL3.
+
+ Revision 1.3 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
+ Revision 1.2 2008/04/26 18:05:22 sybreon
+ Minor cosmetic changes.
+
+ Revision 1.1 2008/04/09 19:48:37 sybreon
+ Added new C++ files
+
+*/
aeMB/sw/aemb/stdio.hh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/aemb/semaphore.hh
===================================================================
--- aeMB/sw/aemb/semaphore.hh (nonexistent)
+++ aeMB/sw/aemb/semaphore.hh (revision 17)
@@ -0,0 +1,103 @@
+/* $Id: semaphore.hh,v 1.1 2008-04-28 20:29:15 sybreon Exp $
+**
+** AEMB2 HI-PERFORMANCE CPU
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU General Public License as published by
+** the Free Software Foundation, either version 3 of the License, or
+** (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+** License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with AEMB. If not, see .
+*/
+
+/**
+ General semaphore library
+ @file semaphore.hh
+ */
+
+#include "thread.hh"
+
+#ifndef _AEMB_SEMAPHORE_HH
+#define _AEMB_SEMAPHORE_HH
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ // TODO: Extend this library to include threading mechanisms such as
+ // semaphores, mutexes and such.
+
+ /**
+ Semaphore struct.
+ Presently implemented as software solution but a hardware one may be
+ required as the threads are hardware.
+ */
+
+ typedef int semaphore;
+
+ /**
+ Software Semaphore Signal.
+
+ Increment the semaphore and run. This is a software mechanism.
+ */
+ inline void aembSignal(volatile semaphore _sem)
+ {
+ _aembLockMTX();
+ _sem++;
+ _aembFreeMTX();
+ }
+
+ /**
+ Software Semaphore Wait.
+
+ Decrement the semaphore and block if < 0. This is a software
+ mechanism.
+ */
+ inline void aembWait(volatile semaphore _sem)
+ {
+ _aembLockMTX();
+ _sem--;
+ _aembFreeMTX();
+ while (_sem < 0);
+ }
+
+ semaphore __mutex_rendezvous0 = 0; ///< internal rendezvous mutex
+ semaphore __mutex_rendezvous1 = 1; ///< internal rendezvous mutex
+
+ /**
+ Implements a simple rendezvous mechanism
+ */
+ /*
+ inline void aembRendezvous()
+ {
+ if (isThread1())
+ {
+ wait(__mutex_rendezvous0);
+ signal(__mutex_rendezvous1);
+ }
+ else
+ {
+ signal(__mutex_rendezvous0);
+ wait(__mutex_rendezvous1);
+ }
+ }
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*
+$log$
+*/
aeMB/sw/aemb/semaphore.hh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/aemb/stack.hh
===================================================================
--- aeMB/sw/aemb/stack.hh (nonexistent)
+++ aeMB/sw/aemb/stack.hh (revision 17)
@@ -0,0 +1,145 @@
+/* $Id: stack.hh,v 1.8 2008-04-28 20:29:15 sybreon Exp $
+**
+** AEMB2 HI-PERFORMANCE CPU
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU General Public License as published by
+** the Free Software Foundation, either version 3 of the License, or
+** (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+** License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with AEMB. If not, see .
+*/
+
+/**
+ Basic stack related functions
+ @file stack.hh
+ */
+
+#ifndef _AEMB_STACK_HH
+#define _AEMB_STACK_HH
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ /**
+ Reads the size of the memory space allocated for the stack in bytes.
+ @return size of stack
+ */
+
+ inline int aembGetStackSize()
+ {
+ int tmp;
+ asm ("la %0, r0, _STACK_SIZE":"=r"(tmp));
+ return tmp;
+ }
+
+ /**
+ Reads the end of the memory space allocated for the stack. This is
+ where the stack ends.
+ @return end of stack
+ */
+
+ inline int aembGetStackEnd()
+ {
+ int tmp;
+ asm ("la %0, r0, _stack_end":"=r"(tmp));
+ return tmp;
+ }
+
+ /**
+ Reads the top of the memory space allocated for the stack. This is
+ where the stack starts.
+ @return top of stack
+ */
+
+ inline int aembGetStackTop()
+ {
+ int tmp;
+ asm ("la %0, r0, _stack":"=r"(tmp));
+ return tmp;
+ }
+
+ /**
+ Reads register R1 which is the designated stack pointer.
+ @return stack pointer
+ */
+
+ inline int aembGetStack()
+ {
+ int tmp;
+ asm ("addk %0, r0, r1":"=r"(tmp));
+ return tmp;
+ }
+
+ /**
+ Sets register R1 to the new stack pointer.
+ @param stk new stack pointer
+ @return new stack pointer
+ */
+
+ inline int aembSetStack(int stk)
+ {
+ asm ("addk r1, r0, %0"::"r"(stk));
+ return stk;
+ }
+
+ /**
+ Duplicates the stack
+ @param newp new stack pointer
+ @param oldp old stack pointer
+ @param endp end of the stack
+ */
+
+ inline void aembDupStack(unsigned int *newp, unsigned int *oldp, unsigned int *endp)
+ {
+ while (oldp < endp)
+ {
+ // copy the stack content
+ *newp = *oldp;
+ // this increments 1 word (not 1 byte)
+ newp++;
+ oldp++;
+ }
+ }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*
+ $Log: not supported by cvs2svn $
+ Revision 1.7 2008/04/27 16:33:42 sybreon
+ License change to GPL3.
+
+ Revision 1.6 2008/04/27 16:04:42 sybreon
+ Minor cosmetic changes.
+
+ Revision 1.5 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
+ Revision 1.4 2008/04/26 18:04:31 sybreon
+ Updated software to freeze T0 and run T1.
+
+ Revision 1.3 2008/04/23 14:19:39 sybreon
+ Fixed minor bugs.
+ Initial use of hardware mutex.
+
+ Revision 1.2 2008/04/20 16:35:53 sybreon
+ Added C/C++ compatible #ifdef statements
+
+ Revision 1.1 2008/04/09 19:48:37 sybreon
+ Added new C++ files
+
+*/
aeMB/sw/aemb/stack.hh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/aemb/thread.hh
===================================================================
--- aeMB/sw/aemb/thread.hh (nonexistent)
+++ aeMB/sw/aemb/thread.hh (revision 17)
@@ -0,0 +1,101 @@
+/* $Id: thread.hh,v 1.10 2008-04-28 20:29:15 sybreon Exp $
+**
+** AEMB2 HI-PERFORMANCE CPU
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU General Public License as published by
+** the Free Software Foundation, either version 3 of the License, or
+** (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+** License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with AEMB. If not, see .
+*/
+
+/**
+ Basic thread functions
+ @file thread.hh
+
+ These functions deal with the various hardware threads. It also
+ provides simple mechanisms for toggling semaphores.
+ */
+
+#include "msr.hh"
+
+#ifndef _AEMB_THREAD_HH
+#define _AEMB_THREAD_HH
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ /**
+ Checks to see if currently executing Thread 1
+ @return true if is Thread 1
+ */
+
+ inline int aembIsThread1()
+ {
+ int rmsr = aembGetMSR();
+ return ((rmsr & AEMB_MSR_PHA));
+ }
+
+ /**
+ Checks to see if currently executing Thread 0
+ @return true if is Thread 0
+ */
+
+ inline int aembIsThread0()
+ {
+ int rmsr = aembGetMSR();
+ return (!(rmsr & AEMB_MSR_PHA));
+ }
+
+ /**
+ Checks to see if it is multi-threaded or not.
+ @return true if thread capable
+ */
+ inline int aembIsThreaded()
+ {
+ int rmsr = aembGetMSR();
+ return (rmsr & AEMB_MSR_HTX);
+ }
+
+ /**
+ Hardware Mutex Signal.
+ Unlock the hardware mutex, which is unlocked on reset.
+ */
+ inline void _aembFreeMTX()
+ {
+ int tmp;
+ asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(AEMB_MSR_MTX));
+ }
+
+ /**
+ Hardware Mutex Wait.
+
+ Waits until the hardware mutex is unlocked. This should be used
+ as part of a larger software mutex mechanism.
+ */
+ inline void _aembLockMTX()
+ {
+ int rmsr;
+ do
+ {
+ asm volatile ("msrset %0, %1":"=r"(rmsr):"K"(AEMB_MSR_MTX));
+ }
+ while (rmsr & AEMB_MSR_MTX);
+ }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
aeMB/sw/aemb/thread.hh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/aemb/core.hh
===================================================================
--- aeMB/sw/aemb/core.hh (nonexistent)
+++ aeMB/sw/aemb/core.hh (revision 17)
@@ -0,0 +1,53 @@
+/* $Id: core.hh,v 1.5 2008-05-31 17:02:04 sybreon Exp $
+**
+** AEMB2 HI-PERFORMANCE CPU
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU General Public License as published by
+** the Free Software Foundation, either version 3 of the License, or
+** (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+** License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with AEMB. If not, see .
+*/
+
+/**
+ General AEMB2 core library
+ @file core.hh
+ */
+
+#ifdef __MICROBLAZE__
+
+#include "msr.hh"
+#include "stack.hh"
+#include "heap.hh"
+#include "thread.hh"
+#include "hook.hh"
+#include "stdio.hh"
+#include "semaphore.hh"
+
+#endif
+
+/*
+ $Log: not supported by cvs2svn $
+ Revision 1.4 2008/04/28 20:29:15 sybreon
+ Made files C compatible under C++.
+
+ Revision 1.3 2008/04/27 16:33:42 sybreon
+ License change to GPL3.
+
+ Revision 1.2 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
+ Revision 1.1 2008/04/09 19:48:37 sybreon
+ Added new C++ files
+
+ */
aeMB/sw/aemb/core.hh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/aemb/heap.hh
===================================================================
--- aeMB/sw/aemb/heap.hh (nonexistent)
+++ aeMB/sw/aemb/heap.hh (revision 17)
@@ -0,0 +1,93 @@
+/* $Id: heap.hh,v 1.6 2008-04-28 20:29:15 sybreon Exp $
+**
+** AEMB2 HI-PERFORMANCE CPU
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU General Public License as published by
+** the Free Software Foundation, either version 3 of the License, or
+** (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+** License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with AEMB. If not, see .
+*/
+
+/**
+ Basic heap related functions
+ @file heap.hh
+ */
+
+#ifndef _AEMB_HEAP_HH
+#define _AEMB_HEAP_HH
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ /**
+ Extracts the heap size from the linker
+ @return heap size
+ */
+
+ inline int aembGetHeapSize()
+ {
+ int tmp;
+ asm ("la %0, r0, _HEAP_SIZE":"=r"(tmp));
+ return tmp;
+ }
+
+ /**
+ Extracts the heap end from the linker
+ @return heap end
+ */
+
+ inline int aembGetHeapEnd()
+ {
+ int tmp;
+ asm ("la %0, r0, _heap_end":"=r"(tmp));
+ return tmp;
+ }
+
+ /**
+ Extracts the heap top from the linker
+ @return heap top
+ */
+
+ inline int aembGetHeapTop()
+ {
+ int tmp;
+ asm ("la %0, r0, _heap":"=r"(tmp));
+ return tmp;
+ }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*
+ $Log: not supported by cvs2svn $
+ Revision 1.5 2008/04/27 16:33:42 sybreon
+ License change to GPL3.
+
+ Revision 1.4 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
+ Revision 1.3 2008/04/26 18:05:22 sybreon
+ Minor cosmetic changes.
+
+ Revision 1.2 2008/04/20 16:35:53 sybreon
+ Added C/C++ compatible #ifdef statements
+
+ Revision 1.1 2008/04/09 19:48:37 sybreon
+ Added new C++ files
+
+*/
aeMB/sw/aemb/heap.hh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/aemb/hook.hh
===================================================================
--- aeMB/sw/aemb/hook.hh (nonexistent)
+++ aeMB/sw/aemb/hook.hh (revision 17)
@@ -0,0 +1,169 @@
+/* $Id: hook.hh,v 1.11 2008-04-28 20:31:40 sybreon Exp $
+**
+** AEMB2 HI-PERFORMANCE CPU
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU General Public License as published by
+** the Free Software Foundation, either version 3 of the License, or
+** (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+** License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with AEMB. If not, see .
+*/
+
+/**
+ Basic begin/end hooks
+ @file hook.hh
+
+ These routines hook themselves onto parts of the main programme to
+ enable the hardware threads to work properly.
+ */
+
+#include "stack.hh"
+#include "heap.hh"
+#include "thread.hh"
+
+#ifndef _AEMB_HOOK_HH
+#define _AEMB_HOOK_HH
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ void _program_init();
+ void _program_clean();
+
+ // newlib locks
+ void __malloc_lock(struct _reent *reent);
+ void __malloc_unlock(struct _reent *reent);
+ //void __env_lock(struct _reent *reent);
+ //void __env_unlock(struct _reent *reent);
+
+ /**
+ Finalisation hook
+
+ This function executes during the shutdown phase after the
+ finalisation routine is called. It will merge the changes made
+ during initialisation.
+ */
+
+ void _program_clean()
+ {
+ _aembLockMTX(); // enter critical section
+
+ // unify the stack backwards
+ if (aembIsThread0())
+ {
+ aembSetStack(aembGetStack() + (aembGetStackSize() >> 1));
+ }
+
+ _aembFreeMTX(); // exit critical section
+ }
+
+ /**
+ Initialisation hook
+
+ This function executes during the startup phase before the
+ initialisation routine is called. It splits the stack between the
+ threads. For now, it will lock up T0 for compatibility purposes.
+ */
+
+ void _program_init()
+ {
+ _aembLockMTX(); // enter critical section
+
+ // split and shift the stack for thread 1
+ if (aembIsThread0()) // main thread
+ {
+ // NOTE: Dupe the stack otherwise it will FAIL!
+ int oldstk = aembGetStack();
+ int newstk = aembSetStack(aembGetStack() - (aembGetStackSize() >> 1));
+ aembDupStack((unsigned int *)newstk,
+ (unsigned int *)oldstk,
+ (unsigned int *)aembGetStackTop());
+ _aembFreeMTX(); // exit critical section
+ while (1) asm volatile ("nop"); // lock thread
+ }
+
+ _aembFreeMTX(); // exit critical section
+ }
+
+ /**
+ Heap Lock
+
+ This function is called during malloc() to lock out the shared
+ heap to avoid data corruption.
+ */
+
+ void __malloc_lock(struct _reent *reent)
+ {
+ _aembLockMTX();
+ }
+
+ /**
+ Heap Unlock
+
+ This function is called during malloc() to indicate that the
+ shared heap is now available for another thread.
+ */
+
+ void __malloc_unlock(struct _reent *reent)
+ {
+ _aembFreeMTX();
+ }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#ifndef __OPTIMIZE__
+// The main programme needs to be compiled with optimisations turned
+// on (at least -O1). If not, the MUTEX value will be written to the
+// same RAM location, giving both threads the same value.
+OPTIMISATION_REQUIRED OPTIMISATION_REQUIRED
+#endif
+
+/*
+ $Log: not supported by cvs2svn $
+ Revision 1.10 2008/04/28 20:29:15 sybreon
+ Made files C compatible under C++.
+
+ Revision 1.9 2008/04/27 16:33:42 sybreon
+ License change to GPL3.
+
+ Revision 1.8 2008/04/27 16:04:42 sybreon
+ Minor cosmetic changes.
+
+ Revision 1.7 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
+ Revision 1.6 2008/04/26 18:04:31 sybreon
+ Updated software to freeze T0 and run T1.
+
+ Revision 1.5 2008/04/23 14:19:39 sybreon
+ Fixed minor bugs.
+ Initial use of hardware mutex.
+
+ Revision 1.4 2008/04/20 16:35:53 sybreon
+ Added C/C++ compatible #ifdef statements
+
+ Revision 1.3 2008/04/12 13:46:02 sybreon
+ Added malloc() lock and unlock routines
+
+ Revision 1.2 2008/04/11 15:20:31 sybreon
+ added static assert hack
+
+ Revision 1.1 2008/04/09 19:48:37 sybreon
+ Added new C++ files
+
+*/
aeMB/sw/aemb/hook.hh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/program/prog.tcl
===================================================================
--- aeMB/sw/program/prog.tcl (nonexistent)
+++ aeMB/sw/program/prog.tcl (revision 17)
@@ -0,0 +1,80 @@
+#/usr/bin/tclsh
+
+proc hold_reset {} {
+ global device_name usb
+ start_insystem_source_probe -device_name $device_name -hardware_name $usb
+ write_source_data -instance_index 127 -value 0x1 -value_in_hex
+ end_insystem_source_probe
+}
+
+proc release_reset {} {
+ global device_name usb
+ start_insystem_source_probe -device_name $device_name -hardware_name $usb
+ write_source_data -instance_index 127 -value 0x0 -value_in_hex
+ end_insystem_source_probe
+}
+
+## Setup USB hardware - assumes only USB Blaster is installed and
+## an FPGA is the only device in the JTAG chain
+set usb [lindex [get_hardware_names] 0]
+set device_name [lindex [get_device_names -hardware_name $usb] 0]
+
+puts $usb
+puts $device_name
+
+#reset all processors
+hold_reset
+
+
+# Initiate a editing sequence
+begin_memory_edit -hardware_name $usb -device_name $device_name
+
+foreach instance \
+ [get_editable_mem_instances -hardware_name $usb -device_name $device_name] {
+ set inst_name [lindex $instance 5]
+ set inst_index [lindex $instance 0]
+ puts $inst_name
+ puts $inst_index
+ #set xx [string range $inst_name 0 1]
+ #set yy [string range $inst_name 2 end]
+ #puts $xx
+ #puts $yy
+ set ram_file_name ../ram${inst_name}.mif
+
+#update prog memory
+ if {[file exists $ram_file_name] == 1} {
+ puts "memory ${inst_name} is programed with $ram_file_name"
+ update_content_to_memory_from_file -instance_index $inst_index -mem_file_path $ram_file_name -mem_file_type mif
+ } else {
+ puts "file $ram_file_name does not exist! memory ${inst_name} left unprogramed"
+ }
+
+}
+
+
+
+
+#set xx 0
+#set yy 0
+# for {set yy 0} {$yy<$Y_NODE_NUM} {incr yy} {
+# for {set xx 0} {$xx<$X_NODE_NUM} {incr xx} {
+# set ram_file_name [format "ram/cpu%02d_%02d.mif" $xx $yy]
+# set mem_index [format "%02d%02d" $xx $yy]
+
+#update prog memory
+# update_content_to_memory_from_file -instance_index $mem_index -mem_file_path $ram_file_name -mem_file_type mif
+
+#puts $ram_file_name\n
+#puts $mem_index\n
+
+# }}
+
+
+
+
+
+#End the editing sequence
+end_memory_edit
+
+#release reset
+release_reset
aeMB/sw/program/prog.tcl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/compile/aemb.specs
===================================================================
--- aeMB/sw/compile/aemb.specs (nonexistent)
+++ aeMB/sw/compile/aemb.specs (revision 17)
@@ -0,0 +1,178 @@
+*asm:
+%{microblaze1} %(target_asm_spec) %(subtarget_asm_spec)
+
+*asm_debug:
+%{gstabs*:--gstabs}%{!gstabs*:%{g*:--gdwarf2}}
+
+*asm_final:
+
+
+*asm_options:
+%a %Y %{c:%W{o*}%{!o*:-o %w%b%O}}%{!c:-o %d%w%u%O}
+
+*invoke_as:
+%{!S:-o %|.s |
+ as %(asm_options) %m.s %A }
+
+*cpp:
+%{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} %{mno-xl-soft-mul: -DHAVE_HW_MUL} %{mxl-multiply-high: -DHAVE_HW_MUL_HIGH} %{mno-xl-soft-div: -DHAVE_HW_DIV} %{mxl-barrel-shift: -DHAVE_HW_BSHIFT} %{mxl-pattern-compare: -DHAVE_HW_PCMP} %{mhard-float: -DHAVE_HW_FPU} %{mxl-float-convert: -DHAVE_HW_FPU_CONVERT} %{mxl-float-sqrt: -DHAVE_HW_FPU_SQRT}
+
+*cpp_options:
+%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w} %{f*} %{g*:%{!g0:%{!fno-working-directory:-fworking-directory}}} %{O*} %{undef} %{save-temps:-fpch-preprocess}
+
+*cpp_debug_options:
+%{d*}
+
+*cpp_unique_options:
+%{C|CC:%{!E:%eGCC does not support -C or -CC without -E}} %{!Q:-quiet} %{nostdinc*} %{C} %{CC} %{v} %{I*&F*} %{P} %I %{MD:-MD %{!o:%b.d}%{o*:%.d%*}} %{MMD:-MMD %{!o:%b.d}%{o*:%.d%*}} %{M} %{MM} %{MF*} %{MG} %{MP} %{MQ*} %{MT*} %{!E:%{!M:%{!MM:%{MD|MMD:%{o*:-MQ %*}}}}} %{remap} %{g3:-dD} %{H} %C %{D*&U*&A*} %{i*} %Z %i %{fmudflap:-D_MUDFLAP -include mf-runtime.h} %{fmudflapth:-D_MUDFLAP -D_MUDFLAPTH -include mf-runtime.h} %{E|M|MM:%W{o*}}
+
+*trad_capable_cpp:
+cc1 -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}
+
+*cc1:
+ %{G*} %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} %{save-temps: } %(subtarget_cc1_spec) %{Zxl-blazeit: -mno-xl-soft-mul -mno-xl-soft-div -mxl-barrel-shift -mxl-pattern-compare -mxl-multiply-high}
+
+*cc1_options:
+%{pg:%{fomit-frame-pointer:%e-pg and -fomit-frame-pointer are incompatible}} %1 %{!Q:-quiet} -dumpbase %B %{d*} %{m*} %{a*} %{c|S:%{o*:-auxbase-strip %*}%{!o*:-auxbase %b}}%{!c:%{!S:-auxbase %b}} %{g*} %{O*} %{W*&pedantic*} %{w} %{std*&ansi&trigraphs} %{v:-version} %{pg:-p} %{p} %{f*} %{undef} %{Qn:-fno-ident} %{--help:--help} %{--target-help:--target-help} %{!fsyntax-only:%{S:%W{o*}%{!o*:-o %b.s}}} %{fsyntax-only:-o %j} %{-param*} %{fmudflap|fmudflapth:-fno-builtin -fno-merge-constants} %{coverage:-fprofile-arcs -ftest-coverage}
+
+*cc1plus:
+
+
+*link_gcc_c_sequence:
+%G %L %G
+
+*link_ssp:
+%{fstack-protector|fstack-protector-all:-lssp_nonshared -lssp}
+
+*endfile:
+crtend.o%s crtn.o%s
+
+*link:
+%{shared:-shared} -N -relax %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} %{!mxl-gp-opt: -G 0} %{!Wl,-T*: %{!T*: -T xilinx.ld%s}}
+
+*lib:
+%{!pg:%{!nostdlib:%{!Zxl-no-libxil:-start-group -lxil -lc_m_bs -lm_m_bs -end-group }}} %{pg:%{!nostdlib:-start-group -lxilprofile -lxil -lc_m_bs -lm_m_bs -end-group }} %{Zxl-no-libxil: %{!nostdlib: -start-group -lc_m_bs -lm_m_bs -end-group }}
+
+*mfwrap:
+ %{static: %{fmudflap|fmudflapth: --wrap=malloc --wrap=free --wrap=calloc --wrap=realloc --wrap=mmap --wrap=munmap --wrap=alloca} %{fmudflapth: --wrap=pthread_create}} %{fmudflap|fmudflapth: --wrap=main}
+
+*mflib:
+%{fmudflap|fmudflapth: -export-dynamic}
+
+*libgcc:
+-lgcc
+
+*startfile:
+%{Zxl-mode-executable : %(startfile_executable) ; Zxl-mode-xmdstub : %(startfile_xmdstub) ; Zxl-mode-bootstrap : %(startfile_bootstrap) ; Zxl-mode-novectors : %(startfile_novectors) ; Zxl-mode-xilkernel : %(startfile_xilkernel) ; : %(startfile_default) } %(startfile_crtinit)
+
+*switches_need_spaces:
+
+
+*cross_compile:
+1
+
+*version:
+4.1.1
+
+*multilib:
+. !mxl-barrel-shift !mno-xl-soft-mul !mxl-multiply-high;bs mxl-barrel-shift !mno-xl-soft-mul !mxl-multiply-high;m !mxl-barrel-shift mno-xl-soft-mul !mxl-multiply-high;m/mh !mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high;bs/m mxl-barrel-shift mno-xl-soft-mul !mxl-multiply-high;bs/m/mh mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high;
+
+*multilib_defaults:
+
+
+*multilib_extra:
+
+
+*multilib_matches:
+mxl-barrel-shift mxl-barrel-shift;mno-xl-soft-mul mno-xl-soft-mul;mxl-multiply-high mxl-multiply-high;
+
+*multilib_exclusions:
+
+
+*multilib_options:
+mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high
+
+*linker:
+collect2
+
+*link_libgcc:
+%D
+
+*md_exec_prefix:
+
+
+*md_startfile_prefix:
+
+
+*md_startfile_prefix_1:
+
+
+*startfile_prefix_spec:
+
+
+*sysroot_spec:
+--sysroot=%R
+
+*sysroot_suffix_spec:
+
+
+*sysroot_hdrs_suffix_spec:
+
+
+*subtarget_cc1_spec:
+
+
+*subtarget_cpp_spec:
+
+
+*subtarget_cpp_size_spec:
+-D__SIZE_TYPE__=unsigned\ int -D__PTRDIFF_TYPE__=int
+
+*microblaze_as_asm_spec:
+%{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} %{pipe: %e-pipe is not supported.} %{K} %(subtarget_microblaze_as_asm_spec)
+
+*gas_asm_spec:
+%{v}
+
+*target_asm_spec:
+
+
+*subtarget_microblaze_as_asm_spec:
+%{v}
+
+*subtarget_asm_optimizing_spec:
+
+
+*subtarget_asm_debugging_spec:
+%{g} %{g0} %{g1} %{g2} %{g3} %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3}
+
+*subtarget_asm_spec:
+
+
+*linker_endian_spec:
+
+
+*startfile_executable:
+crt0.o%s crti.o%s crtbegin.o%s
+
+*startfile_xmdstub:
+crt1.o%s crti.o%s crtbegin.o%s
+
+*startfile_bootstrap:
+crt2.o%s crti.o%s crtbegin.o%s
+
+*startfile_novectors:
+crt3.o%s crti.o%s crtbegin.o%s
+
+*startfile_xilkernel:
+crt4.o%s crti.o%s crtbegin.o%s
+
+*startfile_crtinit:
+%{!pg: %{!mno-clearbss: crtinit.o%s} %{mno-clearbss: sim-crtinit.o%s}} %{pg: %{!mno-clearbss: pgcrtinit.o%s} %{mno-clearbss: sim-pgcrtinit.o%s}}
+
+*startfile_default:
+crt0.o%s crti.o%s crtbegin.o%s
+
+*link_command:
+%{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S: %(linker) %l %{pie:-pie} %X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r} %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}} %{static:} %{L*} %(mfwrap) %(link_libgcc) %o %(mflib) %{fprofile-arcs|fprofile-generate|coverage:-lgcov} %{!nostdlib:%{!nodefaultlibs:%(link_ssp) %(link_gcc_c_sequence)}} %{!A:%{!nostdlib:%{!nostartfiles:%E}}} %{T*} }}}}}}
+
aeMB/sw/compile/aemb.specs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/compile/custom_crt/crt0.s
===================================================================
--- aeMB/sw/compile/custom_crt/crt0.s (nonexistent)
+++ aeMB/sw/compile/custom_crt/crt0.s (revision 17)
@@ -0,0 +1,100 @@
+###################################-*-asm*-
+#
+# Copyright (c) 2001 Xilinx, Inc. All rights reserved.
+#
+# Xilinx, Inc.
+#
+# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+# AND FITNESS FOR A PARTICULAR PURPOSE.
+#
+# crt0.s
+#
+# Default C run-time initialization for MicroBlaze standalone
+# executables (compiled with -xl-mode-executable or no switches)
+#
+# $Id: crt0.s,v 1.7.2.6 2005/11/15 23:32:53 salindac Exp $
+#
+#######################################
+
+/*
+
+ MicroBlaze Vector Map for standalone executables
+
+ Address Vector type Label
+ ------- ----------- ------
+
+ # 0x00 # (-- IMM --)
+ # 0x04 # Reset _start1
+
+ # 0x08 # (-- IMM --)
+ # 0x0c # Software Exception _exception_handler
+
+ # 0x10 # (-- IMM --)
+ # 0x14 # Hardware Interrupt _interrupt_handler
+
+ # 0x18 # (-- IMM --)
+ # 0x1C # Breakpoint Exception (-- Don't Care --)
+
+ # 0x20 # (-- IMM --)
+ # 0x24 # Hardware Exception _hw_exception_handler
+
+*/
+
+
+ .globl _start
+ .section .vectors.reset, "ax"
+ .align 2
+_start:
+ brai _start1
+
+ .section .vectors.sw_exception, "ax"
+ .align 2
+_vector_sw_exception:
+ brai _exception_handler
+
+ .section .vectors.interrupt, "ax"
+ .align 2
+_vector_interrupt:
+ brai _interrupt_handler
+
+ .section .vectors.hw_exception, "ax"
+ .align 2
+_vector_hw_exception:
+ brai _hw_exception_handler
+
+ .section .text
+ .globl _start1
+ .align 2
+_start1:
+ la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */
+ la r2, r0, _SDA2_BASE_
+ la r1, r0, _stack-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */
+
+ brlid r15, _crtinit /* Initialize BSS and run program */
+ nop
+
+ brlid r15, exit /* Call exit with the return value of main */
+ addik r5, r3, 0
+
+ /* Control does not reach here */
+
+/*
+ _exit
+ Our simple _exit
+*/
+ .globl _exit
+ .align 2
+ .ent _exit
+_exit:
+ bri 0
+ .end _exit
+
aeMB/sw/compile/custom_crt/crt0.s
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/compile/custom_crt/crtinit.s
===================================================================
--- aeMB/sw/compile/custom_crt/crtinit.s (nonexistent)
+++ aeMB/sw/compile/custom_crt/crtinit.s (revision 17)
@@ -0,0 +1,83 @@
+###################################-*-asm*-
+#
+# Copyright (c) 2001 Xilinx, Inc. All rights reserved.
+#
+# Xilinx, Inc.
+#
+# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+# AND FITNESS FOR A PARTICULAR PURPOSE.
+#
+# crtinit.s
+#
+# Default second stage of C run-time initialization
+#
+# $Id: crtinit.s,v 1.5.2.7 2006/07/05 18:53:54 vasanth Exp $
+#
+#######################################
+
+ .globl _crtinit
+ .align 2
+ .ent _crtinit
+
+_crtinit:
+ addi r1, r1, -20 /* Save Link register */
+ swi r15, r1, 0
+
+ addi r6, r0, __sbss_start /* clear SBSS */
+ addi r7, r0, __sbss_end
+ rsub r18, r6, r7
+ blei r18, .Lendsbss
+
+.Lloopsbss:
+ swi r0, r6, 0
+ addi r6, r6, 4
+ rsub r18, r6, r7
+ bgti r18, .Lloopsbss
+.Lendsbss:
+
+ addi r6, r0, __bss_start /* clear BSS */
+ addi r7, r0, __bss_end
+ rsub r18, r6, r7
+ blei r18, .Lendbss
+.Lloopbss:
+ swi r0, r6, 0
+ addi r6, r6, 4
+ rsub r18, r6, r7
+ bgti r18, .Lloopbss
+.Lendbss:
+
+ brlid r15, _program_init /* Initialize the program */
+ nop
+
+# brlid r15, __init /* Invoke language initialization functions */
+# nop
+
+ addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */
+ addi r7, r0, 0
+ brlid r15, main /* Execute the program */
+ addi r5, r0, 0
+
+ addik r19, r3, 0 /* Save return value */
+
+# brlid r15, __fini /* Invoke language cleanup functions */
+# nop
+
+ brlid r15, _program_clean /* Cleanup the program */
+ nop
+
+ lw r15, r1, r0 /* Return back to CRT */
+
+ addik r3, r19, 0 /* Restore return value */
+ rtsd r15, 8
+ addi r1, r1, 20
+ .end _crtinit
+
aeMB/sw/compile/custom_crt/crtinit.s
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/compile/gccrom
===================================================================
--- aeMB/sw/compile/gccrom (nonexistent)
+++ aeMB/sw/compile/gccrom (revision 17)
@@ -0,0 +1,45 @@
+#!/bin/sh
+# $Id: gccrom,v 1.18 2008-05-01 08:35:04 sybreon Exp $
+
+TOOLCHAIN="$PRONOC_WORK/toolchain"
+
+
+# Compile using C pre-processor
+ELFFILE="rom"
+XILFLAGS="-mtune=v5.00 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul"
+CXXFLAGS="-O1"
+LNKFLAGS="-Wl,-defsym -Wl,_STACK_SIZE=0x400 -Wl,-defsym -Wl,_HEAP_SIZE=0x400"
+LIBFLAGS=""
+INCFLAGS="-Icc/"
+RAMSIZE="3FFF" #for aeMB ramwith of 12
+
+$TOOLCHAIN/aemb/bin/mb-g++ $XILFLAGS $CXXFLAGS $LNKFLAGS $LIBFLAGS $INCFLAGS -specs=aemb.specs $@ -o $ELFFILE && \
+echo "xgcc=$?" && \
+
+# Create a text listing of the compiled code
+#$TOOLCHAIN/mb-objdump -DSCz $ELFFILE > $ELFFILE.dump && \
+#echo "dump=$?" && \
+
+# Convert the ELF file to an SREC file
+#$TOOLCHAIN/mb-objcopy -O srec $ELFFILE $ELFFILE.srec && \
+#echo "copy=$?" && \
+
+# Generate a Verilog VMEM file from the SREC file
+#srec_cat $ELFFILE.srec -fill 0xFF -within $ELFFILE.srec --range-pad 4 -o out/dump.vmem -vmem 32 && \
+#echo "srec=$?" && \
+
+
+# Convert the ELF file to an IHEX file
+$TOOLCHAIN/aemb/bin/mb-objcopy -O ihex $ELFFILE $ELFFILE.ihex && \
+#echo "copy2ihex=$?" && \
+
+# Generate a MIF file from the IHEX file
+$TOOLCHAIN/ihex2mif/ihex2mif -f $ELFFILE.ihex -e $RAMSIZE -o ram.mif && \
+echo "ihex2mif=$?"
+
+# echo the checksum
+#MD5=$(sha1sum $ELFFILE | cut -c1-32) && \
+#echo "sha1=$MD5"
+
+# Cleanup code
+#rm $ELFFILE.srec && rm $ELFFILE
aeMB/sw/compile/gccrom
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeMB/sw/Makefile
===================================================================
--- aeMB/sw/Makefile (nonexistent)
+++ aeMB/sw/Makefile (revision 17)
@@ -0,0 +1,4 @@
+all:
+ cd compile; ./gccrom ../main.c;
+ cd compile; cp ram.mif ../ram00.mif;
+
Index: lm32/verilog/src/lm32.v
===================================================================
--- lm32/verilog/src/lm32.v (nonexistent)
+++ lm32/verilog/src/lm32.v (revision 17)
@@ -0,0 +1,178 @@
+
+`include "system_conf.v"
+`include "lm32_include.v"
+
+module lm32 #(
+ parameter INTR_NUM=32,
+ parameter CFG_PL_MULTIPLY= "ENABLED", //"ENABLED","DISABLED"
+ parameter CFG_PL_BARREL_SHIFT= "ENABLED",
+ parameter CFG_SIGN_EXTEND="ENABLED",
+ parameter CFG_MC_DIVIDE="DISABLED"
+
+)(
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ interrupt,
+ // Instruction Wishbone master
+ I_DAT_I,
+ I_ACK_I,
+ I_ERR_I,
+ I_RTY_I,
+ I_DAT_O,
+ I_ADR_O,
+ I_CYC_O,
+ I_SEL_O,
+ I_STB_O,
+ I_WE_O,
+ I_CTI_O,
+ //I_LOCK_O,
+ I_BTE_O,
+
+ // Data Wishbone master
+ D_DAT_I,
+ D_ACK_I,
+ D_ERR_I,
+ D_RTY_I,
+ D_DAT_O,
+ D_ADR_O,
+ D_CYC_O,
+ D_SEL_O,
+ D_STB_O,
+ D_WE_O,
+ D_CTI_O,
+ //D_LOCK_O,
+ D_BTE_O
+
+);
+
+
+
+input clk_i; // Clock
+input rst_i; // Reset
+
+//`ifdef CFG_INTERRUPTS_ENABLED
+input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
+//`endif
+
+`ifdef CFG_USER_ENABLED
+input [`LM32_WORD_RNG] user_result; // User-defined instruction result
+input user_complete; // Indicates the user-defined instruction result is valid
+`endif
+
+`ifdef CFG_IWB_ENABLED
+input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
+input I_ACK_I; // Instruction Wishbone interface acknowledgement
+input I_ERR_I; // Instruction Wishbone interface error
+input I_RTY_I; // Instruction Wishbone interface retry
+`endif
+
+
+
+`ifdef CFG_USER_ENABLED
+output user_valid; // Indicates that user_opcode and user_operand_* are valid
+wire user_valid;
+output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
+reg [`LM32_USER_OPCODE_RNG] user_opcode;
+output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
+wire [`LM32_WORD_RNG] user_operand_0;
+output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
+wire [`LM32_WORD_RNG] user_operand_1;
+`endif
+
+
+
+
+
+`ifdef CFG_IWB_ENABLED
+output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
+wire [`LM32_WORD_RNG] I_DAT_O;
+output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
+wire [`LM32_WORD_RNG] I_ADR_O;
+output I_CYC_O; // Instruction Wishbone interface cycle
+wire I_CYC_O;
+output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
+wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
+output I_STB_O; // Instruction Wishbone interface strobe
+wire I_STB_O;
+output I_WE_O; // Instruction Wishbone interface write enable
+wire I_WE_O;
+output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] I_CTI_O;
+//output I_LOCK_O; // Instruction Wishbone interface lock bus
+//wire I_LOCK_O;
+output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] I_BTE_O;
+`endif
+
+
+input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
+input D_ACK_I; // Data Wishbone interface acknowledgement
+input D_ERR_I; // Data Wishbone interface error
+input D_RTY_I; // Data Wishbone interface retry
+
+
+output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
+wire [`LM32_WORD_RNG] D_DAT_O;
+output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
+wire [`LM32_WORD_RNG] D_ADR_O;
+output D_CYC_O; // Data Wishbone interface cycle
+wire D_CYC_O;
+output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
+wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
+output D_STB_O; // Data Wishbone interface strobe
+wire D_STB_O;
+output D_WE_O; // Data Wishbone interface write enable
+wire D_WE_O;
+output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] D_CTI_O;
+//output D_LOCK_O; // Date Wishbone interface lock bus
+//wire D_LOCK_O;
+output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] D_BTE_O;
+
+
+wire [31:0] iadr_o,dadr_o;
+
+lm32_top the_lm32_top(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+ .interrupt_n(~interrupt),
+ .I_DAT_I(I_DAT_I),
+ .I_ACK_I(I_ACK_I),
+ .I_ERR_I(I_ERR_I),
+ .I_RTY_I(I_RTY_I),
+ .D_DAT_I(D_DAT_I),
+ .D_ACK_I(D_ACK_I),
+ .D_ERR_I(D_ERR_I),
+ .D_RTY_I(D_RTY_I),
+ .I_DAT_O(I_DAT_O),
+ .I_ADR_O(iadr_o),
+ .I_CYC_O(I_CYC_O),
+ .I_SEL_O(I_SEL_O),
+ .I_STB_O(I_STB_O),
+ .I_WE_O(I_WE_O),
+ .I_CTI_O(I_CTI_O),
+ .I_LOCK_O(),
+ .I_BTE_O(I_BTE_O),
+ .D_DAT_O(D_DAT_O),
+ .D_ADR_O(dadr_o),
+ .D_CYC_O(D_CYC_O),
+ .D_SEL_O(D_SEL_O),
+ .D_STB_O(D_STB_O),
+ .D_WE_O(D_WE_O),
+ .D_CTI_O(D_CTI_O),
+ .D_LOCK_O(),
+ .D_BTE_O(D_BTE_O)
+);
+
+ assign D_ADR_O= {2'b00,dadr_o[31:2]};
+ assign I_ADR_O= {2'b00,iadr_o[31:2]};
+ // assign iwb_dat_o = 0;
+ // assign iwb_tag_o = 3'b000; // clasic wishbone without burst
+ // assign dwb_tag_o = 3'b000; // clasic wishbone without burst
+ // assign iwb_adr_o[31:30] = 2'b00;
+ // assign dwb_adr_o[31:30] = 2'b00;
+
+endmodule
+
lm32/verilog/src/lm32.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_instruction_unit.v
===================================================================
--- lm32/verilog/src/lm32_instruction_unit.v (nonexistent)
+++ lm32/verilog/src/lm32_instruction_unit.v (revision 17)
@@ -0,0 +1,751 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_instruction_unit.v
+// Title : Instruction unit
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_instruction_unit (
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ // From pipeline
+ stall_a,
+ stall_f,
+ stall_d,
+ stall_x,
+ stall_m,
+ valid_f,
+ kill_f,
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+ branch_taken_x,
+ branch_target_x,
+`endif
+ branch_taken_m,
+ branch_target_m,
+`ifdef CFG_ICACHE_ENABLED
+ iflush,
+`endif
+`ifdef CFG_DCACHE_ENABLED
+ dcache_restart_request,
+ dcache_refill_request,
+ dcache_refilling,
+`endif
+`ifdef CFG_IWB_ENABLED
+ // From Wishbone
+ i_dat_i,
+ i_ack_i,
+ i_err_i,
+ i_rty_i,
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ jtag_read_enable,
+ jtag_write_enable,
+ jtag_write_data,
+ jtag_address,
+`endif
+ // ----- Outputs -------
+ // To pipeline
+ pc_f,
+ pc_d,
+ pc_x,
+ pc_m,
+ pc_w,
+`ifdef CFG_ICACHE_ENABLED
+ icache_stall_request,
+ icache_restart_request,
+ icache_refill_request,
+ icache_refilling,
+`endif
+`ifdef CFG_IWB_ENABLED
+ // To Wishbone
+ i_dat_o,
+ i_adr_o,
+ i_cyc_o,
+ i_sel_o,
+ i_stb_o,
+ i_we_o,
+ i_cti_o,
+ i_lock_o,
+ i_bte_o,
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ jtag_read_data,
+ jtag_access_complete,
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+ bus_error_d,
+`endif
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+ instruction_f,
+`endif
+ instruction_d
+ );
+
+/////////////////////////////////////////////////////
+// Parameters
+/////////////////////////////////////////////////////
+
+parameter associativity = 1; // Associativity of the cache (Number of ways)
+parameter sets = 512; // Number of sets
+parameter bytes_per_line = 16; // Number of bytes per cache line
+parameter base_address = 0; // Base address of cachable memory
+parameter limit = 0; // Limit (highest address) of cachable memory
+
+// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
+//localparam addr_offset_width = (bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2);
+localparam addr_offset_width = 2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+
+input stall_a; // Stall A stage instruction
+input stall_f; // Stall F stage instruction
+input stall_d; // Stall D stage instruction
+input stall_x; // Stall X stage instruction
+input stall_m; // Stall M stage instruction
+input valid_f; // Instruction in F stage is valid
+input kill_f; // Kill instruction in F stage
+
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+input branch_taken_x; // Branch instruction in X stage is taken
+input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction
+`endif
+input branch_taken_m; // Branch instruction in M stage is taken
+input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction
+
+`ifdef CFG_ICACHE_ENABLED
+input iflush; // Flush instruction cache
+`endif
+`ifdef CFG_DCACHE_ENABLED
+input dcache_restart_request; // Restart instruction that caused a data cache miss
+input dcache_refill_request; // Request to refill data cache
+input dcache_refilling;
+`endif
+
+`ifdef CFG_IWB_ENABLED
+input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data
+input i_ack_i; // Instruction Wishbone interface acknowledgement
+input i_err_i; // Instruction Wishbone interface error
+input i_rty_i; // Instruction Wishbone interface retry
+`endif
+
+`ifdef CFG_HW_DEBUG_ENABLED
+input jtag_read_enable; // JTAG read memory request
+input jtag_write_enable; // JTAG write memory request
+input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data
+input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address
+`endif
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_PC_RNG] pc_f; // F stage PC
+reg [`LM32_PC_RNG] pc_f;
+output [`LM32_PC_RNG] pc_d; // D stage PC
+reg [`LM32_PC_RNG] pc_d;
+output [`LM32_PC_RNG] pc_x; // X stage PC
+reg [`LM32_PC_RNG] pc_x;
+output [`LM32_PC_RNG] pc_m; // M stage PC
+reg [`LM32_PC_RNG] pc_m;
+output [`LM32_PC_RNG] pc_w; // W stage PC
+reg [`LM32_PC_RNG] pc_w;
+
+`ifdef CFG_ICACHE_ENABLED
+output icache_stall_request; // Instruction cache stall request
+wire icache_stall_request;
+output icache_restart_request; // Request to restart instruction that cached instruction cache miss
+wire icache_restart_request;
+output icache_refill_request; // Instruction cache refill request
+wire icache_refill_request;
+output icache_refilling; // Indicates the icache is refilling
+wire icache_refilling;
+`endif
+
+`ifdef CFG_IWB_ENABLED
+output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data
+`ifdef CFG_HW_DEBUG_ENABLED
+reg [`LM32_WORD_RNG] i_dat_o;
+`else
+wire [`LM32_WORD_RNG] i_dat_o;
+`endif
+output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address
+reg [`LM32_WORD_RNG] i_adr_o;
+output i_cyc_o; // Instruction Wishbone interface cycle
+reg i_cyc_o;
+output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select
+`ifdef CFG_HW_DEBUG_ENABLED
+reg [`LM32_BYTE_SELECT_RNG] i_sel_o;
+`else
+wire [`LM32_BYTE_SELECT_RNG] i_sel_o;
+`endif
+output i_stb_o; // Instruction Wishbone interface strobe
+reg i_stb_o;
+output i_we_o; // Instruction Wishbone interface write enable
+`ifdef CFG_HW_DEBUG_ENABLED
+reg i_we_o;
+`else
+wire i_we_o;
+`endif
+output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type
+reg [`LM32_CTYPE_RNG] i_cti_o;
+output i_lock_o; // Instruction Wishbone interface lock bus
+reg i_lock_o;
+output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] i_bte_o;
+`endif
+
+`ifdef CFG_HW_DEBUG_ENABLED
+output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface
+reg [`LM32_BYTE_RNG] jtag_read_data;
+output jtag_access_complete; // Requested memory access by JTAG interface is complete
+wire jtag_access_complete;
+`endif
+
+`ifdef CFG_BUS_ERRORS_ENABLED
+output bus_error_d; // Indicates a bus error occured while fetching the instruction
+reg bus_error_d;
+`endif
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from)
+wire [`LM32_INSTRUCTION_RNG] instruction_f;
+`endif
+output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded
+reg [`LM32_INSTRUCTION_RNG] instruction_d;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+reg [`LM32_PC_RNG] pc_a; // A stage PC
+
+`ifdef LM32_CACHE_ENABLED
+reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss
+`endif
+
+`ifdef CFG_ICACHE_ENABLED
+wire icache_read_enable_f; // Indicates if instruction cache miss is valid
+wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss
+reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache
+reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone
+wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache
+wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
+wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
+wire last_word; // Indicates if this is the last word in the cache line
+wire [`LM32_PC_RNG] first_address; // First cache refill address
+`else
+`ifdef CFG_IWB_ENABLED
+reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone
+`endif
+`endif
+`ifdef CFG_IROM_ENABLED
+wire irom_select_a; // Indicates if A stage PC maps to a ROM address
+reg irom_select_f; // Indicates if F stage PC maps to a ROM address
+wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM
+`endif
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+`else
+wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage
+`endif
+
+`ifdef CFG_HW_DEBUG_ENABLED
+reg jtag_access; // Indicates if a JTAG WB access is in progress
+`endif
+
+/////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////
+`define INCLUDE_FUNCTION
+`include "lm32_functions.v"
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+// Instruction ROM
+`ifdef CFG_IROM_ENABLED
+pmi_ram_dp #(
+ // ----- Parameters -------
+ .pmi_wr_addr_depth (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
+ .pmi_wr_addr_width ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
+ .pmi_wr_data_width (`LM32_INSTRUCTION_WIDTH),
+ .pmi_rd_addr_depth (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
+ .pmi_rd_addr_width ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
+ .pmi_rd_data_width (`LM32_INSTRUCTION_WIDTH),
+ .pmi_regmode ("noreg"),
+ .pmi_gsr ("enable"),
+ .pmi_resetmode ("async"),
+ .pmi_init_file (`CFG_IROM_INIT_FILE),
+ .pmi_init_file_format ("hex"),
+ .module_type ("pmi_ram_dp")
+ ) ram (
+ // ----- Inputs -------
+ .RdClock (clk_i),
+ .WrClock (`FALSE),
+ .Reset (rst_i),
+ .Data ({32{1'b0}}),
+ .RdAddress (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
+ .WrAddress ({(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1){1'b0}}),
+ .RdClockEn (~stall_a),
+ .WrClockEn (`FALSE),
+ .WE (`FALSE),
+ // ----- Outputs -------
+ .Q (irom_data_f)
+ );
+`endif
+
+`ifdef CFG_ICACHE_ENABLED
+// Instruction cache
+lm32_icache #(
+ .associativity (associativity),
+ .sets (sets),
+ .bytes_per_line (bytes_per_line),
+ .base_address (base_address),
+ .limit (limit)
+ ) icache (
+ // ----- Inputs -----
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_a (stall_a),
+ .stall_f (stall_f),
+ .address_a (pc_a),
+ .address_f (pc_f),
+ .read_enable_f (icache_read_enable_f),
+ .refill_ready (icache_refill_ready),
+ .refill_data (icache_refill_data),
+ .iflush (iflush),
+ // ----- Outputs -----
+ .stall_request (icache_stall_request),
+ .restart_request (icache_restart_request),
+ .refill_request (icache_refill_request),
+ .refill_address (icache_refill_address),
+ .refilling (icache_refilling),
+ .inst (icache_data_f)
+ );
+`endif
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+`ifdef CFG_ICACHE_ENABLED
+// Generate signal that indicates when instruction cache misses are valid
+assign icache_read_enable_f = (valid_f == `TRUE)
+ && (kill_f == `FALSE)
+`ifdef CFG_DCACHE_ENABLED
+ && (dcache_restart_request == `FALSE)
+`endif
+`ifdef CFG_IROM_ENABLED
+ && (irom_select_f == `FALSE)
+`endif
+ ;
+`endif
+
+// Compute address of next instruction to fetch
+always @(*)
+begin
+ // The request from the latest pipeline stage must take priority
+`ifdef CFG_DCACHE_ENABLED
+ if (dcache_restart_request == `TRUE)
+ pc_a = restart_address;
+ else
+`endif
+ if (branch_taken_m == `TRUE)
+ pc_a = branch_target_m;
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+ else if (branch_taken_x == `TRUE)
+ pc_a = branch_target_x;
+`endif
+ else
+`ifdef CFG_ICACHE_ENABLED
+ if (icache_restart_request == `TRUE)
+ pc_a = restart_address;
+ else
+`endif
+ pc_a = pc_f + 1'b1;
+end
+
+// Select where instruction should be fetched from
+`ifdef CFG_IROM_ENABLED
+assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
+`endif
+
+// Select instruction from selected source
+`ifdef CFG_ICACHE_ENABLED
+`ifdef CFG_IROM_ENABLED
+assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
+`else
+assign instruction_f = icache_data_f;
+`endif
+`else
+`ifdef CFG_IROM_ENABLED
+`ifdef CFG_IWB_ENABLED
+assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
+`else
+assign instruction_f = irom_data_f;
+`endif
+`else
+assign instruction_f = wb_data_f;
+`endif
+`endif
+
+// Unused/constant Wishbone signals
+`ifdef CFG_IWB_ENABLED
+`ifdef CFG_HW_DEBUG_ENABLED
+`else
+assign i_dat_o = 32'd0;
+assign i_we_o = `FALSE;
+assign i_sel_o = 4'b1111;
+`endif
+assign i_bte_o = `LM32_BTYPE_LINEAR;
+`endif
+
+`ifdef CFG_ICACHE_ENABLED
+// Determine parameters for next cache refill Wishbone access
+// generate
+// case (bytes_per_line)
+// 4:
+// begin
+// assign first_cycle_type = `LM32_CTYPE_END;
+// assign next_cycle_type = `LM32_CTYPE_END;
+// assign last_word = `TRUE;
+// assign first_address = icache_refill_address;
+// end
+// 8:
+// begin
+// assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
+// assign next_cycle_type = `LM32_CTYPE_END;
+// assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+// assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+// end
+// 16:
+// begin
+assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+// end
+// endcase
+// endgenerate
+`endif
+
+/////////////////////////////////////////////////////
+// Sequential Logic
+/////////////////////////////////////////////////////
+
+// PC
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ pc_f <= (`CFG_EBA_RESET-4)/4;
+ pc_d <= {`LM32_PC_WIDTH{1'b0}};
+ pc_x <= {`LM32_PC_WIDTH{1'b0}};
+ pc_m <= {`LM32_PC_WIDTH{1'b0}};
+ pc_w <= {`LM32_PC_WIDTH{1'b0}};
+ end
+ else
+ begin
+ if (stall_f == `FALSE)
+ pc_f <= pc_a;
+ if (stall_d == `FALSE)
+ pc_d <= pc_f;
+ if (stall_x == `FALSE)
+ pc_x <= pc_d;
+ if (stall_m == `FALSE)
+ pc_m <= pc_x;
+ pc_w <= pc_m;
+ end
+end
+
+`ifdef LM32_CACHE_ENABLED
+// Address to restart from after a cache miss has been handled
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ restart_address <= {`LM32_PC_WIDTH{1'b0}};
+ else
+ begin
+`ifdef CFG_DCACHE_ENABLED
+`ifdef CFG_ICACHE_ENABLED
+ // D-cache restart address must take priority, otherwise instructions will be lost
+ if (dcache_refill_request == `TRUE)
+ restart_address <= pc_w;
+ else if ((icache_refill_request == `TRUE) && (!dcache_refilling))
+ restart_address <= icache_refill_address;
+`else
+ if (dcache_refill_request == `TRUE)
+ restart_address <= pc_w;
+`endif
+`else
+`ifdef CFG_ICACHE_ENABLED
+ if (icache_refill_request == `TRUE)
+ restart_address <= icache_refill_address;
+`endif
+`endif
+ end
+end
+`endif
+
+// Record where instruction was fetched from
+`ifdef CFG_IROM_ENABLED
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ irom_select_f <= `FALSE;
+ else
+ begin
+ if (stall_f == `FALSE)
+ irom_select_f <= irom_select_a;
+ end
+end
+`endif
+
+`ifdef CFG_HW_DEBUG_ENABLED
+assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
+always @*
+begin
+ case (jtag_address[1:0])
+ 2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
+ 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
+ 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
+ 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
+ endcase
+end
+`endif
+
+`ifdef CFG_IWB_ENABLED
+// Instruction Wishbone interface
+`ifdef CFG_ICACHE_ENABLED
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ i_cyc_o <= `FALSE;
+ i_stb_o <= `FALSE;
+ i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
+ i_cti_o <= `LM32_CTYPE_END;
+ i_lock_o <= `FALSE;
+ icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
+ icache_refill_ready <= `FALSE;
+`ifdef CFG_BUS_ERRORS_ENABLED
+ bus_error_f <= `FALSE;
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ i_we_o <= `FALSE;
+ i_sel_o <= 4'b1111;
+ jtag_access <= `FALSE;
+`endif
+ end
+ else
+ begin
+ icache_refill_ready <= `FALSE;
+ // Is a cycle in progress?
+ if (i_cyc_o == `TRUE)
+ begin
+ // Has cycle completed?
+ if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
+ begin
+`ifdef CFG_HW_DEBUG_ENABLED
+ if (jtag_access == `TRUE)
+ begin
+ i_cyc_o <= `FALSE;
+ i_stb_o <= `FALSE;
+ i_we_o <= `FALSE;
+ jtag_access <= `FALSE;
+ end
+ else
+`endif
+ begin
+ if (last_word == `TRUE)
+ begin
+ // Cache line fill complete
+ i_cyc_o <= `FALSE;
+ i_stb_o <= `FALSE;
+ i_lock_o <= `FALSE;
+ end
+ // Fetch next word in cache line
+ i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+ i_cti_o <= next_cycle_type;
+ // Write fetched data into instruction cache
+ icache_refill_ready <= `TRUE;
+ icache_refill_data <= i_dat_i;
+ end
+ end
+`ifdef CFG_BUS_ERRORS_ENABLED
+ if (i_err_i == `TRUE)
+ begin
+ bus_error_f <= `TRUE;
+ $display ("Instruction bus error. Address: %x", i_adr_o);
+ end
+`endif
+ end
+ else
+ begin
+ if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
+ begin
+ // Read first word of cache line
+`ifdef CFG_HW_DEBUG_ENABLED
+ i_sel_o <= 4'b1111;
+`endif
+ i_adr_o <= {first_address, 2'b00};
+ i_cyc_o <= `TRUE;
+ i_stb_o <= `TRUE;
+ i_cti_o <= first_cycle_type;
+ //i_lock_o <= `TRUE;
+`ifdef CFG_BUS_ERRORS_ENABLED
+ bus_error_f <= `FALSE;
+`endif
+ end
+`ifdef CFG_HW_DEBUG_ENABLED
+ else
+ begin
+ if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
+ begin
+ case (jtag_address[1:0])
+ 2'b00: i_sel_o <= 4'b1000;
+ 2'b01: i_sel_o <= 4'b0100;
+ 2'b10: i_sel_o <= 4'b0010;
+ 2'b11: i_sel_o <= 4'b0001;
+ endcase
+ i_adr_o <= jtag_address;
+ i_dat_o <= {4{jtag_write_data}};
+ i_cyc_o <= `TRUE;
+ i_stb_o <= `TRUE;
+ i_we_o <= jtag_write_enable;
+ i_cti_o <= `LM32_CTYPE_END;
+ jtag_access <= `TRUE;
+ end
+ end
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+ // Clear bus error when exception taken, otherwise they would be
+ // continually generated if exception handler is cached
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+ if (branch_taken_x == `TRUE)
+ bus_error_f <= `FALSE;
+`endif
+ if (branch_taken_m == `TRUE)
+ bus_error_f <= `FALSE;
+`endif
+ end
+ end
+end
+`else
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ i_cyc_o <= `FALSE;
+ i_stb_o <= `FALSE;
+ i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
+ i_cti_o <= `LM32_CTYPE_CLASSIC;
+ i_lock_o <= `FALSE;
+ wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
+`ifdef CFG_BUS_ERRORS_ENABLED
+ bus_error_f <= `FALSE;
+`endif
+ end
+ else
+ begin
+ // Is a cycle in progress?
+ if (i_cyc_o == `TRUE)
+ begin
+ // Has cycle completed?
+ if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
+ begin
+ // Cycle complete
+ i_cyc_o <= `FALSE;
+ i_stb_o <= `FALSE;
+ // Register fetched instruction
+ wb_data_f <= i_dat_i;
+ end
+`ifdef CFG_BUS_ERRORS_ENABLED
+ if (i_err_i == `TRUE)
+ begin
+ bus_error_f <= `TRUE;
+ $display ("Instruction bus error. Address: %x", i_adr_o);
+ end
+`endif
+ end
+ else
+ begin
+ // Wait for an instruction fetch from an external address
+ if ( (stall_a == `FALSE)
+`ifdef CFG_IROM_ENABLED
+ && (irom_select_a == `FALSE)
+`endif
+ )
+ begin
+ // Fetch instruction
+`ifdef CFG_HW_DEBUG_ENABLED
+ i_sel_o <= 4'b1111;
+`endif
+ i_adr_o <= {pc_a, 2'b00};
+ i_cyc_o <= `TRUE;
+ i_stb_o <= `TRUE;
+`ifdef CFG_BUS_ERRORS_ENABLED
+ bus_error_f <= `FALSE;
+`endif
+ end
+ end
+ end
+end
+`endif
+`endif
+
+// Instruction register
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
+`ifdef CFG_BUS_ERRORS_ENABLED
+ bus_error_d <= `FALSE;
+`endif
+ end
+ else
+ begin
+ if (stall_d == `FALSE)
+ begin
+ instruction_d <= instruction_f;
+`ifdef CFG_BUS_ERRORS_ENABLED
+ bus_error_d <= bus_error_f;
+`endif
+ end
+ end
+end
+
+endmodule
lm32/verilog/src/lm32_instruction_unit.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/jtag_cores.v
===================================================================
--- lm32/verilog/src/jtag_cores.v (nonexistent)
+++ lm32/verilog/src/jtag_cores.v (revision 17)
@@ -0,0 +1,216 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : jtag_cores.v
+// Title : Instantiates all IP cores on JTAG chain.
+// Dependencies : system_conf.v
+// Version : 6.0.13
+// =============================================================================
+
+`include "system_conf.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module jtag_cores#(
+ parameter test="ali"
+
+)
+ (
+ // ----- Inputs -------
+`ifdef INCLUDE_LM32
+ reg_d,
+ reg_addr_d,
+`endif
+`ifdef INCLUDE_SPI
+ spi_q,
+`endif
+ // ----- Outputs -------
+`ifdef INCLUDE_LM32
+ reg_update,
+ reg_q,
+ reg_addr_q,
+`endif
+`ifdef INCLUDE_SPI
+ spi_c,
+ spi_d,
+ spi_sn,
+`endif
+ jtck,
+ jrstn
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+`ifdef INCLUDE_LM32
+input [7:0] reg_d;
+input [2:0] reg_addr_d;
+`endif
+
+`ifdef INCLUDE_SPI
+input spi_q;
+`endif
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+`ifdef INCLUDE_LM32
+output reg_update;
+wire reg_update;
+output [7:0] reg_q;
+wire [7:0] reg_q;
+output [2:0] reg_addr_q;
+wire [2:0] reg_addr_q;
+`endif
+
+`ifdef INCLUDE_SPI
+output spi_c;
+wire spi_c;
+output spi_d;
+wire spi_d;
+output spi_sn;
+wire spi_sn;
+`endif
+
+output jtck;
+wire jtck; /* synthesis ER1_MARK="jtck" */ /* synthesis syn_keep=1 */
+output jrstn;
+wire jrstn; /* synthesis ER1_MARK="jrstn" */ /* synthesis syn_keep=1 */
+
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+wire rtiER1;
+wire rtiER2;
+wire tdi;/* synthesis ER1_MARK="jtdi" */ /* synthesis syn_keep=1 */
+wire tdoEr1;/* synthesis ER1_MARK="jtdo1" */ /* synthesis syn_keep=1 */
+wire tdoEr2;
+wire jtdo2_mux;/* synthesis ER1_MARK="jtdo2" */ /* synthesis syn_keep=1 */
+wire spi_tdo2;
+wire shiftDr;/* synthesis ER1_MARK="jshift" */ /* synthesis syn_keep=1 */
+wire updateDr;/* synthesis ER1_MARK="jupdate" */ /* synthesis syn_keep=1 */
+wire enableEr1;/* synthesis ER1_MARK="jce1" */ /* synthesis syn_keep=1 */
+wire enableEr2;/* synthesis ER1_MARK="jce2" */ /* synthesis syn_keep=1 */
+wire [14:0] ipEnable;/* synthesis ER1_MARK="ip_enable" */ /* synthesis syn_keep=1 */
+wire controlDataN;/* synthesis ER1_MARK="control_datan" */ /* synthesis syn_keep=1 */
+wire lm32_isptracy_enable;/* synthesis ER1_MARK="isptracy_enable" */ /* synthesis syn_keep=1 */
+
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+generate
+ if (lat_family == "EC" || lat_family == "ECP" || lat_family == "XP") begin
+ JTAGB jtagb (.JTCK (jtck),
+ .JRTI1 (rtiER1),
+ .JRTI2 (rtiER2),
+ .JTDI (tdi),
+ .JSHIFT (shiftDr),
+ .JUPDATE (updateDr),
+ .JRSTN (jrstn),
+ .JCE1 (enableEr1),
+ .JCE2 (enableEr2),
+ .JTDO1 (tdoEr1),
+ .JTDO2 (jtdo2_mux)) /* synthesis ER1="ENABLED" */ /* synthesis ER2="ENABLED" */ /* synthesis JTAG_FLASH_PRGRM="DISABLED" */;
+ end else if (lat_family == "ECP2" || lat_family == "ECP2M") begin
+ JTAGC jtagc (.JTCK (jtck),
+ .JRTI1 (rtiER1),
+ .JRTI2 (rtiER2),
+ .JTDI (tdi),
+ .JSHIFT (shiftDr),
+ .JUPDATE (updateDr),
+ .JRSTN (jrstn),
+ .IJTAGEN (1'b1),
+ .JCE1 (enableEr1),
+ .JCE2 (enableEr2),
+ .JTDO1 (tdoEr1),
+ .JTDO2 (jtdo2_mux)) /* synthesis ER1="ENABLED" */ /* synthesis ER2="ENABLED" */ /* synthesis JTAG_FLASH_PRGRM="DISABLED" */;
+ end else if (lat_family == "SC" || lat_family == "SCM") begin // if (lat_family == "ECP2" || lat_family == "ECP2M")
+ JTAGA jtaga(.JTCK (jtck),
+ .JRTI1 (rtiER1),
+ .JRTI2 (rtiER2),
+ .JTDI (tdi),
+ .JSHIFT (shiftDr),
+ .JUPDATE (updateDr),
+ .JRSTN (jrstn),
+ .JCE1 (enableEr1),
+ .JCE2 (enableEr2),
+ .JTDO1 (tdoEr1),
+ .JTDO2 (jtdo2_mux)) /* synthesis ER1="ENABLED" */ /* synthesis ER2="ENABLED" */ /* synthesis JTAG_FLASH_PRGRM="DISABLED" */;
+ end
+endgenerate
+
+ER1 er1 (
+ .JTCK (jtck),
+ .JTDI (tdi),
+ .JTDO1 (tdoEr1),
+ .JTDO2 (jtdo2_mux),
+ .JSHIFT (shiftDr),
+ .JUPDATE (updateDr),
+ .JRSTN (jrstn),
+ .JCE1 (enableEr1),
+ .ER2_TDO ({13'b0,tdoEr2,spi_tdo2}),
+ .IP_ENABLE (ipEnable),
+ .ISPTRACY_ENABLE(lm32_isptracy_enable),
+ .ISPTRACY_ER2_TDO(lm32_isptracy_enable),
+ .CONTROL_DATAN (controlDataN));
+
+`ifdef INCLUDE_LM32
+jtag_lm32 jtag_lm32 (
+ .JTCK (jtck),
+ .JTDI (tdi),
+ .JTDO2 (tdoEr2),
+ .JSHIFT (shiftDr),
+ .JUPDATE (updateDr),
+ .JRSTN (jrstn),
+ .JCE2 (enableEr2),
+ .JTAGREG_ENABLE (ipEnable[1]),
+ .CONTROL_DATAN (controlDataN),
+ .REG_UPDATE (reg_update),
+ .REG_D (reg_d),
+ .REG_ADDR_D (reg_addr_d),
+ .REG_Q (reg_q),
+ .REG_ADDR_Q (reg_addr_q)
+ );
+`endif
+
+`ifdef INCLUDE_SPI
+SPIPROG spiprog_inst (
+ .JTCK (tck),
+ .JTDI (tdi),
+ .JTDO2 (spi_tdo2),
+ .JSHIFT (shiftDr),
+ .JUPDATE (updateDr),
+ .JRSTN (resetN),
+ .JCE2 (enableEr2),
+ .SPIPROG_ENABLE (ipEnable[0]),
+ .CONTROL_DATAN (controlDataN),
+ .SPI_C (spi_c),
+ .SPI_D (spi_d),
+ .SPI_SN (spi_sn),
+ .SPI_Q (spi_q)
+ );
+`endif
+
+endmodule
lm32/verilog/src/jtag_cores.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/typea.v
===================================================================
--- lm32/verilog/src/typea.v (nonexistent)
+++ lm32/verilog/src/typea.v (revision 17)
@@ -0,0 +1,74 @@
+/*-- ---------------------------------------------------------------------------
+--
+-- Name : TYPEA.v
+--
+-- Description:
+--
+-- This is one of the two types of cells that are used to create ER1/ER2
+-- register bits.
+--
+-- $Log: typea.vhd,v $
+-- Revision 1.2 2002-11-13 18:33:59-08 jhsin
+-- The SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 signals of the
+-- dedicate logic JTAG_PORT didn't act as what their names implied.
+-- The SHIFT_DR_CAPTURE_DR actually acts as SHIFT_DR.
+-- The ENABLE_ER1/2 actually acts as SHIFT_DR_CAPTURE_DR.
+-- These had caused a lot of headaches for a long time and now they are
+-- fixed by:
+-- (1) Use SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 to create
+-- CAPTURE_DR for all typeA, typeB bits in the ER1, ER2 registers.
+-- (2) Use ENABLE_ER1 or the enESR, enCSR, enBAR (these 3 signals
+-- have the same waveform of ENABLE_ER2) directly to be the CLKEN
+-- of all typeA, typeB bits in the ER1, ER2 registers.
+-- (3) Modify typea.vhd to use only UPDATE_DR signal for the clock enable
+-- of the holding flip-flop.
+-- These changes caused ispTracy.vhd and cge.dat changes and the new
+-- CGE.exe version will be 1.3.5.
+--
+-- Revision 1.1 2002-05-01 18:13:51-07 jhsin
+-- Added RCS version control header to file. No code changes.
+--
+-- $Header: \\\\hqfile2\\ipcores\\rcs\\hqfile2\\ipcores\\rcswork\\isptracy\\VHDL\\Implementation\\typea.vhd,v 1.2 2002-11-13 18:33:59-08 jhsin Exp $
+--
+-- Copyright (C) 2002 Lattice Semiconductor Corp. All rights reserved.
+--
+-- ---------------------------------------------------------------------------*/
+
+module TYPEA(
+ input CLK,
+ input RESET_N,
+ input CLKEN,
+ input TDI,
+ output TDO,
+ output reg DATA_OUT,
+ input DATA_IN,
+ input CAPTURE_DR,
+ input UPDATE_DR
+ );
+
+ reg tdoInt;
+
+
+ always @ (negedge CLK or negedge RESET_N)
+ begin
+ if (RESET_N == 1'b0)
+ tdoInt <= 1'b0;
+ else if (CLK == 1'b0)
+ if (CLKEN == 1'b1)
+ if (CAPTURE_DR == 1'b0)
+ tdoInt <= TDI;
+ else
+ tdoInt <= DATA_IN;
+ end
+
+ assign TDO = tdoInt;
+
+ always @ (negedge CLK or negedge RESET_N)
+ begin
+ if (RESET_N == 1'b0)
+ DATA_OUT <= 1'b0;
+ else if (CLK == 1'b0)
+ if (UPDATE_DR == 1'b1)
+ DATA_OUT <= tdoInt;
+ end
+endmodule
lm32/verilog/src/typea.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_debug.v
===================================================================
--- lm32/verilog/src/lm32_debug.v (nonexistent)
+++ lm32/verilog/src/lm32_debug.v (revision 17)
@@ -0,0 +1,340 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_debug.v
+// Title : Hardware debug registers and associated logic.
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+`ifdef CFG_DEBUG_ENABLED
+
+// States for single-step FSM
+`define LM32_DEBUG_SS_STATE_RNG 2:0
+`define LM32_DEBUG_SS_STATE_IDLE 3'b000
+`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001
+`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010
+`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011
+`define LM32_DEBUG_SS_STATE_RESTART 3'b100
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_debug (
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ pc_x,
+ load_x,
+ store_x,
+ load_store_address_x,
+ csr_write_enable_x,
+ csr_write_data,
+ csr_x,
+`ifdef CFG_HW_DEBUG_ENABLED
+ jtag_csr_write_enable,
+ jtag_csr_write_data,
+ jtag_csr,
+`endif
+`ifdef LM32_SINGLE_STEP_ENABLED
+ eret_q_x,
+ bret_q_x,
+ stall_x,
+ exception_x,
+ q_x,
+`ifdef CFG_DCACHE_ENABLED
+ dcache_refill_request,
+`endif
+`endif
+ // ----- Outputs -------
+`ifdef LM32_SINGLE_STEP_ENABLED
+ dc_ss,
+`endif
+ dc_re,
+ bp_match,
+ wp_match
+ );
+
+/////////////////////////////////////////////////////
+// Parameters
+/////////////////////////////////////////////////////
+
+parameter breakpoints = 0; // Number of breakpoint CSRs
+parameter watchpoints = 0; // Number of watchpoint CSRs
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+
+input [`LM32_PC_RNG] pc_x; // X stage PC
+input load_x; // Load instruction in X stage
+input store_x; // Store instruction in X stage
+input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address
+input csr_write_enable_x; // wcsr instruction in X stage
+input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR
+input [`LM32_CSR_RNG] csr_x; // Which CSR to write
+`ifdef CFG_HW_DEBUG_ENABLED
+input jtag_csr_write_enable; // JTAG interface CSR write enable
+input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR
+input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
+`endif
+`ifdef LM32_SINGLE_STEP_ENABLED
+input eret_q_x; // eret instruction in X stage
+input bret_q_x; // bret instruction in X stage
+input stall_x; // Instruction in X stage is stalled
+input exception_x; // An exception has occured in X stage
+input q_x; // Indicates the instruction in the X stage is qualified
+`ifdef CFG_DCACHE_ENABLED
+input dcache_refill_request; // Indicates data cache wants to be refilled
+`endif
+`endif
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+`ifdef LM32_SINGLE_STEP_ENABLED
+output dc_ss; // Single-step enable
+reg dc_ss;
+`endif
+output dc_re; // Remap exceptions
+reg dc_re;
+output bp_match; // Indicates a breakpoint has matched
+wire bp_match;
+output wp_match; // Indicates a watchpoint has matched
+wire wp_match;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+genvar i; // Loop index for generate statements
+
+// Debug CSRs
+
+reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address
+reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable
+wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched
+
+reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable
+reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address
+wire [0:watchpoints-1]wp_match_n; // Indicates if a h/w data watchpoint matched
+
+wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger)
+wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR
+wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to
+
+`ifdef LM32_SINGLE_STEP_ENABLED
+// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
+//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM
+integer state; // State of single-step FSM
+`endif
+
+/////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////
+`define INCLUDE_FUNCTION
+`include "lm32_functions.v"
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+// Check for breakpoints
+generate
+ for (i = 0; i < breakpoints; i = i + 1)
+ begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
+ end
+endgenerate
+generate
+`ifdef LM32_SINGLE_STEP_ENABLED
+ if (breakpoints > 0)
+assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
+ else
+assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
+`else
+ if (breakpoints > 0)
+assign bp_match = |bp_match_n;
+ else
+assign bp_match = `FALSE;
+`endif
+endgenerate
+
+// Check for watchpoints
+generate
+ for (i = 0; i < watchpoints; i = i + 1)
+ begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+ end
+endgenerate
+generate
+ if (watchpoints > 0)
+assign wp_match = |wp_match_n;
+ else
+assign wp_match = `FALSE;
+endgenerate
+
+`ifdef CFG_HW_DEBUG_ENABLED
+// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
+assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
+assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
+`else
+assign debug_csr_write_enable = csr_write_enable_x;
+assign debug_csr_write_data = csr_write_data;
+assign debug_csr = csr_x;
+`endif
+
+/////////////////////////////////////////////////////
+// Sequential Logic
+/////////////////////////////////////////////////////
+
+// Breakpoint address and enable CSRs
+generate
+ for (i = 0; i < breakpoints; i = i + 1)
+ begin : bp_seq
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
+ bp_e[i] <= `FALSE;
+ end
+ else
+ begin
+ if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
+ begin
+ bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
+ bp_e[i] <= debug_csr_write_data[0];
+ end
+ end
+end
+ end
+endgenerate
+
+// Watchpoint address and control flags CSRs
+generate
+ for (i = 0; i < watchpoints; i = i + 1)
+ begin : wp_seq
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
+ wpc_c[i] <= `LM32_WPC_C_DISABLED;
+ end
+ else
+ begin
+ if (debug_csr_write_enable == `TRUE)
+ begin
+ if (debug_csr == `LM32_CSR_DC)
+ wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+ if (debug_csr == `LM32_CSR_WP0 + i)
+ wp[i] <= debug_csr_write_data;
+ end
+ end
+end
+ end
+endgenerate
+
+// Remap exceptions control bit
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ dc_re <= `FALSE;
+ else
+ begin
+ if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
+ dc_re <= debug_csr_write_data[1];
+ end
+end
+
+`ifdef LM32_SINGLE_STEP_ENABLED
+// Single-step control flag
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ state <= `LM32_DEBUG_SS_STATE_IDLE;
+ dc_ss <= `FALSE;
+ end
+ else
+ begin
+ if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
+ begin
+ dc_ss <= debug_csr_write_data[0];
+ if (debug_csr_write_data[0] == `FALSE)
+ state <= `LM32_DEBUG_SS_STATE_IDLE;
+ else
+ state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
+ end
+ case (state)
+ `LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
+ begin
+ // Wait for eret or bret instruction to be executed
+ if ( ( (eret_q_x == `TRUE)
+ || (bret_q_x == `TRUE)
+ )
+ && (stall_x == `FALSE)
+ )
+ state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
+ end
+ `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
+ begin
+ // Wait for an instruction to be executed
+ if ((q_x == `TRUE) && (stall_x == `FALSE))
+ state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
+ end
+ `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
+ begin
+ // Wait for exception to be raised
+`ifdef CFG_DCACHE_ENABLED
+ if (dcache_refill_request == `TRUE)
+ state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
+ else
+`endif
+ if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
+ begin
+ dc_ss <= `FALSE;
+ state <= `LM32_DEBUG_SS_STATE_RESTART;
+ end
+ end
+ `LM32_DEBUG_SS_STATE_RESTART:
+ begin
+ // Watch to see if stepped instruction is restarted due to a cache miss
+`ifdef CFG_DCACHE_ENABLED
+ if (dcache_refill_request == `TRUE)
+ state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
+ else
+`endif
+ state <= `LM32_DEBUG_SS_STATE_IDLE;
+ end
+ endcase
+ end
+end
+`endif
+
+endmodule
+
+`endif
lm32/verilog/src/lm32_debug.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/typeb.v
===================================================================
--- lm32/verilog/src/typeb.v (nonexistent)
+++ lm32/verilog/src/typeb.v (revision 17)
@@ -0,0 +1,50 @@
+/*-- ---------------------------------------------------------------------------
+--
+-- Name : TYPEB.vhd
+--
+-- Description:
+--
+-- This is one of the two types of cells that are used to create ER1/ER2
+-- register bits.
+--
+-- $Log: typeb.vhd,v $
+-- Revision 1.2 2002-08-01 16:39:33-07 jhsin
+-- Modified typeb module to remove redundant DATA_OUT port.
+--
+-- Revision 1.1 2002-05-01 18:13:51-07 jhsin
+-- Added RCS version control header to file. No code changes.
+--
+-- $Header: \\\\hqfile2\\ipcores\\rcs\\hqfile2\\ipcores\\rcswork\\isptracy\\VHDL\\Implementation\\typeb.vhd,v 1.2 2002-08-01 16:39:33-07 jhsin Exp $
+--
+-- Copyright (C) 2002 Lattice Semiconductor Corp. All rights reserved.
+--
+-- ---------------------------------------------------------------------------*/
+module TYPEB
+ (
+ input CLK,
+ input RESET_N,
+ input CLKEN,
+ input TDI,
+ output TDO,
+ input DATA_IN,
+ input CAPTURE_DR
+ );
+
+ reg tdoInt;
+
+ always @ (negedge CLK or negedge RESET_N)
+ begin
+ if (RESET_N== 1'b0)
+ tdoInt <= 1'b0;
+ else if (CLK == 1'b0)
+ if (CLKEN==1'b1)
+ if (CAPTURE_DR==1'b0)
+ tdoInt <= TDI;
+ else
+ tdoInt <= DATA_IN;
+ end
+
+ assign TDO = tdoInt;
+
+endmodule
+
lm32/verilog/src/typeb.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_monitor_ram.v
===================================================================
--- lm32/verilog/src/lm32_monitor_ram.v (nonexistent)
+++ lm32/verilog/src/lm32_monitor_ram.v (revision 17)
@@ -0,0 +1,1397 @@
+`include "system_conf.v"
+
+`timescale 1 ns / 1 ps
+module lm32_monitor_ram (DataInA, DataInB, AddressA, AddressB, ClockA,
+ ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB, QA, QB);
+ input [31:0] DataInA;
+ input [31:0] DataInB;
+ input [8:0] AddressA;
+ input [8:0] AddressB;
+ input ClockA;
+ input ClockB;
+ input ClockEnA;
+ input ClockEnB;
+ input WrA;
+ input WrB;
+ input ResetA;
+ input ResetB;
+ output [31:0] QA;
+ output [31:0] QB;
+
+ parameter lat_family = `LATTICE_FAMILY;
+
+ generate
+ if (lat_family == "EC" || lat_family == "ECP" || lat_family == "XP") begin
+ /* Verilog netlist generated by SCUBA ispLever_v51_SP2_Build (10) */
+ /* Module Version: 2.0 */
+ /* c:\applications\ispTools5.1\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5g00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr ENABLED -writemode NORMAL -resetmode ASYNC -memfile ../../source/jtag_rom_monitor/rom.mem -memformat hex */
+
+ // synopsys translate_off
+ defparam lm32_monitor_ram_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_17 = 320'h00000000000000000000000000000000000000003FF8C300003FF8E300003FF90300003FF923FF5B;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_16 = 320'h1004F3FF95300003FF97300003FF99300003FF9B300003FF9D300003FF9F300003FFA1300003FFFB;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_15 = 320'h0000130001100003FF691001400000068003FF7E058003FF803FFFB300013FF7800001100001FFB3;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_14 = 320'h00000068003FF89058003FF8B3FFB93FF9B008003FFBC300000FFBE1001B000331001A0002C10019;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_13 = 320'h00035100180003510013000301001200030100110003010010000301000900030100080003010007;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_12 = 320'h010003FF97058003FFAA3FFFC00800078003FFDB3FFBD0080000004100063FFA2000000001C10004;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_11 = 320'h000083000C2001010014000183001C0000000000000001000000000000000000010000100010FFF3;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_10 = 320'h10063000481004D0003F1006D0003E1007200024100570001D10077010003FFC210000100540FFFF;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_0F = 320'h0080010000100540FFFF008000700010004000083000C2001010014000183001C0FFE40000000008;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_0E = 320'h100043FFDD100083FFDF100093FFE11000A3FFE31000B10008100040FFF8000000000C1000410008;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_0D = 320'h100083FFE7100093FFE91000A3FFEB1000B3FFED100040FFF400000200000FFFF010000000000002;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_0C = 320'h10054100000FFFF01000100FF00000100FF000000FFFE10100010000000000070300803000030090;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_0B = 320'h300003008C300003008820078100743006C2006810064000603005C2005810054000503004C20048;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_0A = 320'h10044000403003C2003810034000303002C2002810024000203001C2001810014000103000C20008;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_09 = 320'h100040000000070200802000020090200002008C20000200883007C100743006C200681006400060;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_08 = 320'h3005C2005810054000503004C2004810044000403003C2003810034000303002C200281002400020;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_07 = 320'h3001C2001810014000103000C2000810004000001F9940E000000001007410000100841000110001;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_06 = 320'h100011000110001100FF1F99410090008001008C0080010088008003007C20078000703006C20068;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_05 = 320'h10064000603005C2005810054000503004C2004810044000403003C2003810034000303002C20028;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_04 = 320'h10024000203001C2001810014000103000C200081000400000000001066C3FFC530000007F40E000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_03 = 320'h000000003B000B500800200800000A00000000000000000043000BD0080020080000120000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_02 = 320'h000000004B000C500800200800001A00000000000000000053000CD0080020080000220000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_01 = 320'h0000000081000D500800300800002A00000000000000000063000DD0080020080000320000000000;
+ defparam lm32_monitor_ram_0_0_1.INITVAL_00 = 320'h0000000091000E500800300800003A00000000000000000000000000000000000000000003F00000;
+ defparam lm32_monitor_ram_0_0_1.CSDECODE_B = "000";
+ defparam lm32_monitor_ram_0_0_1.CSDECODE_A = "000";
+ defparam lm32_monitor_ram_0_0_1.WRITEMODE_B = "NORMAL";
+ defparam lm32_monitor_ram_0_0_1.WRITEMODE_A = "NORMAL";
+ defparam lm32_monitor_ram_0_0_1.GSR = "ENABLED";
+ defparam lm32_monitor_ram_0_0_1.RESETMODE = "ASYNC";
+ defparam lm32_monitor_ram_0_0_1.REGMODE_B = "NOREG";
+ defparam lm32_monitor_ram_0_0_1.REGMODE_A = "NOREG";
+ defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_B = 18;
+ defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_A = 18;
+ // synopsys translate_on
+ DP8KA lm32_monitor_ram_0_0_1 (.CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA),
+ .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA),
+ .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo),
+ .CSB2(scuba_vlo), .RSTB(ResetB), .DIA0(DataInA[0]), .DIA1(DataInA[1]),
+ .DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]),
+ .DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]),
+ .DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]),
+ .DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]),
+ .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
+ .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
+ .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
+ .ADA12(AddressA[8]), .DIB0(DataInB[0]), .DIB1(DataInB[1]), .DIB2(DataInB[2]),
+ .DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]), .DIB6(DataInB[6]),
+ .DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]), .DIB10(DataInB[10]),
+ .DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]), .DIB14(DataInB[14]),
+ .DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]), .ADB0(scuba_vhi),
+ .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]),
+ .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]),
+ .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]),
+ .DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]), .DOA4(QA[4]),
+ .DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]), .DOA9(QA[9]),
+ .DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]),
+ .DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]),
+ .DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]),
+ .DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]),
+ .DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]),
+ .DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17]))
+ /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_19="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_18="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_17="0x00000000000000000000000000000000000000003FF8C300003FF8E300003FF90300003FF923FF5B" */
+ /* synthesis INITVAL_16="0x1004F3FF95300003FF97300003FF99300003FF9B300003FF9D300003FF9F300003FFA1300003FFFB" */
+ /* synthesis INITVAL_15="0x0000130001100003FF691001400000068003FF7E058003FF803FFFB300013FF7800001100001FFB3" */
+ /* synthesis INITVAL_14="0x00000068003FF89058003FF8B3FFB93FF9B008003FFBC300000FFBE1001B000331001A0002C10019" */
+ /* synthesis INITVAL_13="0x00035100180003510013000301001200030100110003010010000301000900030100080003010007" */
+ /* synthesis INITVAL_12="0x010003FF97058003FFAA3FFFC00800078003FFDB3FFBD0080000004100063FFA2000000001C10004" */
+ /* synthesis INITVAL_11="0x000083000C2001010014000183001C0000000000000001000000000000000000010000100010FFF3" */
+ /* synthesis INITVAL_10="0x10063000481004D0003F1006D0003E1007200024100570001D10077010003FFC210000100540FFFF" */
+ /* synthesis INITVAL_0F="0x0080010000100540FFFF008000700010004000083000C2001010014000183001C0FFE40000000008" */
+ /* synthesis INITVAL_0E="0x100043FFDD100083FFDF100093FFE11000A3FFE31000B10008100040FFF8000000000C1000410008" */
+ /* synthesis INITVAL_0D="0x100083FFE7100093FFE91000A3FFEB1000B3FFED100040FFF400000200000FFFF010000000000002" */
+ /* synthesis INITVAL_0C="0x10054100000FFFF01000100FF00000100FF000000FFFE10100010000000000070300803000030090" */
+ /* synthesis INITVAL_0B="0x300003008C300003008820078100743006C2006810064000603005C2005810054000503004C20048" */
+ /* synthesis INITVAL_0A="0x10044000403003C2003810034000303002C2002810024000203001C2001810014000103000C20008" */
+ /* synthesis INITVAL_09="0x100040000000070200802000020090200002008C20000200883007C100743006C200681006400060" */
+ /* synthesis INITVAL_08="0x3005C2005810054000503004C2004810044000403003C2003810034000303002C200281002400020" */
+ /* synthesis INITVAL_07="0x3001C2001810014000103000C2000810004000001F9940E000000001007410000100841000110001" */
+ /* synthesis INITVAL_06="0x100011000110001100FF1F99410090008001008C0080010088008003007C20078000703006C20068" */
+ /* synthesis INITVAL_05="0x10064000603005C2005810054000503004C2004810044000403003C2003810034000303002C20028" */
+ /* synthesis INITVAL_04="0x10024000203001C2001810014000103000C200081000400000000001066C3FFC530000007F40E000" */
+ /* synthesis INITVAL_03="0x000000003B000B500800200800000A00000000000000000043000BD0080020080000120000000000" */
+ /* synthesis INITVAL_02="0x000000004B000C500800200800001A00000000000000000053000CD0080020080000220000000000" */
+ /* synthesis INITVAL_01="0x0000000081000D500800300800002A00000000000000000063000DD0080020080000320000000000" */
+ /* synthesis INITVAL_00="0x0000000091000E500800300800003A00000000000000000000000000000000000000000003F00000" */
+ /* synthesis CSDECODE_B="000" */
+ /* synthesis CSDECODE_A="000" */
+ /* synthesis WRITEMODE_B="NORMAL" */
+ /* synthesis WRITEMODE_A="NORMAL" */
+ /* synthesis GSR="ENABLED" */
+ /* synthesis RESETMODE="ASYNC" */
+ /* synthesis REGMODE_B="NOREG" */
+ /* synthesis REGMODE_A="NOREG" */
+ /* synthesis DATA_WIDTH_B="18" */
+ /* synthesis DATA_WIDTH_A="18" */;
+
+ VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ // synopsys translate_off
+ defparam lm32_monitor_ram_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_17 = 320'h0000000000000000000000000000000000000000038FF034D2038FF034C2038FF0349A038FF03EFF;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_16 = 320'h00D00038FF034CA038FF03492038FF0348A038FF03482038FF0344A038FF03442038FF0343A038FF;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_15 = 320'h00D6300D5A00C5803EFF0136300D0302E0803EFF02E0803EFF038FF00D5A03EFF00D630105801363;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_14 = 320'h00D0302E0803EFF02E0803EFF038FF03EFF02E70038FF034DA0170801F100110801F100110801F10;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_13 = 320'h0110801F100110801F100110801F100110801F100110801F100110801F100110801F100110801F08;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_12 = 320'h02E0803EFF02E0803EFF038FF02E7802430038FF03EFF02E780110801F0803EFF030E800DE700AE7;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_11 = 320'h00AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D000341800D0001708;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_10 = 320'h01F100110801F100110801F100110801F100110801F100110801F0802E0803EFF0347000D0001708;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_0F = 320'h024700347000D00017080247002E08016E7016E4016E3016E3016E3016E3016E200DE7030E800DE7;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_0E = 320'h00AE703EFF010E003EFF010E003EFF010E003EFF010E0016E0016E700DE7030E800DE700AE700AE0;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_0D = 320'h00CE003EFF00CE003EFF00CE003EFF00CE003EFF016E700DE7030E8034700171002470030E801108;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_0C = 320'h01F0803470017100247000808030E80081003478011080081002478030F800AE700AE70340700AE7;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_0B = 320'h0344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE500AE400AE4;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_0A = 320'h00AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE100AE000AE0;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_09 = 320'h00AE0030F000AE700AE70340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE6;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_08 = 320'h00AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE2;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_07 = 320'h00AE100AE100AE100AE100AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E80000800008;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_06 = 320'h0000800008000080080800DE8016E802400016E802448016E802438016EF016EF016EF016EE016EE;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_03 = 320'h00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_02 = 320'h00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_01 = 320'h00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600;
+ defparam lm32_monitor_ram_0_1_0.INITVAL_00 = 320'h00D000380003E0002EE0016E703E0002EE80260000D0000D0000D0000D0000D0000D0003E0002600;
+ defparam lm32_monitor_ram_0_1_0.CSDECODE_B = "000";
+ defparam lm32_monitor_ram_0_1_0.CSDECODE_A = "000";
+ defparam lm32_monitor_ram_0_1_0.WRITEMODE_B = "NORMAL";
+ defparam lm32_monitor_ram_0_1_0.WRITEMODE_A = "NORMAL";
+ defparam lm32_monitor_ram_0_1_0.GSR = "ENABLED";
+ defparam lm32_monitor_ram_0_1_0.RESETMODE = "ASYNC";
+ defparam lm32_monitor_ram_0_1_0.REGMODE_B = "NOREG";
+ defparam lm32_monitor_ram_0_1_0.REGMODE_A = "NOREG";
+ defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_B = 18;
+ defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_A = 18;
+ // synopsys translate_on
+ DP8KA lm32_monitor_ram_0_1_0 (.CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA),
+ .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA),
+ .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo),
+ .CSB2(scuba_vlo), .RSTB(ResetB), .DIA0(DataInA[18]), .DIA1(DataInA[19]),
+ .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]),
+ .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]),
+ .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]),
+ .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo),
+ .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
+ .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
+ .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
+ .ADA12(AddressA[8]), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]),
+ .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]),
+ .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]),
+ .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo),
+ .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi),
+ .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]),
+ .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]),
+ .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]),
+ .DOA0(QA[18]), .DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]),
+ .DOA5(QA[23]), .DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]),
+ .DOA10(QA[28]), .DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]),
+ .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]),
+ .DOB2(QB[20]), .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]),
+ .DOB7(QB[25]), .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]),
+ .DOB12(QB[30]), .DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17())
+ /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_19="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_18="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_17="0x0000000000000000000000000000000000000000038FF034D2038FF034C2038FF0349A038FF03EFF" */
+ /* synthesis INITVAL_16="0x00D00038FF034CA038FF03492038FF0348A038FF03482038FF0344A038FF03442038FF0343A038FF" */
+ /* synthesis INITVAL_15="0x00D6300D5A00C5803EFF0136300D0302E0803EFF02E0803EFF038FF00D5A03EFF00D630105801363" */
+ /* synthesis INITVAL_14="0x00D0302E0803EFF02E0803EFF038FF03EFF02E70038FF034DA0170801F100110801F100110801F10" */
+ /* synthesis INITVAL_13="0x0110801F100110801F100110801F100110801F100110801F100110801F100110801F100110801F08" */
+ /* synthesis INITVAL_12="0x02E0803EFF02E0803EFF038FF02E7802430038FF03EFF02E780110801F0803EFF030E800DE700AE7" */
+ /* synthesis INITVAL_11="0x00AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D000341800D0001708" */
+ /* synthesis INITVAL_10="0x01F100110801F100110801F100110801F100110801F100110801F0802E0803EFF0347000D0001708" */
+ /* synthesis INITVAL_0F="0x024700347000D00017080247002E08016E7016E4016E3016E3016E3016E3016E200DE7030E800DE7" */
+ /* synthesis INITVAL_0E="0x00AE703EFF010E003EFF010E003EFF010E003EFF010E0016E0016E700DE7030E800DE700AE700AE0" */
+ /* synthesis INITVAL_0D="0x00CE003EFF00CE003EFF00CE003EFF00CE003EFF016E700DE7030E8034700171002470030E801108" */
+ /* synthesis INITVAL_0C="0x01F0803470017100247000808030E80081003478011080081002478030F800AE700AE70340700AE7" */
+ /* synthesis INITVAL_0B="0x0344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE500AE400AE4" */
+ /* synthesis INITVAL_0A="0x00AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE100AE000AE0" */
+ /* synthesis INITVAL_09="0x00AE0030F000AE700AE70340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE6" */
+ /* synthesis INITVAL_08="0x00AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE2" */
+ /* synthesis INITVAL_07="0x00AE100AE100AE100AE100AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E80000800008" */
+ /* synthesis INITVAL_06="0x0000800008000080080800DE8016E802400016E802448016E802438016EF016EF016EF016EE016EE" */
+ /* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */
+ /* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */
+ /* synthesis INITVAL_03="0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600" */
+ /* synthesis INITVAL_02="0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600" */
+ /* synthesis INITVAL_01="0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600" */
+ /* synthesis INITVAL_00="0x00D000380003E0002EE0016E703E0002EE80260000D0000D0000D0000D0000D0000D0003E0002600" */
+ /* synthesis CSDECODE_B="000" */
+ /* synthesis CSDECODE_A="000" */
+ /* synthesis WRITEMODE_B="NORMAL" */
+ /* synthesis WRITEMODE_A="NORMAL" */
+ /* synthesis GSR="ENABLED" */
+ /* synthesis RESETMODE="ASYNC" */
+ /* synthesis REGMODE_B="NOREG" */
+ /* synthesis REGMODE_A="NOREG" */
+ /* synthesis DATA_WIDTH_B="18" */
+ /* synthesis DATA_WIDTH_A="18" */;
+
+
+
+ // exemplar begin
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_19 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_18 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_17 0x00000000000000000000000000000000000000003FF8C300003FF8E300003FF90300003FF923FF5B
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_16 0x1004F3FF95300003FF97300003FF99300003FF9B300003FF9D300003FF9F300003FFA1300003FFFB
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_15 0x0000130001100003FF691001400000068003FF7E058003FF803FFFB300013FF7800001100001FFB3
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_14 0x00000068003FF89058003FF8B3FFB93FF9B008003FFBC300000FFBE1001B000331001A0002C10019
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_13 0x00035100180003510013000301001200030100110003010010000301000900030100080003010007
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_12 0x010003FF97058003FFAA3FFFC00800078003FFDB3FFBD0080000004100063FFA2000000001C10004
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_11 0x000083000C2001010014000183001C0000000000000001000000000000000000010000100010FFF3
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_10 0x10063000481004D0003F1006D0003E1007200024100570001D10077010003FFC210000100540FFFF
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0F 0x0080010000100540FFFF008000700010004000083000C2001010014000183001C0FFE40000000008
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0E 0x100043FFDD100083FFDF100093FFE11000A3FFE31000B10008100040FFF8000000000C1000410008
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0D 0x100083FFE7100093FFE91000A3FFEB1000B3FFED100040FFF400000200000FFFF010000000000002
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0C 0x10054100000FFFF01000100FF00000100FF000000FFFE10100010000000000070300803000030090
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0B 0x300003008C300003008820078100743006C2006810064000603005C2005810054000503004C20048
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0A 0x10044000403003C2003810034000303002C2002810024000203001C2001810014000103000C20008
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_09 0x100040000000070200802000020090200002008C20000200883007C100743006C200681006400060
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_08 0x3005C2005810054000503004C2004810044000403003C2003810034000303002C200281002400020
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_07 0x3001C2001810014000103000C2000810004000001F9940E000000001007410000100841000110001
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_06 0x100011000110001100FF1F99410090008001008C0080010088008003007C20078000703006C20068
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_05 0x10064000603005C2005810054000503004C2004810044000403003C2003810034000303002C20028
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_04 0x10024000203001C2001810014000103000C200081000400000000001066C3FFC530000007F40E000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_03 0x000000003B000B500800200800000A00000000000000000043000BD0080020080000120000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_02 0x000000004B000C500800200800001A00000000000000000053000CD0080020080000220000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_01 0x0000000081000D500800300800002A00000000000000000063000DD0080020080000320000000000
+ // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_00 0x0000000091000E500800300800003A00000000000000000000000000000000000000000003F00000
+ // exemplar attribute lm32_monitor_ram_0_0_1 CSDECODE_B 000
+ // exemplar attribute lm32_monitor_ram_0_0_1 CSDECODE_A 000
+ // exemplar attribute lm32_monitor_ram_0_0_1 WRITEMODE_B NORMAL
+ // exemplar attribute lm32_monitor_ram_0_0_1 WRITEMODE_A NORMAL
+ // exemplar attribute lm32_monitor_ram_0_0_1 GSR ENABLED
+ // exemplar attribute lm32_monitor_ram_0_0_1 RESETMODE ASYNC
+ // exemplar attribute lm32_monitor_ram_0_0_1 REGMODE_B NOREG
+ // exemplar attribute lm32_monitor_ram_0_0_1 REGMODE_A NOREG
+ // exemplar attribute lm32_monitor_ram_0_0_1 DATA_WIDTH_B 18
+ // exemplar attribute lm32_monitor_ram_0_0_1 DATA_WIDTH_A 18
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_19 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_18 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_17 0x0000000000000000000000000000000000000000038FF034D2038FF034C2038FF0349A038FF03EFF
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_16 0x00D00038FF034CA038FF03492038FF0348A038FF03482038FF0344A038FF03442038FF0343A038FF
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_15 0x00D6300D5A00C5803EFF0136300D0302E0803EFF02E0803EFF038FF00D5A03EFF00D630105801363
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_14 0x00D0302E0803EFF02E0803EFF038FF03EFF02E70038FF034DA0170801F100110801F100110801F10
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_13 0x0110801F100110801F100110801F100110801F100110801F100110801F100110801F100110801F08
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_12 0x02E0803EFF02E0803EFF038FF02E7802430038FF03EFF02E780110801F0803EFF030E800DE700AE7
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_11 0x00AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D000341800D0001708
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_10 0x01F100110801F100110801F100110801F100110801F100110801F0802E0803EFF0347000D0001708
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0F 0x024700347000D00017080247002E08016E7016E4016E3016E3016E3016E3016E200DE7030E800DE7
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0E 0x00AE703EFF010E003EFF010E003EFF010E003EFF010E0016E0016E700DE7030E800DE700AE700AE0
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0D 0x00CE003EFF00CE003EFF00CE003EFF00CE003EFF016E700DE7030E8034700171002470030E801108
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0C 0x01F0803470017100247000808030E80081003478011080081002478030F800AE700AE70340700AE7
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0B 0x0344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE500AE400AE4
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0A 0x00AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE100AE000AE0
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_09 0x00AE0030F000AE700AE70340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE6
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_08 0x00AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE2
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_07 0x00AE100AE100AE100AE100AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E80000800008
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_06 0x0000800008000080080800DE8016E802400016E802448016E802438016EF016EF016EF016EE016EE
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_03 0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_02 0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_01 0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600
+ // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_00 0x00D000380003E0002EE0016E703E0002EE80260000D0000D0000D0000D0000D0000D0003E0002600
+ // exemplar attribute lm32_monitor_ram_0_1_0 CSDECODE_B 000
+ // exemplar attribute lm32_monitor_ram_0_1_0 CSDECODE_A 000
+ // exemplar attribute lm32_monitor_ram_0_1_0 WRITEMODE_B NORMAL
+ // exemplar attribute lm32_monitor_ram_0_1_0 WRITEMODE_A NORMAL
+ // exemplar attribute lm32_monitor_ram_0_1_0 GSR ENABLED
+ // exemplar attribute lm32_monitor_ram_0_1_0 RESETMODE ASYNC
+ // exemplar attribute lm32_monitor_ram_0_1_0 REGMODE_B NOREG
+ // exemplar attribute lm32_monitor_ram_0_1_0 REGMODE_A NOREG
+ // exemplar attribute lm32_monitor_ram_0_1_0 DATA_WIDTH_B 18
+ // exemplar attribute lm32_monitor_ram_0_1_0 DATA_WIDTH_A 18
+ // exemplar end
+ end else if (lat_family == "ECP2" || lat_family == "ECP2M") begin
+ /* Verilog netlist generated by SCUBA ispLever_v60_PROD_Build (36) */
+ /* Module Version: 3.0 */
+ /* c:\ispTOOLS6_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5a00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr ENABLED -writemode NORMAL -resetmode ASYNC -memfile ./rom.mem -memformat hex -e -n lm32_monitor_ram_ecp2 */
+ // synopsys translate_off
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_17 = 320'h00000000000000000000000000000000000000003FF8C300003FF8E300003FF90300003FF923FF5B ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_16 = 320'h1004F3FF95300003FF97300003FF99300003FF9B300003FF9D300003FF9F300003FFA1300003FFFB ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_15 = 320'h0000130001100003FF691001400000068003FF7E058003FF803FFFB300013FF7800001100001FFB3 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_14 = 320'h00000068003FF89058003FF8B3FFB93FF9B008003FFBC300000FFBE1001B000331001A0002C10019 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_13 = 320'h00035100180003510013000301001200030100110003010010000301000900030100080003010007 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_12 = 320'h010003FF97058003FFAA3FFFC00800078003FFDB3FFBD0080000004100063FFA2000000001C10004 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_11 = 320'h000083000C2001010014000183001C0000000000000001000000000000000000010000100010FFF3 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_10 = 320'h10063000481004D0003F1006D0003E1007200024100570001D10077010003FFC210000100540FFFF ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0F = 320'h0080010000100540FFFF008000700010004000083000C2001010014000183001C0FFE40000000008 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0E = 320'h100043FFDD100083FFDF100093FFE11000A3FFE31000B10008100040FFF8000000000C1000410008 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0D = 320'h100083FFE7100093FFE91000A3FFEB1000B3FFED100040FFF400000200000FFFF010000000000002 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0C = 320'h10054100000FFFF01000100FF00000100FF000000FFFE10100010000000000070300803000030090 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0B = 320'h300003008C300003008820078100743006C2006810064000603005C2005810054000503004C20048 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0A = 320'h10044000403003C2003810034000303002C2002810024000203001C2001810014000103000C20008 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_09 = 320'h100040000000070200802000020090200002008C20000200883007C100743006C200681006400060 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_08 = 320'h3005C2005810054000503004C2004810044000403003C2003810034000303002C200281002400020 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_07 = 320'h3001C2001810014000103000C2000810004000001F9940E000000001007410000100841000110001 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_06 = 320'h100011000110001100FF1F99410090008001008C0080010088008003007C20078000703006C20068 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_05 = 320'h10064000603005C2005810054000503004C2004810044000403003C2003810034000303002C20028 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_04 = 320'h10024000203001C2001810014000103000C200081000400000000001066C3FFC530000007F40E000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_03 = 320'h000000003B000B500800200800000A00000000000000000043000BD0080020080000120000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_02 = 320'h000000004B000C500800200800001A00000000000000000053000CD0080020080000220000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_01 = 320'h0000000081000D500800300800002A00000000000000000063000DD0080020080000320000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_00 = 320'h0000000091000E500800300800003A00000000000000000000000000000000000000000003F00000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.CSDECODE_B = 3'b000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.CSDECODE_A = 3'b000 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.WRITEMODE_B = "NORMAL" ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.WRITEMODE_A = "NORMAL" ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.GSR = "ENABLED" ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.RESETMODE = "ASYNC" ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.REGMODE_B = "NOREG" ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.REGMODE_A = "NOREG" ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.DATA_WIDTH_B = 18 ;
+ defparam lm32_monitor_ram_ecp2_0_0_1.DATA_WIDTH_A = 18 ;
+ // synopsys translate_on
+ DP16KB lm32_monitor_ram_ecp2_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]),
+ .DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]),
+ .DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]),
+ .DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]),
+ .DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]),
+ .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
+ .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
+ .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
+ .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA),
+ .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo),
+ .RSTA(ResetA), .DIB0(DataInB[0]), .DIB1(DataInB[1]), .DIB2(DataInB[2]),
+ .DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]), .DIB6(DataInB[6]),
+ .DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]), .DIB10(DataInB[10]),
+ .DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]), .DIB14(DataInB[14]),
+ .DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]), .ADB0(scuba_vhi),
+ .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]),
+ .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]),
+ .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]),
+ .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo),
+ .CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[0]),
+ .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]), .DOA4(QA[4]), .DOA5(QA[5]),
+ .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]), .DOA9(QA[9]), .DOA10(QA[10]),
+ .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]), .DOA14(QA[14]),
+ .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]), .DOB0(QB[0]), .DOB1(QB[1]),
+ .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]), .DOB5(QB[5]), .DOB6(QB[6]),
+ .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]), .DOB10(QB[10]), .DOB11(QB[11]),
+ .DOB12(QB[12]), .DOB13(QB[13]), .DOB14(QB[14]), .DOB15(QB[15]),
+ .DOB16(QB[16]), .DOB17(QB[17]))
+ /* synthesis MEM_LPC_FILE="lm32_monitor_ram_ecp2.lpc" */
+ /* synthesis MEM_INIT_FILE="rom.mem" */
+ /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_19="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_18="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_17="0x00000000000000000000000000000000000000003FF8C300003FF8E300003FF90300003FF923FF5B" */
+ /* synthesis INITVAL_16="0x1004F3FF95300003FF97300003FF99300003FF9B300003FF9D300003FF9F300003FFA1300003FFFB" */
+ /* synthesis INITVAL_15="0x0000130001100003FF691001400000068003FF7E058003FF803FFFB300013FF7800001100001FFB3" */
+ /* synthesis INITVAL_14="0x00000068003FF89058003FF8B3FFB93FF9B008003FFBC300000FFBE1001B000331001A0002C10019" */
+ /* synthesis INITVAL_13="0x00035100180003510013000301001200030100110003010010000301000900030100080003010007" */
+ /* synthesis INITVAL_12="0x010003FF97058003FFAA3FFFC00800078003FFDB3FFBD0080000004100063FFA2000000001C10004" */
+ /* synthesis INITVAL_11="0x000083000C2001010014000183001C0000000000000001000000000000000000010000100010FFF3" */
+ /* synthesis INITVAL_10="0x10063000481004D0003F1006D0003E1007200024100570001D10077010003FFC210000100540FFFF" */
+ /* synthesis INITVAL_0F="0x0080010000100540FFFF008000700010004000083000C2001010014000183001C0FFE40000000008" */
+ /* synthesis INITVAL_0E="0x100043FFDD100083FFDF100093FFE11000A3FFE31000B10008100040FFF8000000000C1000410008" */
+ /* synthesis INITVAL_0D="0x100083FFE7100093FFE91000A3FFEB1000B3FFED100040FFF400000200000FFFF010000000000002" */
+ /* synthesis INITVAL_0C="0x10054100000FFFF01000100FF00000100FF000000FFFE10100010000000000070300803000030090" */
+ /* synthesis INITVAL_0B="0x300003008C300003008820078100743006C2006810064000603005C2005810054000503004C20048" */
+ /* synthesis INITVAL_0A="0x10044000403003C2003810034000303002C2002810024000203001C2001810014000103000C20008" */
+ /* synthesis INITVAL_09="0x100040000000070200802000020090200002008C20000200883007C100743006C200681006400060" */
+ /* synthesis INITVAL_08="0x3005C2005810054000503004C2004810044000403003C2003810034000303002C200281002400020" */
+ /* synthesis INITVAL_07="0x3001C2001810014000103000C2000810004000001F9940E000000001007410000100841000110001" */
+ /* synthesis INITVAL_06="0x100011000110001100FF1F99410090008001008C0080010088008003007C20078000703006C20068" */
+ /* synthesis INITVAL_05="0x10064000603005C2005810054000503004C2004810044000403003C2003810034000303002C20028" */
+ /* synthesis INITVAL_04="0x10024000203001C2001810014000103000C200081000400000000001066C3FFC530000007F40E000" */
+ /* synthesis INITVAL_03="0x000000003B000B500800200800000A00000000000000000043000BD0080020080000120000000000" */
+ /* synthesis INITVAL_02="0x000000004B000C500800200800001A00000000000000000053000CD0080020080000220000000000" */
+ /* synthesis INITVAL_01="0x0000000081000D500800300800002A00000000000000000063000DD0080020080000320000000000" */
+ /* synthesis INITVAL_00="0x0000000091000E500800300800003A00000000000000000000000000000000000000000003F00000" */
+ /* synthesis CSDECODE_B="0b000" */
+ /* synthesis CSDECODE_A="0b000" */
+ /* synthesis WRITEMODE_B="NORMAL" */
+ /* synthesis WRITEMODE_A="NORMAL" */
+ /* synthesis GSR="ENABLED" */
+ /* synthesis RESETMODE="ASYNC" */
+ /* synthesis REGMODE_B="NOREG" */
+ /* synthesis REGMODE_A="NOREG" */
+ /* synthesis DATA_WIDTH_B="18" */
+ /* synthesis DATA_WIDTH_A="18" */;
+
+ VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ // synopsys translate_off
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_17 = 320'h0000000000000000000000000000000000000000038FF034D2038FF034C2038FF0349A038FF03EFF ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_16 = 320'h00D00038FF034CA038FF03492038FF0348A038FF03482038FF0344A038FF03442038FF0343A038FF ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_15 = 320'h00D6300D5A00C5803EFF0136300D0302E0803EFF02E0803EFF038FF00D5A03EFF00D630105801363 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_14 = 320'h00D0302E0803EFF02E0803EFF038FF03EFF02E70038FF034DA0170801F100110801F100110801F10 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_13 = 320'h0110801F100110801F100110801F100110801F100110801F100110801F100110801F100110801F08 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_12 = 320'h02E0803EFF02E0803EFF038FF02E7802430038FF03EFF02E780110801F0803EFF030E800DE700AE7 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_11 = 320'h00AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D000341800D0001708 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_10 = 320'h01F100110801F100110801F100110801F100110801F100110801F0802E0803EFF0347000D0001708 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0F = 320'h024700347000D00017080247002E08016E7016E4016E3016E3016E3016E3016E200DE7030E800DE7 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0E = 320'h00AE703EFF010E003EFF010E003EFF010E003EFF010E0016E0016E700DE7030E800DE700AE700AE0 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0D = 320'h00CE003EFF00CE003EFF00CE003EFF00CE003EFF016E700DE7030E8034700171002470030E801108 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0C = 320'h01F0803470017100247000808030E80081003478011080081002478030F800AE700AE70340700AE7 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0B = 320'h0344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE500AE400AE4 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0A = 320'h00AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE100AE000AE0 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_09 = 320'h00AE0030F000AE700AE70340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE6 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_08 = 320'h00AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE2 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_07 = 320'h00AE100AE100AE100AE100AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E80000800008 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_06 = 320'h0000800008000080080800DE8016E802400016E802448016E802438016EF016EF016EF016EE016EE ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_03 = 320'h00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_02 = 320'h00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_01 = 320'h00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_00 = 320'h00D000380003E0002EE0016E703E0002EE80260000D0000D0000D0000D0000D0000D0003E0002600 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.CSDECODE_B = 3'b000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.CSDECODE_A = 3'b000 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.WRITEMODE_B = "NORMAL" ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.WRITEMODE_A = "NORMAL" ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.GSR = "ENABLED" ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.RESETMODE = "ASYNC" ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.REGMODE_B = "NOREG" ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.REGMODE_A = "NOREG" ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.DATA_WIDTH_B = 18 ;
+ defparam lm32_monitor_ram_ecp2_0_1_0.DATA_WIDTH_A = 18 ;
+ // synopsys translate_on
+ DP16KB lm32_monitor_ram_ecp2_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]),
+ .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]),
+ .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]),
+ .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]),
+ .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo),
+ .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
+ .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
+ .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
+ .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA),
+ .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo),
+ .RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]),
+ .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]),
+ .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]),
+ .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo),
+ .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi),
+ .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]),
+ .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]),
+ .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]),
+ .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo),
+ .CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]),
+ .DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]),
+ .DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]),
+ .DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]), .DOA14(), .DOA15(),
+ .DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]), .DOB2(QB[20]),
+ .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]), .DOB7(QB[25]),
+ .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]), .DOB12(QB[30]),
+ .DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17())
+ /* synthesis MEM_LPC_FILE="lm32_monitor_ram_ecp2.lpc" */
+ /* synthesis MEM_INIT_FILE="rom.mem" */
+ /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_19="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_18="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_17="0x0000000000000000000000000000000000000000038FF034D2038FF034C2038FF0349A038FF03EFF" */
+ /* synthesis INITVAL_16="0x00D00038FF034CA038FF03492038FF0348A038FF03482038FF0344A038FF03442038FF0343A038FF" */
+ /* synthesis INITVAL_15="0x00D6300D5A00C5803EFF0136300D0302E0803EFF02E0803EFF038FF00D5A03EFF00D630105801363" */
+ /* synthesis INITVAL_14="0x00D0302E0803EFF02E0803EFF038FF03EFF02E70038FF034DA0170801F100110801F100110801F10" */
+ /* synthesis INITVAL_13="0x0110801F100110801F100110801F100110801F100110801F100110801F100110801F100110801F08" */
+ /* synthesis INITVAL_12="0x02E0803EFF02E0803EFF038FF02E7802430038FF03EFF02E780110801F0803EFF030E800DE700AE7" */
+ /* synthesis INITVAL_11="0x00AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D000341800D0001708" */
+ /* synthesis INITVAL_10="0x01F100110801F100110801F100110801F100110801F100110801F0802E0803EFF0347000D0001708" */
+ /* synthesis INITVAL_0F="0x024700347000D00017080247002E08016E7016E4016E3016E3016E3016E3016E200DE7030E800DE7" */
+ /* synthesis INITVAL_0E="0x00AE703EFF010E003EFF010E003EFF010E003EFF010E0016E0016E700DE7030E800DE700AE700AE0" */
+ /* synthesis INITVAL_0D="0x00CE003EFF00CE003EFF00CE003EFF00CE003EFF016E700DE7030E8034700171002470030E801108" */
+ /* synthesis INITVAL_0C="0x01F0803470017100247000808030E80081003478011080081002478030F800AE700AE70340700AE7" */
+ /* synthesis INITVAL_0B="0x0344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE500AE400AE4" */
+ /* synthesis INITVAL_0A="0x00AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE100AE000AE0" */
+ /* synthesis INITVAL_09="0x00AE0030F000AE700AE70340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE6" */
+ /* synthesis INITVAL_08="0x00AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE2" */
+ /* synthesis INITVAL_07="0x00AE100AE100AE100AE100AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E80000800008" */
+ /* synthesis INITVAL_06="0x0000800008000080080800DE8016E802400016E802448016E802438016EF016EF016EF016EE016EE" */
+ /* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */
+ /* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */
+ /* synthesis INITVAL_03="0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600" */
+ /* synthesis INITVAL_02="0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600" */
+ /* synthesis INITVAL_01="0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600" */
+ /* synthesis INITVAL_00="0x00D000380003E0002EE0016E703E0002EE80260000D0000D0000D0000D0000D0000D0003E0002600" */
+ /* synthesis CSDECODE_B="0b000" */
+ /* synthesis CSDECODE_A="0b000" */
+ /* synthesis WRITEMODE_B="NORMAL" */
+ /* synthesis WRITEMODE_A="NORMAL" */
+ /* synthesis GSR="ENABLED" */
+ /* synthesis RESETMODE="ASYNC" */
+ /* synthesis REGMODE_B="NOREG" */
+ /* synthesis REGMODE_A="NOREG" */
+ /* synthesis DATA_WIDTH_B="18" */
+ /* synthesis DATA_WIDTH_A="18" */;
+
+
+
+ // exemplar begin
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 MEM_LPC_FILE lm32_monitor_ram_ecp2.lpc
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 MEM_INIT_FILE rom.mem
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_19 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_18 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_17 0x00000000000000000000000000000000000000003FF8C300003FF8E300003FF90300003FF923FF5B
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_16 0x1004F3FF95300003FF97300003FF99300003FF9B300003FF9D300003FF9F300003FFA1300003FFFB
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_15 0x0000130001100003FF691001400000068003FF7E058003FF803FFFB300013FF7800001100001FFB3
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_14 0x00000068003FF89058003FF8B3FFB93FF9B008003FFBC300000FFBE1001B000331001A0002C10019
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_13 0x00035100180003510013000301001200030100110003010010000301000900030100080003010007
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_12 0x010003FF97058003FFAA3FFFC00800078003FFDB3FFBD0080000004100063FFA2000000001C10004
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_11 0x000083000C2001010014000183001C0000000000000001000000000000000000010000100010FFF3
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_10 0x10063000481004D0003F1006D0003E1007200024100570001D10077010003FFC210000100540FFFF
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0F 0x0080010000100540FFFF008000700010004000083000C2001010014000183001C0FFE40000000008
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0E 0x100043FFDD100083FFDF100093FFE11000A3FFE31000B10008100040FFF8000000000C1000410008
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0D 0x100083FFE7100093FFE91000A3FFEB1000B3FFED100040FFF400000200000FFFF010000000000002
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0C 0x10054100000FFFF01000100FF00000100FF000000FFFE10100010000000000070300803000030090
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0B 0x300003008C300003008820078100743006C2006810064000603005C2005810054000503004C20048
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0A 0x10044000403003C2003810034000303002C2002810024000203001C2001810014000103000C20008
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_09 0x100040000000070200802000020090200002008C20000200883007C100743006C200681006400060
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_08 0x3005C2005810054000503004C2004810044000403003C2003810034000303002C200281002400020
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_07 0x3001C2001810014000103000C2000810004000001F9940E000000001007410000100841000110001
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_06 0x100011000110001100FF1F99410090008001008C0080010088008003007C20078000703006C20068
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_05 0x10064000603005C2005810054000503004C2004810044000403003C2003810034000303002C20028
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_04 0x10024000203001C2001810014000103000C200081000400000000001066C3FFC530000007F40E000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_03 0x000000003B000B500800200800000A00000000000000000043000BD0080020080000120000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_02 0x000000004B000C500800200800001A00000000000000000053000CD0080020080000220000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_01 0x0000000081000D500800300800002A00000000000000000063000DD0080020080000320000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_00 0x0000000091000E500800300800003A00000000000000000000000000000000000000000003F00000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 CSDECODE_B 0b000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 CSDECODE_A 0b000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 WRITEMODE_B NORMAL
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 WRITEMODE_A NORMAL
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 GSR ENABLED
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 RESETMODE ASYNC
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 REGMODE_B NOREG
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 REGMODE_A NOREG
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 DATA_WIDTH_B 18
+ // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 DATA_WIDTH_A 18
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 MEM_LPC_FILE lm32_monitor_ram_ecp2.lpc
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 MEM_INIT_FILE rom.mem
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_19 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_18 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_17 0x0000000000000000000000000000000000000000038FF034D2038FF034C2038FF0349A038FF03EFF
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_16 0x00D00038FF034CA038FF03492038FF0348A038FF03482038FF0344A038FF03442038FF0343A038FF
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_15 0x00D6300D5A00C5803EFF0136300D0302E0803EFF02E0803EFF038FF00D5A03EFF00D630105801363
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_14 0x00D0302E0803EFF02E0803EFF038FF03EFF02E70038FF034DA0170801F100110801F100110801F10
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_13 0x0110801F100110801F100110801F100110801F100110801F100110801F100110801F100110801F08
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_12 0x02E0803EFF02E0803EFF038FF02E7802430038FF03EFF02E780110801F0803EFF030E800DE700AE7
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_11 0x00AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D000341800D0001708
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_10 0x01F100110801F100110801F100110801F100110801F100110801F0802E0803EFF0347000D0001708
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0F 0x024700347000D00017080247002E08016E7016E4016E3016E3016E3016E3016E200DE7030E800DE7
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0E 0x00AE703EFF010E003EFF010E003EFF010E003EFF010E0016E0016E700DE7030E800DE700AE700AE0
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0D 0x00CE003EFF00CE003EFF00CE003EFF00CE003EFF016E700DE7030E8034700171002470030E801108
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0C 0x01F0803470017100247000808030E80081003478011080081002478030F800AE700AE70340700AE7
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0B 0x0344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE500AE400AE4
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0A 0x00AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE100AE000AE0
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_09 0x00AE0030F000AE700AE70340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE6
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_08 0x00AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE2
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_07 0x00AE100AE100AE100AE100AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E80000800008
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_06 0x0000800008000080080800DE8016E802400016E802448016E802438016EF016EF016EF016EE016EE
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_03 0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_02 0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_01 0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_00 0x00D000380003E0002EE0016E703E0002EE80260000D0000D0000D0000D0000D0000D0003E0002600
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 CSDECODE_B 0b000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 CSDECODE_A 0b000
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 WRITEMODE_B NORMAL
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 WRITEMODE_A NORMAL
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 GSR ENABLED
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 RESETMODE ASYNC
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 REGMODE_B NOREG
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 REGMODE_A NOREG
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 DATA_WIDTH_B 18
+ // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 DATA_WIDTH_A 18
+ // exemplar end
+ end else if (lat_family == "SC" || lat_family == "SCM") begin
+ // synopsys translate_off
+ defparam sc_rom_monitor_0_0_1.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_17 = 320'h00000000000000000000000000000000000000003FF8C300003FF8E300003FF90300003FF923FF5B ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_16 = 320'h1004F3FF95300003FF97300003FF99300003FF9B300003FF9D300003FF9F300003FFA1300003FFFB ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_15 = 320'h0000130001100003FF691001400000068003FF7E058003FF803FFFB300013FF7800001100001FFB3 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_14 = 320'h00000068003FF89058003FF8B3FFB93FF9B008003FFBC300000FFBE1001B000331001A0002C10019 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_13 = 320'h00035100180003510013000301001200030100110003010010000301000900030100080003010007 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_12 = 320'h010003FF97058003FFAA3FFFC00800078003FFDB3FFBD0080000004100063FFA2000000001C10004 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_11 = 320'h000083000C2001010014000183001C0000000000000001000000000000000000010000100010FFF3 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_10 = 320'h10063000481004D0003F1006D0003E1007200024100570001D10077010003FFC210000100540FFFF ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_0F = 320'h0080010000100540FFFF008000700010004000083000C2001010014000183001C0FFE40000000008 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_0E = 320'h100043FFDD100083FFDF100093FFE11000A3FFE31000B10008100040FFF8000000000C1000410008 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_0D = 320'h100083FFE7100093FFE91000A3FFEB1000B3FFED100040FFF400000200000FFFF010000000000002 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_0C = 320'h10054100000FFFF01000100FF00000100FF000000FFFE10100010000000000070300803000030090 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_0B = 320'h300003008C300003008820078100743006C2006810064000603005C2005810054000503004C20048 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_0A = 320'h10044000403003C2003810034000303002C2002810024000203001C2001810014000103000C20008 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_09 = 320'h100040000000070200802000020090200002008C20000200883007C100743006C200681006400060 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_08 = 320'h3005C2005810054000503004C2004810044000403003C2003810034000303002C200281002400020 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_07 = 320'h3001C2001810014000103000C2000810004000001F9940E000000001007410000100841000110001 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_06 = 320'h100011000110001100FF1F99410090008001008C0080010088008003007C20078000703006C20068 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_05 = 320'h10064000603005C2005810054000503004C2004810044000403003C2003810034000303002C20028 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_04 = 320'h10024000203001C2001810014000103000C200081000400000000001066C3FFC530000007F40E000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_03 = 320'h000000003B000B500800200800000A00000000000000000043000BD0080020080000120000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_02 = 320'h000000004B000C500800200800001A00000000000000000053000CD0080020080000220000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_01 = 320'h0000000081000D500800300800002A00000000000000000063000DD0080020080000320000000000 ;
+ defparam sc_rom_monitor_0_0_1.INITVAL_00 = 320'h0000000091000E500800300800003A00000000000000000000000000000000000000000003F00000 ;
+ defparam sc_rom_monitor_0_0_1.CSDECODE_B = 3'b000 ;
+ defparam sc_rom_monitor_0_0_1.CSDECODE_A = 3'b000 ;
+ defparam sc_rom_monitor_0_0_1.WRITEMODE_B = "NORMAL" ;
+ defparam sc_rom_monitor_0_0_1.WRITEMODE_A = "NORMAL" ;
+ defparam sc_rom_monitor_0_0_1.GSR = "ENABLED" ;
+ defparam sc_rom_monitor_0_0_1.RESETMODE = "ASYNC" ;
+ defparam sc_rom_monitor_0_0_1.REGMODE_B = "NOREG" ;
+ defparam sc_rom_monitor_0_0_1.REGMODE_A = "NOREG" ;
+ defparam sc_rom_monitor_0_0_1.DATA_WIDTH_B = 18 ;
+ defparam sc_rom_monitor_0_0_1.DATA_WIDTH_A = 18 ;
+ // synopsys translate_on
+ DP16KA sc_rom_monitor_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]), .DIA2(DataInA[2]),
+ .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]), .DIA6(DataInA[6]),
+ .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]), .DIA10(DataInA[10]),
+ .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]), .DIA14(DataInA[14]),
+ .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]), .ADA0(scuba_vhi),
+ .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), .ADA4(AddressA[0]),
+ .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), .ADA8(AddressA[4]),
+ .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), .ADA12(AddressA[8]),
+ .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA0(scuba_vlo),
+ .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA), .DIB0(DataInB[0]),
+ .DIB1(DataInB[1]), .DIB2(DataInB[2]), .DIB3(DataInB[3]), .DIB4(DataInB[4]),
+ .DIB5(DataInB[5]), .DIB6(DataInB[6]), .DIB7(DataInB[7]), .DIB8(DataInB[8]),
+ .DIB9(DataInB[9]), .DIB10(DataInB[10]), .DIB11(DataInB[11]), .DIB12(DataInB[12]),
+ .DIB13(DataInB[13]), .DIB14(DataInB[14]), .DIB15(DataInB[15]), .DIB16(DataInB[16]),
+ .DIB17(DataInB[17]), .ADB0(scuba_vhi), .ADB1(scuba_vhi), .ADB2(scuba_vlo),
+ .ADB3(scuba_vlo), .ADB4(AddressB[0]), .ADB5(AddressB[1]), .ADB6(AddressB[2]),
+ .ADB7(AddressB[3]), .ADB8(AddressB[4]), .ADB9(AddressB[5]), .ADB10(AddressB[6]),
+ .ADB11(AddressB[7]), .ADB12(AddressB[8]), .ADB13(scuba_vlo), .CEB(ClockEnB),
+ .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), .CSB2(scuba_vlo),
+ .RSTB(ResetB), .DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]),
+ .DOA4(QA[4]), .DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]),
+ .DOA9(QA[9]), .DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]),
+ .DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]),
+ .DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]),
+ .DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]),
+ .DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]),
+ .DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17]))
+ /* synthesis MEM_LPC_FILE="sc_rom_monitor.lpc" */
+ /* synthesis MEM_INIT_FILE="rom.mem" */
+ /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_19="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_18="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_17="0x00000000000000000000000000000000000000003FF8C300003FF8E300003FF90300003FF923FF5B" */
+ /* synthesis INITVAL_16="0x1004F3FF95300003FF97300003FF99300003FF9B300003FF9D300003FF9F300003FFA1300003FFFB" */
+ /* synthesis INITVAL_15="0x0000130001100003FF691001400000068003FF7E058003FF803FFFB300013FF7800001100001FFB3" */
+ /* synthesis INITVAL_14="0x00000068003FF89058003FF8B3FFB93FF9B008003FFBC300000FFBE1001B000331001A0002C10019" */
+ /* synthesis INITVAL_13="0x00035100180003510013000301001200030100110003010010000301000900030100080003010007" */
+ /* synthesis INITVAL_12="0x010003FF97058003FFAA3FFFC00800078003FFDB3FFBD0080000004100063FFA2000000001C10004" */
+ /* synthesis INITVAL_11="0x000083000C2001010014000183001C0000000000000001000000000000000000010000100010FFF3" */
+ /* synthesis INITVAL_10="0x10063000481004D0003F1006D0003E1007200024100570001D10077010003FFC210000100540FFFF" */
+ /* synthesis INITVAL_0F="0x0080010000100540FFFF008000700010004000083000C2001010014000183001C0FFE40000000008" */
+ /* synthesis INITVAL_0E="0x100043FFDD100083FFDF100093FFE11000A3FFE31000B10008100040FFF8000000000C1000410008" */
+ /* synthesis INITVAL_0D="0x100083FFE7100093FFE91000A3FFEB1000B3FFED100040FFF400000200000FFFF010000000000002" */
+ /* synthesis INITVAL_0C="0x10054100000FFFF01000100FF00000100FF000000FFFE10100010000000000070300803000030090" */
+ /* synthesis INITVAL_0B="0x300003008C300003008820078100743006C2006810064000603005C2005810054000503004C20048" */
+ /* synthesis INITVAL_0A="0x10044000403003C2003810034000303002C2002810024000203001C2001810014000103000C20008" */
+ /* synthesis INITVAL_09="0x100040000000070200802000020090200002008C20000200883007C100743006C200681006400060" */
+ /* synthesis INITVAL_08="0x3005C2005810054000503004C2004810044000403003C2003810034000303002C200281002400020" */
+ /* synthesis INITVAL_07="0x3001C2001810014000103000C2000810004000001F9940E000000001007410000100841000110001" */
+ /* synthesis INITVAL_06="0x100011000110001100FF1F99410090008001008C0080010088008003007C20078000703006C20068" */
+ /* synthesis INITVAL_05="0x10064000603005C2005810054000503004C2004810044000403003C2003810034000303002C20028" */
+ /* synthesis INITVAL_04="0x10024000203001C2001810014000103000C200081000400000000001066C3FFC530000007F40E000" */
+ /* synthesis INITVAL_03="0x000000003B000B500800200800000A00000000000000000043000BD0080020080000120000000000" */
+ /* synthesis INITVAL_02="0x000000004B000C500800200800001A00000000000000000053000CD0080020080000220000000000" */
+ /* synthesis INITVAL_01="0x0000000081000D500800300800002A00000000000000000063000DD0080020080000320000000000" */
+ /* synthesis INITVAL_00="0x0000000091000E500800300800003A00000000000000000000000000000000000000000003F00000" */
+ /* synthesis CSDECODE_B="0b000" */
+ /* synthesis CSDECODE_A="0b000" */
+ /* synthesis WRITEMODE_B="NORMAL" */
+ /* synthesis WRITEMODE_A="NORMAL" */
+ /* synthesis GSR="ENABLED" */
+ /* synthesis RESETMODE="ASYNC" */
+ /* synthesis REGMODE_B="NOREG" */
+ /* synthesis REGMODE_A="NOREG" */
+ /* synthesis DATA_WIDTH_B="18" */
+ /* synthesis DATA_WIDTH_A="18" */;
+
+ VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ // synopsys translate_off
+ defparam sc_rom_monitor_0_1_0.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_17 = 320'h0000000000000000000000000000000000000000038FF034D2038FF034C2038FF0349A038FF03EFF ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_16 = 320'h00D00038FF034CA038FF03492038FF0348A038FF03482038FF0344A038FF03442038FF0343A038FF ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_15 = 320'h00D6300D5A00C5803EFF0136300D0302E0803EFF02E0803EFF038FF00D5A03EFF00D630105801363 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_14 = 320'h00D0302E0803EFF02E0803EFF038FF03EFF02E70038FF034DA0170801F100110801F100110801F10 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_13 = 320'h0110801F100110801F100110801F100110801F100110801F100110801F100110801F100110801F08 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_12 = 320'h02E0803EFF02E0803EFF038FF02E7802430038FF03EFF02E780110801F0803EFF030E800DE700AE7 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_11 = 320'h00AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D000341800D0001708 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_10 = 320'h01F100110801F100110801F100110801F100110801F100110801F0802E0803EFF0347000D0001708 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_0F = 320'h024700347000D00017080247002E08016E7016E4016E3016E3016E3016E3016E200DE7030E800DE7 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_0E = 320'h00AE703EFF010E003EFF010E003EFF010E003EFF010E0016E0016E700DE7030E800DE700AE700AE0 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_0D = 320'h00CE003EFF00CE003EFF00CE003EFF00CE003EFF016E700DE7030E8034700171002470030E801108 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_0C = 320'h01F0803470017100247000808030E80081003478011080081002478030F800AE700AE70340700AE7 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_0B = 320'h0344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE500AE400AE4 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_0A = 320'h00AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE100AE000AE0 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_09 = 320'h00AE0030F000AE700AE70340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE6 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_08 = 320'h00AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE2 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_07 = 320'h00AE100AE100AE100AE100AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E80000800008 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_06 = 320'h0000800008000080080800DE8016E802400016E802448016E802438016EF016EF016EF016EE016EE ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_03 = 320'h00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_02 = 320'h00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_01 = 320'h00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600 ;
+ defparam sc_rom_monitor_0_1_0.INITVAL_00 = 320'h00D000380003E0002EE0016E703E0002EE80260000D0000D0000D0000D0000D0000D0003E0002600 ;
+ defparam sc_rom_monitor_0_1_0.CSDECODE_B = 3'b000 ;
+ defparam sc_rom_monitor_0_1_0.CSDECODE_A = 3'b000 ;
+ defparam sc_rom_monitor_0_1_0.WRITEMODE_B = "NORMAL" ;
+ defparam sc_rom_monitor_0_1_0.WRITEMODE_A = "NORMAL" ;
+ defparam sc_rom_monitor_0_1_0.GSR = "ENABLED" ;
+ defparam sc_rom_monitor_0_1_0.RESETMODE = "ASYNC" ;
+ defparam sc_rom_monitor_0_1_0.REGMODE_B = "NOREG" ;
+ defparam sc_rom_monitor_0_1_0.REGMODE_A = "NOREG" ;
+ defparam sc_rom_monitor_0_1_0.DATA_WIDTH_B = 18 ;
+ defparam sc_rom_monitor_0_1_0.DATA_WIDTH_A = 18 ;
+ // synopsys translate_on
+ DP16KA sc_rom_monitor_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]),
+ .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]),
+ .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]),
+ .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]),
+ .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo),
+ .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
+ .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
+ .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
+ .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA),
+ .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo),
+ .RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]),
+ .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]),
+ .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]),
+ .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo),
+ .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi),
+ .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]),
+ .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]),
+ .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]),
+ .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo),
+ .CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]),
+ .DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]),
+ .DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]),
+ .DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]), .DOA14(), .DOA15(),
+ .DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]), .DOB2(QB[20]),
+ .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]), .DOB7(QB[25]),
+ .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]), .DOB12(QB[30]),
+ .DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17())
+ /* synthesis MEM_LPC_FILE="sc_rom_monitor.lpc" */
+ /* synthesis MEM_INIT_FILE="rom.mem" */
+ /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_19="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_18="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
+ /* synthesis INITVAL_17="0x0000000000000000000000000000000000000000038FF034D2038FF034C2038FF0349A038FF03EFF" */
+ /* synthesis INITVAL_16="0x00D00038FF034CA038FF03492038FF0348A038FF03482038FF0344A038FF03442038FF0343A038FF" */
+ /* synthesis INITVAL_15="0x00D6300D5A00C5803EFF0136300D0302E0803EFF02E0803EFF038FF00D5A03EFF00D630105801363" */
+ /* synthesis INITVAL_14="0x00D0302E0803EFF02E0803EFF038FF03EFF02E70038FF034DA0170801F100110801F100110801F10" */
+ /* synthesis INITVAL_13="0x0110801F100110801F100110801F100110801F100110801F100110801F100110801F100110801F08" */
+ /* synthesis INITVAL_12="0x02E0803EFF02E0803EFF038FF02E7802430038FF03EFF02E780110801F0803EFF030E800DE700AE7" */
+ /* synthesis INITVAL_11="0x00AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D000341800D0001708" */
+ /* synthesis INITVAL_10="0x01F100110801F100110801F100110801F100110801F100110801F0802E0803EFF0347000D0001708" */
+ /* synthesis INITVAL_0F="0x024700347000D00017080247002E08016E7016E4016E3016E3016E3016E3016E200DE7030E800DE7" */
+ /* synthesis INITVAL_0E="0x00AE703EFF010E003EFF010E003EFF010E003EFF010E0016E0016E700DE7030E800DE700AE700AE0" */
+ /* synthesis INITVAL_0D="0x00CE003EFF00CE003EFF00CE003EFF00CE003EFF016E700DE7030E8034700171002470030E801108" */
+ /* synthesis INITVAL_0C="0x01F0803470017100247000808030E80081003478011080081002478030F800AE700AE70340700AE7" */
+ /* synthesis INITVAL_0B="0x0344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE500AE400AE4" */
+ /* synthesis INITVAL_0A="0x00AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE100AE000AE0" */
+ /* synthesis INITVAL_09="0x00AE0030F000AE700AE70340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE6" */
+ /* synthesis INITVAL_08="0x00AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE2" */
+ /* synthesis INITVAL_07="0x00AE100AE100AE100AE100AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E80000800008" */
+ /* synthesis INITVAL_06="0x0000800008000080080800DE8016E802400016E802448016E802438016EF016EF016EF016EE016EE" */
+ /* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */
+ /* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */
+ /* synthesis INITVAL_03="0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600" */
+ /* synthesis INITVAL_02="0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600" */
+ /* synthesis INITVAL_01="0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600" */
+ /* synthesis INITVAL_00="0x00D000380003E0002EE0016E703E0002EE80260000D0000D0000D0000D0000D0000D0003E0002600" */
+ /* synthesis CSDECODE_B="0b000" */
+ /* synthesis CSDECODE_A="0b000" */
+ /* synthesis WRITEMODE_B="NORMAL" */
+ /* synthesis WRITEMODE_A="NORMAL" */
+ /* synthesis GSR="ENABLED" */
+ /* synthesis RESETMODE="ASYNC" */
+ /* synthesis REGMODE_B="NOREG" */
+ /* synthesis REGMODE_A="NOREG" */
+ /* synthesis DATA_WIDTH_B="18" */
+ /* synthesis DATA_WIDTH_A="18" */;
+
+
+
+ // exemplar begin
+ // exemplar attribute sc_rom_monitor_0_0_1 MEM_LPC_FILE sc_rom_monitor.lpc
+ // exemplar attribute sc_rom_monitor_0_0_1 MEM_INIT_FILE rom.mem
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_19 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_18 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_17 0x00000000000000000000000000000000000000003FF8C300003FF8E300003FF90300003FF923FF5B
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_16 0x1004F3FF95300003FF97300003FF99300003FF9B300003FF9D300003FF9F300003FFA1300003FFFB
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_15 0x0000130001100003FF691001400000068003FF7E058003FF803FFFB300013FF7800001100001FFB3
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_14 0x00000068003FF89058003FF8B3FFB93FF9B008003FFBC300000FFBE1001B000331001A0002C10019
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_13 0x00035100180003510013000301001200030100110003010010000301000900030100080003010007
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_12 0x010003FF97058003FFAA3FFFC00800078003FFDB3FFBD0080000004100063FFA2000000001C10004
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_11 0x000083000C2001010014000183001C0000000000000001000000000000000000010000100010FFF3
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_10 0x10063000481004D0003F1006D0003E1007200024100570001D10077010003FFC210000100540FFFF
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0F 0x0080010000100540FFFF008000700010004000083000C2001010014000183001C0FFE40000000008
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0E 0x100043FFDD100083FFDF100093FFE11000A3FFE31000B10008100040FFF8000000000C1000410008
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0D 0x100083FFE7100093FFE91000A3FFEB1000B3FFED100040FFF400000200000FFFF010000000000002
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0C 0x10054100000FFFF01000100FF00000100FF000000FFFE10100010000000000070300803000030090
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0B 0x300003008C300003008820078100743006C2006810064000603005C2005810054000503004C20048
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0A 0x10044000403003C2003810034000303002C2002810024000203001C2001810014000103000C20008
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_09 0x100040000000070200802000020090200002008C20000200883007C100743006C200681006400060
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_08 0x3005C2005810054000503004C2004810044000403003C2003810034000303002C200281002400020
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_07 0x3001C2001810014000103000C2000810004000001F9940E000000001007410000100841000110001
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_06 0x100011000110001100FF1F99410090008001008C0080010088008003007C20078000703006C20068
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_05 0x10064000603005C2005810054000503004C2004810044000403003C2003810034000303002C20028
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_04 0x10024000203001C2001810014000103000C200081000400000000001066C3FFC530000007F40E000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_03 0x000000003B000B500800200800000A00000000000000000043000BD0080020080000120000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_02 0x000000004B000C500800200800001A00000000000000000053000CD0080020080000220000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_01 0x0000000081000D500800300800002A00000000000000000063000DD0080020080000320000000000
+ // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_00 0x0000000091000E500800300800003A00000000000000000000000000000000000000000003F00000
+ // exemplar attribute sc_rom_monitor_0_0_1 CSDECODE_B 0b000
+ // exemplar attribute sc_rom_monitor_0_0_1 CSDECODE_A 0b000
+ // exemplar attribute sc_rom_monitor_0_0_1 WRITEMODE_B NORMAL
+ // exemplar attribute sc_rom_monitor_0_0_1 WRITEMODE_A NORMAL
+ // exemplar attribute sc_rom_monitor_0_0_1 GSR ENABLED
+ // exemplar attribute sc_rom_monitor_0_0_1 RESETMODE ASYNC
+ // exemplar attribute sc_rom_monitor_0_0_1 REGMODE_B NOREG
+ // exemplar attribute sc_rom_monitor_0_0_1 REGMODE_A NOREG
+ // exemplar attribute sc_rom_monitor_0_0_1 DATA_WIDTH_B 18
+ // exemplar attribute sc_rom_monitor_0_0_1 DATA_WIDTH_A 18
+ // exemplar attribute sc_rom_monitor_0_1_0 MEM_LPC_FILE sc_rom_monitor.lpc
+ // exemplar attribute sc_rom_monitor_0_1_0 MEM_INIT_FILE rom.mem
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_19 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_18 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_17 0x0000000000000000000000000000000000000000038FF034D2038FF034C2038FF0349A038FF03EFF
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_16 0x00D00038FF034CA038FF03492038FF0348A038FF03482038FF0344A038FF03442038FF0343A038FF
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_15 0x00D6300D5A00C5803EFF0136300D0302E0803EFF02E0803EFF038FF00D5A03EFF00D630105801363
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_14 0x00D0302E0803EFF02E0803EFF038FF03EFF02E70038FF034DA0170801F100110801F100110801F10
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_13 0x0110801F100110801F100110801F100110801F100110801F100110801F100110801F100110801F08
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_12 0x02E0803EFF02E0803EFF038FF02E7802430038FF03EFF02E780110801F0803EFF030E800DE700AE7
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_11 0x00AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D000341800D0001708
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_10 0x01F100110801F100110801F100110801F100110801F100110801F0802E0803EFF0347000D0001708
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0F 0x024700347000D00017080247002E08016E7016E4016E3016E3016E3016E3016E200DE7030E800DE7
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0E 0x00AE703EFF010E003EFF010E003EFF010E003EFF010E0016E0016E700DE7030E800DE700AE700AE0
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0D 0x00CE003EFF00CE003EFF00CE003EFF00CE003EFF016E700DE7030E8034700171002470030E801108
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0C 0x01F0803470017100247000808030E80081003478011080081002478030F800AE700AE70340700AE7
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0B 0x0344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE500AE400AE4
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0A 0x00AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE100AE000AE0
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_09 0x00AE0030F000AE700AE70340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE6
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_08 0x00AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE2
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_07 0x00AE100AE100AE100AE100AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E80000800008
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_06 0x0000800008000080080800DE8016E802400016E802448016E802438016EF016EF016EF016EE016EE
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_03 0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_02 0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_01 0x00D000380003E0002EE0016E703E0002EE80260000D000380003E0002EE0016E703E0002EE802600
+ // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_00 0x00D000380003E0002EE0016E703E0002EE80260000D0000D0000D0000D0000D0000D0003E0002600
+ // exemplar attribute sc_rom_monitor_0_1_0 CSDECODE_B 0b000
+ // exemplar attribute sc_rom_monitor_0_1_0 CSDECODE_A 0b000
+ // exemplar attribute sc_rom_monitor_0_1_0 WRITEMODE_B NORMAL
+ // exemplar attribute sc_rom_monitor_0_1_0 WRITEMODE_A NORMAL
+ // exemplar attribute sc_rom_monitor_0_1_0 GSR ENABLED
+ // exemplar attribute sc_rom_monitor_0_1_0 RESETMODE ASYNC
+ // exemplar attribute sc_rom_monitor_0_1_0 REGMODE_B NOREG
+ // exemplar attribute sc_rom_monitor_0_1_0 REGMODE_A NOREG
+ // exemplar attribute sc_rom_monitor_0_1_0 DATA_WIDTH_B 18
+ // exemplar attribute sc_rom_monitor_0_1_0 DATA_WIDTH_A 18
+ // exemplar end
+ end
+ endgenerate
+
+endmodule
lm32/verilog/src/lm32_monitor_ram.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_multiplier.v
===================================================================
--- lm32/verilog/src/lm32_multiplier.v (nonexistent)
+++ lm32/verilog/src/lm32_multiplier.v (revision 17)
@@ -0,0 +1,94 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_multiplier.v
+// Title : Pipelined multiplier.
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_multiplier (
+ // ----- Inputs -----
+ clk_i,
+ rst_i,
+ stall_x,
+ stall_m,
+ operand_0,
+ operand_1,
+ // ----- Ouputs -----
+ result
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+input stall_x; // Stall instruction in X stage
+input stall_m; // Stall instruction in M stage
+input [`LM32_WORD_RNG] operand_0; // Muliplicand
+input [`LM32_WORD_RNG] operand_1; // Multiplier
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] result; // Product of multiplication
+reg [`LM32_WORD_RNG] result;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+reg [`LM32_WORD_RNG] muliplicand;
+reg [`LM32_WORD_RNG] multiplier;
+reg [`LM32_WORD_RNG] product;
+
+/////////////////////////////////////////////////////
+// Sequential logic
+/////////////////////////////////////////////////////
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ muliplicand <= {`LM32_WORD_WIDTH{1'b0}};
+ multiplier <= {`LM32_WORD_WIDTH{1'b0}};
+ product <= {`LM32_WORD_WIDTH{1'b0}};
+ result <= {`LM32_WORD_WIDTH{1'b0}};
+ end
+ else
+ begin
+ if (stall_x == `FALSE)
+ begin
+ muliplicand <= operand_0;
+ multiplier <= operand_1;
+ end
+ if (stall_m == `FALSE)
+ product <= muliplicand * multiplier;
+ result <= product;
+ end
+end
+
+endmodule
lm32/verilog/src/lm32_multiplier.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/spiprog.v
===================================================================
--- lm32/verilog/src/spiprog.v (nonexistent)
+++ lm32/verilog/src/spiprog.v (revision 17)
@@ -0,0 +1,159 @@
+//---------------------------------------------------------------------------
+//
+//Name : SPIPROG.v
+//
+//Description:
+//
+// This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
+// core. There are only three ER2 registers, one control register and two
+// data registers, in this IP core. The control register is a 8-bit wide
+// register for selecting which data register will be accessed when the
+// Control/Data# bit in ER1 register is low. Data register 0 is a readonly
+// ID register. It is composed of three register fields -- an 8-bit
+// "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
+// Data register 1 is a variable length register for sending commands to or
+// receiving readback data from the SPI Serial FLASH device.
+//
+//$Log: spiprog.vhd,v $
+//Revision 1.2 2004-09-09 11:43:26-07 jhsin
+//1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
+//2. Same as TYPEA and TYPEB modules, use falling edge clock
+// for all TCK Flip-Flops.
+//
+//Revision 1.1 2004-08-12 13:22:05-07 jhsin
+//Added 7 delay Flip-Flops so that the DR1 readback data from SPI Serial FLASH is in the byte boundary.
+//
+//Revision 1.0 2004-08-03 18:35:56-07 jhsin
+//Initial revision
+//
+//
+//$Header: \\\\hqfs2\\ip\040cores\\rcs\\hqfs2\\ip\040cores\\rcswork\\isptracy\\VHDL\\Implementation\\spiprog.vhd,v 1.2 2004-09-09 11:43:26-07 jhsin Exp $
+//
+//Copyright (C) 2004 Lattice Semiconductor Corp. All rights reserved.
+//
+//---------------------------------------------------------------------------
+
+module SPIPROG (input JTCK ,
+ input JTDI ,
+ output JTDO2 ,
+ input JSHIFT ,
+ input JUPDATE ,
+ input JRSTN ,
+ input JCE2 ,
+ input SPIPROG_ENABLE ,
+ input CONTROL_DATAN ,
+ output SPI_C ,
+ output SPI_D ,
+ output SPI_SN ,
+ input SPI_Q);
+
+ wire er2Cr_enable ;
+ wire er2Dr0_enable;
+ wire er2Dr1_enable;
+
+ wire tdo_er2Cr ;
+ wire tdo_er2Dr0;
+ wire tdo_er2Dr1;
+
+ wire [7:0] encodedDrSelBits ;
+ wire [8:0] er2CrTdiBit ;
+ wire [8:0] er2Dr0TdiBit ;
+
+ wire captureDrER2;
+ reg spi_s ;
+ reg [6:0] spi_q_dly;
+
+ wire [7:0] ip_functionality_id;
+
+ genvar i;
+
+ // ------ Control Register 0 ------
+
+ assign er2Cr_enable = JCE2 & SPIPROG_ENABLE & CONTROL_DATAN;
+
+ assign tdo_er2Cr = er2CrTdiBit[0];
+
+ // CR_BIT0_BIT7
+ generate
+ for(i=0; i<=7; i=i+1)
+ begin:CR_BIT0_BIT7
+ TYPEA BIT_N (.CLK (JTCK),
+ .RESET_N (JRSTN),
+ .CLKEN (er2Cr_enable),
+ .TDI (er2CrTdiBit[i + 1]),
+ .TDO (er2CrTdiBit[i]),
+ .DATA_OUT (encodedDrSelBits[i]),
+ .DATA_IN (encodedDrSelBits[i]),
+ .CAPTURE_DR (captureDrER2),
+ .UPDATE_DR (JUPDATE));
+ end
+ endgenerate // CR_BIT0_BIT7
+
+ assign er2CrTdiBit[8] = JTDI;
+
+// ------ Data Register 0 ------
+ assign er2Dr0_enable = (JCE2 & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000000)) ? 1'b1 : 1'b0;
+
+ assign tdo_er2Dr0 = er2Dr0TdiBit[0];
+
+ assign ip_functionality_id = 8'b00000001; //-- SPI Serial FLASH Programmer (0x01)
+
+// DR0_BIT0_BIT7
+ generate
+ for(i=0; i<=7; i=i+1)
+ begin:DR0_BIT0_BIT7
+ TYPEB BIT_N (.CLK (JTCK),
+ .RESET_N (JRSTN),
+ .CLKEN (er2Dr0_enable),
+ .TDI (er2Dr0TdiBit[i + 1]),
+ .TDO (er2Dr0TdiBit[i]),
+ .DATA_IN (ip_functionality_id[i]),
+ .CAPTURE_DR (captureDrER2));
+ end
+ endgenerate // DR0_BIT0_BIT7
+
+ assign er2Dr0TdiBit[8] = JTDI;
+
+// ------ Data Register 1 ------
+
+ assign er2Dr1_enable = (JCE2 & JSHIFT & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000001)) ? 1'b1 : 1'b0;
+
+ assign SPI_C = ~ (JTCK & er2Dr1_enable & spi_s);
+
+ assign SPI_D = JTDI & er2Dr1_enable;
+
+ // SPI_S_Proc
+ always @(negedge JTCK or negedge JRSTN)
+ begin
+ if (~JRSTN)
+ spi_s <= 1'b0;
+ else
+ if (JUPDATE)
+ spi_s <= 1'b0;
+ else
+ spi_s <= er2Dr1_enable;
+ end
+
+ assign SPI_SN = ~spi_s;
+
+ // SPI_Q_Proc
+ always @(negedge JTCK or negedge JRSTN)
+ begin
+ if (~JRSTN)
+ spi_q_dly <= 'b0;
+ else
+ if (er2Dr1_enable)
+ spi_q_dly <= {spi_q_dly[5:0],SPI_Q};
+ end
+
+ assign tdo_er2Dr1 = spi_q_dly[6];
+
+ // ------ JTDO2 MUX ------
+
+ assign JTDO2 = CONTROL_DATAN ? tdo_er2Cr :
+ (encodedDrSelBits == 8'b00000000) ? tdo_er2Dr0 :
+ (encodedDrSelBits == 8'b00000001) ? tdo_er2Dr1 : 1'b0;
+
+ assign captureDrER2 = ~JSHIFT & JCE2;
+
+endmodule
lm32/verilog/src/spiprog.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_cpu.v
===================================================================
--- lm32/verilog/src/lm32_cpu.v (nonexistent)
+++ lm32/verilog/src/lm32_cpu.v (revision 17)
@@ -0,0 +1,2305 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_cpu.v
+// Title : Top-level of CPU.
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_cpu (
+ // ----- Inputs -------
+ clk_i,
+`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
+ clk_n_i,
+`endif
+ rst_i,
+ // From external devices
+`ifdef CFG_INTERRUPTS_ENABLED
+ interrupt_n,
+`endif
+ // From user logic
+`ifdef CFG_USER_ENABLED
+ user_result,
+ user_complete,
+`endif
+`ifdef CFG_JTAG_ENABLED
+ // From JTAG
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+`endif
+`ifdef CFG_IWB_ENABLED
+ // Instruction Wishbone master
+ I_DAT_I,
+ I_ACK_I,
+ I_ERR_I,
+ I_RTY_I,
+`endif
+ // Data Wishbone master
+ D_DAT_I,
+ D_ACK_I,
+ D_ERR_I,
+ D_RTY_I,
+ // ----- Outputs -------
+`ifdef CFG_TRACE_ENABLED
+ trace_pc,
+ trace_pc_valid,
+ trace_exception,
+ trace_eid,
+ trace_eret,
+`ifdef CFG_DEBUG_ENABLED
+ trace_bret,
+`endif
+`endif
+`ifdef CFG_JTAG_ENABLED
+ jtag_reg_d,
+ jtag_reg_addr_d,
+`endif
+`ifdef CFG_USER_ENABLED
+ user_valid,
+ user_opcode,
+ user_operand_0,
+ user_operand_1,
+`endif
+`ifdef CFG_IWB_ENABLED
+ // Instruction Wishbone master
+ I_DAT_O,
+ I_ADR_O,
+ I_CYC_O,
+ I_SEL_O,
+ I_STB_O,
+ I_WE_O,
+ I_CTI_O,
+ I_LOCK_O,
+ I_BTE_O,
+`endif
+ // Data Wishbone master
+ D_DAT_O,
+ D_ADR_O,
+ D_CYC_O,
+ D_SEL_O,
+ D_STB_O,
+ D_WE_O,
+ D_CTI_O,
+ D_LOCK_O,
+ D_BTE_O
+ );
+
+/////////////////////////////////////////////////////
+// Parameters
+/////////////////////////////////////////////////////
+
+parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR
+`ifdef CFG_DEBUG_ENABLED
+parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR
+`endif
+
+`ifdef CFG_ICACHE_ENABLED
+parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
+parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets
+parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line
+parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory
+parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory
+`else
+parameter icache_associativity = 1;
+parameter icache_sets = 512;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 0;
+parameter icache_limit = 0;
+`endif
+
+`ifdef CFG_DCACHE_ENABLED
+parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
+parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets
+parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line
+parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory
+parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory
+`else
+parameter dcache_associativity = 1;
+parameter dcache_sets = 512;
+parameter dcache_bytes_per_line = 16;
+parameter dcache_base_address = 0;
+parameter dcache_limit = 0;
+`endif
+
+`ifdef CFG_DEBUG_ENABLED
+parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs
+`else
+parameter watchpoints = 4'h0;
+`endif
+`ifdef CFG_ROM_DEBUG_ENABLED
+parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs
+`else
+parameter breakpoints = 4'h0;
+`endif
+
+`ifdef CFG_INTERRUPTS_ENABLED
+parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
+`else
+parameter interrupts = 0;
+`endif
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
+input clk_n_i; // Inverted clock
+`endif
+input rst_i; // Reset
+
+`ifdef CFG_INTERRUPTS_ENABLED
+input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
+`endif
+
+`ifdef CFG_USER_ENABLED
+input [`LM32_WORD_RNG] user_result; // User-defined instruction result
+input user_complete; // User-defined instruction execution is complete
+`endif
+
+`ifdef CFG_JTAG_ENABLED
+input jtag_clk; // JTAG clock
+input jtag_update; // JTAG state machine is in data register update state
+input [`LM32_BYTE_RNG] jtag_reg_q;
+input [2:0] jtag_reg_addr_q;
+`endif
+
+`ifdef CFG_IWB_ENABLED
+input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
+input I_ACK_I; // Instruction Wishbone interface acknowledgement
+input I_ERR_I; // Instruction Wishbone interface error
+input I_RTY_I; // Instruction Wishbone interface retry
+`endif
+
+input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
+input D_ACK_I; // Data Wishbone interface acknowledgement
+input D_ERR_I; // Data Wishbone interface error
+input D_RTY_I; // Data Wishbone interface retry
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+`ifdef CFG_TRACE_ENABLED
+output [`LM32_PC_RNG] trace_pc; // PC to trace
+reg [`LM32_PC_RNG] trace_pc;
+output trace_pc_valid; // Indicates that a new trace PC is valid
+reg trace_pc_valid;
+output trace_exception; // Indicates an exception has occured
+reg trace_exception;
+output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
+reg [`LM32_EID_RNG] trace_eid;
+output trace_eret; // Indicates an eret instruction has been executed
+reg trace_eret;
+`ifdef CFG_DEBUG_ENABLED
+output trace_bret; // Indicates a bret instruction has been executed
+reg trace_bret;
+`endif
+`endif
+
+`ifdef CFG_JTAG_ENABLED
+output [`LM32_BYTE_RNG] jtag_reg_d;
+wire [`LM32_BYTE_RNG] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
+`endif
+
+`ifdef CFG_USER_ENABLED
+output user_valid; // Indicates if user_opcode is valid
+wire user_valid;
+output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
+reg [`LM32_USER_OPCODE_RNG] user_opcode;
+output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
+wire [`LM32_WORD_RNG] user_operand_0;
+output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
+wire [`LM32_WORD_RNG] user_operand_1;
+`endif
+
+`ifdef CFG_IWB_ENABLED
+output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
+wire [`LM32_WORD_RNG] I_DAT_O;
+output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
+wire [`LM32_WORD_RNG] I_ADR_O;
+output I_CYC_O; // Instruction Wishbone interface cycle
+wire I_CYC_O;
+output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
+wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
+output I_STB_O; // Instruction Wishbone interface strobe
+wire I_STB_O;
+output I_WE_O; // Instruction Wishbone interface write enable
+wire I_WE_O;
+output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] I_CTI_O;
+output I_LOCK_O; // Instruction Wishbone interface lock bus
+wire I_LOCK_O;
+output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] I_BTE_O;
+`endif
+
+output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
+wire [`LM32_WORD_RNG] D_DAT_O;
+output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
+wire [`LM32_WORD_RNG] D_ADR_O;
+output D_CYC_O; // Data Wishbone interface cycle
+wire D_CYC_O;
+output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
+wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
+output D_STB_O; // Data Wishbone interface strobe
+wire D_STB_O;
+output D_WE_O; // Data Wishbone interface write enable
+wire D_WE_O;
+output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] D_CTI_O;
+output D_LOCK_O; // Date Wishbone interface lock bus
+wire D_LOCK_O;
+output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] D_BTE_O;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+// Pipeline registers
+
+`ifdef LM32_CACHE_ENABLED
+reg valid_a; // Instruction in A stage is valid
+`endif
+reg valid_f; // Instruction in F stage is valid
+reg valid_d; // Instruction in D stage is valid
+reg valid_x; // Instruction in X stage is valid
+reg valid_m; // Instruction in M stage is valid
+reg valid_w; // Instruction in W stage is valid
+
+wire [`LM32_WORD_RNG] immediate_d; // Immediate operand
+wire load_d; // Indicates a load instruction
+reg load_x;
+reg load_m;
+wire store_d; // Indicates a store instruction
+reg store_x;
+reg store_m;
+wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word)
+reg [`LM32_SIZE_RNG] size_x;
+wire branch_d; // Indicates a branch instruction
+reg branch_x;
+reg branch_m;
+wire branch_reg_d; // Branch to register or immediate
+wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches
+reg [`LM32_PC_RNG] branch_target_x; // Address to branch to
+reg [`LM32_PC_RNG] branch_target_m;
+wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
+wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
+
+wire x_result_sel_csr_d; // Select X stage result from CSRs
+reg x_result_sel_csr_x;
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit
+reg x_result_sel_mc_arith_x;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+wire x_result_sel_shift_d; // Select X stage result from shifter
+reg x_result_sel_shift_x;
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+wire x_result_sel_sext_d; // Select X stage result from sign-extend logic
+reg x_result_sel_sext_x;
+`endif
+wire x_result_sel_logic_d; // Select X stage result from logic op unit
+reg x_result_sel_logic_x;
+`ifdef CFG_USER_ENABLED
+wire x_result_sel_user_d; // Select X stage result from user-defined logic
+reg x_result_sel_user_x;
+`endif
+wire x_result_sel_add_d; // Select X stage result from adder
+reg x_result_sel_add_x;
+wire m_result_sel_compare_d; // Select M stage result from comparison logic
+reg m_result_sel_compare_x;
+reg m_result_sel_compare_m;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+wire m_result_sel_shift_d; // Select M stage result from shifter
+reg m_result_sel_shift_x;
+reg m_result_sel_shift_m;
+`endif
+wire w_result_sel_load_d; // Select W stage result from load/store unit
+reg w_result_sel_load_x;
+reg w_result_sel_load_m;
+reg w_result_sel_load_w;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+wire w_result_sel_mul_d; // Select W stage result from multiplier
+reg w_result_sel_mul_x;
+reg w_result_sel_mul_m;
+reg w_result_sel_mul_w;
+`endif
+wire x_bypass_enable_d; // Whether result is bypassable in X stage
+reg x_bypass_enable_x;
+wire m_bypass_enable_d; // Whether result is bypassable in M stage
+reg m_bypass_enable_x;
+reg m_bypass_enable_m;
+wire sign_extend_d; // Whether to sign-extend or zero-extend
+reg sign_extend_x;
+wire write_enable_d; // Register file write enable
+reg write_enable_x;
+wire write_enable_q_x;
+reg write_enable_m;
+wire write_enable_q_m;
+reg write_enable_w;
+wire write_enable_q_w;
+wire read_enable_0_d; // Register file read enable 0
+wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0
+wire read_enable_1_d; // Register file read enable 1
+wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1
+wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index
+reg [`LM32_REG_IDX_RNG] write_idx_x;
+reg [`LM32_REG_IDX_RNG] write_idx_m;
+reg [`LM32_REG_IDX_RNG] write_idx_w;
+wire [`LM32_CSR_RNG] csr_d; // CSR read/write index
+reg [`LM32_CSR_RNG] csr_x;
+wire [`LM32_CONDITION_RNG] condition_d; // Branch condition
+reg [`LM32_CONDITION_RNG] condition_x;
+`ifdef CFG_DEBUG_ENABLED
+wire break_d; // Indicates a break instruction
+reg break_x;
+`endif
+wire scall_d; // Indicates a scall instruction
+reg scall_x;
+wire eret_d; // Indicates an eret instruction
+reg eret_x;
+wire eret_q_x;
+reg eret_m;
+`ifdef CFG_TRACE_ENABLED
+reg eret_w;
+`endif
+`ifdef CFG_DEBUG_ENABLED
+wire bret_d; // Indicates a bret instruction
+reg bret_x;
+wire bret_q_x;
+reg bret_m;
+`ifdef CFG_TRACE_ENABLED
+reg bret_w;
+`endif
+`endif
+wire csr_write_enable_d; // CSR write enable
+reg csr_write_enable_x;
+wire csr_write_enable_q_x;
+`ifdef CFG_USER_ENABLED
+wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode
+`endif
+
+`ifdef CFG_BUS_ERRORS_ENABLED
+wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage
+reg bus_error_x;
+`endif
+
+reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0)
+reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1)
+reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage
+reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage
+reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage
+
+reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction
+reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction
+reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
+reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction
+reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction
+
+// To/from register file
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+wire [`LM32_WORD_RNG] reg_data_live_0;
+wire [`LM32_WORD_RNG] reg_data_live_1;
+reg use_buf; // Whether to use reg_data_live or reg_data_buf
+reg [`LM32_WORD_RNG] reg_data_buf_0;
+reg [`LM32_WORD_RNG] reg_data_buf_1;
+`endif
+`ifdef LM32_EBR_REGISTER_FILE
+`else
+reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file
+`endif
+wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data
+wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data
+reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing
+reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing
+wire reg_write_enable_q_w;
+
+reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard
+
+wire stall_a; // Stall instruction in A pipeline stage
+wire stall_f; // Stall instruction in F pipeline stage
+wire stall_d; // Stall instruction in D pipeline stage
+wire stall_x; // Stall instruction in X pipeline stage
+wire stall_m; // Stall instruction in M pipeline stage
+
+// To/from adder
+wire adder_op_d; // Whether to add or subtract
+reg adder_op_x;
+reg adder_op_x_n; // Inverted version of adder_op_x
+wire [`LM32_WORD_RNG] adder_result_x; // Result from adder
+wire adder_overflow_x; // Whether a signed overflow occured
+wire adder_carry_n_x; // Whether a carry was generated
+
+// To/from logical operations unit
+wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform
+reg [`LM32_LOGIC_OP_RNG] logic_op_x;
+wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation
+
+`ifdef CFG_SIGN_EXTEND_ENABLED
+// From sign-extension unit
+wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension
+wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion
+wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction
+`endif
+
+// To/from shifter
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+`ifdef CFG_ROTATE_ENABLED
+wire rotate_d; // Whether we should rotate or shift
+reg rotate_x;
+`endif
+wire direction_d; // Which direction to shift in
+reg direction_x;
+reg direction_m;
+wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+wire shift_left_d; // Indicates whether to perform a left shift or not
+wire shift_left_q_d;
+wire shift_right_d; // Indicates whether to perform a right shift or not
+wire shift_right_q_d;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter
+`endif
+
+// To/from multiplier
+`ifdef LM32_MULTIPLY_ENABLED
+wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+wire multiply_d; // Indicates whether to perform a multiply or not
+wire multiply_q_d;
+`endif
+
+// To/from divider
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire divide_d; // Indicates whether to perform a divider or not
+wire divide_q_d;
+wire modulus_d;
+wire modulus_q_d;
+wire divide_by_zero_x; // Indicates an attempt was made to divide by zero
+`endif
+
+// To from multi-cycle arithmetic unit
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request
+wire [`LM32_WORD_RNG] mc_result_x;
+`endif
+
+// From CSRs
+`ifdef CFG_INTERRUPTS_ENABLED
+wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
+`endif
+wire [`LM32_WORD_RNG] cfg; // Configuration CSR
+`ifdef CFG_CYCLE_COUNTER_ENABLED
+reg [`LM32_WORD_RNG] cc; // Cycle counter CSR
+`endif
+reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs
+
+// To/from instruction unit
+wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage
+wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage
+wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage
+wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage
+wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage
+`ifdef CFG_TRACE_ENABLED
+reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction
+`endif
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage
+`endif
+wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage
+`ifdef CFG_ICACHE_ENABLED
+wire iflush; // Flush instruction cache
+wire icache_stall_request; // Stall pipeline because instruction cache is busy
+wire icache_restart_request; // Restart instruction that caused an instruction cache miss
+wire icache_refill_request; // Request to refill instruction cache
+wire icache_refilling; // Indicates the instruction cache is being refilled
+`endif
+
+// To/from load/store unit
+`ifdef CFG_DCACHE_ENABLED
+wire dflush_x; // Flush data cache
+reg dflush_m;
+wire dcache_stall_request; // Stall pipeline because data cache is busy
+wire dcache_restart_request; // Restart instruction that caused a data cache miss
+wire dcache_refill_request; // Request to refill data cache
+wire dcache_refilling; // Indicates the data cache is being refilled
+`endif
+wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
+wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface
+
+// To/from JTAG interface
+`ifdef CFG_JTAG_ENABLED
+`ifdef CFG_JTAG_UART_ENABLED
+wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR
+wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+wire jtag_csr_write_enable; // Debugger CSR write enable
+wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
+wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
+wire jtag_read_enable;
+wire [`LM32_BYTE_RNG] jtag_read_data;
+wire jtag_write_enable;
+wire [`LM32_BYTE_RNG] jtag_write_data;
+wire [`LM32_WORD_RNG] jtag_address;
+wire jtag_access_complete;
+`endif
+`ifdef CFG_DEBUG_ENABLED
+wire jtag_break; // Request from debugger to raise a breakpoint
+`endif
+`endif
+
+// Hazzard detection
+wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0
+wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1
+wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0
+wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1
+wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0
+wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1
+
+// Control flow
+wire cmp_zero; // Result of comparison is zero
+wire cmp_negative; // Result of comparison is negative
+wire cmp_overflow; // Comparison produced an overflow
+wire cmp_carry_n; // Comparison produced a carry, inverted
+reg condition_met_x; // Condition of branch instruction is met
+reg condition_met_m;
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+wire branch_taken_x; // Branch is taken in X stage
+`endif
+wire branch_taken_m; // Branch is taken in M stage
+
+wire kill_f; // Kill instruction in F stage
+wire kill_d; // Kill instruction in D stage
+wire kill_x; // Kill instruction in X stage
+wire kill_m; // Kill instruction in M stage
+wire kill_w; // Kill instruction in W stage
+
+reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR
+`ifdef CFG_DEBUG_ENABLED
+reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR
+`endif
+reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage
+`ifdef CFG_TRACE_ENABLED
+reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage
+reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage
+`endif
+
+`ifdef CFG_DEBUG_ENABLED
+`ifdef LM32_SINGLE_STEP_ENABLED
+wire dc_ss; // Is single-step enabled
+`endif
+wire dc_re; // Remap all exceptions
+wire exception_x; // An exception occured in the X stage
+reg exception_m; // An instruction that caused an exception is in the M stage
+wire debug_exception_x; // Indicates if a debug exception has occured
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x; // Indicates if a non debug exception has occured
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
+`else
+wire exception_x; // Indicates if a debug exception has occured
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+`endif
+
+`ifdef CFG_DEBUG_ENABLED
+`ifdef CFG_JTAG_ENABLED
+wire reset_exception; // Indicates if a reset exception has occured
+`endif
+`endif
+`ifdef CFG_INTERRUPTS_ENABLED
+wire interrupt_exception; // Indicates if an interrupt exception has occured
+`endif
+`ifdef CFG_DEBUG_ENABLED
+wire breakpoint_exception; // Indicates if a breakpoint exception has occured
+wire watchpoint_exception; // Indicates if a watchpoint exception has occured
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured
+wire data_bus_error_exception; // Indicates if a data bus error exception has occured
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured
+`endif
+wire system_call_exception; // Indicates if a system call exception has occured
+
+`ifdef CFG_BUS_ERRORS_ENABLED
+reg data_bus_error_seen; // Indicates if a data bus error was seen
+`endif
+
+/////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////
+`define INCLUDE_FUNCTION
+`include "lm32_functions.v"
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+// Instruction unit
+lm32_instruction_unit #(
+ .associativity (icache_associativity),
+ .sets (icache_sets),
+ .bytes_per_line (icache_bytes_per_line),
+ .base_address (icache_base_address),
+ .limit (icache_limit)
+ ) instruction_unit (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ // From pipeline
+ .stall_a (stall_a),
+ .stall_f (stall_f),
+ .stall_d (stall_d),
+ .stall_x (stall_x),
+ .stall_m (stall_m),
+ .valid_f (valid_f),
+ .kill_f (kill_f),
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+ .branch_taken_x (branch_taken_x),
+ .branch_target_x (branch_target_x),
+`endif
+ .branch_taken_m (branch_taken_m),
+ .branch_target_m (branch_target_m),
+`ifdef CFG_ICACHE_ENABLED
+ .iflush (iflush),
+`endif
+`ifdef CFG_DCACHE_ENABLED
+ .dcache_restart_request (dcache_restart_request),
+ .dcache_refill_request (dcache_refill_request),
+ .dcache_refilling (dcache_refilling),
+`endif
+`ifdef CFG_IWB_ENABLED
+ // From Wishbone
+ .i_dat_i (I_DAT_I),
+ .i_ack_i (I_ACK_I),
+ .i_err_i (I_ERR_I),
+ .i_rty_i (I_RTY_I),
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
+`endif
+ // ----- Outputs -------
+ // To pipeline
+ .pc_f (pc_f),
+ .pc_d (pc_d),
+ .pc_x (pc_x),
+ .pc_m (pc_m),
+ .pc_w (pc_w),
+`ifdef CFG_ICACHE_ENABLED
+ .icache_stall_request (icache_stall_request),
+ .icache_restart_request (icache_restart_request),
+ .icache_refill_request (icache_refill_request),
+ .icache_refilling (icache_refilling),
+`endif
+`ifdef CFG_IWB_ENABLED
+ // To Wishbone
+ .i_dat_o (I_DAT_O),
+ .i_adr_o (I_ADR_O),
+ .i_cyc_o (I_CYC_O),
+ .i_sel_o (I_SEL_O),
+ .i_stb_o (I_STB_O),
+ .i_we_o (I_WE_O),
+ .i_cti_o (I_CTI_O),
+ .i_lock_o (I_LOCK_O),
+ .i_bte_o (I_BTE_O),
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+ .bus_error_d (bus_error_d),
+`endif
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+ .instruction_f (instruction_f),
+`endif
+ .instruction_d (instruction_d)
+ );
+
+// Trace instructions in simulation
+lm32_simtrace simtrace (
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_x (stall_x),
+ .stall_m (stall_m),
+ .valid_w (valid_w),
+ .kill_w (kill_w),
+ .instruction_d (instruction_d),
+ .pc_w (pc_w)
+ );
+
+// Instruction decoder
+lm32_decoder decoder (
+ // ----- Inputs -------
+ .instruction (instruction_d),
+ // ----- Outputs -------
+ .d_result_sel_0 (d_result_sel_0_d),
+ .d_result_sel_1 (d_result_sel_1_d),
+ .x_result_sel_csr (x_result_sel_csr_d),
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+ .x_result_sel_mc_arith (x_result_sel_mc_arith_d),
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+ .x_result_sel_shift (x_result_sel_shift_d),
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+ .x_result_sel_sext (x_result_sel_sext_d),
+`endif
+ .x_result_sel_logic (x_result_sel_logic_d),
+`ifdef CFG_USER_ENABLED
+ .x_result_sel_user (x_result_sel_user_d),
+`endif
+ .x_result_sel_add (x_result_sel_add_d),
+ .m_result_sel_compare (m_result_sel_compare_d),
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ .m_result_sel_shift (m_result_sel_shift_d),
+`endif
+ .w_result_sel_load (w_result_sel_load_d),
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ .w_result_sel_mul (w_result_sel_mul_d),
+`endif
+ .x_bypass_enable (x_bypass_enable_d),
+ .m_bypass_enable (m_bypass_enable_d),
+ .read_enable_0 (read_enable_0_d),
+ .read_idx_0 (read_idx_0_d),
+ .read_enable_1 (read_enable_1_d),
+ .read_idx_1 (read_idx_1_d),
+ .write_enable (write_enable_d),
+ .write_idx (write_idx_d),
+ .immediate (immediate_d),
+ .branch_offset (branch_offset_d),
+ .load (load_d),
+ .store (store_d),
+ .size (size_d),
+ .sign_extend (sign_extend_d),
+ .adder_op (adder_op_d),
+ .logic_op (logic_op_d),
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ .direction (direction_d),
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ .shift_left (shift_left_d),
+ .shift_right (shift_right_d),
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+ .multiply (multiply_d),
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+ .divide (divide_d),
+ .modulus (modulus_d),
+`endif
+ .branch (branch_d),
+ .branch_reg (branch_reg_d),
+ .condition (condition_d),
+`ifdef CFG_DEBUG_ENABLED
+ .break (break_d),
+`endif
+ .scall (scall_d),
+ .eret (eret_d),
+`ifdef CFG_DEBUG_ENABLED
+ .bret (bret_d),
+`endif
+`ifdef CFG_USER_ENABLED
+ .user_opcode (user_opcode_d),
+`endif
+ .csr_write_enable (csr_write_enable_d)
+ );
+wire load_q_x,load_q_m,store_q_m;
+
+// Load/store unit
+lm32_load_store_unit #(
+ .associativity (dcache_associativity),
+ .sets (dcache_sets),
+ .bytes_per_line (dcache_bytes_per_line),
+ .base_address (dcache_base_address),
+ .limit (dcache_limit)
+ ) load_store_unit (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ // From pipeline
+ .stall_a (stall_a),
+ .stall_x (stall_x),
+ .stall_m (stall_m),
+ .kill_x (kill_x),
+ .kill_m (kill_m),
+ .exception_m (exception_m),
+ .store_operand_x (store_operand_x),
+ .load_store_address_x (adder_result_x),
+ .load_store_address_m (operand_m),
+ .load_store_address_w (operand_w[1:0]),
+ .load_q_x (load_q_x),
+ .load_q_m (load_q_m),
+ .store_q_m (store_q_m),
+ .sign_extend_x (sign_extend_x),
+ .size_x (size_x),
+`ifdef CFG_DCACHE_ENABLED
+ .dflush (dflush_m),
+`endif
+ // From Wishbone
+ .d_dat_i (D_DAT_I),
+ .d_ack_i (D_ACK_I),
+ .d_err_i (D_ERR_I),
+ .d_rty_i (D_RTY_I),
+ // ----- Outputs -------
+ // To pipeline
+`ifdef CFG_DCACHE_ENABLED
+ .dcache_refill_request (dcache_refill_request),
+ .dcache_restart_request (dcache_restart_request),
+ .dcache_stall_request (dcache_stall_request),
+ .dcache_refilling (dcache_refilling),
+`endif
+ .load_data_w (load_data_w),
+ .stall_wb_load (stall_wb_load),
+ // To Wishbone
+ .d_dat_o (D_DAT_O),
+ .d_adr_o (D_ADR_O),
+ .d_cyc_o (D_CYC_O),
+ .d_sel_o (D_SEL_O),
+ .d_stb_o (D_STB_O),
+ .d_we_o (D_WE_O),
+ .d_cti_o (D_CTI_O),
+ .d_lock_o (D_LOCK_O),
+ .d_bte_o (D_BTE_O)
+ );
+
+// Adder
+lm32_adder adder (
+ // ----- Inputs -------
+ .adder_op_x (adder_op_x),
+ .adder_op_x_n (adder_op_x_n),
+ .operand_0_x (operand_0_x),
+ .operand_1_x (operand_1_x),
+ // ----- Outputs -------
+ .adder_result_x (adder_result_x),
+ .adder_carry_n_x (adder_carry_n_x),
+ .adder_overflow_x (adder_overflow_x)
+ );
+
+// Logic operations
+lm32_logic_op logic_op (
+ // ----- Inputs -------
+ .logic_op_x (logic_op_x),
+ .operand_0_x (operand_0_x),
+
+ .operand_1_x (operand_1_x),
+ // ----- Outputs -------
+ .logic_result_x (logic_result_x)
+ );
+
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+// Pipelined barrel-shifter
+lm32_shifter shifter (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_x (stall_x),
+ .direction_x (direction_x),
+ .sign_extend_x (sign_extend_x),
+ .operand_0_x (operand_0_x),
+ .operand_1_x (operand_1_x),
+ // ----- Outputs -------
+ .shifter_result_m (shifter_result_m)
+ );
+`endif
+
+`ifdef CFG_PL_MULTIPLY_ENABLED
+// Pipeline fixed-point multiplier
+lm32_multiplier multiplier (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_x (stall_x),
+ .stall_m (stall_m),
+ .operand_0 (d_result_0),
+ .operand_1 (d_result_1),
+ // ----- Outputs -------
+ .result (multiplier_result_w)
+ );
+`endif
+
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+// Multi-cycle arithmetic
+lm32_mc_arithmetic mc_arithmetic (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_d (stall_d),
+ .kill_x (kill_x),
+`ifdef CFG_MC_DIVIDE_ENABLED
+ .divide_d (divide_q_d),
+ .modulus_d (modulus_q_d),
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+ .multiply_d (multiply_q_d),
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ .shift_left_d (shift_left_q_d),
+ .shift_right_d (shift_right_q_d),
+ .sign_extend_d (sign_extend_d),
+`endif
+ .operand_0_d (d_result_0),
+ .operand_1_d (d_result_1),
+ // ----- Outputs -------
+ .result_x (mc_result_x),
+`ifdef CFG_MC_DIVIDE_ENABLED
+ .divide_by_zero_x (divide_by_zero_x),
+`endif
+ .stall_request_x (mc_stall_request_x)
+ );
+`endif
+
+`ifdef CFG_INTERRUPTS_ENABLED
+// Interrupt unit
+lm32_interrupt interrupt (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ // From external devices
+ .interrupt_n (interrupt_n),
+ // From pipeline
+ .stall_x (stall_x),
+`ifdef CFG_DEBUG_ENABLED
+ .non_debug_exception (non_debug_exception_q_w),
+ .debug_exception (debug_exception_q_w),
+`else
+ .exception (exception_q_w),
+`endif
+ .eret_q_x (eret_q_x),
+`ifdef CFG_DEBUG_ENABLED
+ .bret_q_x (bret_q_x),
+`endif
+ .csr (csr_x),
+ .csr_write_data (operand_1_x),
+ .csr_write_enable (csr_write_enable_q_x),
+ // ----- Outputs -------
+ .interrupt_exception (interrupt_exception),
+ // To pipeline
+ .csr_read_data (interrupt_csr_read_data_x)
+ );
+`endif
+
+`ifdef CFG_JTAG_ENABLED
+// JTAG interface
+lm32_jtag jtag (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ // From JTAG
+ .jtag_clk (jtag_clk),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+ // From pipeline
+`ifdef CFG_JTAG_UART_ENABLED
+ .csr (csr_x),
+ .csr_write_data (operand_1_x),
+ .csr_write_enable (csr_write_enable_q_x),
+ .stall_x (stall_x),
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
+`endif
+ // ----- Outputs -------
+ // To pipeline
+`ifdef CFG_JTAG_UART_ENABLED
+ .jtx_csr_read_data (jtx_csr_read_data),
+ .jrx_csr_read_data (jrx_csr_read_data),
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ .jtag_break (jtag_break),
+ .jtag_reset (reset_exception),
+`endif
+ // To JTAG
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d)
+ );
+`endif
+
+`ifdef CFG_DEBUG_ENABLED
+// Debug unit
+lm32_debug #(
+ .breakpoints (breakpoints),
+ .watchpoints (watchpoints)
+ ) hw_debug (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .pc_x (pc_x),
+ .load_x (load_x),
+ .store_x (store_x),
+ .load_store_address_x (adder_result_x),
+ .csr_write_enable_x (csr_write_enable_q_x),
+ .csr_write_data (operand_1_x),
+ .csr_x (csr_x),
+`ifdef CFG_HW_DEBUG_ENABLED
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
+`endif
+`ifdef LM32_SINGLE_STEP_ENABLED
+ .eret_q_x (eret_q_x),
+ .bret_q_x (bret_q_x),
+ .stall_x (stall_x),
+ .exception_x (exception_x),
+ .q_x (q_x),
+`ifdef CFG_DCACHE_ENABLED
+ .dcache_refill_request (dcache_refill_request),
+`endif
+`endif
+ // ----- Outputs -------
+`ifdef LM32_SINGLE_STEP_ENABLED
+ .dc_ss (dc_ss),
+`endif
+ .dc_re (dc_re),
+ .bp_match (bp_match),
+ .wp_match (wp_match)
+ );
+`endif
+
+// Register file
+
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+
+lm32_ram #(
+ // ----- Parameters -------
+ .data_width (`LM32_WORD_WIDTH),
+ .address_width (`LM32_REG_IDX_WIDTH)
+ ) reg_0 (
+ // ----- Inputs -------
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .enable_read (stall_d == `FALSE),
+ .read_address (instruction_f[25:21]),
+ .enable_write (`TRUE),
+ .write_address (write_idx_w),
+ .write_data (w_result),
+ .write_enable (reg_write_enable_q_w),
+ // ----- Outputs -------
+ .read_data (reg_data_live_0)
+ );
+
+lm32_ram #(
+ // ----- Parameters -------
+ .data_width (`LM32_WORD_WIDTH),
+ .address_width (`LM32_REG_IDX_WIDTH)
+ ) reg_1 (
+ // ----- Inputs -------
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .enable_read (stall_d == `FALSE),
+ .read_address (instruction_f[20:16]),
+ .enable_write (`TRUE),
+ .write_address (write_idx_w),
+ .write_data (w_result),
+ .write_enable (reg_write_enable_q_w),
+ // ----- Outputs -------
+ .read_data (reg_data_live_1)
+ );
+
+`endif
+
+`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
+
+lm32_ram #(
+ // ----- Parameters -------
+ .data_width (`LM32_WORD_WIDTH),
+ .address_width (`LM32_REG_IDX_WIDTH)
+ ) reg_0 (
+ // ----- Inputs -------
+ .read_clk (clk_n_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .enable_read (stall_f == `FALSE),
+ .read_address (read_idx_0_d),
+ .enable_write (`TRUE),
+ .write_address (write_idx_w),
+ .write_data (w_result),
+ .write_enable (reg_write_enable_q_w),
+ // ----- Outputs -------
+ .read_data (reg_data_0)
+ );
+
+lm32_ram #(
+ // ----- Parameters -------
+ .data_width (`LM32_WORD_WIDTH),
+ .address_width (`LM32_REG_IDX_WIDTH)
+ ) reg_1 (
+ // ----- Inputs -------
+ .read_clk (clk_n_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .enable_read (stall_f == `FALSE),
+ .read_address (read_idx_1_d),
+ .enable_write (`TRUE),
+ .write_address (write_idx_w),
+ .write_data (w_result),
+ .write_enable (reg_write_enable_q_w),
+ // ----- Outputs -------
+ .read_data (reg_data_1)
+ );
+
+`endif
+
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+// Select between buffered and live data from register file
+assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
+assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
+`endif
+`ifdef LM32_EBR_REGISTER_FILE
+`else
+// Register file read ports
+assign reg_data_0 = registers[read_idx_0_d];
+assign reg_data_1 = registers[read_idx_1_d];
+`endif
+
+// Detect read-after-write hazzards
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
+
+// Interlock detection - Raise an interlock for RAW hazzards
+always @*
+begin
+ if ( ( (x_bypass_enable_x == `FALSE)
+ && ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
+ || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
+ )
+ )
+ || ( (m_bypass_enable_m == `FALSE)
+ && ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
+ || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
+ )
+ )
+ )
+ interlock = `TRUE;
+ else
+ interlock = `FALSE;
+end
+
+// Bypass for reg port 0
+always @*
+begin
+ if (raw_x_0 == `TRUE)
+ bypass_data_0 = x_result;
+ else if (raw_m_0 == `TRUE)
+ bypass_data_0 = m_result;
+ else if (raw_w_0 == `TRUE)
+ bypass_data_0 = w_result;
+ else
+ bypass_data_0 = reg_data_0;
+end
+
+// Bypass for reg port 1
+always @*
+begin
+ if (raw_x_1 == `TRUE)
+ bypass_data_1 = x_result;
+ else if (raw_m_1 == `TRUE)
+ bypass_data_1 = m_result;
+ else if (raw_w_1 == `TRUE)
+ bypass_data_1 = w_result;
+ else
+ bypass_data_1 = reg_data_1;
+end
+
+// D stage result selection
+always @*
+begin
+ d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
+ case (d_result_sel_1_d)
+ `LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
+ `LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1;
+ `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
+ default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
+ endcase
+end
+
+`ifdef CFG_USER_ENABLED
+// Operands for user-defined instructions
+assign user_operand_0 = operand_0_x;
+assign user_operand_1 = operand_1_x;
+`endif
+
+`ifdef CFG_SIGN_EXTEND_ENABLED
+// Sign-extension
+assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
+assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
+assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
+`endif
+
+`ifdef LM32_NO_BARREL_SHIFT
+// Only single bit shift operations are supported when barrel-shifter isn't implemented
+assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
+`endif
+
+// Condition evaluation
+assign cmp_zero = operand_0_x == operand_1_x;
+assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
+assign cmp_overflow = adder_overflow_x;
+assign cmp_carry_n = adder_carry_n_x;
+always @*
+begin
+ case (condition_x)
+ `LM32_CONDITION_U1: condition_met_x = `TRUE;
+ `LM32_CONDITION_U2: condition_met_x = `TRUE;
+ `LM32_CONDITION_E: condition_met_x = cmp_zero;
+ `LM32_CONDITION_NE: condition_met_x = !cmp_zero;
+ `LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+ `LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero;
+ `LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow;
+ `LM32_CONDITION_GEU: condition_met_x = cmp_carry_n;
+ default: condition_met_x = 1'bx;
+ endcase
+end
+
+// X stage result selection
+always @*
+begin
+ x_result = x_result_sel_add_x ? adder_result_x
+ : x_result_sel_csr_x ? csr_read_data_x
+`ifdef CFG_SIGN_EXTEND_ENABLED
+ : x_result_sel_sext_x ? sext_result_x
+`endif
+`ifdef CFG_USER_ENABLED
+ : x_result_sel_user_x ? user_result
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+ : x_result_sel_shift_x ? shifter_result_x
+`endif
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+ : x_result_sel_mc_arith_x ? mc_result_x
+`endif
+ : logic_result_x;
+end
+
+// M stage result selection
+always @*
+begin
+ m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ : m_result_sel_shift_m ? shifter_result_m
+`endif
+ : operand_m;
+end
+
+// W stage result selection
+always @*
+begin
+ w_result = w_result_sel_load_w ? load_data_w
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ : w_result_sel_mul_w ? multiplier_result_w
+`endif
+ : operand_w;
+end
+
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+// Indicate when a branch should be taken in X stage
+assign branch_taken_x = (stall_x == `FALSE)
+ && ( (branch_x == `TRUE)
+ && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
+ && (valid_x == `TRUE)
+ );
+`endif
+
+// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
+assign branch_taken_m = (stall_m == `FALSE)
+ && ( ( (branch_m == `TRUE)
+ && (condition_met_m == `TRUE)
+ && (valid_m == `TRUE)
+ )
+ || (exception_m == `TRUE)
+ );
+
+// Generate signal that will kill instructions in each pipeline stage when necessary
+assign kill_f = (branch_taken_m == `TRUE)
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+ || (branch_taken_x == `TRUE)
+`endif
+`ifdef CFG_ICACHE_ENABLED
+ || (icache_refill_request == `TRUE)
+`endif
+`ifdef CFG_DCACHE_ENABLED
+ || (dcache_refill_request == `TRUE)
+`endif
+ ;
+assign kill_d = (branch_taken_m == `TRUE)
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+ || (branch_taken_x == `TRUE)
+`endif
+`ifdef CFG_ICACHE_ENABLED
+ || (icache_refill_request == `TRUE)
+`endif
+`ifdef CFG_DCACHE_ENABLED
+ || (dcache_refill_request == `TRUE)
+`endif
+ ;
+assign kill_x = (branch_taken_m == `TRUE)
+`ifdef CFG_DCACHE_ENABLED
+ || (dcache_refill_request == `TRUE)
+`endif
+ ;
+assign kill_m = `FALSE
+`ifdef CFG_DCACHE_ENABLED
+ || (dcache_refill_request == `TRUE)
+`endif
+ ;
+assign kill_w = `FALSE
+`ifdef CFG_DCACHE_ENABLED
+ || (dcache_refill_request == `TRUE)
+`endif
+ ;
+
+// Exceptions
+
+`ifdef CFG_DEBUG_ENABLED
+assign breakpoint_exception = (break_x == `TRUE)
+ || (bp_match == `TRUE)
+`ifdef CFG_JTAG_ENABLED
+ || (jtag_break == `TRUE)
+`endif
+ ;
+assign watchpoint_exception = wp_match == `TRUE;
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+assign instruction_bus_error_exception = bus_error_x == `TRUE;
+assign data_bus_error_exception = data_bus_error_seen == `TRUE;
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
+`endif
+assign system_call_exception = scall_x == `TRUE;
+
+`ifdef CFG_DEBUG_ENABLED
+assign debug_exception_x = (breakpoint_exception == `TRUE)
+ || (watchpoint_exception == `TRUE)
+ ;
+
+assign non_debug_exception_x = (system_call_exception == `TRUE)
+`ifdef CFG_JTAG_ENABLED
+ || (reset_exception == `TRUE)
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+ || (instruction_bus_error_exception == `TRUE)
+ || (data_bus_error_exception == `TRUE)
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+ || (divide_by_zero_exception == `TRUE)
+`endif
+`ifdef CFG_INTERRUPTS_ENABLED
+ || ( (interrupt_exception == `TRUE)
+`ifdef LM32_SINGLE_STEP_ENABLED
+ && (dc_ss == `FALSE)
+`endif
+ )
+`endif
+ ;
+
+assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
+`else
+assign exception_x = (system_call_exception == `TRUE)
+`ifdef CFG_BUS_ERRORS_ENABLED
+ || (instruction_bus_error_exception == `TRUE)
+ || (data_bus_error_exception == `TRUE)
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+ || (divide_by_zero_exception == `TRUE)
+`endif
+`ifdef CFG_INTERRUPTS_ENABLED
+ || ( (interrupt_exception == `TRUE)
+`ifdef LM32_SINGLE_STEP_ENABLED
+ && (dc_ss == `FALSE)
+`endif
+ )
+`endif
+ ;
+`endif
+
+// Exception ID
+always @*
+begin
+`ifdef CFG_DEBUG_ENABLED
+`ifdef CFG_JTAG_ENABLED
+ if (reset_exception == `TRUE)
+ eid_x = `LM32_EID_RESET;
+ else
+`endif
+ if (breakpoint_exception == `TRUE)
+ eid_x = `LM32_EID_BREAKPOINT;
+ else
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+ if (instruction_bus_error_exception == `TRUE)
+ eid_x = `LM32_EID_INST_BUS_ERROR;
+ else
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ if (watchpoint_exception == `TRUE)
+ eid_x = `LM32_EID_WATCHPOINT;
+ else
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+ if (data_bus_error_exception == `TRUE)
+ eid_x = `LM32_EID_DATA_BUS_ERROR;
+ else
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+ if (divide_by_zero_exception == `TRUE)
+ eid_x = `LM32_EID_DIVIDE_BY_ZERO;
+ else
+`endif
+`ifdef CFG_INTERRUPTS_ENABLED
+ if ( (interrupt_exception == `TRUE)
+`ifdef LM32_SINGLE_STEP_ENABLED
+ && (dc_ss == `FALSE)
+`endif
+ )
+ eid_x = `LM32_EID_INTERRUPT;
+ else
+`endif
+ eid_x = `LM32_EID_SCALL;
+end
+
+// Stall generation
+
+assign stall_a = (stall_f == `TRUE);
+
+assign stall_f = (stall_d == `TRUE);
+
+assign stall_d = (stall_x == `TRUE)
+ || ( (interlock == `TRUE)
+ && (kill_d == `FALSE)
+ )
+ || ( (eret_d == `TRUE)
+ && (load_q_x == `TRUE)
+ )
+`ifdef CFG_DEBUG_ENABLED
+ || ( (bret_d == `TRUE)
+ && (load_q_x == `TRUE)
+ )
+`endif
+ || ( (csr_write_enable_d == `TRUE)
+ && (load_q_x == `TRUE)
+ )
+ ;
+
+assign stall_x = (stall_m == `TRUE)
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+ || ( (mc_stall_request_x == `TRUE)
+ && (kill_x == `FALSE)
+ )
+`endif
+ ;
+
+assign stall_m = (stall_wb_load == `TRUE)
+`ifdef CFG_SIZE_OVER_SPEED
+ || (D_CYC_O == `TRUE)
+`else
+ || ( (D_CYC_O == `TRUE)
+ && ( (store_m == `TRUE)
+ || (load_m == `TRUE)
+ || (load_x == `TRUE)
+ )
+ )
+`endif
+`ifdef CFG_DCACHE_ENABLED
+ || (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
+`endif
+`ifdef CFG_ICACHE_ENABLED
+ || (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost
+ || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE)))
+`else
+`ifdef CFG_IWB_ENABLED
+ || (I_CYC_O == `TRUE)
+`endif
+`endif
+`ifdef CFG_USER_ENABLED
+ || ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
+ && (user_complete == `FALSE)
+ )
+`endif
+ ;
+
+// Qualify state changing control signals
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+wire q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
+assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
+assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
+`endif
+wire q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
+assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
+assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
+`ifdef CFG_DEBUG_ENABLED
+assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
+`endif
+assign load_q_x = (load_x == `TRUE)
+ && (q_x == `TRUE)
+`ifdef CFG_DEBUG_ENABLED
+ && (bp_match == `FALSE)
+`endif
+ ;
+`ifdef CFG_USER_ENABLED
+assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
+`endif
+wire q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
+assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
+assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
+`ifdef CFG_DEBUG_ENABLED
+assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
+assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));
+`else
+assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));
+`endif
+// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
+assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE);
+assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
+assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
+// The enable that actually does write the registers needs to be qualified with kill
+assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
+
+// Configuration (CFG) CSR
+assign cfg = {
+ `LM32_REVISION,
+ watchpoints[3:0],
+ breakpoints[3:0],
+ interrupts[5:0],
+`ifdef CFG_JTAG_UART_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef CFG_ROM_DEBUG_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef CFG_ICACHE_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef CFG_DCACHE_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef CFG_CYCLE_COUNTER_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef CFG_USER_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef LM32_BARREL_SHIFT_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+ `TRUE,
+`else
+ `FALSE,
+`endif
+`ifdef LM32_MULTIPLY_ENABLED
+ `TRUE
+`else
+ `FALSE
+`endif
+ };
+
+// Cache flush
+`ifdef CFG_ICACHE_ENABLED
+assign iflush = (csr_write_enable_d == `TRUE)
+ && (csr_d == `LM32_CSR_ICC)
+ && (stall_d == `FALSE)
+ && (kill_d == `FALSE)
+ && (valid_d == `TRUE);
+`endif
+`ifdef CFG_DCACHE_ENABLED
+assign dflush_x = (csr_write_enable_q_x == `TRUE)
+ && (csr_x == `LM32_CSR_DCC);
+`endif
+
+// Extract CSR index
+assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
+
+// CSR reads
+always @*
+begin
+ case (csr_x)
+`ifdef CFG_INTERRUPTS_ENABLED
+ `LM32_CSR_IE,
+ `LM32_CSR_IM,
+ `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x;
+`endif
+`ifdef CFG_CYCLE_COUNTER_ENABLED
+ `LM32_CSR_CC: csr_read_data_x = cc;
+`endif
+ `LM32_CSR_CFG: csr_read_data_x = cfg;
+ `LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00};
+`ifdef CFG_DEBUG_ENABLED
+ `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
+`endif
+`ifdef CFG_JTAG_UART_ENABLED
+ `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data;
+ `LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
+`endif
+ default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
+ endcase
+end
+
+/////////////////////////////////////////////////////
+// Sequential Logic
+/////////////////////////////////////////////////////
+
+// Exception Base Address (EBA) CSR
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
+ else
+ begin
+ if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
+ eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
+`ifdef CFG_HW_DEBUG_ENABLED
+ if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
+ eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
+`endif
+ end
+end
+
+`ifdef CFG_DEBUG_ENABLED
+// Debug Exception Base Address (DEBA) CSR
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
+ else
+ begin
+ if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
+ deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
+`ifdef CFG_HW_DEBUG_ENABLED
+ if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
+ deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
+`endif
+ end
+end
+`endif
+
+// Cycle Counter (CC) CSR
+`ifdef CFG_CYCLE_COUNTER_ENABLED
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ cc <= {`LM32_WORD_WIDTH{1'b0}};
+ else
+ cc <= cc + 1'b1;
+end
+`endif
+
+`ifdef CFG_BUS_ERRORS_ENABLED
+// Watch for data bus errors
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ data_bus_error_seen <= `FALSE;
+ else
+ begin
+ // Set flag when bus error is detected
+ if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
+ data_bus_error_seen <= `TRUE;
+ // Clear flag when exception is taken
+ if ((exception_m == `TRUE) && (kill_m == `FALSE))
+ data_bus_error_seen <= `FALSE;
+ end
+end
+`endif
+
+// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
+
+`ifdef CFG_ICACHE_ENABLED
+`ifdef CFG_DCACHE_ENABLED
+always @*
+begin
+ if ( (icache_refill_request == `TRUE)
+ || (dcache_refill_request == `TRUE)
+ )
+ valid_a = `FALSE;
+ else if ( (icache_restart_request == `TRUE)
+ || (dcache_restart_request == `TRUE)
+ )
+ valid_a = `TRUE;
+ else
+ valid_a = !icache_refilling && !dcache_refilling;
+end
+`else
+always @*
+begin
+ if (icache_refill_request == `TRUE)
+ valid_a = `FALSE;
+ else if (icache_restart_request == `TRUE)
+ valid_a = `TRUE;
+ else
+ valid_a = !icache_refilling;
+end
+`endif
+`else
+`ifdef CFG_DCACHE_ENABLED
+always @*
+begin
+ if (dcache_refill_request == `TRUE)
+ valid_a = `FALSE;
+ else if (dcache_restart_request == `TRUE)
+ valid_a = `TRUE;
+ else
+ valid_a = !dcache_refilling;
+end
+`endif
+`endif
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ valid_f <= `FALSE;
+ valid_d <= `FALSE;
+ valid_x <= `FALSE;
+ valid_m <= `FALSE;
+ valid_w <= `FALSE;
+ end
+ else
+ begin
+ if ((kill_f == `TRUE) || (stall_a == `FALSE))
+`ifdef LM32_CACHE_ENABLED
+ valid_f <= valid_a;
+`else
+ valid_f <= `TRUE;
+`endif
+ else if (stall_f == `FALSE)
+ valid_f <= `FALSE;
+ if (kill_d == `TRUE)
+ valid_d <= `FALSE;
+ else if (stall_f == `FALSE)
+ valid_d <= valid_f & !kill_f;
+ else if (stall_d == `FALSE)
+ valid_d <= `FALSE;
+ if (kill_x == `TRUE)
+ valid_x <= `FALSE;
+ else if (stall_d == `FALSE)
+ valid_x <= valid_d & !kill_d;
+ else if (stall_x == `FALSE)
+ valid_x <= `FALSE;
+ if (kill_m == `TRUE)
+ valid_m <= `FALSE;
+ else if (stall_x == `FALSE)
+ valid_m <= valid_x & !kill_x;
+ else if (stall_m == `FALSE)
+ valid_m <= `FALSE;
+ if (stall_m == `FALSE)
+ valid_w <= valid_m & !kill_m;
+ else
+ valid_w <= `FALSE;
+ end
+end
+
+// Microcode pipeline registers
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+`ifdef CFG_USER_ENABLED
+ user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};
+`endif
+ operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
+ operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
+ store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
+ branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};
+ x_result_sel_csr_x <= `FALSE;
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+ x_result_sel_mc_arith_x <= `FALSE;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+ x_result_sel_shift_x <= `FALSE;
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+ x_result_sel_sext_x <= `FALSE;
+`endif
+ x_result_sel_logic_x <= `FALSE;
+`ifdef CFG_USER_ENABLED
+ x_result_sel_user_x <= `FALSE;
+`endif
+ x_result_sel_add_x <= `FALSE;
+ m_result_sel_compare_x <= `FALSE;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ m_result_sel_shift_x <= `FALSE;
+`endif
+ w_result_sel_load_x <= `FALSE;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ w_result_sel_mul_x <= `FALSE;
+`endif
+ x_bypass_enable_x <= `FALSE;
+ m_bypass_enable_x <= `FALSE;
+ write_enable_x <= `FALSE;
+ write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
+ csr_x <= {`LM32_CSR_WIDTH{1'b0}};
+ load_x <= `FALSE;
+ store_x <= `FALSE;
+ size_x <= {`LM32_SIZE_WIDTH{1'b0}};
+ sign_extend_x <= `FALSE;
+ adder_op_x <= `FALSE;
+ adder_op_x_n <= `FALSE;
+ logic_op_x <= 4'h0;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ direction_x <= `FALSE;
+`endif
+`ifdef CFG_ROTATE_ENABLED
+ rotate_x <= `FALSE;
+
+`endif
+ branch_x <= `FALSE;
+ condition_x <= `LM32_CONDITION_U1;
+`ifdef CFG_DEBUG_ENABLED
+ break_x <= `FALSE;
+`endif
+ scall_x <= `FALSE;
+ eret_x <= `FALSE;
+`ifdef CFG_DEBUG_ENABLED
+ bret_x <= `FALSE;
+`endif
+`ifdef CFG_BUS_ERRORS_ENABLED
+ bus_error_x <= `FALSE;
+`endif
+ csr_write_enable_x <= `FALSE;
+ operand_m <= {`LM32_WORD_WIDTH{1'b0}};
+ branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
+ m_result_sel_compare_m <= `FALSE;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ m_result_sel_shift_m <= `FALSE;
+`endif
+ w_result_sel_load_m <= `FALSE;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ w_result_sel_mul_m <= `FALSE;
+`endif
+ m_bypass_enable_m <= `FALSE;
+ branch_m <= `FALSE;
+ exception_m <= `FALSE;
+ load_m <= `FALSE;
+ store_m <= `FALSE;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ direction_m <= `FALSE;
+`endif
+ write_enable_m <= `FALSE;
+ write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
+ condition_met_m <= `FALSE;
+`ifdef CFG_DCACHE_ENABLED
+ dflush_m <= `FALSE;
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ debug_exception_m <= `FALSE;
+ non_debug_exception_m <= `FALSE;
+`endif
+ operand_w <= {`LM32_WORD_WIDTH{1'b0}};
+ w_result_sel_load_w <= `FALSE;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ w_result_sel_mul_w <= `FALSE;
+`endif
+ write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};
+ write_enable_w <= `FALSE;
+`ifdef CFG_DEBUG_ENABLED
+ debug_exception_w <= `FALSE;
+ non_debug_exception_w <= `FALSE;
+`else
+ exception_w <= `FALSE;
+`endif
+ end
+ else
+ begin
+ // D/X stage registers
+
+ if (stall_x == `FALSE)
+ begin
+`ifdef CFG_USER_ENABLED
+ user_opcode <= user_opcode_d;
+`endif
+ operand_0_x <= d_result_0;
+ operand_1_x <= d_result_1;
+ store_operand_x <= bypass_data_1;
+ branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : pc_d + branch_offset_d;
+ x_result_sel_csr_x <= x_result_sel_csr_d;
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+ x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+ x_result_sel_shift_x <= x_result_sel_shift_d;
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+ x_result_sel_sext_x <= x_result_sel_sext_d;
+`endif
+ x_result_sel_logic_x <= x_result_sel_logic_d;
+`ifdef CFG_USER_ENABLED
+ x_result_sel_user_x <= x_result_sel_user_d;
+`endif
+ x_result_sel_add_x <= x_result_sel_add_d;
+ m_result_sel_compare_x <= m_result_sel_compare_d;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ m_result_sel_shift_x <= m_result_sel_shift_d;
+`endif
+ w_result_sel_load_x <= w_result_sel_load_d;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ w_result_sel_mul_x <= w_result_sel_mul_d;
+`endif
+ x_bypass_enable_x <= x_bypass_enable_d;
+ m_bypass_enable_x <= m_bypass_enable_d;
+ load_x <= load_d;
+ store_x <= store_d;
+ branch_x <= branch_d;
+ write_idx_x <= write_idx_d;
+ csr_x <= csr_d;
+ size_x <= size_d;
+ sign_extend_x <= sign_extend_d;
+ adder_op_x <= adder_op_d;
+ adder_op_x_n <= ~adder_op_d;
+ logic_op_x <= logic_op_d;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ direction_x <= direction_d;
+`endif
+`ifdef CFG_ROTATE_ENABLED
+ rotate_x <= rotate_d;
+`endif
+ condition_x <= condition_d;
+ csr_write_enable_x <= csr_write_enable_d;
+`ifdef CFG_DEBUG_ENABLED
+ break_x <= break_d;
+`endif
+ scall_x <= scall_d;
+`ifdef CFG_BUS_ERRORS_ENABLED
+ bus_error_x <= bus_error_d;
+`endif
+ eret_x <= eret_d;
+`ifdef CFG_DEBUG_ENABLED
+ bret_x <= bret_d;
+`endif
+ write_enable_x <= write_enable_d;
+ end
+
+ // X/M stage registers
+
+ if (stall_m == `FALSE)
+ begin
+ operand_m <= x_result;
+ m_result_sel_compare_m <= m_result_sel_compare_x;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ m_result_sel_shift_m <= m_result_sel_shift_x;
+`endif
+ if (exception_x == `TRUE)
+ begin
+ w_result_sel_load_m <= `FALSE;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ w_result_sel_mul_m <= `FALSE;
+`endif
+ end
+ else
+ begin
+ w_result_sel_load_m <= w_result_sel_load_x;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ w_result_sel_mul_m <= w_result_sel_mul_x;
+`endif
+ end
+ m_bypass_enable_m <= m_bypass_enable_x;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ direction_m <= direction_x;
+`endif
+ load_m <= load_x;
+ store_m <= store_x;
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+ branch_m <= branch_x && !branch_taken_x;
+`else
+ branch_m <= branch_x;
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ if (debug_exception_x == `TRUE)
+ write_idx_m <= `LM32_BA_REG;
+ else if (non_debug_exception_x == `TRUE)
+ write_idx_m <= `LM32_EA_REG;
+ else
+ write_idx_m <= write_idx_x;
+`else
+ if (exception_x == `TRUE)
+ write_idx_m <= `LM32_EA_REG;
+ else
+ write_idx_m <= write_idx_x;
+`endif
+ condition_met_m <= condition_met_x;
+`ifdef CFG_DEBUG_ENABLED
+ branch_target_m <= exception_x == `TRUE ? {(debug_exception_x == `TRUE) || (dc_re == `TRUE) ? deba : eba, eid_x, {3{1'b0}}} : branch_target_x;
+`else
+ branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+`endif
+`ifdef CFG_TRACE_ENABLED
+ eid_m <= eid_x;
+`endif
+`ifdef CFG_DCACHE_ENABLED
+ dflush_m <= dflush_x;
+`endif
+ eret_m <= eret_q_x;
+`ifdef CFG_DEBUG_ENABLED
+ bret_m <= bret_q_x;
+`endif
+ write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;
+`ifdef CFG_DEBUG_ENABLED
+ debug_exception_m <= debug_exception_x;
+ non_debug_exception_m <= non_debug_exception_x;
+`endif
+ end
+
+ // State changing regs
+ if (stall_m == `FALSE)
+ begin
+ if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
+ exception_m <= `TRUE;
+ else
+ exception_m <= `FALSE;
+ end
+
+ // M/W stage registers
+
+ operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
+ w_result_sel_load_w <= w_result_sel_load_m;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ w_result_sel_mul_w <= w_result_sel_mul_m;
+`endif
+ write_idx_w <= write_idx_m;
+`ifdef CFG_TRACE_ENABLED
+ eid_w <= eid_m;
+ eret_w <= eret_m;
+`ifdef CFG_DEBUG_ENABLED
+ bret_w <= bret_m;
+`endif
+`endif
+ write_enable_w <= write_enable_m;
+`ifdef CFG_DEBUG_ENABLED
+ debug_exception_w <= debug_exception_m;
+ non_debug_exception_w <= non_debug_exception_m;
+`else
+ exception_w <= exception_m;
+`endif
+ end
+end
+
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+// Buffer data read from register file, in case a stall occurs, and watch for
+// any writes to the modified registers
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ use_buf <= `FALSE;
+ reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
+ reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
+ end
+ else
+ begin
+ if (stall_d == `FALSE)
+ use_buf <= `FALSE;
+ else if (use_buf == `FALSE)
+ begin
+ reg_data_buf_0 <= reg_data_live_0;
+ reg_data_buf_1 <= reg_data_live_1;
+ use_buf <= `TRUE;
+ end
+ if (reg_write_enable_q_w == `TRUE)
+ begin
+ if (write_idx_w == read_idx_0_d)
+ reg_data_buf_0 <= w_result;
+ if (write_idx_w == read_idx_1_d)
+ reg_data_buf_1 <= w_result;
+ end
+ end
+end
+`endif
+
+`ifdef LM32_EBR_REGISTER_FILE
+`else
+// Register file write port
+// Adding a reset causes a huge slowdown and requires lots of extra LUTs
+always @(posedge clk_i)
+begin
+ if (reg_write_enable_q_w == `TRUE)
+ registers[write_idx_w] <= w_result;
+end
+`endif
+
+`ifdef CFG_TRACE_ENABLED
+// PC tracing logic
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ trace_pc_valid <= `FALSE;
+ trace_pc <= {`LM32_PC_WIDTH{1'b0}};
+ trace_exception <= `FALSE;
+ trace_eid <= `LM32_EID_RESET;
+ trace_eret <= `FALSE;
+`ifdef CFG_DEBUG_ENABLED
+ trace_bret <= `FALSE;
+`endif
+ pc_c <= `CFG_EBA_RESET/4;
+ end
+ else
+ begin
+ trace_pc_valid <= `FALSE;
+
+ // Has an exception occured
+`ifdef CFG_DEBUG_ENABLED
+ if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
+`else
+ if (exception_q_w == `TRUE)
+`endif
+ begin
+ trace_exception <= `TRUE;
+ trace_pc_valid <= `TRUE;
+ trace_pc <= pc_w;
+ trace_eid <= eid_w;
+ end
+ else
+ trace_exception <= `FALSE;
+
+ if ((valid_w == `TRUE) && (!kill_w))
+ begin
+ // An instruction is commiting. Determine if it is non-sequential
+ if (pc_c + 1'b1 != pc_w)
+ begin
+ // Non-sequential instruction
+ trace_pc_valid <= `TRUE;
+ trace_pc <= pc_w;
+ end
+ // Record PC so we can determine if next instruction is sequential or not
+ pc_c <= pc_w;
+ // Indicate if it was an eret/bret instruction
+ trace_eret <= eret_w;
+`ifdef CFG_DEBUG_ENABLED
+ trace_bret <= bret_w;
+`endif
+ end
+ else
+ begin
+ trace_eret <= `FALSE;
+`ifdef CFG_DEBUG_ENABLED
+ trace_bret <= `FALSE;
+`endif
+ end
+ end
+end
+`endif
+
+/////////////////////////////////////////////////////
+// Behavioural Logic
+/////////////////////////////////////////////////////
+
+// synthesis translate_off
+
+// Reset register 0. Only needed for simulation.
+initial
+begin
+`ifdef LM32_EBR_REGISTER_FILE
+ reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
+ reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
+`else
+ registers[0] = {`LM32_WORD_WIDTH{1'b0}};
+`endif
+end
+
+// synthesis translate_on
+
+endmodule
lm32/verilog/src/lm32_cpu.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_load_store_unit.v
===================================================================
--- lm32/verilog/src/lm32_load_store_unit.v (nonexistent)
+++ lm32/verilog/src/lm32_load_store_unit.v (revision 17)
@@ -0,0 +1,588 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_load_store_unit.v
+// Title : Load and store unit
+// Dependencies : lm32_include.v
+// Version : 6.0.13
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_load_store_unit (
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ // From pipeline
+ stall_a,
+ stall_x,
+ stall_m,
+ kill_x,
+ kill_m,
+ exception_m,
+ store_operand_x,
+ load_store_address_x,
+ load_store_address_m,
+ load_store_address_w,
+ load_q_x,
+ load_q_m,
+ store_q_m,
+ sign_extend_x,
+ size_x,
+`ifdef CFG_DCACHE_ENABLED
+ dflush,
+`endif
+ // From Wishbone
+ d_dat_i,
+ d_ack_i,
+ d_err_i,
+ d_rty_i,
+ // ----- Outputs -------
+ // To pipeline
+`ifdef CFG_DCACHE_ENABLED
+ dcache_refill_request,
+ dcache_restart_request,
+ dcache_stall_request,
+ dcache_refilling,
+`endif
+ load_data_w,
+ stall_wb_load,
+ // To Wishbone
+ d_dat_o,
+ d_adr_o,
+ d_cyc_o,
+ d_sel_o,
+ d_stb_o,
+ d_we_o,
+ d_cti_o,
+ d_lock_o,
+ d_bte_o
+ );
+
+/////////////////////////////////////////////////////
+// Parameters
+/////////////////////////////////////////////////////
+
+parameter associativity = 1; // Associativity of the cache (Number of ways)
+parameter sets = 512; // Number of sets
+parameter bytes_per_line = 16; // Number of bytes per cache line
+parameter base_address = 0; // Base address of cachable memory
+parameter limit = 0; // Limit (highest address) of cachable memory
+
+// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
+//localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_width = 2;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+
+input stall_a; // A stage stall
+input stall_x; // X stage stall
+input stall_m; // M stage stall
+input kill_x; // Kill instruction in X stage
+input kill_m; // Kill instruction in M stage
+input exception_m; // An exception occured in the M stage
+
+input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
+input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
+input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address
+input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed)
+input load_q_x; // Load instruction in X stage
+input load_q_m; // Load instruction in M stage
+input store_q_m; // Store instruction in M stage
+input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend
+input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word)
+
+`ifdef CFG_DCACHE_ENABLED
+input dflush; // Flush the data cache
+`endif
+
+input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
+input d_ack_i; // Data Wishbone interface acknowledgement
+input d_err_i; // Data Wishbone interface error
+input d_rty_i; // Data Wishbone interface retry
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+`ifdef CFG_DCACHE_ENABLED
+output dcache_refill_request; // Request to refill data cache
+wire dcache_refill_request;
+output dcache_restart_request; // Request to restart the instruction that caused a data cache miss
+wire dcache_restart_request;
+output dcache_stall_request; // Data cache stall request
+wire dcache_stall_request;
+output dcache_refilling;
+wire dcache_refilling;
+`endif
+
+output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
+reg [`LM32_WORD_RNG] load_data_w;
+output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface
+reg stall_wb_load;
+
+output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data
+reg [`LM32_WORD_RNG] d_dat_o;
+output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address
+reg [`LM32_WORD_RNG] d_adr_o;
+output d_cyc_o; // Data Wishbone interface cycle
+reg d_cyc_o;
+output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select
+reg [`LM32_BYTE_SELECT_RNG] d_sel_o;
+output d_stb_o; // Data Wishbone interface strobe
+reg d_stb_o;
+output d_we_o; // Data Wishbone interface write enable
+reg d_we_o;
+output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] d_cti_o;
+output d_lock_o; // Date Wishbone interface lock bus
+wire d_lock_o;
+output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] d_bte_o;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+// Microcode pipeline registers - See inputs for description
+reg [`LM32_SIZE_RNG] size_m;
+reg [`LM32_SIZE_RNG] size_w;
+reg sign_extend_m;
+reg sign_extend_w;
+reg [`LM32_WORD_RNG] store_data_x;
+reg [`LM32_WORD_RNG] store_data_m;
+reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
+reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
+wire [`LM32_WORD_RNG] data_m;
+reg [`LM32_WORD_RNG] data_w;
+
+`ifdef CFG_DCACHE_ENABLED
+wire dcache_select_x; // Select data cache to load from / store to
+reg dcache_select_m;
+wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
+wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
+reg dcache_refill_ready; // Indicates the next word of refill data is ready
+wire last_word; // Indicates if this is the last word in the cache line
+wire [`LM32_WORD_RNG] first_address; // First cache refill address
+`endif
+`ifdef CFG_DRAM_ENABLED
+wire dram_select_x; // Select data RAM to load from / store to
+reg dram_select_m;
+wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM
+wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM
+`endif
+wire wb_select_x; // Select Wishbone to load from / store to
+reg wb_select_m;
+reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
+reg wb_load_complete; // Indicates when a Wishbone load is complete
+
+/////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////
+`define INCLUDE_FUNCTION
+`include "lm32_functions.v"
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+`ifdef CFG_DRAM_ENABLED
+// Data RAM
+pmi_ram_dp_true #(
+ // ----- Parameters -------
+ .pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
+ .pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
+ .pmi_data_width_a (`LM32_WORD_WIDTH),
+ .pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
+ .pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
+ .pmi_data_width_b (`LM32_WORD_WIDTH),
+ .pmi_regmode_a ("noreg"),
+ .pmi_regmode_b ("noreg"),
+ .pmi_gsr ("enable"),
+ .pmi_resetmode ("async"),
+ .pmi_init_file (`CFG_DRAM_INIT_FILE),
+ .pmi_init_file_format ("hex"),
+ .module_type ("pmi_ram_dp")
+ ) ram (
+ // ----- Inputs -------
+ .ClockA (clk_i),
+ .ClockB (clk_i),
+ .ResetA (rst_i),
+ .ResetB (rst_i),
+ .DataInA ({32{1'b0}}),
+ .DataInB (dram_store_data_m),
+ .AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
+ .AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
+ .ClockEnA (!stall_x),
+ .ClockEnB (!stall_m),
+ .WrA (`FALSE),
+ .WrB (store_q_m),
+ // ----- Outputs -------
+ .QA (dram_data_m),
+ .QB ()
+ );
+`endif
+
+`ifdef CFG_DCACHE_ENABLED
+// Data cache
+lm32_dcache #(
+ .associativity (associativity),
+ .sets (sets),
+ .bytes_per_line (bytes_per_line),
+ .base_address (base_address),
+ .limit (limit)
+ ) dcache (
+ // ----- Inputs -----
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_a (stall_a),
+ .stall_x (stall_x),
+ .stall_m (stall_m),
+ .address_x (load_store_address_x),
+ .address_m (load_store_address_m),
+ .load_q_m (load_q_m & dcache_select_m),
+ .store_q_m (store_q_m),
+ .store_data (store_data_m),
+ .store_byte_select (byte_enable_m),
+ .refill_ready (dcache_refill_ready),
+ .refill_data (wb_data_m),
+ .dflush (dflush),
+ // ----- Outputs -----
+ .stall_request (dcache_stall_request),
+ .restart_request (dcache_restart_request),
+ .refill_request (dcache_refill_request),
+ .refill_address (dcache_refill_address),
+ .refilling (dcache_refilling),
+ .load_data (dcache_data_m)
+ );
+`endif
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+// Select where data should be loaded from / stored to
+`ifdef CFG_DCACHE_ENABLED
+assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) && (load_store_address_x <= `CFG_DCACHE_LIMIT);
+//assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) && ~|load_store_address_x[`LM32_WORD_WIDTH-1:clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1];
+`endif
+`ifdef CFG_DRAM_ENABLED
+assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) && (load_store_address_x <= `CFG_DRAM_LIMIT);
+`endif
+assign wb_select_x = `TRUE
+`ifdef CFG_DCACHE_ENABLED
+ && !dcache_select_x
+`endif
+`ifdef CFG_DRAM_ENABLED
+ && !dram_select_x
+`endif
+ ;
+
+// Make sure data to store is in correct byte lane
+always @(*)
+begin
+ case (size_x)
+ `LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}};
+ `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
+ `LM32_SIZE_WORD: store_data_x = store_operand_x;
+ default: store_data_x = {`LM32_WORD_WIDTH{1'bx}};
+ endcase
+end
+
+// Generate byte enable accoring to size of load or store and address being accessed
+always @(*)
+begin
+ casez ({size_x, load_store_address_x[1:0]})
+ {`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001;
+ {`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010;
+ {`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100;
+ {`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000;
+ {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
+ {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
+ {`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111;
+ default: byte_enable_x = 4'bxxxx;
+ endcase
+end
+
+`ifdef CFG_DRAM_ENABLED
+// Only replace selected bytes
+assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
+assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
+assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
+assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
+`endif
+
+// Select data from selected source
+`ifdef CFG_DCACHE_ENABLED
+`ifdef CFG_DRAM_ENABLED
+assign data_m = wb_select_m == `TRUE
+ ? wb_data_m
+ : dram_select_m == `TRUE
+ ? dram_data_m
+ : dcache_data_m;
+`else
+assign data_m = wb_select_m == `TRUE ? wb_data_m : dcache_data_m;
+`endif
+`else
+`ifdef CFG_DRAM_ENABLED
+assign data_m = wb_select_m == `TRUE ? wb_data_m : dram_data_m;
+`else
+assign data_m = wb_data_m;
+`endif
+`endif
+
+// Sub-word selection and sign/zero-extension for loads
+always @(*)
+begin
+ casez ({size_w, load_store_address_w[1:0]})
+ {`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+ {`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+ {`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+ {`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+ {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+ {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+ {`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w;
+ default: load_data_w = {`LM32_WORD_WIDTH{1'bx}};
+ endcase
+end
+
+// Unused Wishbone signals
+assign d_cti_o = `LM32_CTYPE_WIDTH'd0;
+assign d_lock_o = `FALSE;
+assign d_bte_o = `LM32_BTYPE_WIDTH'd0;
+
+`ifdef CFG_DCACHE_ENABLED
+// Generate signal to indicate last word in cache line
+generate
+ if (bytes_per_line > 4)
+ begin
+assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
+ end
+ else
+ begin
+assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
+assign last_word = `TRUE;
+ end
+endgenerate
+`endif
+
+/////////////////////////////////////////////////////
+// Sequential Logic
+/////////////////////////////////////////////////////
+
+// Data Wishbone interface
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ d_cyc_o <= `FALSE;
+ d_stb_o <= `FALSE;
+ d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
+ d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
+ d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
+ d_we_o <= `FALSE;
+ wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
+ wb_load_complete <= `FALSE;
+ stall_wb_load <= `FALSE;
+`ifdef CFG_DCACHE_ENABLED
+ dcache_refill_ready <= `FALSE;
+`endif
+ end
+ else
+ begin
+`ifdef CFG_DCACHE_ENABLED
+ // Refill ready should only be asserted for a single cycle
+ dcache_refill_ready <= `FALSE;
+`endif
+ // Is a Wishbone cycle already in progress?
+ if (d_cyc_o == `TRUE)
+ begin
+ // Is the cycle complete?
+ if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
+ begin
+`ifdef CFG_DCACHE_ENABLED
+ if ((dcache_refilling == `TRUE) && (!last_word))
+ begin
+ // Fetch next word of cache line
+ d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+ end
+ else
+`endif
+ begin
+ // Refill/access complete
+ d_cyc_o <= `FALSE;
+ d_stb_o <= `FALSE;
+ end
+`ifdef CFG_DCACHE_ENABLED
+ // If we are performing a refill, indicate to cache next word of data is ready
+ dcache_refill_ready <= dcache_refilling;
+`endif
+ // Register data read from Wishbone interface
+ wb_data_m <= d_dat_i;
+ // Don't set when stores complete - otherwise we'll deadlock if load in m stage
+ wb_load_complete <= !d_we_o;
+ end
+ // synthesis translate_off
+ if (d_err_i == `TRUE)
+ $display ("Data bus error. Address: %x", d_adr_o);
+ // synthesis translate_on
+ end
+ else
+ begin
+`ifdef CFG_DCACHE_ENABLED
+ if (dcache_refill_request == `TRUE)
+ begin
+ // Start cache refill
+ d_adr_o <= first_address;
+ d_cyc_o <= `TRUE;
+ d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
+ d_stb_o <= `TRUE;
+ d_we_o <= `FALSE;
+ end
+ else
+`endif
+ if ( (store_q_m == `TRUE)
+ && (stall_m == `FALSE)
+`ifdef CFG_DRAM_ENABLED
+ && !dram_select_m
+`endif
+ )
+ begin
+ // Data cache is write through, so all stores go to memory
+ d_dat_o <= store_data_m;
+ d_adr_o <= load_store_address_m;
+ d_cyc_o <= `TRUE;
+ d_sel_o <= byte_enable_m;
+ d_stb_o <= `TRUE;
+ d_we_o <= `TRUE;
+ end
+ else if ( (load_q_m == `TRUE)
+ && (wb_select_m == `TRUE)
+ && (wb_load_complete == `FALSE)
+ /* stall_m will be TRUE, because stall_wb_load will be TRUE */
+ )
+ begin
+ // Read requested address
+ stall_wb_load <= `FALSE;
+ d_adr_o <= load_store_address_m;
+ d_cyc_o <= `TRUE;
+ d_sel_o <= byte_enable_m;
+ d_stb_o <= `TRUE;
+ d_we_o <= `FALSE;
+ end
+ end
+ // Clear load/store complete flag when instruction leaves M stage
+ if (stall_m == `FALSE)
+ wb_load_complete <= `FALSE;
+ // When a Wishbone load first enters the M stage, we need to stall it
+ if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
+ stall_wb_load <= `TRUE;
+ // Clear stall request if load instruction is killed
+ if ((kill_m == `TRUE) || (exception_m == `TRUE))
+ stall_wb_load <= `FALSE;
+ end
+end
+
+// Pipeline registers
+
+// X/M stage pipeline registers
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ sign_extend_m <= `FALSE;
+ size_m <= 2'b00;
+ byte_enable_m <= `FALSE;
+ store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
+`ifdef CFG_DCACHE_ENABLED
+ dcache_select_m <= `FALSE;
+`endif
+`ifdef CFG_DRAM_ENABLED
+ dram_select_m <= `FALSE;
+`endif
+ wb_select_m <= `FALSE;
+ end
+ else
+ begin
+ if (stall_m == `FALSE)
+ begin
+ sign_extend_m <= sign_extend_x;
+ size_m <= size_x;
+ byte_enable_m <= byte_enable_x;
+ store_data_m <= store_data_x;
+`ifdef CFG_DCACHE_ENABLED
+ dcache_select_m <= dcache_select_x;
+`endif
+`ifdef CFG_DRAM_ENABLED
+ dram_select_m <= dram_select_x;
+`endif
+ wb_select_m <= wb_select_x;
+ end
+ end
+end
+
+// M/W stage pipeline registers
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ size_w <= 2'b00;
+ data_w <= {`LM32_WORD_WIDTH{1'b0}};
+ sign_extend_w <= `FALSE;
+ end
+ else
+ begin
+ size_w <= size_m;
+ data_w <= data_m;
+ sign_extend_w <= sign_extend_m;
+ end
+end
+
+/////////////////////////////////////////////////////
+// Behavioural Logic
+/////////////////////////////////////////////////////
+
+// synthesis translate_off
+
+// Check for non-aligned loads or stores
+always @(posedge clk_i)
+begin
+ if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE))
+ begin
+ if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
+ $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
+ if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
+ $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
+ end
+end
+
+// synthesis translate_on
+
+endmodule
+
lm32/verilog/src/lm32_load_store_unit.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_logic_op.v
===================================================================
--- lm32/verilog/src/lm32_logic_op.v (nonexistent)
+++ lm32/verilog/src/lm32_logic_op.v (revision 17)
@@ -0,0 +1,71 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_logic_op.v
+// Title : Logic operations (and / or / not etc)
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_logic_op (
+ // ----- Inputs -------
+ logic_op_x,
+ operand_0_x,
+ operand_1_x,
+ // ----- Outputs -------
+ logic_result_x
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input [`LM32_LOGIC_OP_RNG] logic_op_x;
+input [`LM32_WORD_RNG] operand_0_x;
+input [`LM32_WORD_RNG] operand_1_x;
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] logic_result_x;
+reg [`LM32_WORD_RNG] logic_result_x;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+integer logic_idx;
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+always @*
+begin
+ for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1)
+ logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
+end
+
+endmodule
+
lm32/verilog/src/lm32_logic_op.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_interrupt.v
===================================================================
--- lm32/verilog/src/lm32_interrupt.v (nonexistent)
+++ lm32/verilog/src/lm32_interrupt.v (revision 17)
@@ -0,0 +1,333 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_interrupt.v
+// Title : Interrupt logic
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "system_conf.v"
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_interrupt (
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ // From external devices
+ interrupt_n,
+ // From pipeline
+ stall_x,
+`ifdef CFG_DEBUG_ENABLED
+ non_debug_exception,
+ debug_exception,
+`else
+ exception,
+`endif
+ eret_q_x,
+`ifdef CFG_DEBUG_ENABLED
+ bret_q_x,
+`endif
+ csr,
+ csr_write_data,
+ csr_write_enable,
+ // ----- Outputs -------
+ interrupt_exception,
+ // To pipeline
+ csr_read_data
+ );
+
+/////////////////////////////////////////////////////
+// Parameters
+/////////////////////////////////////////////////////
+
+parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+
+input [interrupts-1:0] interrupt_n; // Interrupt pins, active-low
+
+input stall_x; // Stall X pipeline stage
+
+`ifdef CFG_DEBUG_ENABLED
+input non_debug_exception; // Non-debug related exception has been raised
+input debug_exception; // Debug-related exception has been raised
+`else
+input exception; // Exception has been raised
+`endif
+input eret_q_x; // Return from exception
+`ifdef CFG_DEBUG_ENABLED
+input bret_q_x; // Return from breakpoint
+`endif
+
+input [`LM32_CSR_RNG] csr; // CSR read/write index
+input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
+input csr_write_enable; // CSR write enable
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output interrupt_exception; // Request to raide an interrupt exception
+wire interrupt_exception;
+
+output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR
+reg [`LM32_WORD_RNG] csr_read_data;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
+wire [interrupts-1:0] interrupt_n_exception;
+
+// Interrupt CSRs
+
+reg ie; // Interrupt enable
+reg eie; // Exception interrupt enable
+`ifdef CFG_DEBUG_ENABLED
+reg bie; // Breakpoint interrupt enable
+`endif
+reg [interrupts-1:0] ip; // Interrupt pending
+reg [interrupts-1:0] im; // Interrupt mask
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+// Determine which interrupts have occured and are unmasked
+assign interrupt_n_exception = ip & im;
+
+// Determine if any unmasked interrupts have occured
+assign interrupt_exception = (|interrupt_n_exception) & ie;
+
+// Determine which interrupts are currently being asserted (active-low) or are already pending
+assign asserted = ip | ~interrupt_n;
+
+//assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
+//`ifdef CFG_DEBUG_ENABLED
+// bie,
+//`else
+// 1'b0,
+//`endif
+// eie,
+// ie
+// };
+wire ip_csr_read_data = ip;
+wire im_csr_read_data = im;
+// XXX JB XXX
+// generate
+// if (interrupts > 1)
+// begin
+// CSR read
+always @*
+begin
+ case (csr)
+ `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
+`ifdef CFG_DEBUG_ENABLED
+ bie,
+`else
+ 1'b0,
+`endif
+ eie,
+ ie
+ };
+ `LM32_CSR_IP: csr_read_data = ip;
+ `LM32_CSR_IM: csr_read_data = im;
+ default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
+ endcase
+end
+// XXX JB XXX
+// end
+// else
+// begin
+//// CSR read
+//always @*
+//begin
+// case (csr)
+// `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
+//`ifdef CFG_DEBUG_ENABLED
+// bie,
+//`else
+// 1'b0,
+//`endif
+// eie,
+// ie
+// };
+// `LM32_CSR_IP: csr_read_data = ip;
+// default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
+// endcase
+//end
+// end
+//endgenerate
+
+/////////////////////////////////////////////////////
+// Sequential Logic
+/////////////////////////////////////////////////////
+
+// XXX JB XXX
+//generate
+// if (interrupts > 1)
+// begin
+// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ ie <= `FALSE;
+ eie <= `FALSE;
+`ifdef CFG_DEBUG_ENABLED
+ bie <= `FALSE;
+`endif
+ im <= {interrupts{1'b0}};
+ ip <= {interrupts{1'b0}};
+ end
+ else
+ begin
+ // Set IP bit when interrupt line is asserted
+ ip <= asserted;
+`ifdef CFG_DEBUG_ENABLED
+ if (non_debug_exception == `TRUE)
+ begin
+ // Save and then clear interrupt enable
+ eie <= ie;
+ ie <= `FALSE;
+ end
+ else if (debug_exception == `TRUE)
+ begin
+ // Save and then clear interrupt enable
+ bie <= ie;
+ ie <= `FALSE;
+ end
+`else
+ if (exception == `TRUE)
+ begin
+ // Save and then clear interrupt enable
+ eie <= ie;
+ ie <= `FALSE;
+ end
+`endif
+ else if (stall_x == `FALSE)
+ begin
+ if (eret_q_x == `TRUE)
+ // Restore interrupt enable
+ ie <= eie;
+`ifdef CFG_DEBUG_ENABLED
+ else if (bret_q_x == `TRUE)
+ // Restore interrupt enable
+ ie <= bie;
+`endif
+ else if (csr_write_enable == `TRUE)
+ begin
+ // Handle wcsr write
+ if (csr == `LM32_CSR_IE)
+ begin
+ ie <= csr_write_data[0];
+ eie <= csr_write_data[1];
+`ifdef CFG_DEBUG_ENABLED
+ bie <= csr_write_data[2];
+`endif
+ end
+ if (csr == `LM32_CSR_IM)
+ im <= csr_write_data[interrupts-1:0];
+ if (csr == `LM32_CSR_IP)
+ ip <= asserted & ~csr_write_data[interrupts-1:0];
+ end
+ end
+ end
+end
+// end
+//else
+// begin
+//// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
+//always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+//begin
+// if (rst_i == `TRUE)
+// begin
+// ie <= `FALSE;
+// eie <= `FALSE;
+//`ifdef CFG_DEBUG_ENABLED
+// bie <= `FALSE;
+//`endif
+// ip <= {interrupts{1'b0}};
+// end
+// else
+// begin
+// // Set IP bit when interrupt line is asserted
+// ip <= asserted;
+//`ifdef CFG_DEBUG_ENABLED
+// if (non_debug_exception == `TRUE)
+// begin
+// // Save and then clear interrupt enable
+// eie <= ie;
+// ie <= `FALSE;
+// end
+// else if (debug_exception == `TRUE)
+// begin
+// // Save and then clear interrupt enable
+// bie <= ie;
+// ie <= `FALSE;
+// end
+//`else
+// if (exception == `TRUE)
+// begin
+// // Save and then clear interrupt enable
+// eie <= ie;
+// ie <= `FALSE;
+// end
+//`endif
+// else if (stall_x == `FALSE)
+// begin
+// if (eret_q_x == `TRUE)
+// // Restore interrupt enable
+// ie <= eie;
+//`ifdef CFG_DEBUG_ENABLED
+// else if (bret_q_x == `TRUE)
+// // Restore interrupt enable
+// ie <= bie;
+//`endif
+// else if (csr_write_enable == `TRUE)
+// begin
+// // Handle wcsr write
+// if (csr == `LM32_CSR_IE)
+// begin
+// ie <= csr_write_data[0];
+// eie <= csr_write_data[1];
+//`ifdef CFG_DEBUG_ENABLED
+// bie <= csr_write_data[2];
+//`endif
+// end
+// if (csr == `LM32_CSR_IP)
+// ip <= asserted & ~csr_write_data[interrupts-1:0];
+// end
+// end
+// end
+//end
+// end
+//endgenerate
+
+endmodule
+
lm32/verilog/src/lm32_interrupt.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_dp_ram.v
===================================================================
--- lm32/verilog/src/lm32_dp_ram.v (nonexistent)
+++ lm32/verilog/src/lm32_dp_ram.v (revision 17)
@@ -0,0 +1,41 @@
+module lm32_dp_ram(
+ clk_i,
+ rst_i,
+ we_i,
+ waddr_i,
+ wdata_i,
+ raddr_i,
+ rdata_o);
+
+parameter addr_width = 32;
+parameter addr_depth = 1024;
+parameter data_width = 8;
+
+input clk_i;
+input rst_i;
+input we_i;
+input [addr_width-1:0] waddr_i;
+input [data_width-1:0] wdata_i;
+input [addr_width-1:0] raddr_i;
+output [data_width-1:0] rdata_o;
+
+reg [data_width-1:0] ram[addr_depth-1:0];
+
+reg [addr_width-1:0] raddr_r;
+assign rdata_o = ram[raddr_r];
+
+integer i;
+initial begin
+ for (i=0;i
lm32/verilog/src/lm32_dp_ram.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_addsub.v
===================================================================
--- lm32/verilog/src/lm32_addsub.v (nonexistent)
+++ lm32/verilog/src/lm32_addsub.v (revision 17)
@@ -0,0 +1,69 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_addsub.v
+// Title : PMI adder/subtractor.
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_addsub (
+ // ----- Inputs -------
+ DataA,
+ DataB,
+ Cin,
+ Add_Sub,
+ // ----- Outputs -------
+ Result,
+ Cout
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input [31:0] DataA;
+input [31:0] DataB;
+input Cin;
+input Add_Sub;
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [31:0] Result;
+wire [31:0] Result;
+output Cout;
+wire Cout;
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+ wire [32:0] tmp_addResult = DataA + DataB + Cin;
+ wire [32:0] tmp_subResult = DataA - DataB - !Cin;
+
+ assign Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
+ assign Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
+
+
+endmodule
lm32/verilog/src/lm32_addsub.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_shifter.v
===================================================================
--- lm32/verilog/src/lm32_shifter.v (nonexistent)
+++ lm32/verilog/src/lm32_shifter.v (revision 17)
@@ -0,0 +1,129 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_shifter.v
+// Title : Barrel shifter
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_shifter (
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ stall_x,
+ direction_x,
+ sign_extend_x,
+ operand_0_x,
+ operand_1_x,
+ // ----- Outputs -------
+ shifter_result_m
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+input stall_x; // Stall instruction in X stage
+input direction_x; // Direction to shift
+input sign_extend_x; // Whether shift is arithmetic (1'b1) or logical (1'b0)
+input [`LM32_WORD_RNG] operand_0_x; // Operand to shift
+input [`LM32_WORD_RNG] operand_1_x; // Operand that specifies how many bits to shift by
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] shifter_result_m; // Result of shift
+wire [`LM32_WORD_RNG] shifter_result_m;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+reg direction_m;
+reg [`LM32_WORD_RNG] left_shift_result;
+reg [`LM32_WORD_RNG] right_shift_result;
+reg [`LM32_WORD_RNG] left_shift_operand;
+wire [`LM32_WORD_RNG] right_shift_operand;
+wire fill_value;
+wire [`LM32_WORD_RNG] right_shift_in;
+
+integer shift_idx_0;
+integer shift_idx_1;
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+// Select operands - To perform a left shift, we reverse the bits and perform a right shift
+always @*
+begin
+ for (shift_idx_0 = 0; shift_idx_0 < `LM32_WORD_WIDTH; shift_idx_0 = shift_idx_0 + 1)
+ left_shift_operand[`LM32_WORD_WIDTH-1-shift_idx_0] = operand_0_x[shift_idx_0];
+end
+assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x;
+
+// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
+assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT)
+ ? operand_0_x[`LM32_WORD_WIDTH-1]
+ : 1'b0;
+
+// Determine bits to shift in for right shift or rotate
+assign right_shift_in = {`LM32_WORD_WIDTH{fill_value}};
+
+// Reverse bits to get left shift result
+always @*
+begin
+ for (shift_idx_1 = 0; shift_idx_1 < `LM32_WORD_WIDTH; shift_idx_1 = shift_idx_1 + 1)
+ left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result[shift_idx_1];
+end
+
+// Select result
+assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result;
+
+/////////////////////////////////////////////////////
+// Sequential Logic
+/////////////////////////////////////////////////////
+
+// Perform right shift
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ right_shift_result <= {`LM32_WORD_WIDTH{1'b0}};
+ direction_m <= `FALSE;
+ end
+ else
+ begin
+ if (stall_x == `FALSE)
+ begin
+ right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG];
+ direction_m <= direction_x;
+ end
+ end
+end
+
+endmodule
lm32/verilog/src/lm32_shifter.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_simtrace.v
===================================================================
--- lm32/verilog/src/lm32_simtrace.v (nonexistent)
+++ lm32/verilog/src/lm32_simtrace.v (revision 17)
@@ -0,0 +1,165 @@
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_simtrace.v
+// Title : Trace excecution in simulation
+// Dependencies : lm32_include.v
+// Version : soc-lm32 only
+// =============================================================================
+
+`include "lm32_include.v"
+
+// Index of opcode field in an instruction
+`define LM32_OPCODE_RNG 31:26
+`define LM32_OP_RNG 30:26
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_simtrace (
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ // From pipeline
+ stall_x,
+ stall_m,
+ valid_w,
+ kill_w,
+ instruction_d,
+ pc_w
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i;
+input rst_i;
+input stall_x; //
+input stall_m; //
+input valid_w; //
+input kill_w; //
+input [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction to decode
+input [`LM32_PC_RNG] pc_w; // PC of instruction in D stage
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+reg [`LM32_INSTRUCTION_RNG] instruction_x; // Instruction to decode
+reg [`LM32_INSTRUCTION_RNG] instruction_m; // Instruction to decode
+reg [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode
+
+wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate
+wire [`LM32_WORD_RNG] high_immediate; // Immedate as high 16 bits
+wire [`LM32_WORD_RNG] immediate; // Immedate as high 16 bits
+wire [`LM32_WORD_RNG] call_immediate; // Call immediate
+wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate
+
+/////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////
+`define INCLUDE_FUNCTION
+`include "lm32_functions.v"
+
+
+wire [4:0] r3 = instruction[25:21];
+wire [4:0] r2 = instruction[20:16];
+wire [4:0] r1 = instruction[15:11];
+
+wire [ 4:0] imm5 = instruction[ 4:0];
+wire [15:0] imm16 = instruction[15:0];
+wire [26:0] imm27 = instruction[26:0];
+
+//assign high_imm = {instruction[15:0], 16'h0000};
+wire [`LM32_PC_RNG] call_imm = {{ 4{instruction[25]}}, instruction[25:0]};
+wire [`LM32_PC_RNG] branch_imm = {{14{instruction[15]}}, instruction[15:0] };
+
+// synopsys translate_off
+
+always @(posedge clk_i)
+begin
+ if (stall_x == `FALSE)
+ instruction_x <= instruction_d;
+ if (stall_m == `FALSE)
+ instruction_m <= instruction_x;
+ instruction <= instruction_m;
+
+ if ((valid_w == `TRUE) && (!kill_w)) begin
+ // $write ( $stime/10 );
+ $writeh( " [", pc_w << 2);
+ $writeh( "]\t" );
+
+ case ( instruction[`LM32_OPCODE_RNG] )
+ 6'h00: $display( "srui r%0d, r%0d, 0x%0x", r2, r3, imm5 );
+ 6'h01: $display( "nori r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h02: $display( "muli r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h03: $display( "sh (r%0d + 0x%0x), r%0d", r3, r2, imm16 );
+ 6'h04: $display( "lb r%0d, (r%0d + 0x%0x)", r2, r3, imm16 );
+ 6'h05: $display( "sri r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h06: $display( "xori r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h07: $display( "lh r%0d, (r%0d + 0x%0x)", r2, r3, imm16 );
+ 6'h08: $display( "andi r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h09: $display( "xnori r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h0a: $display( "lw r%0d, (r%0d + 0x%0x)", r2, r3, imm16 );
+ 6'h0b: $display( "lhu r%0d, (r%0d + 0x%0x)", r2, r3, imm16 );
+ 6'h0c: $display( "sb (r%0d + 0x%0x), r%0d", r3, r2, imm16 );
+ 6'h0d: $display( "addi r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h0e: $display( "ori r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h0f: $display( "sli r%0d, r%0d, 0x%0x", r2, r3, imm5 );
+ 6'h10: $display( "lbu r%0d, (r%0d + 0x%0x)", r2, r3, imm16 );
+ 6'h11: $display( "be r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
+ 6'h12: $display( "bg r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
+ 6'h13: $display( "bge r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
+ 6'h14: $display( "bgeu r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
+ 6'h15: $display( "bgu r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
+ 6'h16: $display( "sw (r%0d + 0x%0x), r%0d", r3, r2, imm16 );
+ 6'h17: $display( "bne r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
+ 6'h18: $display( "andhi r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h19: $display( "cmpei r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h1a: $display( "cmpgi r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h1b: $display( "cmpgei r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h1c: $display( "cmpgeui r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h1d: $display( "cmpgui r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h1e: $display( "orhi r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h1f: $display( "cmpnei r%0d, r%0d, 0x%0x", r2, r3, imm16 );
+ 6'h20: $display( "sru r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h21: $display( "nor r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h22: $display( "mul r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h23: $display( "divu r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h24: $display( "rcsr r%0d, csr%0d", r1, r3 );
+ 6'h25: $display( "sr r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h26: $display( "xor r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h27: $display( "div (XXX not documented XXX)" );
+ 6'h28: $display( "and r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h29: $display( "xnor r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h2a: $display( "XXX" );
+ 6'h2b: $display( "raise (XXX: scall or break)" );
+ 6'h2c: $display( "sextb r%0d, r%0d", r1, r3 );
+ 6'h2d: $display( "add r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h2e: $display( "or r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h2f: $display( "sl r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h30: $display( "b r%0d", r3 );
+ 6'h31: $display( "modu r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h32: $display( "sub r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h33: $display( "XXX" );
+ 6'h34: $display( "wcsr csr%0d, r%0d", r3, r2 );
+ 6'h35: $display( "modu r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h36: $display( "call r%0d", r3 );
+ 6'h37: $display( "sexth r%0d, r%0d", r1, r3 );
+ 6'h38: $display( "bi 0x%x", (pc_w + call_imm) << 2 );
+ 6'h39: $display( "cmpe r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h3a: $display( "cmpg r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h3b: $display( "cmpge r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h3c: $display( "cmpgeu r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h3d: $display( "cmpgu r%0d, r%0d, r%0d", r1, r3, r2 );
+ 6'h3e: $display( "calli 0x%x", (pc_w + call_imm) << 2 );
+ 6'h3f: $display( "cmpne r%0d, r%0d, r%0d", r1, r3, r2 );
+ endcase
+ end
+end
+
+// synopsys translate_on
+
+endmodule
+
lm32/verilog/src/lm32_simtrace.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_dcache.v
===================================================================
--- lm32/verilog/src/lm32_dcache.v (nonexistent)
+++ lm32/verilog/src/lm32_dcache.v (revision 17)
@@ -0,0 +1,494 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_dcache.v
+// Title : Data cache
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+`ifdef CFG_DCACHE_ENABLED
+
+`define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
+`define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
+`define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
+`define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
+
+`define LM32_DC_TMEM_ADDR_WIDTH addr_set_width
+`define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0
+`define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
+`define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0
+
+`define LM32_DC_TAGS_WIDTH (addr_tag_width+1)
+`define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0
+`define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1
+`define LM32_DC_TAGS_VALID_RNG 0
+
+`define LM32_DC_STATE_RNG 2:0
+`define LM32_DC_STATE_FLUSH 3'b001
+`define LM32_DC_STATE_CHECK 3'b010
+`define LM32_DC_STATE_REFILL 3'b100
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_dcache (
+ // ----- Inputs -----
+ clk_i,
+ rst_i,
+ stall_a,
+ stall_x,
+ stall_m,
+ address_x,
+ address_m,
+ load_q_m,
+ store_q_m,
+ store_data,
+ store_byte_select,
+ refill_ready,
+ refill_data,
+ dflush,
+ // ----- Outputs -----
+ stall_request,
+ restart_request,
+ refill_request,
+ refill_address,
+ refilling,
+ load_data
+ );
+
+/////////////////////////////////////////////////////
+// Parameters
+/////////////////////////////////////////////////////
+
+parameter associativity = 1; // Associativity of the cache (Number of ways)
+parameter sets = 512; // Number of sets
+parameter bytes_per_line = 16; // Number of bytes per cache line
+parameter base_address = 0; // Base address of cachable memory
+parameter limit = 0; // Limit (highest address) of cachable memory
+
+//localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_offset_width = 2;
+//localparam addr_set_width = clogb2(sets)-1;
+localparam addr_set_width = 9;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = 31;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+
+input stall_a; // Stall A stage
+input stall_x; // Stall X stage
+input stall_m; // Stall M stage
+
+input [`LM32_WORD_RNG] address_x; // X stage load/store address
+input [`LM32_WORD_RNG] address_m; // M stage load/store address
+input load_q_m; // Load instruction in M stage
+input store_q_m; // Store instruction in M stage
+input [`LM32_WORD_RNG] store_data; // Data to store
+input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified
+
+input refill_ready; // Indicates next word of refill data is ready
+input [`LM32_WORD_RNG] refill_data; // Refill data
+
+input dflush; // Indicates cache should be flushed
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output stall_request; // Request pipeline be stalled because cache is busy
+wire stall_request;
+output restart_request; // Request to restart instruction that caused the cache miss
+reg restart_request;
+output refill_request; // Request a refill
+reg refill_request;
+output [`LM32_WORD_RNG] refill_address; // Address to refill from
+reg [`LM32_WORD_RNG] refill_address;
+output refilling; // Indicates if the cache is currently refilling
+reg refilling;
+output [`LM32_WORD_RNG] load_data; // Data read from cache
+wire [`LM32_WORD_RNG] load_data;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+wire read_port_enable; // Cache memory read port clock enable
+wire write_port_enable; // Cache memory write port clock enable
+wire [0:associativity-1] way_tmem_we; // Tag memory write enable
+wire [0:associativity-1] way_dmem_we; // Data memory write enable
+wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory
+wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
+wire [0:associativity-1] way_valid; // Indicates which ways are valid
+wire [0:associativity-1] way_match; // Indicates which ways matched
+wire miss; // Indicates no ways matched
+
+wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address
+wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address
+wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address
+wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address
+wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
+reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data
+
+reg [`LM32_DC_STATE_RNG] state; // Current state of FSM
+wire flushing; // Indicates if cache is currently flushing
+wire check; // Indicates if cache is currently checking for hits/misses
+wire refill; // Indicates if cache is currently refilling
+
+wire valid_store; // Indicates if there is a valid store instruction
+reg [associativity-1:0] refill_way_select; // Which way should be refilled
+reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled
+wire last_refill; // Indicates when on last cycle of cache refill
+reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed
+
+genvar i, j;
+
+/////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////
+ `define INCLUDE_FUNCTION
+`include "lm32_functions.v"
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+generate
+ for (i = 0; i < associativity; i = i + 1)
+ begin : memories
+// Way data
+
+ if (`LM32_DC_DMEM_ADDR_WIDTH < 7)
+ begin : data_memories
+lm32_ram #(
+ // ----- Parameters -------
+ .data_width (32),
+ .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
+ ) way_0_data_ram (
+ // ----- Inputs -------
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .read_address (dmem_read_address),
+ .enable_read (read_port_enable),
+ .write_address (dmem_write_address),
+ .enable_write (write_port_enable),
+ .write_enable (way_dmem_we[i]),
+ .write_data (dmem_write_data),
+ // ----- Outputs -------
+ .read_data (way_data[i])
+ );
+ end
+ else
+ begin
+ for (j = 0; j < 4; j = j + 1)
+ begin : byte_memories
+lm32_ram #(
+ // ----- Parameters -------
+ .data_width (8),
+ .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
+ ) way_0_data_ram (
+ // ----- Inputs -------
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .read_address (dmem_read_address),
+ .enable_read (read_port_enable),
+ .write_address (dmem_write_address),
+ .enable_write (write_port_enable),
+ .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
+ .write_data (dmem_write_data[(j+1)*8-1:j*8]),
+ // ----- Outputs -------
+ .read_data (way_data[i][(j+1)*8-1:j*8])
+ );
+ end
+ end
+
+// Way tags
+lm32_ram #(
+ // ----- Parameters -------
+ .data_width (`LM32_DC_TAGS_WIDTH),
+ .address_width (`LM32_DC_TMEM_ADDR_WIDTH)
+ ) way_0_tag_ram (
+ // ----- Inputs -------
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .read_address (tmem_read_address),
+ .enable_read (read_port_enable),
+ .write_address (tmem_write_address),
+ .enable_write (`TRUE),
+ .write_enable (way_tmem_we[i]),
+ .write_data (tmem_write_data),
+ // ----- Outputs -------
+ .read_data ({way_tag[i], way_valid[i]})
+ );
+
+ end
+
+endgenerate
+
+/////////////////////////////////////////////////////
+// Combinational logic
+/////////////////////////////////////////////////////
+
+// Compute which ways in the cache match the address being read
+generate
+ for (i = 0; i < associativity; i = i + 1)
+ begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
+ end
+endgenerate
+
+// Select data from way that matched the address being read
+generate
+ if (associativity == 1)
+ begin : data_1
+assign load_data = way_data[0];
+ end
+ else if (associativity == 2)
+ begin : data_2
+assign load_data = way_match[0] ? way_data[0] : way_data[1];
+ end
+endgenerate
+
+generate
+ if (`LM32_DC_DMEM_ADDR_WIDTH < 7)
+ begin
+// Select data to write to data memories
+always @(*)
+begin
+ if (refill == `TRUE)
+ dmem_write_data = refill_data;
+ else
+ begin
+ dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
+ dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
+ dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
+ dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
+ end
+end
+ end
+ else
+ begin
+// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
+always @(*)
+begin
+ if (refill == `TRUE)
+ dmem_write_data = refill_data;
+ else
+ dmem_write_data = store_data;
+end
+ end
+endgenerate
+
+// Compute address to use to index into the data memories
+generate
+ if (bytes_per_line > 4)
+assign dmem_write_address = (refill == `TRUE)
+ ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
+ : address_m[`LM32_DC_ADDR_IDX_RNG];
+ else
+assign dmem_write_address = (refill == `TRUE)
+ ? refill_address[`LM32_DC_ADDR_SET_RNG]
+ : address_m[`LM32_DC_ADDR_IDX_RNG];
+endgenerate
+assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
+// Compute address to use to index into the tag memories
+assign tmem_write_address = (flushing == `TRUE)
+ ? flush_set
+ : refill_address[`LM32_DC_ADDR_SET_RNG];
+assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
+
+// Compute signal to indicate when we are on the last refill accesses
+generate
+ if (bytes_per_line > 4)
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+ else
+assign last_refill = `TRUE;
+endgenerate
+
+// Compute data and tag memory access enable
+assign read_port_enable = (stall_x == `FALSE);
+assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
+
+// Determine when we have a valid store
+assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
+
+// Compute data and tag memory write enables
+generate
+ if (associativity == 1)
+ begin : we_1
+assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
+assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
+ end
+ else
+ begin : we_2
+assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
+assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
+assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
+assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
+ end
+endgenerate
+
+// On the last refill cycle set the valid bit, for all other writes it should be cleared
+assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
+assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
+
+// Signals that indicate which state we are in
+assign flushing = state[0];
+assign check = state[1];
+assign refill = state[2];
+
+assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
+assign stall_request = (check == `FALSE);
+
+/////////////////////////////////////////////////////
+// Sequential logic
+/////////////////////////////////////////////////////
+
+// Record way selected for replacement on a cache miss
+generate
+ if (associativity >= 2)
+ begin : way_select
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+ else
+ begin
+ if (refill_request == `TRUE)
+ refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+ end
+end
+ end
+endgenerate
+
+// Record whether we are currently refilling
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ refilling <= `FALSE;
+ else
+ refilling <= refill;
+end
+
+// Instruction cache control FSM
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ state <= `LM32_DC_STATE_FLUSH;
+ flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
+ refill_request <= `FALSE;
+ refill_address <= {`LM32_WORD_WIDTH{1'bx}};
+ restart_request <= `FALSE;
+ end
+ else
+ begin
+ case (state)
+
+ // Flush the cache
+ `LM32_DC_STATE_FLUSH:
+ begin
+ if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
+ state <= `LM32_DC_STATE_CHECK;
+ flush_set <= flush_set - 1'b1;
+ end
+
+ // Check for cache misses
+ `LM32_DC_STATE_CHECK:
+ begin
+ if (stall_a == `FALSE)
+ restart_request <= `FALSE;
+ if (miss == `TRUE)
+ begin
+ refill_request <= `TRUE;
+ refill_address <= address_m;
+ state <= `LM32_DC_STATE_REFILL;
+ end
+ else if (dflush == `TRUE)
+ state <= `LM32_DC_STATE_FLUSH;
+ end
+
+ // Refill a cache line
+ `LM32_DC_STATE_REFILL:
+ begin
+ refill_request <= `FALSE;
+ if (refill_ready == `TRUE)
+ begin
+ if (last_refill == `TRUE)
+ begin
+ restart_request <= `TRUE;
+ state <= `LM32_DC_STATE_CHECK;
+ end
+ end
+ end
+
+ endcase
+ end
+end
+
+generate
+ if (bytes_per_line > 4)
+ begin
+// Refill offset
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else
+ begin
+ case (state)
+
+ // Check for cache misses
+ `LM32_DC_STATE_CHECK:
+ begin
+ if (miss == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ end
+
+ // Refill a cache line
+ `LM32_DC_STATE_REFILL:
+ begin
+ if (refill_ready == `TRUE)
+ refill_offset <= refill_offset + 1'b1;
+ end
+
+ endcase
+ end
+end
+ end
+endgenerate
+
+endmodule
+
+`endif
+
lm32/verilog/src/lm32_dcache.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_ram.v
===================================================================
--- lm32/verilog/src/lm32_ram.v (nonexistent)
+++ lm32/verilog/src/lm32_ram.v (revision 17)
@@ -0,0 +1,105 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_ram.v
+// Title : Pseudo dual-port RAM.
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_ram (
+ // ----- Inputs -------
+ read_clk,
+ write_clk,
+ reset,
+ enable_read,
+ read_address,
+ enable_write,
+ write_address,
+ write_data,
+ write_enable,
+ // ----- Outputs -------
+ read_data
+ );
+
+/////////////////////////////////////////////////////
+// Parameters
+/////////////////////////////////////////////////////
+
+parameter data_width = 1; // Width of the data ports
+parameter address_width = 1; // Width of the address ports
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input read_clk; // Read clock
+input write_clk; // Write clock
+input reset; // Reset
+
+input enable_read; // Access enable
+input [address_width-1:0] read_address; // Read/write address
+input enable_write; // Access enable
+input [address_width-1:0] write_address;// Read/write address
+input [data_width-1:0] write_data; // Data to write to specified address
+input write_enable; // Write enable
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [data_width-1:0] read_data; // Data read from specified addess
+wire [data_width-1:0] read_data;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+reg [data_width-1:0] mem[0:(1<
lm32/verilog/src/lm32_ram.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_adder.v
===================================================================
--- lm32/verilog/src/lm32_adder.v (nonexistent)
+++ lm32/verilog/src/lm32_adder.v (revision 17)
@@ -0,0 +1,110 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// ============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_adder.v
+// Title : Integer adder / subtractor with comparison flag generation
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_adder (
+ // ----- Inputs -------
+ adder_op_x,
+ adder_op_x_n,
+ operand_0_x,
+ operand_1_x,
+ // ----- Outputs -------
+ adder_result_x,
+ adder_carry_n_x,
+ adder_overflow_x
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction
+input adder_op_x_n; // Inverted version of adder_op_x
+input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from
+input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction
+wire [`LM32_WORD_RNG] adder_result_x;
+output adder_carry_n_x; // Inverted carry
+wire adder_carry_n_x;
+output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions
+reg adder_overflow_x;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+wire a_sign; // Sign (i.e. positive or negative) of operand 0
+wire b_sign; // Sign of operand 1
+wire result_sign; // Sign of result
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+lm32_addsub addsub (
+ // ----- Inputs -----
+ .DataA (operand_0_x),
+ .DataB (operand_1_x),
+ .Cin (adder_op_x),
+ .Add_Sub (adder_op_x_n),
+ // ----- Ouputs -----
+ .Result (adder_result_x),
+ .Cout (adder_carry_n_x)
+ );
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+// Extract signs of operands and result
+
+assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
+assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
+assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
+
+// Determine whether an overflow occured when performing a subtraction
+
+always @*
+begin
+ // +ve - -ve = -ve -> overflow
+ // -ve - +ve = +ve -> overflow
+ if ( (!a_sign & b_sign & result_sign)
+ || (a_sign & !b_sign & !result_sign)
+ )
+ adder_overflow_x = `TRUE;
+ else
+ adder_overflow_x = `FALSE;
+end
+
+endmodule
+
lm32/verilog/src/lm32_adder.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_include.v
===================================================================
--- lm32/verilog/src/lm32_include.v (nonexistent)
+++ lm32/verilog/src/lm32_include.v (revision 17)
@@ -0,0 +1,320 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_include.v
+// Title : CPU global macros
+// Version : 6.1.17
+// =============================================================================
+
+`ifdef LM32_INCLUDE_V
+`else
+`define LM32_INCLUDE_V
+
+// Configuration options
+`include "system_conf.v"
+
+`ifdef TRUE
+`else
+`define TRUE 1'b1
+`define FALSE 1'b0
+`define TRUE_N 1'b0
+`define FALSE_N 1'b1
+`endif
+
+// Wishbone configuration
+`define CFG_IWB_ENABLED
+`define CFG_DWB_ENABLED
+
+// Data-path width
+`define LM32_WORD_WIDTH 32
+`define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0
+`define LM32_SHIFT_WIDTH 5
+`define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0
+`define LM32_BYTE_SELECT_WIDTH 4
+`define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0
+
+// Register file size
+`define LM32_REGISTERS 32
+`define LM32_REG_IDX_WIDTH 5
+`define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0
+
+// Standard register numbers
+`define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29
+`define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30
+`define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31
+
+// Range of Program Counter. Two LSBs are always 0.
+`ifdef CFG_ICACHE_ENABLED
+// XXX `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2) XXX
+`define LM32_PC_WIDTH 30
+`else
+`ifdef CFG_IWB_ENABLED
+`define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2)
+`else
+`define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH
+`endif
+`endif
+`define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2
+
+// Range of an instruction
+`define LM32_INSTRUCTION_WIDTH 32
+`define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0
+
+// Adder operation
+`define LM32_ADDER_OP_ADD 1'b0
+`define LM32_ADDER_OP_SUBTRACT 1'b1
+
+// Shift direction
+`define LM32_SHIFT_OP_RIGHT 1'b0
+`define LM32_SHIFT_OP_LEFT 1'b1
+
+// Currently always enabled
+`define CFG_BUS_ERRORS_ENABLED
+
+// Derive macro that indicates whether we have single-stepping or not
+`ifdef CFG_ROM_DEBUG_ENABLED
+`define LM32_SINGLE_STEP_ENABLED
+`else
+`ifdef CFG_HW_DEBUG_ENABLED
+`define LM32_SINGLE_STEP_ENABLED
+`endif
+`endif
+
+// Derive macro that indicates whether JTAG interface is required
+`ifdef CFG_JTAG_UART_ENABLED
+`define LM32_JTAG_ENABLED
+`else
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_JTAG_ENABLED
+`else
+`endif
+`endif
+
+// Derive macro that indicates whether we have a barrel-shifter or not
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+`define LM32_BARREL_SHIFT_ENABLED
+`else // CFG_PL_BARREL_SHIFT_ENABLED
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+`define LM32_BARREL_SHIFT_ENABLED
+`else
+`define LM32_NO_BARREL_SHIFT
+`endif
+`endif // CFG_PL_BARREL_SHIFT_ENABLED
+
+// Derive macro that indicates whether we have a multiplier or not
+`ifdef CFG_PL_MULTIPLY_ENABLED
+`define LM32_MULTIPLY_ENABLED
+`else
+`ifdef CFG_MC_MULTIPLY_ENABLED
+`define LM32_MULTIPLY_ENABLED
+`endif
+`endif
+
+// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
+`ifdef CFG_MC_DIVIDE_ENABLED
+`define LM32_MC_ARITHMETIC_ENABLED
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+`define LM32_MC_ARITHMETIC_ENABLED
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+`define LM32_MC_ARITHMETIC_ENABLED
+`endif
+
+// Derive macro that indicates if we are using an EBR register file
+`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
+`define LM32_EBR_REGISTER_FILE
+`endif
+`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
+`define LM32_EBR_REGISTER_FILE
+`endif
+
+// Revision number
+`define LM32_REVISION 6'h11
+
+// Logical operations - Function encoded directly in instruction
+`define LM32_LOGIC_OP_RNG 3:0
+
+// Conditions for conditional branches
+`define LM32_CONDITION_WIDTH 3
+`define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0
+`define LM32_CONDITION_E 3'b001
+`define LM32_CONDITION_G 3'b010
+`define LM32_CONDITION_GE 3'b011
+`define LM32_CONDITION_GEU 3'b100
+`define LM32_CONDITION_GU 3'b101
+`define LM32_CONDITION_NE 3'b111
+`define LM32_CONDITION_U1 3'b000
+`define LM32_CONDITION_U2 3'b110
+
+// Size of load or store instruction - Encoding corresponds to opcode
+`define LM32_SIZE_WIDTH 2
+`define LM32_SIZE_RNG 1:0
+`define LM32_SIZE_BYTE 2'b00
+`define LM32_SIZE_HWORD 2'b11
+`define LM32_SIZE_WORD 2'b10
+`define LM32_ADDRESS_LSBS_WIDTH 2
+
+// Width and range of a CSR index
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_CSR_WIDTH 5
+`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
+`else
+`ifdef CFG_JTAG_ENABLED
+`define LM32_CSR_WIDTH 4
+`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
+`else
+`define LM32_CSR_WIDTH 3
+`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
+`endif
+`endif
+
+// CSR indices
+`define LM32_CSR_IE `LM32_CSR_WIDTH'h0
+`define LM32_CSR_IM `LM32_CSR_WIDTH'h1
+`define LM32_CSR_IP `LM32_CSR_WIDTH'h2
+`define LM32_CSR_ICC `LM32_CSR_WIDTH'h3
+`define LM32_CSR_DCC `LM32_CSR_WIDTH'h4
+`define LM32_CSR_CC `LM32_CSR_WIDTH'h5
+`define LM32_CSR_CFG `LM32_CSR_WIDTH'h6
+`define LM32_CSR_EBA `LM32_CSR_WIDTH'h7
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_CSR_DC `LM32_CSR_WIDTH'h8
+`define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9
+`endif
+`ifdef CFG_JTAG_ENABLED
+`define LM32_CSR_JTX `LM32_CSR_WIDTH'he
+`define LM32_CSR_JRX `LM32_CSR_WIDTH'hf
+`endif
+`ifdef CFG_DEBUG_ENABLED
+`define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10
+`define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11
+`define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12
+`define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13
+`define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18
+`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
+`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
+`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
+`endif
+
+// Values for WPC CSR
+`define LM32_WPC_C_RNG 1:0
+`define LM32_WPC_C_DISABLED 2'b00
+`define LM32_WPC_C_READ 2'b01
+`define LM32_WPC_C_WRITE 2'b10
+`define LM32_WPC_C_READ_WRITE 2'b11
+
+// Exception IDs
+`define LM32_EID_WIDTH 3
+`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
+`define LM32_EID_RESET 3'h0
+`define LM32_EID_BREAKPOINT 3'd1
+`define LM32_EID_INST_BUS_ERROR 3'h2
+`define LM32_EID_WATCHPOINT 3'd3
+`define LM32_EID_DATA_BUS_ERROR 3'h4
+`define LM32_EID_DIVIDE_BY_ZERO 3'h5
+`define LM32_EID_INTERRUPT 3'h6
+`define LM32_EID_SCALL 3'h7
+
+// Pipeline result selection mux controls
+
+`define LM32_D_RESULT_SEL_0_RNG 0:0
+`define LM32_D_RESULT_SEL_0_REG_0 1'b0
+`define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1
+
+`define LM32_D_RESULT_SEL_1_RNG 1:0
+`define LM32_D_RESULT_SEL_1_ZERO 2'b00
+`define LM32_D_RESULT_SEL_1_REG_1 2'b01
+`define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10
+
+`define LM32_USER_OPCODE_WIDTH 11
+`define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0
+
+// Derive a macro to indicate if either of the caches are implemented
+`ifdef CFG_ICACHE_ENABLED
+`define LM32_CACHE_ENABLED
+`else
+`ifdef CFG_DCACHE_ENABLED
+`define LM32_CACHE_ENABLED
+`endif
+`endif
+
+/////////////////////////////////////////////////////
+// Interrupts
+/////////////////////////////////////////////////////
+
+// Always enable interrupts
+`define CFG_INTERRUPTS_ENABLED
+
+// Currently this is fixed to 32 and should not be changed
+`define CFG_INTERRUPTS 32
+`define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS
+`define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0
+
+/////////////////////////////////////////////////////
+// General
+/////////////////////////////////////////////////////
+
+// Sub-word range types
+`define LM32_BYTE_WIDTH 8
+`define LM32_BYTE_RNG 7:0
+`define LM32_HWORD_WIDTH 16
+`define LM32_HWORD_RNG 15:0
+
+// Word sub-byte indicies
+`define LM32_BYTE_0_RNG 7:0
+`define LM32_BYTE_1_RNG 15:8
+`define LM32_BYTE_2_RNG 23:16
+`define LM32_BYTE_3_RNG 31:24
+
+// Word sub-halfword indices
+`define LM32_HWORD_0_RNG 15:0
+`define LM32_HWORD_1_RNG 31:16
+
+// Use an asynchronous reset
+// To use a synchronous reset, define this macro as nothing
+`define CFG_RESET_SENSITIVITY or posedge rst_i
+
+// V.T. Srce
+`define SRCE
+
+// Whether to include context registers for debug exceptions
+// in addition to standard exception handling registers
+// Bizarre - Removing this increases LUT count!
+`define CFG_DEBUG_EXCEPTIONS_ENABLED
+
+// Wishbone defines
+// Refer to Wishbone System-on-Chip Interconnection Architecture
+// These should probably be moved to a Wishbone common file
+
+// Wishbone cycle types
+`define LM32_CTYPE_WIDTH 3
+`define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0
+`define LM32_CTYPE_CLASSIC 3'b000
+`define LM32_CTYPE_CONSTANT 3'b001
+`define LM32_CTYPE_INCREMENTING 3'b010
+`define LM32_CTYPE_END 3'b111
+
+// Wishbone burst types
+`define LM32_BTYPE_WIDTH 2
+`define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0
+`define LM32_BTYPE_LINEAR 2'b00
+`define LM32_BTYPE_4_BEAT 2'b01
+`define LM32_BTYPE_8_BEAT 2'b10
+`define LM32_BTYPE_16_BEAT 2'b11
+
+`endif
lm32/verilog/src/lm32_include.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/jtag_lm32.v
===================================================================
--- lm32/verilog/src/jtag_lm32.v (nonexistent)
+++ lm32/verilog/src/jtag_lm32.v (revision 17)
@@ -0,0 +1,195 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : jtag_lm32.v
+// Title : JTAG data register for LM32 CPU debug interface
+// Version : 6.0.13
+// =============================================================================
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module jtag_lm32 (
+ input JTCK,
+ input JTDI,
+ output JTDO2,
+ input JSHIFT,
+ input JUPDATE,
+ input JRSTN,
+ input JCE2,
+ input JTAGREG_ENABLE,
+ input CONTROL_DATAN,
+ output REG_UPDATE,
+ input [7:0] REG_D,
+ input [2:0] REG_ADDR_D,
+ output [7:0] REG_Q,
+ output [2:0] REG_ADDR_Q
+ );
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+wire [9:0] tdibus;
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+ wire clk_enable,captureDr;
+TYPEA DATA_BIT0 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(JTDI),
+ .TDO(tdibus[0]),
+ .DATA_OUT(REG_Q[0]),
+ .DATA_IN(REG_D[0]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT1 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[0]),
+ .TDO(tdibus[1]),
+ .DATA_OUT(REG_Q[1]),
+ .DATA_IN(REG_D[1]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT2 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[1]),
+ .TDO(tdibus[2]),
+ .DATA_OUT(REG_Q[2]),
+ .DATA_IN(REG_D[2]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT3 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[2]),
+ .TDO(tdibus[3]),
+ .DATA_OUT(REG_Q[3]),
+ .DATA_IN(REG_D[3]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT4 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[3]),
+ .TDO(tdibus[4]),
+ .DATA_OUT(REG_Q[4]),
+ .DATA_IN(REG_D[4]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT5 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[4]),
+ .TDO(tdibus[5]),
+ .DATA_OUT(REG_Q[5]),
+ .DATA_IN(REG_D[5]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT6 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[5]),
+ .TDO(tdibus[6]),
+ .DATA_OUT(REG_Q[6]),
+ .DATA_IN(REG_D[6]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA DATA_BIT7 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[6]),
+ .TDO(tdibus[7]),
+ .DATA_OUT(REG_Q[7]),
+ .DATA_IN(REG_D[7]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA ADDR_BIT0 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[7]),
+ .TDO(tdibus[8]),
+ .DATA_OUT(REG_ADDR_Q[0]),
+ .DATA_IN(REG_ADDR_D[0]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA ADDR_BIT1 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[8]),
+ .TDO(tdibus[9]),
+ .DATA_OUT(REG_ADDR_Q[1]),
+ .DATA_IN(REG_ADDR_D[1]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+TYPEA ADDR_BIT2 (
+ .CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(clk_enable),
+ .TDI(tdibus[9]),
+ .TDO(JTDO2),
+ .DATA_OUT(REG_ADDR_Q[2]),
+ .DATA_IN(REG_ADDR_D[2]),
+ .CAPTURE_DR(captureDr),
+ .UPDATE_DR(JUPDATE)
+ );
+
+/////////////////////////////////////////////////////
+// Combinational logic
+/////////////////////////////////////////////////////
+
+assign clk_enable = JTAGREG_ENABLE & JCE2;
+assign captureDr = !JSHIFT & JCE2;
+// JCE2 is only active during shift
+assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
+
+endmodule
lm32/verilog/src/jtag_lm32.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_jtag.v
===================================================================
--- lm32/verilog/src/lm32_jtag.v (nonexistent)
+++ lm32/verilog/src/lm32_jtag.v (revision 17)
@@ -0,0 +1,491 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_jtag.v
+// Title : JTAG interface
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+`ifdef CFG_JTAG_ENABLED
+
+`define LM32_DP 3'b000
+`define LM32_TX 3'b001
+`define LM32_RX 3'b010
+
+// LM32 Debug Protocol commands IDs
+`define LM32_DP_RNG 3:0
+`define LM32_DP_READ_MEMORY 4'b0001
+`define LM32_DP_WRITE_MEMORY 4'b0010
+`define LM32_DP_READ_SEQUENTIAL 4'b0011
+`define LM32_DP_WRITE_SEQUENTIAL 4'b0100
+`define LM32_DP_WRITE_CSR 4'b0101
+`define LM32_DP_BREAK 4'b0110
+`define LM32_DP_RESET 4'b0111
+
+// States for FSM
+`define LM32_JTAG_STATE_RNG 3:0
+`define LM32_JTAG_STATE_READ_COMMAND 4'h0
+`define LM32_JTAG_STATE_READ_BYTE_0 4'h1
+`define LM32_JTAG_STATE_READ_BYTE_1 4'h2
+`define LM32_JTAG_STATE_READ_BYTE_2 4'h3
+`define LM32_JTAG_STATE_READ_BYTE_3 4'h4
+`define LM32_JTAG_STATE_READ_BYTE_4 4'h5
+`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6
+`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7
+`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_jtag (
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+`ifdef CFG_JTAG_UART_ENABLED
+ csr,
+ csr_write_enable,
+ csr_write_data,
+ stall_x,
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ jtag_read_data,
+ jtag_access_complete,
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ exception_q_w,
+`endif
+ // ----- Outputs -------
+`ifdef CFG_JTAG_UART_ENABLED
+ jtx_csr_read_data,
+ jrx_csr_read_data,
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+ jtag_csr_write_enable,
+ jtag_csr_write_data,
+ jtag_csr,
+ jtag_read_enable,
+ jtag_write_enable,
+ jtag_write_data,
+ jtag_address,
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ jtag_break,
+ jtag_reset,
+`endif
+ jtag_reg_d,
+ jtag_reg_addr_d
+ );
+
+ parameter lat_family = `LATTICE_FAMILY;
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+
+input jtag_clk; // JTAG clock
+input jtag_update; // JTAG data register has been updated
+input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register
+input [2:0] jtag_reg_addr_q; // JTAG data register
+
+`ifdef CFG_JTAG_UART_ENABLED
+input [`LM32_CSR_RNG] csr; // CSR to write
+input csr_write_enable; // CSR write enable
+input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
+input stall_x; // Stall instruction in X stage
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address
+input jtag_access_complete; // Memory access if complete
+`endif
+`ifdef CFG_DEBUG_ENABLED
+input exception_q_w; // Indicates an exception has occured in W stage
+`endif
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+`ifdef CFG_JTAG_UART_ENABLED
+output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions
+wire [`LM32_WORD_RNG] jtx_csr_read_data;
+output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions
+wire [`LM32_WORD_RNG] jrx_csr_read_data;
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+output jtag_csr_write_enable; // CSR write enable
+reg jtag_csr_write_enable;
+output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
+wire [`LM32_WORD_RNG] jtag_csr_write_data;
+output [`LM32_CSR_RNG] jtag_csr; // CSR to write
+wire [`LM32_CSR_RNG] jtag_csr;
+output jtag_read_enable; // Memory read enable
+reg jtag_read_enable;
+output jtag_write_enable; // Memory write enable
+reg jtag_write_enable;
+output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address
+wire [`LM32_BYTE_RNG] jtag_write_data;
+output [`LM32_WORD_RNG] jtag_address; // Memory read/write address
+wire [`LM32_WORD_RNG] jtag_address;
+`endif
+`ifdef CFG_DEBUG_ENABLED
+output jtag_break; // Request to raise a breakpoint exception
+reg jtag_break;
+output jtag_reset; // Request to raise a reset exception
+reg jtag_reset;
+`endif
+output [`LM32_BYTE_RNG] jtag_reg_d;
+reg [`LM32_BYTE_RNG] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+reg rx_toggle; // Clock-domain crossing registers
+reg rx_toggle_r; // Registered version of rx_toggle
+reg rx_toggle_r_r; // Registered version of rx_toggle_r
+reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r
+
+reg [`LM32_BYTE_RNG] rx_byte;
+reg [2:0] rx_addr;
+
+`ifdef CFG_JTAG_UART_ENABLED
+reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data
+reg uart_tx_valid; // TX data is valid
+reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data
+reg uart_rx_valid; // RX data is valid
+`endif
+
+reg [`LM32_DP_RNG] command; // The last received command
+`ifdef CFG_HW_DEBUG_ENABLED
+reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters
+reg [`LM32_BYTE_RNG] jtag_byte_1;
+reg [`LM32_BYTE_RNG] jtag_byte_2;
+reg [`LM32_BYTE_RNG] jtag_byte_3;
+reg [`LM32_BYTE_RNG] jtag_byte_4;
+reg processing; // Indicates if we're still processing a memory read/write
+`endif
+
+reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+`ifdef CFG_HW_DEBUG_ENABLED
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
+`endif
+
+// Generate status flags for reading via the JTAG interface
+`ifdef CFG_JTAG_UART_ENABLED
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
+`else
+assign jtag_reg_addr_d[1:0] = 2'b00;
+`endif
+`ifdef CFG_HW_DEBUG_ENABLED
+assign jtag_reg_addr_d[2] = processing;
+`else
+assign jtag_reg_addr_d[2] = 1'b0;
+`endif
+
+`ifdef CFG_JTAG_UART_ENABLED
+assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+`endif
+
+/////////////////////////////////////////////////////
+// Sequential Logic
+/////////////////////////////////////////////////////
+
+// Toggle a flag when a JTAG write occurs
+generate
+ if (lat_family == "EC" || lat_family == "ECP" ||
+ lat_family == "XP" || lat_family == "ECP2" || lat_family == "ECP2M") begin
+
+ always @(posedge jtag_clk `CFG_RESET_SENSITIVITY)
+ begin
+ if (rst_i == `TRUE)
+ rx_toggle <= 1'b0;
+ else
+ if (jtag_update == `TRUE)
+ rx_toggle <= ~rx_toggle;
+ end
+
+ end else begin // for SC & SCM
+
+ always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
+ begin
+ if (rst_i == `TRUE)
+ rx_toggle <= 1'b0;
+ else
+ rx_toggle <= ~rx_toggle;
+ end
+
+ end
+endgenerate
+
+always @(*)
+begin
+ rx_byte = jtag_reg_q;
+ rx_addr = jtag_reg_addr_q;
+end
+
+// Clock domain crossing from JTAG clock domain to CPU clock domain
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ rx_toggle_r <= 1'b0;
+ rx_toggle_r_r <= 1'b0;
+ rx_toggle_r_r_r <= 1'b0;
+ end
+ else
+ begin
+ rx_toggle_r <= rx_toggle;
+ rx_toggle_r_r <= rx_toggle_r;
+ rx_toggle_r_r_r <= rx_toggle_r_r;
+ end
+end
+
+// LM32 debug protocol state machine
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ state <= `LM32_JTAG_STATE_READ_COMMAND;
+ command <= 4'b0000;
+ jtag_reg_d <= 8'h00;
+`ifdef CFG_HW_DEBUG_ENABLED
+ processing <= `FALSE;
+ jtag_csr_write_enable <= `FALSE;
+ jtag_read_enable <= `FALSE;
+ jtag_write_enable <= `FALSE;
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ jtag_break <= `FALSE;
+ jtag_reset <= `FALSE;
+`endif
+`ifdef CFG_JTAG_UART_ENABLED
+ uart_tx_byte <= 8'h00;
+ uart_tx_valid <= `FALSE;
+ uart_rx_byte <= 8'h00;
+ uart_rx_valid <= `FALSE;
+`endif
+ end
+ else
+ begin
+`ifdef CFG_JTAG_UART_ENABLED
+ if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
+ begin
+ case (csr)
+ `LM32_CSR_JTX:
+ begin
+ // Set flag indicating data is available
+ uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
+ uart_tx_valid <= `TRUE;
+ end
+ `LM32_CSR_JRX:
+ begin
+ // Clear flag indidicating data has been received
+ uart_rx_valid <= `FALSE;
+ end
+ endcase
+ end
+`endif
+`ifdef CFG_DEBUG_ENABLED
+ // When an exception has occured, clear the requests
+ if (exception_q_w == `TRUE)
+ begin
+ jtag_break <= `FALSE;
+ jtag_reset <= `FALSE;
+ end
+`endif
+ case (state)
+ `LM32_JTAG_STATE_READ_COMMAND:
+ begin
+ // Wait for rx register to toggle which indicates new data is available
+ if (rx_toggle_r_r != rx_toggle_r_r_r)
+ begin
+ command <= rx_byte[7:4];
+ case (rx_addr)
+`ifdef CFG_DEBUG_ENABLED
+ `LM32_DP:
+ begin
+ case (rx_byte[7:4])
+`ifdef CFG_HW_DEBUG_ENABLED
+ `LM32_DP_READ_MEMORY:
+ state <= `LM32_JTAG_STATE_READ_BYTE_0;
+ `LM32_DP_READ_SEQUENTIAL:
+ begin
+ {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+ state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
+ end
+ `LM32_DP_WRITE_MEMORY:
+ state <= `LM32_JTAG_STATE_READ_BYTE_0;
+ `LM32_DP_WRITE_SEQUENTIAL:
+ begin
+ {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+ state <= 5;
+ end
+ `LM32_DP_WRITE_CSR:
+ state <= `LM32_JTAG_STATE_READ_BYTE_0;
+`endif
+ `LM32_DP_BREAK:
+ begin
+`ifdef CFG_JTAG_UART_ENABLED
+ uart_rx_valid <= `FALSE;
+ uart_tx_valid <= `FALSE;
+`endif
+ jtag_break <= `TRUE;
+ end
+ `LM32_DP_RESET:
+ begin
+`ifdef CFG_JTAG_UART_ENABLED
+ uart_rx_valid <= `FALSE;
+ uart_tx_valid <= `FALSE;
+`endif
+ jtag_reset <= `TRUE;
+ end
+ endcase
+ end
+`endif
+`ifdef CFG_JTAG_UART_ENABLED
+ `LM32_TX:
+ begin
+ uart_rx_byte <= rx_byte;
+ uart_rx_valid <= `TRUE;
+ end
+ `LM32_RX:
+ begin
+ jtag_reg_d <= uart_tx_byte;
+ uart_tx_valid <= `FALSE;
+ end
+`endif
+ default:
+ ;
+ endcase
+ end
+ end
+`ifdef CFG_HW_DEBUG_ENABLED
+ `LM32_JTAG_STATE_READ_BYTE_0:
+ begin
+ if (rx_toggle_r_r != rx_toggle_r_r_r)
+ begin
+ jtag_byte_0 <= rx_byte;
+ state <= `LM32_JTAG_STATE_READ_BYTE_1;
+ end
+ end
+ `LM32_JTAG_STATE_READ_BYTE_1:
+ begin
+ if (rx_toggle_r_r != rx_toggle_r_r_r)
+ begin
+ jtag_byte_1 <= rx_byte;
+ state <= `LM32_JTAG_STATE_READ_BYTE_2;
+ end
+ end
+ `LM32_JTAG_STATE_READ_BYTE_2:
+ begin
+ if (rx_toggle_r_r != rx_toggle_r_r_r)
+ begin
+ jtag_byte_2 <= rx_byte;
+ state <= `LM32_JTAG_STATE_READ_BYTE_3;
+ end
+ end
+ `LM32_JTAG_STATE_READ_BYTE_3:
+ begin
+ if (rx_toggle_r_r != rx_toggle_r_r_r)
+ begin
+ jtag_byte_3 <= rx_byte;
+ if (command == `LM32_DP_READ_MEMORY)
+ state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
+ else
+ state <= `LM32_JTAG_STATE_READ_BYTE_4;
+ end
+ end
+ `LM32_JTAG_STATE_READ_BYTE_4:
+ begin
+ if (rx_toggle_r_r != rx_toggle_r_r_r)
+ begin
+ jtag_byte_4 <= rx_byte;
+ state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
+ end
+ end
+ `LM32_JTAG_STATE_PROCESS_COMMAND:
+ begin
+ case (command)
+ `LM32_DP_READ_MEMORY,
+ `LM32_DP_READ_SEQUENTIAL:
+ begin
+ jtag_read_enable <= `TRUE;
+ processing <= `TRUE;
+ state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
+ end
+ `LM32_DP_WRITE_MEMORY,
+ `LM32_DP_WRITE_SEQUENTIAL:
+ begin
+ jtag_write_enable <= `TRUE;
+ processing <= `TRUE;
+ state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
+ end
+ `LM32_DP_WRITE_CSR:
+ begin
+ jtag_csr_write_enable <= `TRUE;
+ processing <= `TRUE;
+ state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
+ end
+ endcase
+ end
+ `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
+ begin
+ if (jtag_access_complete == `TRUE)
+ begin
+ jtag_read_enable <= `FALSE;
+ jtag_reg_d <= jtag_read_data;
+ jtag_write_enable <= `FALSE;
+ processing <= `FALSE;
+ state <= `LM32_JTAG_STATE_READ_COMMAND;
+ end
+ end
+ `LM32_JTAG_STATE_WAIT_FOR_CSR:
+ begin
+ jtag_csr_write_enable <= `FALSE;
+ processing <= `FALSE;
+ state <= `LM32_JTAG_STATE_READ_COMMAND;
+ end
+`endif
+ endcase
+ end
+end
+
+endmodule
+
+`endif
lm32/verilog/src/lm32_jtag.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_monitor.v
===================================================================
--- lm32/verilog/src/lm32_monitor.v (nonexistent)
+++ lm32/verilog/src/lm32_monitor.v (revision 17)
@@ -0,0 +1,164 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_monitor.v
+// Title : Debug monitor memory Wishbone interface
+// Version : 6.1.17
+// =============================================================================
+
+`include "system_conf.v"
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_monitor (
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ MON_ADR_I,
+ MON_CYC_I,
+ MON_DAT_I,
+ MON_SEL_I,
+ MON_STB_I,
+ MON_WE_I,
+ MON_LOCK_I,
+ MON_CTI_I,
+ MON_BTE_I,
+ // ----- Outputs -------
+ MON_ACK_O,
+ MON_RTY_O,
+ MON_DAT_O,
+ MON_ERR_O
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Wishbone clock
+input rst_i; // Wishbone reset
+input [`LM32_WORD_RNG] MON_ADR_I; // Wishbone address
+input MON_STB_I; // Wishbone strobe
+input MON_CYC_I; // Wishbone cycle
+input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data
+input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select
+input MON_WE_I; // Wishbone write enable
+input MON_LOCK_I; // Wishbone locked transfer
+input [`LM32_CTYPE_RNG] MON_CTI_I; // Wishbone cycle type
+input [`LM32_BTYPE_RNG] MON_BTE_I; // Wishbone burst type
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output MON_ACK_O; // Wishbone acknowlege
+reg MON_ACK_O;
+output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output
+reg [`LM32_WORD_RNG] MON_DAT_O;
+output MON_RTY_O; // Wishbone retry
+wire MON_RTY_O;
+output MON_ERR_O; // Wishbone error
+wire MON_ERR_O;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+reg [1:0] state; // Current state of FSM
+wire [`LM32_WORD_RNG] data; // Data read from RAM
+reg write_enable; // RAM write enable
+reg [`LM32_WORD_RNG] write_data; // RAM write data
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+lm32_monitor_ram ram (
+ // ----- Inputs -------
+ .ClockA (clk_i),
+ .ClockB (clk_i),
+ .ResetA (rst_i),
+ .ResetB (rst_i),
+ .ClockEnA (`TRUE),
+ .ClockEnB (`FALSE),
+ .AddressA (MON_ADR_I[10:2]),
+ .DataInA (write_data),
+ .WrA (write_enable),
+ .WrB (`FALSE),
+ // ----- Outputs -------
+ .QA (data)
+ );
+
+/////////////////////////////////////////////////////
+// Combinational Logic
+/////////////////////////////////////////////////////
+
+assign MON_RTY_O = `FALSE;
+assign MON_ERR_O = `FALSE;
+
+/////////////////////////////////////////////////////
+// Sequential Logic
+/////////////////////////////////////////////////////
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ write_enable <= `FALSE;
+ MON_ACK_O <= `FALSE;
+ MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
+ state <= 2'b00;
+ end
+ else
+ begin
+ case (state)
+ 2'b00:
+ begin
+ // Wait for a Wishbone access
+ if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
+ state <= 2'b01;
+ end
+ 2'b01:
+ begin
+ // Output read data to Wishbone
+ MON_ACK_O <= `TRUE;
+ MON_DAT_O <= data;
+ // Sub-word writes are performed using read-modify-write
+ // as the Lattice EBRs don't support byte enables
+ if (MON_WE_I == `TRUE)
+ write_enable <= `TRUE;
+ write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
+ write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
+ write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
+ write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
+ state <= 2'b10;
+ end
+ 2'b10:
+ begin
+ // Wishbone access occurs in this cycle
+ write_enable <= `FALSE;
+ MON_ACK_O <= `FALSE;
+ MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
+ state <= 2'b00;
+ end
+ endcase
+ end
+end
+
+endmodule
lm32/verilog/src/lm32_monitor.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/er1.v
===================================================================
--- lm32/verilog/src/er1.v (nonexistent)
+++ lm32/verilog/src/er1.v (revision 17)
@@ -0,0 +1,218 @@
+/*-- ---------------------------------------------------------------------------
+--
+-- Name : ER1.v
+--
+-- Description:
+--
+-- This module is where the ER1 register implemented. ER1 and ER2 registers
+-- can be registers implemented in Lattice FPGAs using normal FPGA's
+-- programmable logic resources. Once they are implemented, they can be
+-- accessed as if they are JTAG data registers through the FPGA JTAG port.
+-- In order to accessing these registers, JTAG instructions ER1(0x32) or
+-- ER2(0x38) needs to be written to the JTAG IR register for enabling the
+-- ER1/ER2 accessing logic. The ER1 or ER2 accessing logic can only be
+-- enabled one at a time. Once they are enabled, they will be disabled if
+-- another JTAG instruction is written into the JTAG instruction register.
+-- The registers allow dynamically accessing the FPGA internal information
+-- even when the device is running. Therefore, they are very useful for some
+-- of the IP cores. In order to let ER1/ER2 registers shared by multiple IP
+-- cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
+-- The ER1/ER2 structure allows only one ER1 register but more than one ER2
+-- registers in an FPGA device. Please refer to the related document for
+-- this patterned ER1/ER2 structure.
+--
+-- $Log: $
+--
+-- $Header: $
+--
+-- Copyright (C) 2004 Lattice Semiconductor Corp. All rights reserved.
+--
+-- ---------------------------------------------------------------------------*/
+
+module ER1 (input JTCK,
+ input JTDI,
+ output JTDO1,
+ output reg JTDO2,
+ input JSHIFT,
+ input JUPDATE,
+ input JRSTN,
+ input JCE1,
+ input [14:0] ER2_TDO,
+ output reg [14:0] IP_ENABLE,
+ input ISPTRACY_ER2_TDO,
+ output ISPTRACY_ENABLE,
+ output CONTROL_DATAN)/* synthesis syn_hier = hard */;
+
+
+ wire controlDataNBit;
+ wire ispTracyEnableBit;
+ wire [3:0] encodedIpEnableBits;
+ wire [9:0] er1TdiBit;
+ wire captureDrER1;
+
+
+ assign JTDO1 = er1TdiBit[0];
+
+ TYPEB BIT0 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[1]),
+ .TDO(er1TdiBit[0]),
+ .DATA_IN(1'b0),
+ .CAPTURE_DR(captureDrER1));
+
+ TYPEB BIT1 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[2]),
+ .TDO(er1TdiBit[1]),
+ .DATA_IN(1'b0),
+ .CAPTURE_DR(captureDrER1));
+
+ TYPEB BIT2 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[3]),
+ .TDO(er1TdiBit[2]),
+ .DATA_IN(1'b1),
+ .CAPTURE_DR(captureDrER1));
+
+ TYPEA BIT3 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[4]),
+ .TDO(er1TdiBit[3]),
+ .DATA_OUT(controlDataNBit),
+ .DATA_IN(controlDataNBit),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE));
+
+ assign CONTROL_DATAN = controlDataNBit;
+
+ TYPEA BIT4 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[5]),
+ .TDO(er1TdiBit[4]),
+ .DATA_OUT(ispTracyEnableBit),
+ .DATA_IN(ispTracyEnableBit),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE)
+ );
+
+ assign ISPTRACY_ENABLE = ispTracyEnableBit;
+
+ TYPEA BIT5 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[6]),
+ .TDO(er1TdiBit[5]),
+ .DATA_OUT(encodedIpEnableBits[0]),
+ .DATA_IN(encodedIpEnableBits[0]),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE));
+
+ TYPEA BIT6 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[7]),
+ .TDO(er1TdiBit[6]),
+ .DATA_OUT(encodedIpEnableBits[1]),
+ .DATA_IN(encodedIpEnableBits[1]),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE));
+
+ TYPEA BIT7 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[8]),
+ .TDO(er1TdiBit[7]),
+ .DATA_OUT(encodedIpEnableBits[2]),
+ .DATA_IN(encodedIpEnableBits[2]),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE));
+
+ TYPEA BIT8 (.CLK(JTCK),
+ .RESET_N(JRSTN),
+ .CLKEN(JCE1),
+ .TDI(er1TdiBit[9]),
+ .TDO(er1TdiBit[8]),
+ .DATA_OUT(encodedIpEnableBits[3]),
+ .DATA_IN(encodedIpEnableBits[3]),
+ .CAPTURE_DR(captureDrER1),
+ .UPDATE_DR(JUPDATE)
+ );
+
+ assign er1TdiBit[9] = JTDI;
+ assign captureDrER1 = !JSHIFT & JCE1;
+
+ always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
+ begin
+ case (encodedIpEnableBits)
+ 4'h0: begin
+ IP_ENABLE <= 15'b000000000000000;
+ JTDO2 <= ISPTRACY_ER2_TDO;
+ end
+ 4'h1: begin
+ IP_ENABLE <= 15'b000000000000001;
+ JTDO2 <= ER2_TDO[0];
+ end
+ 4'h2: begin
+ IP_ENABLE <= 15'b000000000000010;
+ JTDO2 <= ER2_TDO[1];
+ end
+ 4'h3: begin
+ IP_ENABLE <= 15'b000000000000100;
+ JTDO2 <= ER2_TDO[2];
+ end
+ 4'h4: begin
+ IP_ENABLE <= 15'b000000000001000;
+ JTDO2 <= ER2_TDO[3];
+ end
+ 4'h5: begin
+ IP_ENABLE <= 15'b000000000010000;
+ JTDO2 <= ER2_TDO[4];
+ end
+ 4'h6: begin
+ IP_ENABLE <= 15'b000000000100000;
+ JTDO2 <= ER2_TDO[5];
+ end
+ 4'h7: begin
+ IP_ENABLE <= 15'b000000001000000;
+ JTDO2 <= ER2_TDO[6];
+ end
+ 4'h8: begin
+ IP_ENABLE <= 15'b000000010000000;
+ JTDO2 <= ER2_TDO[7];
+ end
+ 4'h9: begin
+ IP_ENABLE <= 15'b000000100000000;
+ JTDO2 <= ER2_TDO[8];
+ end
+ 4'hA: begin
+ IP_ENABLE <= 15'b000001000000000;
+ JTDO2 <= ER2_TDO[9];
+ end
+ 4'hB: begin
+ IP_ENABLE <= 15'b000010000000000;
+ JTDO2 <= ER2_TDO[10];
+ end
+ 4'hC: begin
+ IP_ENABLE <= 15'b000100000000000;
+ JTDO2 <= ER2_TDO[11];
+ end
+ 4'hD: begin
+ IP_ENABLE <= 15'b001000000000000;
+ JTDO2 <= ER2_TDO[12];
+ end
+ 4'hE: begin
+ IP_ENABLE <= 15'b010000000000000;
+ JTDO2 <= ER2_TDO[13];
+ end
+ 4'hF: begin
+ IP_ENABLE <= 15'b100000000000000;
+ JTDO2 <= ER2_TDO[14];
+ end
+ endcase
+ end
+endmodule
lm32/verilog/src/er1.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/JTAGB.v
===================================================================
--- lm32/verilog/src/JTAGB.v (nonexistent)
+++ lm32/verilog/src/JTAGB.v (revision 17)
@@ -0,0 +1,15 @@
+module JTAGB (
+ output JTCK,
+ output JRTI1,
+ output JRTI2,
+ output JTDI,
+ output JSHIFT,
+ output JUPDATE,
+ output JRSTN,
+ output JCE1,
+ output JCE2,
+ input JTDO1,
+ input JTDO2
+ ) /*synthesis syn_black_box */;
+
+endmodule
lm32/verilog/src/JTAGB.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/system_conf.v
===================================================================
--- lm32/verilog/src/system_conf.v (nonexistent)
+++ lm32/verilog/src/system_conf.v (revision 17)
@@ -0,0 +1,45 @@
+//---------------------------------------------------------------------------
+//
+// This file is used by ../rtl/lm32/* to configure CPU parameter
+//
+//---------------------------------------------------------------------------
+`ifndef SYSTEM_CONF
+`define SYSTEM_CONF
+`define INCLUDE_LM32
+
+//`timescale 1ns / 100 ps
+
+`define CFG_EBA_RESET 32'h0
+`define CFG_DEBA_RESET 32'h0
+
+`define CFG_PL_MULTIPLY_ENABLED
+`define CFG_PL_BARREL_SHIFT_ENABLED
+`define CFG_SIGN_EXTEND_ENABLED
+`define CFG_MC_DIVIDE_ENABLED
+
+// Instruction Cache
+// [0x00000000,0x80000000) cachable
+// [0x80000000,0xffffffff] non-cachabel
+`define CFG_ICACHE_ENABLED
+`define CFG_ICACHE_ASSOCIATIVITY 1
+`define CFG_ICACHE_SETS 512
+`define CFG_ICACHE_BYTES_PER_LINE 16
+`define CFG_ICACHE_BASE_ADDRESS 32'h0
+`define CFG_ICACHE_LIMIT 32'h7fffffff
+
+// Data Cache
+// [0x00000000,0x80000000) cachable
+// [0x80000000,0xffffffff] non-cachabel
+// `define CFG_DCACHE_ENABLED
+`define CFG_DCACHE_ASSOCIATIVITY 1
+`define CFG_DCACHE_SETS 512
+`define CFG_DCACHE_BYTES_PER_LINE 16
+`define CFG_DCACHE_BASE_ADDRESS 32'h0
+`define CFG_DCACHE_LIMIT 32'h7fffffff
+
+// `define CFG_DEBUG_ENABLED
+// `define CFG_ROM_DEBUG_ENABLED
+// `define CFG_BREAKPOINTS 32'h1
+// `define CFG_WATCHPOINTS 32'h1
+
+`endif // SYSTEM_CONF
lm32/verilog/src/system_conf.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_top.v
===================================================================
--- lm32/verilog/src/lm32_top.v (nonexistent)
+++ lm32/verilog/src/lm32_top.v (revision 17)
@@ -0,0 +1,370 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_top.v
+// Title : Top-level of CPU.
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_top (
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ // From external devices
+`ifdef CFG_INTERRUPTS_ENABLED
+ interrupt_n,
+`endif
+ // From user logic
+`ifdef CFG_USER_ENABLED
+ user_result,
+ user_complete,
+`endif
+`ifdef CFG_IWB_ENABLED
+ // Instruction Wishbone master
+ I_DAT_I,
+ I_ACK_I,
+ I_ERR_I,
+ I_RTY_I,
+`endif
+ // Data Wishbone master
+ D_DAT_I,
+ D_ACK_I,
+ D_ERR_I,
+ D_RTY_I,
+ // Debug Slave port WishboneInterface
+ DEBUG_ADR_I,
+ DEBUG_DAT_I,
+ DEBUG_SEL_I,
+ DEBUG_WE_I,
+ DEBUG_CTI_I,
+ DEBUG_BTE_I,
+ DEBUG_LOCK_I,
+ DEBUG_CYC_I,
+ DEBUG_STB_I,
+ // ----- Outputs -------
+`ifdef CFG_USER_ENABLED
+ user_valid,
+ user_opcode,
+ user_operand_0,
+ user_operand_1,
+`endif
+`ifdef CFG_IWB_ENABLED
+ // Instruction Wishbone master
+ I_DAT_O,
+ I_ADR_O,
+ I_CYC_O,
+ I_SEL_O,
+ I_STB_O,
+ I_WE_O,
+ I_CTI_O,
+ I_LOCK_O,
+ I_BTE_O,
+`endif
+ // Data Wishbone master
+ D_DAT_O,
+ D_ADR_O,
+ D_CYC_O,
+ D_SEL_O,
+ D_STB_O,
+ D_WE_O,
+ D_CTI_O,
+ D_LOCK_O,
+ D_BTE_O,
+ // Debug Slave port WishboneInterface
+ DEBUG_ACK_O,
+ DEBUG_ERR_O,
+ DEBUG_RTY_O,
+ DEBUG_DAT_O
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+
+`ifdef CFG_INTERRUPTS_ENABLED
+input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
+`endif
+
+`ifdef CFG_USER_ENABLED
+input [`LM32_WORD_RNG] user_result; // User-defined instruction result
+input user_complete; // Indicates the user-defined instruction result is valid
+`endif
+
+`ifdef CFG_IWB_ENABLED
+input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
+input I_ACK_I; // Instruction Wishbone interface acknowledgement
+input I_ERR_I; // Instruction Wishbone interface error
+input I_RTY_I; // Instruction Wishbone interface retry
+`endif
+
+input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
+input D_ACK_I; // Data Wishbone interface acknowledgement
+input D_ERR_I; // Data Wishbone interface error
+input D_RTY_I; // Data Wishbone interface retry
+
+input [`LM32_WORD_RNG] DEBUG_ADR_I; // Debug monitor Wishbone interface address
+input [`LM32_WORD_RNG] DEBUG_DAT_I; // Debug monitor Wishbone interface write data
+input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I; // Debug monitor Wishbone interface byte select
+input DEBUG_WE_I; // Debug monitor Wishbone interface write enable
+input [`LM32_CTYPE_RNG] DEBUG_CTI_I; // Debug monitor Wishbone interface cycle type
+input [`LM32_BTYPE_RNG] DEBUG_BTE_I; // Debug monitor Wishbone interface burst type
+input DEBUG_LOCK_I; // Debug monitor Wishbone interface locked transfer
+input DEBUG_CYC_I; // Debug monitor Wishbone interface cycle
+input DEBUG_STB_I; // Debug monitor Wishbone interface strobe
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+`ifdef CFG_USER_ENABLED
+output user_valid; // Indicates that user_opcode and user_operand_* are valid
+wire user_valid;
+output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
+reg [`LM32_USER_OPCODE_RNG] user_opcode;
+output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
+wire [`LM32_WORD_RNG] user_operand_0;
+output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
+wire [`LM32_WORD_RNG] user_operand_1;
+`endif
+
+`ifdef CFG_IWB_ENABLED
+output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
+wire [`LM32_WORD_RNG] I_DAT_O;
+output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
+wire [`LM32_WORD_RNG] I_ADR_O;
+output I_CYC_O; // Instruction Wishbone interface cycle
+wire I_CYC_O;
+output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
+wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
+output I_STB_O; // Instruction Wishbone interface strobe
+wire I_STB_O;
+output I_WE_O; // Instruction Wishbone interface write enable
+wire I_WE_O;
+output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] I_CTI_O;
+output I_LOCK_O; // Instruction Wishbone interface lock bus
+wire I_LOCK_O;
+output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] I_BTE_O;
+`endif
+
+output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
+wire [`LM32_WORD_RNG] D_DAT_O;
+output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
+wire [`LM32_WORD_RNG] D_ADR_O;
+output D_CYC_O; // Data Wishbone interface cycle
+wire D_CYC_O;
+output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
+wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
+output D_STB_O; // Data Wishbone interface strobe
+wire D_STB_O;
+output D_WE_O; // Data Wishbone interface write enable
+wire D_WE_O;
+output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] D_CTI_O;
+output D_LOCK_O; // Date Wishbone interface lock bus
+wire D_LOCK_O;
+output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] D_BTE_O;
+
+output DEBUG_ACK_O; // Debug monitor Wishbone ack
+wire DEBUG_ACK_O;
+output DEBUG_ERR_O; // Debug monitor Wishbone error
+wire DEBUG_ERR_O;
+output DEBUG_RTY_O; // Debug monitor Wishbone retry
+wire DEBUG_RTY_O;
+output [`LM32_WORD_RNG] DEBUG_DAT_O; // Debug monitor Wishbone read data
+wire [`LM32_WORD_RNG] DEBUG_DAT_O;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+`ifdef CFG_JTAG_ENABLED
+// Signals between JTAG interface and CPU
+wire [`LM32_BYTE_RNG] jtag_reg_d;
+wire [`LM32_BYTE_RNG] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+`endif
+
+`ifdef CFG_TRACE_ENABLED
+// PC trace signals
+wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
+wire trace_pc_valid; // Indicates that a new trace PC is valid
+wire trace_exception; // Indicates an exception has occured
+wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
+wire trace_eret; // Indicates an eret instruction has been executed
+`ifdef CFG_DEBUG_ENABLED
+wire trace_bret; // Indicates a bret instruction has been executed
+`endif
+`endif
+
+/////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////
+`define INCLUDE_FUNCTION
+`include "lm32_functions.v"
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+// LM32 CPU
+lm32_cpu cpu (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
+ .clk_n_i (clk_n),
+`endif
+ .rst_i (rst_i),
+ // From external devices
+`ifdef CFG_INTERRUPTS_ENABLED
+ .interrupt_n (interrupt_n),
+`endif
+ // From user logic
+`ifdef CFG_USER_ENABLED
+ .user_result (user_result),
+ .user_complete (user_complete),
+`endif
+`ifdef CFG_JTAG_ENABLED
+ // From JTAG
+ .jtag_clk (jtck),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+`endif
+`ifdef CFG_IWB_ENABLED
+ // Instruction Wishbone master
+ .I_DAT_I (I_DAT_I),
+ .I_ACK_I (I_ACK_I),
+ .I_ERR_I (I_ERR_I),
+ .I_RTY_I (I_RTY_I),
+`endif
+ // Data Wishbone master
+ .D_DAT_I (D_DAT_I),
+ .D_ACK_I (D_ACK_I),
+ .D_ERR_I (D_ERR_I),
+ .D_RTY_I (D_RTY_I),
+ // ----- Outputs -------
+`ifdef CFG_TRACE_ENABLED
+ .trace_pc (trace_pc),
+ .trace_pc_valid (trace_pc_valid),
+ .trace_exception (trace_exception),
+ .trace_eid (trace_eid),
+ .trace_eret (trace_eret),
+`ifdef CFG_DEBUG_ENABLED
+ .trace_bret (trace_bret),
+`endif
+`endif
+`ifdef CFG_JTAG_ENABLED
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d),
+`endif
+`ifdef CFG_USER_ENABLED
+ .user_valid (user_valid),
+ .user_opcode (user_opcode),
+ .user_operand_0 (user_operand_0),
+ .user_operand_1 (user_operand_1),
+`endif
+`ifdef CFG_IWB_ENABLED
+ // Instruction Wishbone master
+ .I_DAT_O (I_DAT_O),
+ .I_ADR_O (I_ADR_O),
+ .I_CYC_O (I_CYC_O),
+ .I_SEL_O (I_SEL_O),
+ .I_STB_O (I_STB_O),
+ .I_WE_O (I_WE_O),
+ .I_CTI_O (I_CTI_O),
+ .I_LOCK_O (I_LOCK_O),
+ .I_BTE_O (I_BTE_O),
+ `endif
+ // Data Wishbone master
+ .D_DAT_O (D_DAT_O),
+ .D_ADR_O (D_ADR_O),
+ .D_CYC_O (D_CYC_O),
+ .D_SEL_O (D_SEL_O),
+ .D_STB_O (D_STB_O),
+ .D_WE_O (D_WE_O),
+ .D_CTI_O (D_CTI_O),
+ .D_LOCK_O (D_LOCK_O),
+ .D_BTE_O (D_BTE_O)
+ );
+
+`ifdef DEBUG_ROM
+// ROM monitor
+lm32_monitor debug_rom (
+ // ----- Inputs -------
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .MON_ADR_I (DEBUG_ADR_I),
+ .MON_STB_I (DEBUG_STB_I),
+ .MON_CYC_I (DEBUG_CYC_I),
+ .MON_WE_I (DEBUG_WE_I),
+ .MON_SEL_I (DEBUG_SEL_I),
+ .MON_DAT_I (DEBUG_DAT_I),
+ .MON_CTI_I (DEBUG_CTI_I),
+ .MON_BTE_I (DEBUG_BTE_I),
+ .MON_LOCK_I (DEBUG_LOCK_I),
+ // ----- Outputs ------
+ .MON_RTY_O (DEBUG_RTY_O),
+ .MON_ERR_O (DEBUG_ERR_O),
+ .MON_ACK_O (DEBUG_ACK_O),
+ .MON_DAT_O (DEBUG_DAT_O)
+ );
+`endif
+
+`ifdef CFG_JTAG_ENABLED
+// JTAG cores
+jtag_cores jtag_cores (
+ // ----- Inputs -----
+`ifdef INCLUDE_LM32
+ .reg_d (jtag_reg_d),
+ .reg_addr_d (jtag_reg_addr_d),
+`endif
+`ifdef INCLUDE_SPI
+ .spi_q (spi_q),
+`endif
+ // ----- Outputs -----
+`ifdef INCLUDE_LM32
+ .reg_update (jtag_update),
+ .reg_q (jtag_reg_q),
+ .reg_addr_q (jtag_reg_addr_q),
+`endif
+`ifdef INCLUDE_SPI
+ .spi_c (spi_c),
+ .spi_d (spi_d),
+ .spi_sn (spi_sn),
+`endif
+ .jtck (jtck),
+ .jrstn (jrstn)
+ );
+`endif
+
+endmodule
lm32/verilog/src/lm32_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_decoder.v
===================================================================
--- lm32/verilog/src/lm32_decoder.v (nonexistent)
+++ lm32/verilog/src/lm32_decoder.v (revision 17)
@@ -0,0 +1,564 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_decoder.v
+// Title : Instruction decoder
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+// Index of opcode field in an instruction
+`define LM32_OPCODE_RNG 31:26
+`define LM32_OP_RNG 30:26
+
+// Opcodes - Some are only listed as 5 bits as their MSB is a don't care
+`define LM32_OPCODE_ADD 5'b01101
+`define LM32_OPCODE_AND 5'b01000
+`define LM32_OPCODE_ANDHI 6'b011000
+`define LM32_OPCODE_B 6'b110000
+`define LM32_OPCODE_BI 6'b111000
+`define LM32_OPCODE_BE 6'b010001
+`define LM32_OPCODE_BG 6'b010010
+`define LM32_OPCODE_BGE 6'b010011
+`define LM32_OPCODE_BGEU 6'b010100
+`define LM32_OPCODE_BGU 6'b010101
+`define LM32_OPCODE_BNE 6'b010111
+`define LM32_OPCODE_CALL 6'b110110
+`define LM32_OPCODE_CALLI 6'b111110
+`define LM32_OPCODE_CMPE 5'b11001
+`define LM32_OPCODE_CMPG 5'b11010
+`define LM32_OPCODE_CMPGE 5'b11011
+`define LM32_OPCODE_CMPGEU 5'b11100
+`define LM32_OPCODE_CMPGU 5'b11101
+`define LM32_OPCODE_CMPNE 5'b11111
+`define LM32_OPCODE_DIVU 6'b100011
+`define LM32_OPCODE_LB 6'b000100
+`define LM32_OPCODE_LBU 6'b010000
+`define LM32_OPCODE_LH 6'b000111
+`define LM32_OPCODE_LHU 6'b001011
+`define LM32_OPCODE_LW 6'b001010
+`define LM32_OPCODE_MODU 6'b110001
+`define LM32_OPCODE_MUL 5'b00010
+`define LM32_OPCODE_NOR 5'b00001
+`define LM32_OPCODE_OR 5'b01110
+`define LM32_OPCODE_ORHI 6'b011110
+`define LM32_OPCODE_RAISE 6'b101011
+`define LM32_OPCODE_RCSR 6'b100100
+`define LM32_OPCODE_SB 6'b001100
+`define LM32_OPCODE_SEXTB 6'b101100
+`define LM32_OPCODE_SEXTH 6'b110111
+`define LM32_OPCODE_SH 6'b000011
+`define LM32_OPCODE_SL 5'b01111
+`define LM32_OPCODE_SR 5'b00101
+`define LM32_OPCODE_SRU 5'b00000
+`define LM32_OPCODE_SUB 6'b110010
+`define LM32_OPCODE_SW 6'b010110
+`define LM32_OPCODE_USER 6'b110011
+`define LM32_OPCODE_WCSR 6'b110100
+`define LM32_OPCODE_XNOR 5'b01001
+`define LM32_OPCODE_XOR 5'b00110
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_decoder (
+ // ----- Inputs -------
+ instruction,
+ // ----- Outputs -------
+ d_result_sel_0,
+ d_result_sel_1,
+ x_result_sel_csr,
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+ x_result_sel_mc_arith,
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+ x_result_sel_shift,
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+ x_result_sel_sext,
+`endif
+ x_result_sel_logic,
+`ifdef CFG_USER_ENABLED
+ x_result_sel_user,
+`endif
+ x_result_sel_add,
+ m_result_sel_compare,
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ m_result_sel_shift,
+`endif
+ w_result_sel_load,
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ w_result_sel_mul,
+`endif
+ x_bypass_enable,
+ m_bypass_enable,
+ read_enable_0,
+ read_idx_0,
+ read_enable_1,
+ read_idx_1,
+ write_enable,
+ write_idx,
+ immediate,
+ branch_offset,
+ load,
+ store,
+ size,
+ sign_extend,
+ adder_op,
+ logic_op,
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ direction,
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ shift_left,
+ shift_right,
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+ multiply,
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+ divide,
+ modulus,
+`endif
+ branch,
+ branch_reg,
+ condition,
+`ifdef CFG_DEBUG_ENABLED
+ break,
+`endif
+ scall,
+ eret,
+`ifdef CFG_DEBUG_ENABLED
+ bret,
+`endif
+`ifdef CFG_USER_ENABLED
+ user_opcode,
+`endif
+ csr_write_enable
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
+reg [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
+output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
+reg [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
+output x_result_sel_csr;
+reg x_result_sel_csr;
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+output x_result_sel_mc_arith;
+reg x_result_sel_mc_arith;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+output x_result_sel_shift;
+reg x_result_sel_shift;
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+output x_result_sel_sext;
+reg x_result_sel_sext;
+`endif
+output x_result_sel_logic;
+reg x_result_sel_logic;
+`ifdef CFG_USER_ENABLED
+output x_result_sel_user;
+reg x_result_sel_user;
+`endif
+output x_result_sel_add;
+reg x_result_sel_add;
+output m_result_sel_compare;
+reg m_result_sel_compare;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+output m_result_sel_shift;
+reg m_result_sel_shift;
+`endif
+output w_result_sel_load;
+reg w_result_sel_load;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+output w_result_sel_mul;
+reg w_result_sel_mul;
+`endif
+output x_bypass_enable;
+wire x_bypass_enable;
+output m_bypass_enable;
+wire m_bypass_enable;
+output read_enable_0;
+wire read_enable_0;
+output [`LM32_REG_IDX_RNG] read_idx_0;
+wire [`LM32_REG_IDX_RNG] read_idx_0;
+output read_enable_1;
+wire read_enable_1;
+output [`LM32_REG_IDX_RNG] read_idx_1;
+wire [`LM32_REG_IDX_RNG] read_idx_1;
+output write_enable;
+wire write_enable;
+output [`LM32_REG_IDX_RNG] write_idx;
+wire [`LM32_REG_IDX_RNG] write_idx;
+output [`LM32_WORD_RNG] immediate;
+wire [`LM32_WORD_RNG] immediate;
+output [`LM32_PC_RNG] branch_offset;
+wire [`LM32_PC_RNG] branch_offset;
+output load;
+wire load;
+output store;
+wire store;
+output [`LM32_SIZE_RNG] size;
+wire [`LM32_SIZE_RNG] size;
+output sign_extend;
+wire sign_extend;
+output adder_op;
+wire adder_op;
+output [`LM32_LOGIC_OP_RNG] logic_op;
+wire [`LM32_LOGIC_OP_RNG] logic_op;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+output direction;
+wire direction;
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+output shift_left;
+wire shift_left;
+output shift_right;
+wire shift_right;
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+output multiply;
+wire multiply;
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+output divide;
+wire divide;
+output modulus;
+wire modulus;
+`endif
+output branch;
+wire branch;
+output branch_reg;
+wire branch_reg;
+output [`LM32_CONDITION_RNG] condition;
+wire [`LM32_CONDITION_RNG] condition;
+`ifdef CFG_DEBUG_ENABLED
+output break;
+wire break;
+`endif
+output scall;
+wire scall;
+output eret;
+wire eret;
+`ifdef CFG_DEBUG_ENABLED
+output bret;
+wire bret;
+`endif
+`ifdef CFG_USER_ENABLED
+output [`LM32_USER_OPCODE_RNG] user_opcode;
+wire [`LM32_USER_OPCODE_RNG] user_opcode;
+`endif
+output csr_write_enable;
+wire csr_write_enable;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate
+wire [`LM32_WORD_RNG] high_immediate; // Immediate as high 16 bits
+wire [`LM32_WORD_RNG] call_immediate; // Call immediate
+wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate
+wire sign_extend_immediate; // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
+wire select_high_immediate; // Whether to select the high immediate
+wire select_call_immediate; // Whether to select the call immediate
+
+/////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////
+`define INCLUDE_FUNCTION
+`include "lm32_functions.v"
+
+/////////////////////////////////////////////////////
+// Combinational logic
+/////////////////////////////////////////////////////
+
+// Determine opcode
+wire op_add = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD;
+wire op_and = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND;
+wire op_andhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI;
+wire op_b = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B;
+wire op_bi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI;
+wire op_be = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE;
+wire op_bg = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG;
+wire op_bge = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE;
+wire op_bgeu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU;
+wire op_bgu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU;
+wire op_bne = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE;
+wire op_call = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL;
+wire op_calli = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI;
+wire op_cmpe = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE;
+wire op_cmpg = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG;
+wire op_cmpge = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE;
+wire op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU;
+wire op_cmpgu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU;
+wire op_cmpne = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE;
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire op_divu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU;
+`endif
+wire op_lb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB;
+wire op_lbu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU;
+wire op_lh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH;
+wire op_lhu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU;
+wire op_lw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW;
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire op_modu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU;
+`endif
+`ifdef LM32_MULTIPLY_ENABLED
+wire op_mul = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL;
+`endif
+wire op_nor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR;
+wire op_or = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR;
+wire op_orhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI;
+wire op_raise = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE;
+wire op_rcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR;
+wire op_sb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB;
+`ifdef CFG_SIGN_EXTEND_ENABLED
+wire op_sextb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB;
+wire op_sexth = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH;
+`endif
+wire op_sh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH;
+`ifdef LM32_BARREL_SHIFT_ENABLED
+wire op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL;
+`endif
+wire op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
+wire op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
+wire op_sub = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
+wire op_sw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
+wire op_user = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
+wire op_wcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
+wire op_xnor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
+wire op_xor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
+
+// Group opcodes by function
+wire arith = op_add | op_sub;
+wire logicc = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+wire cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+wire bra = op_b | op_bi | op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
+wire call = op_call | op_calli;
+`ifdef LM32_BARREL_SHIFT_ENABLED
+wire shift = op_sl | op_sr | op_sru;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+wire shift = op_sr | op_sru;
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+assign shift_left = op_sl;
+assign shift_right = op_sr | op_sru;
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+wire sext = op_sextb | op_sexth;
+`endif
+`ifdef LM32_MULTIPLY_ENABLED
+wire multiply = op_mul;
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+assign divide = op_divu;
+assign modulus = op_modu;
+`endif
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+
+// Select pipeline multiplexor controls
+always @*
+begin
+ // D stage
+ if (call)
+ d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC;
+ else
+ d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0;
+ if (call)
+ d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO;
+ else if ((instruction[31] == 1'b0) && !bra)
+ d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE;
+ else
+ d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1;
+ // X stage
+ x_result_sel_csr = `FALSE;
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+ x_result_sel_mc_arith = `FALSE;
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+ x_result_sel_shift = `FALSE;
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+ x_result_sel_sext = `FALSE;
+`endif
+ x_result_sel_logic = `FALSE;
+`ifdef CFG_USER_ENABLED
+ x_result_sel_user = `FALSE;
+`endif
+ x_result_sel_add = `FALSE;
+ if (op_rcsr)
+ x_result_sel_csr = `TRUE;
+`ifdef LM32_MC_ARITHMETIC_ENABLED
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ else if (shift_left | shift_right)
+ x_result_sel_mc_arith = `TRUE;
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+ else if (divide | modulus)
+ x_result_sel_mc_arith = `TRUE;
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+ else if (multiply)
+ x_result_sel_mc_arith = `TRUE;
+`endif
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+ else if (shift)
+ x_result_sel_shift = `TRUE;
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+ else if (sext)
+ x_result_sel_sext = `TRUE;
+`endif
+ else if (logicc)
+ x_result_sel_logic = `TRUE;
+`ifdef CFG_USER_ENABLED
+ else if (op_user)
+ x_result_sel_user = `TRUE;
+`endif
+ else
+ x_result_sel_add = `TRUE;
+
+ // M stage
+
+ m_result_sel_compare = cmp;
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ m_result_sel_shift = shift;
+`endif
+
+ // W stage
+ w_result_sel_load = load;
+`ifdef CFG_PL_MULTIPLY_ENABLED
+ w_result_sel_mul = op_mul;
+`endif
+end
+
+// Set if result is valid at end of X stage
+assign x_bypass_enable = arith
+ | logicc
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ | shift_left
+ | shift_right
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+ | multiply
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+ | divide
+ | modulus
+`endif
+`ifdef LM32_NO_BARREL_SHIFT
+ | shift
+`endif
+`ifdef CFG_SIGN_EXTEND_ENABLED
+ | sext
+`endif
+`ifdef CFG_USER_ENABLED
+ | op_user
+`endif
+ | op_rcsr
+ ;
+// Set if result is valid at end of M stage
+assign m_bypass_enable = x_bypass_enable
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+ | shift
+`endif
+ | cmp
+ ;
+// Register file read port 0
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+// Register file read port 1
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+// Register file write port
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+ ? 5'd29
+ : instruction[31] == 1'b0
+ ? instruction[20:16]
+ : instruction[15:11];
+
+// Size of load/stores
+assign size = instruction[27:26];
+// Whether to sign or zero extend
+assign sign_extend = instruction[28];
+// Set adder_op to 1 to perform a subtraction
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+// Logic operation (and, or, etc)
+assign logic_op = instruction[29:26];
+`ifdef CFG_PL_BARREL_SHIFT_ENABLED
+// Shift direction
+assign direction = instruction[29];
+`endif
+// Control flow microcodes
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];
+`ifdef CFG_DEBUG_ENABLED
+assign break = op_raise & ~instruction[2];
+`endif
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+`ifdef CFG_DEBUG_ENABLED
+assign bret = op_b & (instruction[25:21] == 5'd31);
+`endif
+`ifdef CFG_USER_ENABLED
+// Extract user opcode
+assign user_opcode = instruction[10:0];
+`endif
+// CSR read/write
+assign csr_write_enable = op_wcsr;
+
+// Extract immediate from instruction
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate == `TRUE
+ ? high_immediate
+ : extended_immediate;
+
+assign branch_offset = select_call_immediate == `TRUE
+ ? call_immediate
+ : branch_immediate;
+
+endmodule
+
lm32/verilog/src/lm32_decoder.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_mc_arithmetic.v
===================================================================
--- lm32/verilog/src/lm32_mc_arithmetic.v (nonexistent)
+++ lm32/verilog/src/lm32_mc_arithmetic.v (revision 17)
@@ -0,0 +1,283 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm_mc_arithmetic.v
+// Title : Multi-cycle arithmetic unit.
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+`define LM32_MC_STATE_RNG 2:0
+`define LM32_MC_STATE_IDLE 3'b000
+`define LM32_MC_STATE_MULTIPLY 3'b001
+`define LM32_MC_STATE_MODULUS 3'b010
+`define LM32_MC_STATE_DIVIDE 3'b011
+`define LM32_MC_STATE_SHIFT_LEFT 3'b100
+`define LM32_MC_STATE_SHIFT_RIGHT 3'b101
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_mc_arithmetic (
+ // ----- Inputs -----
+ clk_i,
+ rst_i,
+ stall_d,
+ kill_x,
+`ifdef CFG_MC_DIVIDE_ENABLED
+ divide_d,
+ modulus_d,
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+ multiply_d,
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ shift_left_d,
+ shift_right_d,
+ sign_extend_d,
+`endif
+ operand_0_d,
+ operand_1_d,
+ // ----- Ouputs -----
+ result_x,
+`ifdef CFG_MC_DIVIDE_ENABLED
+ divide_by_zero_x,
+`endif
+ stall_request_x
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+input stall_d; // Stall instruction in D stage
+input kill_x; // Kill instruction in X stage
+`ifdef CFG_MC_DIVIDE_ENABLED
+input divide_d; // Perform divide
+input modulus_d; // Perform modulus
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+input multiply_d; // Perform multiply
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+input shift_left_d; // Perform left shift
+input shift_right_d; // Perform right shift
+input sign_extend_d; // Whether to sign-extend (arithmetic) or zero-extend (logical)
+`endif
+input [`LM32_WORD_RNG] operand_0_d;
+input [`LM32_WORD_RNG] operand_1_d;
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] result_x; // Result of operation
+reg [`LM32_WORD_RNG] result_x;
+`ifdef CFG_MC_DIVIDE_ENABLED
+output divide_by_zero_x; // A divide by zero was attempted
+reg divide_by_zero_x;
+`endif
+output stall_request_x; // Request to stall pipeline from X stage back
+wire stall_request_x;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+reg [`LM32_WORD_RNG] p; // Temporary registers
+reg [`LM32_WORD_RNG] a;
+reg [`LM32_WORD_RNG] b;
+`ifdef CFG_MC_DIVIDE_ENABLED
+wire [32:0] t;
+`endif
+
+reg [`LM32_MC_STATE_RNG] state; // Current state of FSM
+reg [5:0] cycles; // Number of cycles remaining in the operation
+
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+reg sign_extend_x; // Whether to sign extend of zero extend right shifts
+wire fill_value; // Value to fill with for right barrel-shifts
+`endif
+
+/////////////////////////////////////////////////////
+// Combinational logic
+/////////////////////////////////////////////////////
+
+// Stall pipeline while any operation is being performed
+assign stall_request_x = state != `LM32_MC_STATE_IDLE;
+
+`ifdef CFG_MC_DIVIDE_ENABLED
+// Subtraction
+assign t = {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]} - b;
+`endif
+
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
+assign fill_value = (sign_extend_x == `TRUE) & b[`LM32_WORD_WIDTH-1];
+`endif
+
+/////////////////////////////////////////////////////
+// Sequential logic
+/////////////////////////////////////////////////////
+
+// Perform right shift
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ cycles <= {6{1'b0}};
+ p <= {`LM32_WORD_WIDTH{1'b0}};
+ a <= {`LM32_WORD_WIDTH{1'b0}};
+ b <= {`LM32_WORD_WIDTH{1'b0}};
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ sign_extend_x <= 1'b0;
+`endif
+`ifdef CFG_MC_DIVIDE_ENABLED
+ divide_by_zero_x <= `FALSE;
+`endif
+ result_x <= {`LM32_WORD_WIDTH{1'b0}};
+ state <= `LM32_MC_STATE_IDLE;
+ end
+ else
+ begin
+`ifdef CFG_MC_DIVIDE_ENABLED
+ divide_by_zero_x <= `FALSE;
+`endif
+ case (state)
+ `LM32_MC_STATE_IDLE:
+ begin
+ if (stall_d == `FALSE)
+ begin
+ cycles <= `LM32_WORD_WIDTH;
+ p <= 32'b0;
+ a <= operand_0_d;
+ b <= operand_1_d;
+`ifdef CFG_MC_DIVIDE_ENABLED
+ if (divide_d == `TRUE)
+ state <= `LM32_MC_STATE_DIVIDE;
+ if (modulus_d == `TRUE)
+ state <= `LM32_MC_STATE_MODULUS;
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+ if (multiply_d == `TRUE)
+ state <= `LM32_MC_STATE_MULTIPLY;
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ if (shift_left_d == `TRUE)
+ begin
+ state <= `LM32_MC_STATE_SHIFT_LEFT;
+ sign_extend_x <= sign_extend_d;
+ cycles <= operand_1_d[4:0];
+ a <= operand_0_d;
+ b <= operand_0_d;
+ end
+ if (shift_right_d == `TRUE)
+ begin
+ state <= `LM32_MC_STATE_SHIFT_RIGHT;
+ sign_extend_x <= sign_extend_d;
+ cycles <= operand_1_d[4:0];
+ a <= operand_0_d;
+ b <= operand_0_d;
+ end
+`endif
+ end
+ end
+`ifdef CFG_MC_DIVIDE_ENABLED
+ `LM32_MC_STATE_DIVIDE:
+ begin
+ if (t[32] == 1'b0)
+ begin
+ p <= t[31:0];
+ a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1};
+ end
+ else
+ begin
+ p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
+ a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
+ end
+ result_x <= a;
+ if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
+ begin
+ // Check for divide by zero
+ divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}};
+ state <= `LM32_MC_STATE_IDLE;
+ end
+ cycles <= cycles - 1'b1;
+ end
+ `LM32_MC_STATE_MODULUS:
+ begin
+ if (t[32] == 1'b0)
+ begin
+ p <= t[31:0];
+ a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1};
+ end
+ else
+ begin
+ p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
+ a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
+ end
+ result_x <= p;
+ if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
+ begin
+ // Check for divide by zero
+ divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}};
+ state <= `LM32_MC_STATE_IDLE;
+ end
+ cycles <= cycles - 1'b1;
+ end
+`endif
+`ifdef CFG_MC_MULTIPLY_ENABLED
+ `LM32_MC_STATE_MULTIPLY:
+ begin
+ if (b[0] == 1'b1)
+ p <= p + a;
+ b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]};
+ a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
+ result_x <= p;
+ if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
+ state <= `LM32_MC_STATE_IDLE;
+ cycles <= cycles - 1'b1;
+ end
+`endif
+`ifdef CFG_MC_BARREL_SHIFT_ENABLED
+ `LM32_MC_STATE_SHIFT_LEFT:
+ begin
+ a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
+ result_x <= a;
+ if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
+ state <= `LM32_MC_STATE_IDLE;
+ cycles <= cycles - 1'b1;
+ end
+ `LM32_MC_STATE_SHIFT_RIGHT:
+ begin
+ b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]};
+ result_x <= b;
+ if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
+ state <= `LM32_MC_STATE_IDLE;
+ cycles <= cycles - 1'b1;
+ end
+`endif
+ endcase
+ end
+end
+
+endmodule
lm32/verilog/src/lm32_mc_arithmetic.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_functions.v
===================================================================
--- lm32/verilog/src/lm32_functions.v (nonexistent)
+++ lm32/verilog/src/lm32_functions.v (revision 17)
@@ -0,0 +1,30 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_functions.v
+// Title : Common functions
+// Version : 6.1.17
+// =============================================================================
+`ifdef INCLUDE_FUNCTION
+function integer clogb2;
+input [31:0] value;
+begin
+ for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+ value = value >> 1;
+end
+endfunction
+`endif
lm32/verilog/src/lm32_functions.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/verilog/src/lm32_icache.v
===================================================================
--- lm32/verilog/src/lm32_icache.v (nonexistent)
+++ lm32/verilog/src/lm32_icache.v (revision 17)
@@ -0,0 +1,428 @@
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_icache.v
+// Title : Instruction cache
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// =============================================================================
+
+`include "lm32_include.v"
+
+`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
+`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
+`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
+`define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
+
+`define LM32_IC_TMEM_ADDR_WIDTH addr_set_width
+`define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0
+`define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
+`define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0
+
+`define LM32_IC_TAGS_WIDTH (addr_tag_width+1)
+`define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0
+`define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1
+`define LM32_IC_TAGS_VALID_RNG 0
+
+`define LM32_IC_STATE_RNG 3:0
+`define LM32_IC_STATE_FLUSH_INIT 4'b0001
+`define LM32_IC_STATE_FLUSH 4'b0010
+`define LM32_IC_STATE_CHECK 4'b0100
+`define LM32_IC_STATE_REFILL 4'b1000
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_icache (
+ // ----- Inputs -----
+ clk_i,
+ rst_i,
+ stall_a,
+ stall_f,
+ address_a,
+ address_f,
+ read_enable_f,
+ refill_ready,
+ refill_data,
+ iflush,
+ // ----- Outputs -----
+ stall_request,
+ restart_request,
+ refill_request,
+ refill_address,
+ refilling,
+ inst
+ );
+
+/////////////////////////////////////////////////////
+// Parameters
+/////////////////////////////////////////////////////
+
+parameter associativity = 1; // Associativity of the cache (Number of ways)
+parameter sets = 512; // Number of sets
+parameter bytes_per_line = 16; // Number of bytes per cache line
+parameter base_address = 0; // Base address of cachable memory
+parameter limit = 0; // Limit (highest address) of cachable memory
+
+localparam addr_offset_width = 2;
+localparam addr_set_width = 9;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = 31;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+
+input stall_a; // Stall instruction in A stage
+input stall_f; // Stall instruction in F stage
+
+input [`LM32_PC_RNG] address_a; // Address of instruction in A stage
+input [`LM32_PC_RNG] address_f; // Address of instruction in F stage
+input read_enable_f; // Indicates if cache access is valid
+
+input refill_ready; // Next word of refill data is ready
+input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with
+
+input iflush; // Flush the cache
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output stall_request; // Request to stall the pipeline
+wire stall_request;
+output restart_request; // Request to restart instruction that caused the cache miss
+reg restart_request;
+output refill_request; // Request to refill a cache line
+wire refill_request;
+output [`LM32_PC_RNG] refill_address; // Base address of cache refill
+reg [`LM32_PC_RNG] refill_address;
+output refilling; // Indicates the instruction cache is currently refilling
+reg refilling;
+output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
+wire [`LM32_INSTRUCTION_RNG] inst;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
+wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
+
+wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
+wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
+wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
+wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
+wire [`LM32_IC_TAGS_RNG] tmem_write_data;
+
+reg [`LM32_IC_STATE_RNG] state;
+wire flushing;
+wire check;
+wire refill;
+
+reg [associativity-1:0] refill_way_select;
+reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
+wire last_refill;
+reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
+
+genvar i;
+
+/////////////////////////////////////////////////////
+// Functions
+/////////////////////////////////////////////////////
+`define INCLUDE_FUNCTION
+`include "lm32_functions.v"
+
+/////////////////////////////////////////////////////
+// Instantiations
+/////////////////////////////////////////////////////
+
+generate
+ for (i = 0; i < associativity; i = i + 1)
+ begin : memories
+
+// Way 0 data
+lm32_ram #(
+ // ----- Parameters -------
+ .data_width (32),
+ .address_width (`LM32_IC_DMEM_ADDR_WIDTH)
+ ) way_0_data_ram (
+ // ----- Inputs -------
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .read_address (dmem_read_address),
+ .enable_read (enable),
+ .write_address (dmem_write_address),
+ .enable_write (`TRUE),
+ .write_enable (way_mem_we[i]),
+ .write_data (refill_data),
+ // ----- Outputs -------
+ .read_data (way_data[i])
+ );
+
+// Way 0 tags
+lm32_ram #(
+ // ----- Parameters -------
+ .data_width (`LM32_IC_TAGS_WIDTH),
+ .address_width (`LM32_IC_TMEM_ADDR_WIDTH)
+ ) way_0_tag_ram (
+ // ----- Inputs -------
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .read_address (tmem_read_address),
+ .enable_read (enable),
+ .write_address (tmem_write_address),
+ .enable_write (`TRUE),
+ .write_enable (way_mem_we[i] | flushing),
+ .write_data (tmem_write_data),
+ // ----- Outputs -------
+ .read_data ({way_tag[i], way_valid[i]})
+ );
+
+ end
+endgenerate
+
+/////////////////////////////////////////////////////
+// Combinational logic
+/////////////////////////////////////////////////////
+
+// Compute which ways in the cache match the address address being read
+generate
+ for (i = 0; i < associativity; i = i + 1)
+ begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
+ end
+endgenerate
+
+// Select data from way that matched the address being read
+generate
+ if (associativity == 1)
+ begin : inst_1
+assign inst = way_data[0];
+ end
+ else if (associativity == 2)
+ begin : inst_2
+assign inst = way_match[0] ? way_data[0] : way_data[1];
+ end
+endgenerate
+
+// Compute address to use to index into the data memories
+generate
+ if (bytes_per_line > 4)
+ begin : wadr1
+assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
+ end
+ else
+ begin : wadr2
+assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
+ end
+endgenerate
+
+assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
+
+// Compute address to use to index into the tag memories
+assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
+assign tmem_write_address = flushing
+ ? flush_set
+ : refill_address[`LM32_IC_ADDR_SET_RNG];
+
+// Compute signal to indicate when we are on the last refill accesses
+generate
+ if (bytes_per_line > 4)
+ begin : lrefil1
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+ end
+ else
+ begin : lrefil2
+assign last_refill = `TRUE;
+ end
+endgenerate
+
+// Compute data and tag memory access enable
+assign enable = (stall_a == `FALSE);
+
+// Compute data and tag memory write enables
+generate
+ if (associativity == 1)
+ begin : we_1
+assign way_mem_we[0] = (refill_ready == `TRUE);
+ end
+ else
+ begin : we_2
+assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
+assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
+ end
+endgenerate
+
+// On the last refill cycle set the valid bit, for all other writes it should be cleared
+assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
+assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
+
+// Signals that indicate which state we are in
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE);
+assign stall_request = (check == `FALSE);
+assign refill_request = (refill == `TRUE);
+
+/////////////////////////////////////////////////////
+// Sequential logic
+/////////////////////////////////////////////////////
+
+// Record way selected for replacement on a cache miss
+generate
+ if (associativity >= 2)
+ begin : way_select
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+ else
+ begin
+ if (miss == `TRUE)
+ refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+ end
+end
+ end
+endgenerate
+
+// Record whether we are refilling
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ refilling <= `FALSE;
+ else
+ refilling <= refill;
+end
+
+// Instruction cache control FSM
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ state <= `LM32_IC_STATE_FLUSH_INIT;
+ flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
+ refill_address <= {`LM32_PC_WIDTH{1'bx}};
+ restart_request <= `FALSE;
+ end
+ else
+ begin
+ case (state)
+
+ // Flush the cache for the first time after reset
+ `LM32_IC_STATE_FLUSH_INIT:
+ begin
+ if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
+ state <= `LM32_IC_STATE_CHECK;
+ flush_set <= flush_set - 1'b1;
+ end
+
+ // Flush the cache in response to an write to the ICC CSR
+ `LM32_IC_STATE_FLUSH:
+ begin
+ if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
+ state <= `LM32_IC_STATE_REFILL;
+ flush_set <= flush_set - 1'b1;
+ end
+
+ // Check for cache misses
+ `LM32_IC_STATE_CHECK:
+ begin
+ if (stall_a == `FALSE)
+ restart_request <= `FALSE;
+ if (iflush == `TRUE)
+ begin
+ refill_address <= address_f;
+ state <= `LM32_IC_STATE_FLUSH;
+ end
+ else if (miss == `TRUE)
+ begin
+ refill_address <= address_f;
+ state <= `LM32_IC_STATE_REFILL;
+ end
+ end
+
+ // Refill a cache line
+ `LM32_IC_STATE_REFILL:
+ begin
+ if (refill_ready == `TRUE)
+ begin
+ if (last_refill == `TRUE)
+ begin
+ restart_request <= `TRUE;
+ state <= `LM32_IC_STATE_CHECK;
+ end
+ end
+ end
+
+ endcase
+ end
+end
+
+generate
+ if (bytes_per_line > 4)
+ begin : refilof1
+// Refill offset
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else
+ begin
+ case (state)
+
+ // Check for cache misses
+ `LM32_IC_STATE_CHECK:
+ begin
+ if (iflush == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else if (miss == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ end
+
+ // Refill a cache line
+ `LM32_IC_STATE_REFILL:
+ begin
+ if (refill_ready == `TRUE)
+ refill_offset <= refill_offset + 1'b1;
+ end
+
+ endcase
+ end
+end
+ end
+endgenerate
+
+endmodule
lm32/verilog/src/lm32_icache.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/sw/linker.ld
===================================================================
--- lm32/sw/linker.ld (nonexistent)
+++ lm32/sw/linker.ld (revision 17)
@@ -0,0 +1,59 @@
+OUTPUT_FORMAT("elf32-lm32")
+ENTRY(_start)
+
+__DYNAMIC = 0;
+
+
+_RAM_START = 0x0000000;
+_RAM_SIZE = 0x4000;
+_RAM_END = _RAM_START + _RAM_SIZE;
+
+MEMORY {
+ ram : ORIGIN = 0x00000000, LENGTH = 0x4000 /* 16k */
+}
+
+SECTIONS
+{
+ .text :
+ {
+ _ftext = .;
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ _etext = .;
+ } > ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ _frodata = .;
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ *(.rodata1)
+ _erodata = .;
+ } > ram
+
+ .data :
+ {
+ . = ALIGN(4);
+ _fdata = .;
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.data1)
+ _gp = ALIGN(16);
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ _edata = .;
+ } > ram
+
+ .bss :
+ {
+ . = ALIGN(4);
+ _fbss = .;
+ *(.dynsbss)
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ _ebss = .;
+ _end = .;
+ } > ram
+}
+
+PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);
lm32/sw/linker.ld
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/sw/lm32_system.h
===================================================================
--- lm32/sw/lm32_system.h (nonexistent)
+++ lm32/sw/lm32_system.h (revision 17)
@@ -0,0 +1,61 @@
+
+#ifndef LM32_SYS_H
+ #define LM32_SYS_H
+
+/***************************************************************************
+ * IRQ handling
+ */
+
+/****************************************************************************
+ * Types
+ */
+typedef unsigned int uint32_t; // 32 Bit
+typedef signed int int32_t; // 32 Bit
+
+typedef unsigned char uint8_t; // 8 Bit
+typedef signed char int8_t; // 8 Bit
+
+/****************************************************************************/
+
+typedef void(*isr_ptr_t)(void);
+void halt();
+void jump(uint32_t addr);
+
+
+isr_ptr_t isr_table[32];
+
+
+
+void isr_null()
+{
+
+}
+
+void irq_handler(uint32_t pending)
+{
+ int i;
+
+ for(i=0; i<32; i++) {
+ if (pending & 0x01) (*isr_table[i])();
+ pending >>= 1;
+ }
+}
+
+void isr_init()
+{
+ int i;
+ for(i=0; i<32; i++)
+ isr_table[i] = &isr_null;
+}
+
+void isr_register(int irq, isr_ptr_t isr)
+{
+ isr_table[irq] = isr;
+}
+
+void isr_unregister(int irq)
+{
+ isr_table[irq] = &isr_null;
+}
+
+#endif
lm32/sw/lm32_system.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/sw/crt0ram.S
===================================================================
--- lm32/sw/crt0ram.S (nonexistent)
+++ lm32/sw/crt0ram.S (revision 17)
@@ -0,0 +1,286 @@
+/*
+ * LatticeMico32 C startup code.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* Exception handlers - Must be 32 bytes long. */
+ .section .text, "ax", @progbits
+ .global _start
+ .global irq_enable, irq_disable, irq_set_mask, irq_get_mask
+ .global jump, halt
+ .global get_sp, get_gp
+
+_start:
+_reset_handler:
+ bi _crt0
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+_breakpoint_handler:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+_ibuserror_handler:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+_watchpoint_handler:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+_dbuserror_handler:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+_divzero_handler:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+_interrupt_handler:
+ sw (sp+0), ra
+ calli _save_all
+ rcsr r1, IP
+ calli irq_handler
+ mvhi r1, 0xffff
+ ori r1, r1, 0xffff
+ wcsr IP, r1
+ bi _restore_all_and_eret
+
+_scall_handler:
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+_crt0:
+ /* Clear r0 */
+ xor r0, r0, r0
+
+ /* Clear all other regs (needed so that simulations match) */
+ mvi r1, 0
+ mvi r2, 0
+ mvi r3, 0
+ mvi r4, 0
+ mvi r5, 0
+ mvi r6, 0
+ mvi r7, 0
+ mvi r8, 0
+ mvi r9, 0
+ mvi r10, 0
+ mvi r11, 0
+ mvi r12, 0
+ mvi r13, 0
+ mvi r14, 0
+ mvi r15, 0
+ mvi r16, 0
+ mvi r17, 0
+ mvi r18, 0
+ mvi r19, 0
+ mvi r20, 0
+ mvi r21, 0
+ mvi r22, 0
+ mvi r23, 0
+ mvi r24, 0
+ mvi r25, 0
+ mvi r26, 0
+ mvi r27, 0
+ mvi r28, 0
+ mvi r29, 0
+ mvi r30, 0
+ mvi r31, 0
+
+ /* Setup stack and global pointer */
+ mvhi sp, hi(_fstack)
+ ori sp, sp, lo(_fstack)
+ mvhi gp, hi(_gp)
+ ori gp, gp, lo(_gp)
+
+ /* Clear BSS */
+ mvhi r1, hi(_fbss)
+ ori r1, r1, lo(_fbss)
+ mvhi r3, hi(_ebss)
+ ori r3, r3, lo(_ebss)
+.clearBSS:
+ be r1, r3, .callMain
+ sw (r1+0), r0
+ addi r1, r1, 4
+ bi .clearBSS
+
+
+.callMain:
+ mvi r1, 0
+ mvi r2, 0
+ mvi r3, 0
+ calli main
+
+irq_enable:
+ mvi r1, 1
+ wcsr IE, r1
+ ret
+
+irq_disable:
+ mvi r1, 0
+ wcsr IE, r1
+ ret
+
+irq_set_mask:
+ wcsr IM, r1
+ ret
+
+irq_get_mask:
+ rcsr r1, IM
+ ret
+
+jump:
+ b r1
+
+halt:
+ bi halt
+
+ /* Save all registers onto the stack */
+_save_all:
+ addi sp, sp, -128
+ sw (sp+4), r1
+ sw (sp+8), r2
+ sw (sp+12), r3
+ sw (sp+16), r4
+ sw (sp+20), r5
+ sw (sp+24), r6
+ sw (sp+28), r7
+ sw (sp+32), r8
+ sw (sp+36), r9
+ sw (sp+40), r10
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+ sw (sp+44), r11
+ sw (sp+48), r12
+ sw (sp+52), r13
+ sw (sp+56), r14
+ sw (sp+60), r15
+ sw (sp+64), r16
+ sw (sp+68), r17
+ sw (sp+72), r18
+ sw (sp+76), r19
+ sw (sp+80), r20
+ sw (sp+84), r21
+ sw (sp+88), r22
+ sw (sp+92), r23
+ sw (sp+96), r24
+ sw (sp+100), r25
+ sw (sp+104), r26
+ sw (sp+108), r27
+#endif
+ sw (sp+120), ea
+ sw (sp+124), ba
+ /* ra and sp need special handling, as they have been modified */
+ lw r1, (sp+128)
+ sw (sp+116), r1
+ mv r1, sp
+ addi r1, r1, 128
+ sw (sp+112), r1
+ ret
+
+ /* Restore all registers and return from exception */
+_restore_all_and_eret:
+ lw r1, (sp+4)
+ lw r2, (sp+8)
+ lw r3, (sp+12)
+ lw r4, (sp+16)
+ lw r5, (sp+20)
+ lw r6, (sp+24)
+ lw r7, (sp+28)
+ lw r8, (sp+32)
+ lw r9, (sp+36)
+ lw r10, (sp+40)
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+ lw r11, (sp+44)
+ lw r12, (sp+48)
+ lw r13, (sp+52)
+ lw r14, (sp+56)
+ lw r15, (sp+60)
+ lw r16, (sp+64)
+ lw r17, (sp+68)
+ lw r18, (sp+72)
+ lw r19, (sp+76)
+ lw r20, (sp+80)
+ lw r21, (sp+84)
+ lw r22, (sp+88)
+ lw r23, (sp+92)
+ lw r24, (sp+96)
+ lw r25, (sp+100)
+ lw r26, (sp+104)
+ lw r27, (sp+108)
+#endif
+ lw ra, (sp+116)
+ lw ea, (sp+120)
+ lw ba, (sp+124)
+ /* Stack pointer must be restored last, in case it has been updated */
+ lw sp, (sp+112)
+ eret
+
+get_sp:
+ mv r1, sp
+ ret
+
+get_gp:
+ mv r1, gp
+ ret
+
lm32/sw/crt0ram.S
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: lm32/sw/Makefile
===================================================================
--- lm32/sw/Makefile (nonexistent)
+++ lm32/sw/Makefile (revision 17)
@@ -0,0 +1,54 @@
+TOOLCHAIN=$(PRONOC_WORK)/toolchain/lm32/bin/
+IHEX2MIF =$(PRONOC_WORK)/toolchain/ihex2mif/ihex2mif
+
+
+#SREC2VRAM ?= ../../../toolchain/lm32/srec2vram/srec2vram
+
+RAMSIZE=3FFF
+
+LM32_CC=$(TOOLCHAIN)lm32-elf-gcc
+LM32_LD=$(TOOLCHAIN)lm32-elf-ld
+LM32_OBJCOPY=$(TOOLCHAIN)lm32-elf-objcopy
+LM32_OBJDUMP=$(TOOLCHAIN)lm32-elf-objdump
+VRAMFILE=image.ram
+
+CFLAGS=-MMD -O2 -Wall -g -s -fomit-frame-pointer -mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled
+LDFLAGS=-nostdlib -nodefaultlibs -Tlinker.ld
+SEGMENTS = -j .text -j .rodata -j .data
+
+all: image.srec $(VRAMFILE)
+
+crt0ram.o: crt0ram.S
+ $(LM32_CC) $(CFLAGS) -c crt0ram.S
+
+main.o: main.c
+ $(LM32_CC) $(CFLAGS) -c main.c
+
+#soc-hw.o: soc-hw.c
+#$(LM32_CC) $(CFLAGS) -c soc-hw.c
+
+image: crt0ram.o main.o linker.ld Makefile
+ $(LM32_LD) $(LDFLAGS) -Map image.map -N -o image crt0ram.o main.o
+
+image.lst: image
+ $(LM32_OBJDUMP) -h -S $< > $@
+
+image.bin: image
+ $(LM32_OBJCOPY) $(SEGMENTS) -O binary image image.bin
+
+image.srec: image image.lst image.bin
+#$(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.srec
+ $(LM32_OBJCOPY) $(SEGMENTS) -O ihex image image.ihex
+
+$(VRAMFILE): image.srec
+#$(SREC2VRAM) image.srec 0x40000000 0x1000 > $(VRAMFILE)
+ $(IHEX2MIF) -f image.ihex -e $(RAMSIZE) -o ram00.mif
+
+clean:
+ rm -f image.ihex image image.lst image.bin image.srec image.map image.ram image.hex *.o *.d
+
+DEPS := $(wildcard *.d)
+ifneq ($(DEPS),)
+include $(DEPS)
+endif
+
lm32/sw/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.