URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_processor
- from Rev 17 to Rev 19
- ↔ Reverse comparison
Rev 17 → Rev 19
/aeMB/compiler/aemb/heap.hh
File deleted
/aeMB/compiler/aemb/hook.hh
File deleted
/aeMB/compiler/aemb/msr.hh
File deleted
/aeMB/compiler/aemb/stdio.hh
File deleted
/aeMB/compiler/aemb/semaphore.hh
File deleted
/aeMB/compiler/aemb/stack.hh
File deleted
/aeMB/compiler/aemb/thread.hh
File deleted
/aeMB/compiler/aemb/core.hh
File deleted
/aeMB/compiler/program/prog.tcl
File deleted
aeMB/compiler/program/prog.tcl
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB/compiler/compile/custom_crt/crt0.s
===================================================================
--- aeMB/compiler/compile/custom_crt/crt0.s (revision 17)
+++ aeMB/compiler/compile/custom_crt/crt0.s (nonexistent)
@@ -1,100 +0,0 @@
-###################################-*-asm*-
-#
-# Copyright (c) 2001 Xilinx, Inc. All rights reserved.
-#
-# Xilinx, Inc.
-#
-# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
-# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
-# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
-# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
-# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
-# AND FITNESS FOR A PARTICULAR PURPOSE.
-#
-# crt0.s
-#
-# Default C run-time initialization for MicroBlaze standalone
-# executables (compiled with -xl-mode-executable or no switches)
-#
-# $Id: crt0.s,v 1.7.2.6 2005/11/15 23:32:53 salindac Exp $
-#
-#######################################
-
-/*
-
- MicroBlaze Vector Map for standalone executables
-
- Address Vector type Label
- ------- ----------- ------
-
- # 0x00 # (-- IMM --)
- # 0x04 # Reset _start1
-
- # 0x08 # (-- IMM --)
- # 0x0c # Software Exception _exception_handler
-
- # 0x10 # (-- IMM --)
- # 0x14 # Hardware Interrupt _interrupt_handler
-
- # 0x18 # (-- IMM --)
- # 0x1C # Breakpoint Exception (-- Don't Care --)
-
- # 0x20 # (-- IMM --)
- # 0x24 # Hardware Exception _hw_exception_handler
-
-*/
-
-
- .globl _start
- .section .vectors.reset, "ax"
- .align 2
-_start:
- brai _start1
-
- .section .vectors.sw_exception, "ax"
- .align 2
-_vector_sw_exception:
- brai _exception_handler
-
- .section .vectors.interrupt, "ax"
- .align 2
-_vector_interrupt:
- brai _interrupt_handler
-
- .section .vectors.hw_exception, "ax"
- .align 2
-_vector_hw_exception:
- brai _hw_exception_handler
-
- .section .text
- .globl _start1
- .align 2
-_start1:
- la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */
- la r2, r0, _SDA2_BASE_
- la r1, r0, _stack-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */
-
- brlid r15, _crtinit /* Initialize BSS and run program */
- nop
-
- brlid r15, exit /* Call exit with the return value of main */
- addik r5, r3, 0
-
- /* Control does not reach here */
-
-/*
- _exit
- Our simple _exit
-*/
- .globl _exit
- .align 2
- .ent _exit
-_exit:
- bri 0
- .end _exit
-
aeMB/compiler/compile/custom_crt/crt0.s
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB/compiler/compile/custom_crt/crtinit.s
===================================================================
--- aeMB/compiler/compile/custom_crt/crtinit.s (revision 17)
+++ aeMB/compiler/compile/custom_crt/crtinit.s (nonexistent)
@@ -1,83 +0,0 @@
-###################################-*-asm*-
-#
-# Copyright (c) 2001 Xilinx, Inc. All rights reserved.
-#
-# Xilinx, Inc.
-#
-# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
-# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
-# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
-# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
-# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
-# AND FITNESS FOR A PARTICULAR PURPOSE.
-#
-# crtinit.s
-#
-# Default second stage of C run-time initialization
-#
-# $Id: crtinit.s,v 1.5.2.7 2006/07/05 18:53:54 vasanth Exp $
-#
-#######################################
-
- .globl _crtinit
- .align 2
- .ent _crtinit
-
-_crtinit:
- addi r1, r1, -20 /* Save Link register */
- swi r15, r1, 0
-
- addi r6, r0, __sbss_start /* clear SBSS */
- addi r7, r0, __sbss_end
- rsub r18, r6, r7
- blei r18, .Lendsbss
-
-.Lloopsbss:
- swi r0, r6, 0
- addi r6, r6, 4
- rsub r18, r6, r7
- bgti r18, .Lloopsbss
-.Lendsbss:
-
- addi r6, r0, __bss_start /* clear BSS */
- addi r7, r0, __bss_end
- rsub r18, r6, r7
- blei r18, .Lendbss
-.Lloopbss:
- swi r0, r6, 0
- addi r6, r6, 4
- rsub r18, r6, r7
- bgti r18, .Lloopbss
-.Lendbss:
-
- brlid r15, _program_init /* Initialize the program */
- nop
-
-# brlid r15, __init /* Invoke language initialization functions */
-# nop
-
- addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */
- addi r7, r0, 0
- brlid r15, main /* Execute the program */
- addi r5, r0, 0
-
- addik r19, r3, 0 /* Save return value */
-
-# brlid r15, __fini /* Invoke language cleanup functions */
-# nop
-
- brlid r15, _program_clean /* Cleanup the program */
- nop
-
- lw r15, r1, r0 /* Return back to CRT */
-
- addik r3, r19, 0 /* Restore return value */
- rtsd r15, 8
- addi r1, r1, 20
- .end _crtinit
-
aeMB/compiler/compile/custom_crt/crtinit.s
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB/compiler/compile/gccrom
===================================================================
--- aeMB/compiler/compile/gccrom (revision 17)
+++ aeMB/compiler/compile/gccrom (nonexistent)
@@ -1,42 +0,0 @@
-#!/bin/sh
-# $Id: gccrom,v 1.18 2008-05-01 08:35:04 sybreon Exp $
-
-# Compile using C pre-processor
-ELFFILE="rom"
-XILFLAGS="-mtune=v5.00 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul"
-CXXFLAGS="-O1"
-LNKFLAGS="-Wl,-defsym -Wl,_STACK_SIZE=0x400 -Wl,-defsym -Wl,_HEAP_SIZE=0x400"
-LIBFLAGS=""
-INCFLAGS="-Icc/"
-RAMSIZE="3FFF" #for aeMB ramwith of 12
-
-mb-g++ $XILFLAGS $CXXFLAGS $LNKFLAGS $LIBFLAGS $INCFLAGS -specs=aemb.specs $@ -o $ELFFILE && \
-echo "xgcc=$?" && \
-
-# Create a text listing of the compiled code
-mb-objdump -DSCz $ELFFILE > $ELFFILE.dump && \
-echo "dump=$?" && \
-
-# Convert the ELF file to an SREC file
-mb-objcopy -O srec $ELFFILE $ELFFILE.srec && \
-echo "copy=$?" && \
-
-# Generate a Verilog VMEM file from the SREC file
-srec_cat $ELFFILE.srec -fill 0xFF -within $ELFFILE.srec --range-pad 4 -o out/dump.vmem -vmem 32 && \
-echo "srec=$?" && \
-
-
-# Convert the ELF file to an IHEX file
-mb-objcopy -O ihex $ELFFILE $ELFFILE.ihex && \
-#echo "copy2ihex=$?" && \
-
-# Generate a MIF file from the IHEX file
-ihex/ihex2mif -f $ELFFILE.ihex -e $RAMSIZE -o out/ram0.mif && \
-echo "ihex2mif=$?" && \
-
-# echo the checksum
-MD5=$(sha1sum $ELFFILE | cut -c1-32) && \
-echo "sha1=$MD5" && \
-
-# Cleanup code
-rm $ELFFILE.srec && rm $ELFFILE
aeMB/compiler/compile/gccrom
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB/compiler/compile/ihex/main.c
===================================================================
--- aeMB/compiler/compile/ihex/main.c (revision 17)
+++ aeMB/compiler/compile/ihex/main.c (nonexistent)
@@ -1,121 +0,0 @@
-#include "ihex.c"
-#include
-#include
-
-#define DEFAULT_OUT_FILE_NAME "out.mif"
-#define DEAFULT_END_SIZE "1FFF"
-
-int memory[65536]; /* the memory is global */
-unsigned int end_addr_int;
-FILE * in, * out;
-char *file_name, *end_addr, *out_file_name ;
-
-void usage (void)
-{
- printf("Usage: ./ihex2mif \n");
- printf("\nOptions: \n");
- printf(" -e : end memory address .\n");
- printf(" -f : input ihex file .\n");
-
-}
-
-void processArgs (int argc, char **argv )
-{
- char c;
-
- opterr = 0;
-
- while ((c = getopt (argc, argv, "e:f:o:h")) != -1)
- {
- switch (c)
- {
- case 'e':
- end_addr = optarg;
- break;
- case 'f':
- file_name = optarg;
- break;
- case 'o':
- out_file_name = optarg;
- break;
- case 'h':
- usage();
- exit(1);
- break;
- case '?':
- if (isprint (optopt))
- fprintf (stderr, "Unknown option `-%c'.\n", optopt);
- else
- fprintf (stderr, "Unknown option character `\\x%x'.\n", optopt);
- default:
- usage();
- exit(1);
- }
- }
-}
-
-void update_out_file(void);
-int main ( int argc, char **argv ){
-
- processArgs (argc,argv );
- if (file_name == NULL) {usage();exit(1);}
- if (end_addr == NULL) end_addr = DEAFULT_END_SIZE;
- if (out_file_name == NULL) out_file_name = DEFAULT_OUT_FILE_NAME;
- //printf("filename=%s & size=%s\n",file_name, end_addr);
- sscanf(end_addr, "%x", &end_addr_int);
- //printf("%u\n", end_addr_int);
- out=fopen(out_file_name,"wb");
- if(out==NULL){printf("Output file cannot be created"); exit(1);}
- load_file(file_name);
- update_out_file();
-
-
- fclose(out);
-
-return 0;
-}
-
-
-void update_out_file(void){
- unsigned int ram_addr=0,zero_count,ram_data,i;
- fprintf(out,"-- Copyright (C) 2013 Alireza Monemi\n\n");
- fprintf(out,"WIDTH=32;\nDEPTH=%d;\nADDRESS_RADIX=HEX;\nDATA_RADIX=HEX;\n\nCONTENT BEGIN\n", (end_addr_int>>2)+1);
- while(ram_addr>2,ram_data);
- }else if (zero_count == 1){
- fprintf(out,"\t%08X\t:\t%08X;\n" , (ram_addr>>2),0);
- if(ram_data!=0)fprintf(out,"\t%08X\t:\t%08X;\n" , (ram_addr>>2)+1,ram_data);
-
- }
- else {
- fprintf(out,"\t[%08X..%08X]\t:\t00000000;\n" ,ram_addr>>2, (ram_addr>>2)+ zero_count-1);
- if(ram_data!=0)fprintf(out,"\t%08X\t:\t%08X;\n" , (ram_addr>>2)+ zero_count,ram_data);
- }
- ram_addr+=(zero_count<<2)+4;
-
-
-
-
- }
- fprintf(out,"END;");
-
-return;
-}
-
aeMB/compiler/compile/ihex/main.c
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB/compiler/compile/ihex/ihex2mif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: aeMB/compiler/compile/ihex/ihex2mif
===================================================================
--- aeMB/compiler/compile/ihex/ihex2mif (revision 17)
+++ aeMB/compiler/compile/ihex/ihex2mif (nonexistent)
aeMB/compiler/compile/ihex/ihex2mif
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: aeMB/compiler/compile/ihex/Makefile
===================================================================
--- aeMB/compiler/compile/ihex/Makefile (revision 17)
+++ aeMB/compiler/compile/ihex/Makefile (nonexistent)
@@ -1,3 +0,0 @@
-#!/bin/sh
-all:
- gcc main.c -o ihex2mif
aeMB/compiler/compile/ihex/Makefile
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB/compiler/compile/ihex/ihex.c
===================================================================
--- aeMB/compiler/compile/ihex/ihex.c (revision 17)
+++ aeMB/compiler/compile/ihex/ihex.c (nonexistent)
@@ -1,216 +0,0 @@
-/* Intel HEX read/write functions, Paul Stoffregen, paul@ece.orst.edu */
-/* This code is in the public domain. Please retain my name and */
-/* email address in distributed copies, and let me know about any bugs */
-
-/* I, Paul Stoffregen, give no warranty, expressed or implied for */
-/* this software and/or documentation provided, including, without */
-/* limitation, warranty of merchantability and fitness for a */
-/* particular purpose. */
-
-
-#include
-#include
-#include
-
-/* some ansi prototypes.. maybe ought to make a .h file */
-
-/* this loads an intel hex file into the memory[] array */
-void load_file(char *filename);
-
-/* this writes a part of memory[] to an intel hex file */
-void save_file(char *command);
-
-/* this is used by load_file to get each line of intex hex */
-int parse_hex_line(char *theline, int bytes[], int *addr, int *num, int *code);
-
-/* this does the dirty work of writing an intel hex file */
-/* caution, static buffering is used, so it is necessary */
-/* to call it with end=1 when finsihed to flush the buffer */
-/* and close the file */
-void hexout(FILE *fhex, int byte, int memory_location, int end);
-
-
-extern int memory[65536]; /* the memory is global */
-
-/* parses a line of intel hex code, stores the data in bytes[] */
-/* and the beginning address in addr, and returns a 1 if the */
-/* line was valid, or a 0 if an error occured. The variable */
-/* num gets the number of bytes that were stored into bytes[] */
-
-int parse_hex_line(theline, bytes, addr, num, code)
-char *theline;
-int *addr, *num, *code, bytes[];
-{
- int sum, len, cksum;
- char *ptr;
-
- *num = 0;
- if (theline[0] != ':') return 0;
- if (strlen(theline) < 11) return 0;
- ptr = theline+1;
- if (!sscanf(ptr, "%02x", &len)) return 0;
- ptr += 2;
- if ( strlen(theline) < (11 + (len * 2)) ) return 0;
- if (!sscanf(ptr, "%04x", addr)) return 0;
- ptr += 4;
- /* printf("Line: length=%d Addr=%d\n", len, *addr); */
- if (!sscanf(ptr, "%02x", code)) return 0;
- ptr += 2;
- sum = (len & 255) + ((*addr >> 8) & 255) + (*addr & 255) + (*code & 255);
- while(*num != len) {
- if (!sscanf(ptr, "%02x", &bytes[*num])) return 0;
- ptr += 2;
- sum += bytes[*num] & 255;
- (*num)++;
- if (*num >= 256) return 0;
- }
- if (!sscanf(ptr, "%02x", &cksum)) return 0;
- if ( ((sum & 255) + (cksum & 255)) & 255 ) return 0; /* checksum error */
- return 1;
-}
-
-/* loads an intel hex file into the global memory[] array */
-/* filename is a string of the file to be opened */
-
-void load_file(filename)
-char *filename;
-{
- char line[1000];
- FILE *fin;
- int addr, n, status, bytes[256];
- int i, total=0, lineno=1;
- int minaddr=65536, maxaddr=0;
-
- if (strlen(filename) == 0) {
- printf(" Can't load a file without the filename.");
- printf(" '?' for help\n");
- return;
- }
- fin = fopen(filename, "r");
- if (fin == NULL) {
- printf(" Can't open file '%s' for reading.\n", filename);
- //return;
- exit(1);
- }
- while (!feof(fin) && !ferror(fin)) {
- line[0] = '\0';
- fgets(line, 1000, fin);
- if (line[strlen(line)-1] == '\n') line[strlen(line)-1] = '\0';
- if (line[strlen(line)-1] == '\r') line[strlen(line)-1] = '\0';
- if (parse_hex_line(line, bytes, &addr, &n, &status)) {
- if (status == 0) { /* data */
- for(i=0; i<=(n-1); i++) {
- memory[addr] = bytes[i] & 255;
- total++;
- if (addr < minaddr) minaddr = addr;
- if (addr > maxaddr) maxaddr = addr;
- addr++;
- }
- }
- if (status == 1) { /* end of file */
- fclose(fin);
- printf(" Loaded %d bytes between:", total);
- printf(" %04X to %04X\n", minaddr, maxaddr);
- return;
- }
- if (status == 2) ; /* begin of file */
- } else {
- printf(" Error: '%s', line: %d\n", filename, lineno);
- }
- lineno++;
- }
-}
-
-
-/* the command string format is "S begin end filename" where */
-/* "begin" and "end" are the locations to dump to the intel */
-/* hex file, specified in hexidecimal. */
-
-void save_file(command)
-char *command;
-{
- int begin, end, addr;
- char *ptr, filename[200];
- FILE *fhex;
-
- ptr = command+1;
- while (isspace(*ptr)) ptr++;
- if (*ptr == '\0') {
- printf(" Must specify address range and filename\n");
- return;
- }
- if (sscanf(ptr, "%x%x%s", &begin, &end, filename) < 3) {
- printf(" Invalid addresses or filename,\n");
- printf(" usage: S begin_addr end_addr filename\n");
- printf(" the addresses must be hexidecimal format\n");
- return;
- }
- begin &= 65535;
- end &= 65535;
- if (begin > end) {
- printf(" Begin address must be less than end address.\n");
- return;
- }
- fhex = fopen(filename, "w");
- if (fhex == NULL) {
- printf(" Can't open '%s' for writing.\n", filename);
- return;
- }
- for (addr=begin; addr <= end; addr++)
- hexout(fhex, memory[addr], addr, 0);
- hexout(fhex, 0, 0, 1);
- printf("Memory %04X to %04X written to '%s'\n", begin, end, filename);
-}
-
-
-/* produce intel hex file output... call this routine with */
-/* each byte to output and it's memory location. The file */
-/* pointer fhex must have been opened for writing. After */
-/* all data is written, call with end=1 (normally set to 0) */
-/* so it will flush the data from its static buffer */
-
-#define MAXHEXLINE 32 /* the maximum number of bytes to put in one line */
-
-void hexout(fhex, byte, memory_location, end)
-FILE *fhex; /* the file to put intel hex into */
-int byte, memory_location, end;
-{
- static int byte_buffer[MAXHEXLINE];
- static int last_mem, buffer_pos, buffer_addr;
- static int writing_in_progress=0;
- register int i, sum;
-
- if (!writing_in_progress) {
- /* initial condition setup */
- last_mem = memory_location-1;
- buffer_pos = 0;
- buffer_addr = memory_location;
- writing_in_progress = 1;
- }
-
- if ( (memory_location != (last_mem+1)) || (buffer_pos >= MAXHEXLINE) \
- || ((end) && (buffer_pos > 0)) ) {
- /* it's time to dump the buffer to a line in the file */
- fprintf(fhex, ":%02X%04X00", buffer_pos, buffer_addr);
- sum = buffer_pos + ((buffer_addr>>8)&255) + (buffer_addr&255);
- for (i=0; i < buffer_pos; i++) {
- fprintf(fhex, "%02X", byte_buffer[i]&255);
- sum += byte_buffer[i]&255;
- }
- fprintf(fhex, "%02X\n", (-sum)&255);
- buffer_addr = memory_location;
- buffer_pos = 0;
- }
-
- if (end) {
- fprintf(fhex, ":00000001FF\n"); /* end of file marker */
- fclose(fhex);
- writing_in_progress = 0;
- }
-
- last_mem = memory_location;
- byte_buffer[buffer_pos] = byte & 255;
- buffer_pos++;
-}
-
-
aeMB/compiler/compile/ihex/ihex.c
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB/compiler/compile/ihex/out.mif
===================================================================
--- aeMB/compiler/compile/ihex/out.mif (revision 17)
+++ aeMB/compiler/compile/ihex/out.mif (nonexistent)
@@ -1,257 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and its AMPP partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, Altera MegaCore Function License
--- Agreement, or other applicable license agreement, including,
--- without limitation, that your use is for the sole purpose of
--- programming logic devices manufactured by Altera and sold by
--- Altera or its authorized distributors. Please refer to the
--- applicable agreement for further details.
-
--- Quartus II generated Memory Initialization File (.mif)
-
-WIDTH=32;
-DEPTH=8191;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
- 0000 : B8080050;
- 0001 : 00000000;
- 0002 : B808017C;
- 0003 : 00000000;
- 0004 : B808018C;
- [0005..0007] : 00000000;
- 0008 : B8080184;
- [0009..0013] : 00000000;
- 0014 : 31A004C0;
- 0015 : 304003B8;
- 0016 : 30200D30;
- 0017 : B9F40014;
- 0018 : 80000000;
- 0019 : B9F40140;
- 001A : 30A30000;
- 001B : B8000000;
- 001C : 2021FFEC;
- 001D : F9E10000;
- 001E : 20C004C0;
- 001F : 20E004C0;
- 0020 : 06463800;
- 0021 : BC720014;
- 0022 : F8060000;
- 0023 : 20C60004;
- 0024 : 06463800;
- 0025 : BC92FFF4;
- 0026 : 20C004C0;
- 0027 : 20E0053C;
- 0028 : 06463800;
- 0029 : BC720014;
- 002A : F8060000;
- 002B : 20C60004;
- 002C : 06463800;
- 002D : BC92FFF4;
- 002E : B9F400E4;
- 002F : 80000000;
- 0030 : 20C00000;
- 0031 : 20E00000;
- 0032 : B9F40024;
- 0033 : 20A00000;
- 0034 : 32630000;
- 0035 : B9F400C0;
- 0036 : 80000000;
- 0037 : C9E10000;
- 0038 : 30730000;
- 0039 : B60F0008;
- 003A : 20210014;
- 003B : E8A003B8;
- 003C : E8E003C0;
- 003D : E94003C4;
- 003E : B00000F8;
- 003F : 312004C0;
- 0040 : B0001A00;
- 0041 : 31000000;
- 0042 : 30600001;
- 0043 : F8650000;
- 0044 : 10C00000;
- 0045 : E8650000;
- 0046 : 30800002;
- 0047 : 30630001;
- 0048 : F8650000;
- 0049 : 10642000;
- 004A : F88304C0;
- 004B : 30840002;
- 004C : AA44001E;
- 004D : BE32FFF4;
- 004E : 10642000;
- 004F : F90004C0;
- 0050 : F9270000;
- 0051 : BC26FFD0;
- 0052 : E86A0000;
- 0053 : A4C30001;
- 0054 : BC26FFC4;
- 0055 : E86A0000;
- 0056 : A4C30001;
- 0057 : BC26FFB8;
- 0058 : B800FFE8;
- 0059 : B8000008;
- 005A : 80000000;
- 005B : BE25FFFC;
- 005C : 30A5FFFF;
- 005D : B60F0008;
- 005E : 80000000;
- 005F : B6110000;
- 0060 : 80000000;
- 0061 : B6910000;
- 0062 : 80000000;
- 0063 : B62E0000;
- 0064 : 80000000;
- 0065 : B60F0008;
- 0066 : 80000000;
- 0067 : B60F0008;
- 0068 : 80000000;
- 0069 : 3021FFE0;
- 006A : 10C00000;
- 006B : FA61001C;
- 006C : F9E10000;
- 006D : B9F40024;
- 006E : 12650000;
- 006F : E8A003AC;
- 0070 : E8650028;
- 0071 : BC03000C;
- 0072 : 99FC1800;
- 0073 : 80000000;
- 0074 : B9F4FE9C;
- 0075 : 10B30000;
- 0076 : E86003AC;
- 0077 : 3021FFC8;
- 0078 : FB410030;
- 0079 : FB610034;
- 007A : F9E10000;
- 007B : FA61001C;
- 007C : FAC10020;
- 007D : FAE10024;
- 007E : FB010028;
- 007F : FB21002C;
- 0080 : EB030048;
- 0081 : 13650000;
- 0082 : BE180050;
- 0083 : 13460000;
- 0084 : E8780004;
- 0085 : EB380088;
- 0086 : 3263FFFF;
- 0087 : BC53003C;
- 0088 : 64930402;
- 0089 : 30640008;
- 008A : 12D81800;
- 008B : BE060074;
- 008C : 12F92000;
- 008D : BC1900C0;
- 008E : E8770080;
- 008F : 1643D000;
- 0090 : BC1200EC;
- 0091 : 3273FFFF;
- 0092 : 32F7FFFC;
- 0093 : AA53FFFF;
- 0094 : BE32FFE8;
- 0095 : 32D6FFFC;
- 0096 : E9E10000;
- 0097 : EA61001C;
- 0098 : EAC10020;
- 0099 : EAE10024;
- 009A : EB010028;
- 009B : EB21002C;
- 009C : EB410030;
- 009D : EB610034;
- 009E : B60F0008;
- 009F : 30210038;
- 00A0 : E8B70000;
- 00A1 : 99FC3800;
- 00A2 : 80000000;
- 00A3 : 3273FFFF;
- 00A4 : 32F7FFFC;
- 00A5 : AA53FFFF;
- 00A6 : BE12FFC0;
- 00A7 : 32D6FFFC;
- 00A8 : E8780004;
- 00A9 : E8F60000;
- 00AA : 3063FFFF;
- 00AB : 16439800;
- 00AC : BC120074;
- 00AD : F8160000;
- 00AE : BC07FFD4;
- 00AF : BE190058;
- 00B0 : 30800001;
- 00B1 : E8790100;
- 00B2 : 44849C00;
- 00B3 : 84641800;
- 00B4 : BC030044;
- 00B5 : E8790104;
- 00B6 : 84641800;
- 00B7 : BC23FFA4;
- 00B8 : E8D70000;
- 00B9 : 99FC3800;
- 00BA : 10BB0000;
- 00BB : B810FFA4;
- [00BC..00BD] : 3273FFFF;
- 00BE : AA53FFFF;
- 00BF : BE12FF5C;
- 00C0 : 3273FFFF;
- 00C1 : AA53FFFF;
- 00C2 : BE32FFF0;
- 00C3 : 3273FFFF;
- 00C4 : B800FF48;
- 00C5 : 99FC3800;
- 00C6 : 3273FFFF;
- 00C7 : B810FF78;
- 00C8 : 32F7FFFC;
- 00C9 : FA780004;
- 00CA : B800FF90;
- 00CB : E8780004;
- 00CC : E8F60000;
- 00CD : 3063FFFF;
- 00CE : 16439800;
- 00CF : BC120054;
- 00D0 : F8160000;
- 00D1 : BC07FF00;
- 00D2 : BC190038;
- 00D3 : 30800001;
- 00D4 : E8790100;
- 00D5 : 44849C00;
- 00D6 : 84641800;
- 00D7 : BC030024;
- 00D8 : E8790104;
- 00D9 : 84641800;
- 00DA : BC230030;
- 00DB : E8D70000;
- 00DC : 99FC3800;
- 00DD : 10BB0000;
- 00DE : B810FED0;
- 00DF : 3273FFFF;
- 00E0 : 99FC3800;
- 00E1 : 3273FFFF;
- 00E2 : B810FEC4;
- 00E3 : 32F7FFFC;
- 00E4 : FA780004;
- 00E5 : B800FFB0;
- 00E6 : E8B70000;
- 00E7 : 99FC3800;
- 00E8 : 3273FFFF;
- 00E9 : B810FEA8;
- 00EA : 32F7FFFC;
- 00EB : 000003CC;
- 00EC : 43000000;
- 00ED : 00000000;
- 00EE : 41000000;
- 00EF : 40000000;
- 00F0 : 40000004;
- 00F1 : 40000008;
- 00F2 : 000003CC;
- [00F3..00FA] : 00000000;
- 00FB : 000003B0;
- [00FC..1FFE] : 00000000;
-END;
aeMB/compiler/compile/ihex/out.mif
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB/compiler/compile/aemb.specs
===================================================================
--- aeMB/compiler/compile/aemb.specs (revision 17)
+++ aeMB/compiler/compile/aemb.specs (nonexistent)
@@ -1,178 +0,0 @@
-*asm:
-%{microblaze1} %(target_asm_spec) %(subtarget_asm_spec)
-
-*asm_debug:
-%{gstabs*:--gstabs}%{!gstabs*:%{g*:--gdwarf2}}
-
-*asm_final:
-
-
-*asm_options:
-%a %Y %{c:%W{o*}%{!o*:-o %w%b%O}}%{!c:-o %d%w%u%O}
-
-*invoke_as:
-%{!S:-o %|.s |
- as %(asm_options) %m.s %A }
-
-*cpp:
-%{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} %{mno-xl-soft-mul: -DHAVE_HW_MUL} %{mxl-multiply-high: -DHAVE_HW_MUL_HIGH} %{mno-xl-soft-div: -DHAVE_HW_DIV} %{mxl-barrel-shift: -DHAVE_HW_BSHIFT} %{mxl-pattern-compare: -DHAVE_HW_PCMP} %{mhard-float: -DHAVE_HW_FPU} %{mxl-float-convert: -DHAVE_HW_FPU_CONVERT} %{mxl-float-sqrt: -DHAVE_HW_FPU_SQRT}
-
-*cpp_options:
-%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w} %{f*} %{g*:%{!g0:%{!fno-working-directory:-fworking-directory}}} %{O*} %{undef} %{save-temps:-fpch-preprocess}
-
-*cpp_debug_options:
-%{d*}
-
-*cpp_unique_options:
-%{C|CC:%{!E:%eGCC does not support -C or -CC without -E}} %{!Q:-quiet} %{nostdinc*} %{C} %{CC} %{v} %{I*&F*} %{P} %I %{MD:-MD %{!o:%b.d}%{o*:%.d%*}} %{MMD:-MMD %{!o:%b.d}%{o*:%.d%*}} %{M} %{MM} %{MF*} %{MG} %{MP} %{MQ*} %{MT*} %{!E:%{!M:%{!MM:%{MD|MMD:%{o*:-MQ %*}}}}} %{remap} %{g3:-dD} %{H} %C %{D*&U*&A*} %{i*} %Z %i %{fmudflap:-D_MUDFLAP -include mf-runtime.h} %{fmudflapth:-D_MUDFLAP -D_MUDFLAPTH -include mf-runtime.h} %{E|M|MM:%W{o*}}
-
-*trad_capable_cpp:
-cc1 -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}
-
-*cc1:
- %{G*} %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} %{save-temps: } %(subtarget_cc1_spec) %{Zxl-blazeit: -mno-xl-soft-mul -mno-xl-soft-div -mxl-barrel-shift -mxl-pattern-compare -mxl-multiply-high}
-
-*cc1_options:
-%{pg:%{fomit-frame-pointer:%e-pg and -fomit-frame-pointer are incompatible}} %1 %{!Q:-quiet} -dumpbase %B %{d*} %{m*} %{a*} %{c|S:%{o*:-auxbase-strip %*}%{!o*:-auxbase %b}}%{!c:%{!S:-auxbase %b}} %{g*} %{O*} %{W*&pedantic*} %{w} %{std*&ansi&trigraphs} %{v:-version} %{pg:-p} %{p} %{f*} %{undef} %{Qn:-fno-ident} %{--help:--help} %{--target-help:--target-help} %{!fsyntax-only:%{S:%W{o*}%{!o*:-o %b.s}}} %{fsyntax-only:-o %j} %{-param*} %{fmudflap|fmudflapth:-fno-builtin -fno-merge-constants} %{coverage:-fprofile-arcs -ftest-coverage}
-
-*cc1plus:
-
-
-*link_gcc_c_sequence:
-%G %L %G
-
-*link_ssp:
-%{fstack-protector|fstack-protector-all:-lssp_nonshared -lssp}
-
-*endfile:
-crtend.o%s crtn.o%s
-
-*link:
-%{shared:-shared} -N -relax %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} %{!mxl-gp-opt: -G 0} %{!Wl,-T*: %{!T*: -T xilinx.ld%s}}
-
-*lib:
-%{!pg:%{!nostdlib:%{!Zxl-no-libxil:-start-group -lxil -lc_m_bs -lm_m_bs -end-group }}} %{pg:%{!nostdlib:-start-group -lxilprofile -lxil -lc_m_bs -lm_m_bs -end-group }} %{Zxl-no-libxil: %{!nostdlib: -start-group -lc_m_bs -lm_m_bs -end-group }}
-
-*mfwrap:
- %{static: %{fmudflap|fmudflapth: --wrap=malloc --wrap=free --wrap=calloc --wrap=realloc --wrap=mmap --wrap=munmap --wrap=alloca} %{fmudflapth: --wrap=pthread_create}} %{fmudflap|fmudflapth: --wrap=main}
-
-*mflib:
-%{fmudflap|fmudflapth: -export-dynamic}
-
-*libgcc:
--lgcc
-
-*startfile:
-%{Zxl-mode-executable : %(startfile_executable) ; Zxl-mode-xmdstub : %(startfile_xmdstub) ; Zxl-mode-bootstrap : %(startfile_bootstrap) ; Zxl-mode-novectors : %(startfile_novectors) ; Zxl-mode-xilkernel : %(startfile_xilkernel) ; : %(startfile_default) } %(startfile_crtinit)
-
-*switches_need_spaces:
-
-
-*cross_compile:
-1
-
-*version:
-4.1.1
-
-*multilib:
-. !mxl-barrel-shift !mno-xl-soft-mul !mxl-multiply-high;bs mxl-barrel-shift !mno-xl-soft-mul !mxl-multiply-high;m !mxl-barrel-shift mno-xl-soft-mul !mxl-multiply-high;m/mh !mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high;bs/m mxl-barrel-shift mno-xl-soft-mul !mxl-multiply-high;bs/m/mh mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high;
-
-*multilib_defaults:
-
-
-*multilib_extra:
-
-
-*multilib_matches:
-mxl-barrel-shift mxl-barrel-shift;mno-xl-soft-mul mno-xl-soft-mul;mxl-multiply-high mxl-multiply-high;
-
-*multilib_exclusions:
-
-
-*multilib_options:
-mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high
-
-*linker:
-collect2
-
-*link_libgcc:
-%D
-
-*md_exec_prefix:
-
-
-*md_startfile_prefix:
-
-
-*md_startfile_prefix_1:
-
-
-*startfile_prefix_spec:
-
-
-*sysroot_spec:
---sysroot=%R
-
-*sysroot_suffix_spec:
-
-
-*sysroot_hdrs_suffix_spec:
-
-
-*subtarget_cc1_spec:
-
-
-*subtarget_cpp_spec:
-
-
-*subtarget_cpp_size_spec:
--D__SIZE_TYPE__=unsigned\ int -D__PTRDIFF_TYPE__=int
-
-*microblaze_as_asm_spec:
-%{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} %{pipe: %e-pipe is not supported.} %{K} %(subtarget_microblaze_as_asm_spec)
-
-*gas_asm_spec:
-%{v}
-
-*target_asm_spec:
-
-
-*subtarget_microblaze_as_asm_spec:
-%{v}
-
-*subtarget_asm_optimizing_spec:
-
-
-*subtarget_asm_debugging_spec:
-%{g} %{g0} %{g1} %{g2} %{g3} %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3}
-
-*subtarget_asm_spec:
-
-
-*linker_endian_spec:
-
-
-*startfile_executable:
-crt0.o%s crti.o%s crtbegin.o%s
-
-*startfile_xmdstub:
-crt1.o%s crti.o%s crtbegin.o%s
-
-*startfile_bootstrap:
-crt2.o%s crti.o%s crtbegin.o%s
-
-*startfile_novectors:
-crt3.o%s crti.o%s crtbegin.o%s
-
-*startfile_xilkernel:
-crt4.o%s crti.o%s crtbegin.o%s
-
-*startfile_crtinit:
-%{!pg: %{!mno-clearbss: crtinit.o%s} %{mno-clearbss: sim-crtinit.o%s}} %{pg: %{!mno-clearbss: pgcrtinit.o%s} %{mno-clearbss: sim-pgcrtinit.o%s}}
-
-*startfile_default:
-crt0.o%s crti.o%s crtbegin.o%s
-
-*link_command:
-%{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S: %(linker) %l %{pie:-pie} %X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r} %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}} %{static:} %{L*} %(mfwrap) %(link_libgcc) %o %(mflib) %{fprofile-arcs|fprofile-generate|coverage:-lgcov} %{!nostdlib:%{!nodefaultlibs:%(link_ssp) %(link_gcc_c_sequence)}} %{!A:%{!nostdlib:%{!nostartfiles:%E}}} %{T*} }}}}}}
-
Index: aeMB/compiler/program_memories.sh
===================================================================
--- aeMB/compiler/program_memories.sh (revision 17)
+++ aeMB/compiler/program_memories.sh (nonexistent)
@@ -1,4 +0,0 @@
-#!/bin/sh
- cd program
- quartus_stp -t prog.tcl
- cd ..
aeMB/compiler/program_memories.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: aeMB/compiler/compile.sh
===================================================================
--- aeMB/compiler/compile.sh (revision 17)
+++ aeMB/compiler/compile.sh (nonexistent)
@@ -1,7 +0,0 @@
-#!/bin/sh
-
- cd compile
- ./gccrom ../main.c
- cp out/ram0.mif ../ram00.mif
- cd ..
-
aeMB/compiler/compile.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: lm32/verilog/src/lm32.v
===================================================================
--- lm32/verilog/src/lm32.v (revision 17)
+++ lm32/verilog/src/lm32.v (revision 19)
@@ -1,178 +1,178 @@
-
-`include "system_conf.v"
-`include "lm32_include.v"
-
-module lm32 #(
- parameter INTR_NUM=32,
- parameter CFG_PL_MULTIPLY= "ENABLED", //"ENABLED","DISABLED"
- parameter CFG_PL_BARREL_SHIFT= "ENABLED",
- parameter CFG_SIGN_EXTEND="ENABLED",
- parameter CFG_MC_DIVIDE="DISABLED"
-
-)(
- // ----- Inputs -------
- clk_i,
- rst_i,
- interrupt,
- // Instruction Wishbone master
- I_DAT_I,
- I_ACK_I,
- I_ERR_I,
- I_RTY_I,
- I_DAT_O,
- I_ADR_O,
- I_CYC_O,
- I_SEL_O,
- I_STB_O,
- I_WE_O,
- I_CTI_O,
- //I_LOCK_O,
- I_BTE_O,
-
- // Data Wishbone master
- D_DAT_I,
- D_ACK_I,
- D_ERR_I,
- D_RTY_I,
- D_DAT_O,
- D_ADR_O,
- D_CYC_O,
- D_SEL_O,
- D_STB_O,
- D_WE_O,
- D_CTI_O,
- //D_LOCK_O,
- D_BTE_O
-
-);
-
-
-
-input clk_i; // Clock
-input rst_i; // Reset
-
-//`ifdef CFG_INTERRUPTS_ENABLED
-input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
-//`endif
-
-`ifdef CFG_USER_ENABLED
-input [`LM32_WORD_RNG] user_result; // User-defined instruction result
-input user_complete; // Indicates the user-defined instruction result is valid
-`endif
-
-`ifdef CFG_IWB_ENABLED
-input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
-input I_ACK_I; // Instruction Wishbone interface acknowledgement
-input I_ERR_I; // Instruction Wishbone interface error
-input I_RTY_I; // Instruction Wishbone interface retry
-`endif
-
-
-
-`ifdef CFG_USER_ENABLED
-output user_valid; // Indicates that user_opcode and user_operand_* are valid
-wire user_valid;
-output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
-reg [`LM32_USER_OPCODE_RNG] user_opcode;
-output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
-wire [`LM32_WORD_RNG] user_operand_0;
-output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
-wire [`LM32_WORD_RNG] user_operand_1;
-`endif
-
-
-
-
-
-`ifdef CFG_IWB_ENABLED
-output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
-wire [`LM32_WORD_RNG] I_DAT_O;
-output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
-wire [`LM32_WORD_RNG] I_ADR_O;
-output I_CYC_O; // Instruction Wishbone interface cycle
-wire I_CYC_O;
-output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
-wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
-output I_STB_O; // Instruction Wishbone interface strobe
-wire I_STB_O;
-output I_WE_O; // Instruction Wishbone interface write enable
-wire I_WE_O;
-output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
-wire [`LM32_CTYPE_RNG] I_CTI_O;
-//output I_LOCK_O; // Instruction Wishbone interface lock bus
-//wire I_LOCK_O;
-output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
-wire [`LM32_BTYPE_RNG] I_BTE_O;
-`endif
-
-
-input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
-input D_ACK_I; // Data Wishbone interface acknowledgement
-input D_ERR_I; // Data Wishbone interface error
-input D_RTY_I; // Data Wishbone interface retry
-
-
-output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
-wire [`LM32_WORD_RNG] D_DAT_O;
-output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
-wire [`LM32_WORD_RNG] D_ADR_O;
-output D_CYC_O; // Data Wishbone interface cycle
-wire D_CYC_O;
-output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
-wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
-output D_STB_O; // Data Wishbone interface strobe
-wire D_STB_O;
-output D_WE_O; // Data Wishbone interface write enable
-wire D_WE_O;
-output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
-wire [`LM32_CTYPE_RNG] D_CTI_O;
-//output D_LOCK_O; // Date Wishbone interface lock bus
-//wire D_LOCK_O;
-output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
-wire [`LM32_BTYPE_RNG] D_BTE_O;
-
-
-wire [31:0] iadr_o,dadr_o;
-
-lm32_top the_lm32_top(
- .clk_i(clk_i),
- .rst_i(rst_i),
- .interrupt_n(~interrupt),
- .I_DAT_I(I_DAT_I),
- .I_ACK_I(I_ACK_I),
- .I_ERR_I(I_ERR_I),
- .I_RTY_I(I_RTY_I),
- .D_DAT_I(D_DAT_I),
- .D_ACK_I(D_ACK_I),
- .D_ERR_I(D_ERR_I),
- .D_RTY_I(D_RTY_I),
- .I_DAT_O(I_DAT_O),
- .I_ADR_O(iadr_o),
- .I_CYC_O(I_CYC_O),
- .I_SEL_O(I_SEL_O),
- .I_STB_O(I_STB_O),
- .I_WE_O(I_WE_O),
- .I_CTI_O(I_CTI_O),
- .I_LOCK_O(),
- .I_BTE_O(I_BTE_O),
- .D_DAT_O(D_DAT_O),
- .D_ADR_O(dadr_o),
- .D_CYC_O(D_CYC_O),
- .D_SEL_O(D_SEL_O),
- .D_STB_O(D_STB_O),
- .D_WE_O(D_WE_O),
- .D_CTI_O(D_CTI_O),
- .D_LOCK_O(),
- .D_BTE_O(D_BTE_O)
-);
-
- assign D_ADR_O= {2'b00,dadr_o[31:2]};
- assign I_ADR_O= {2'b00,iadr_o[31:2]};
- // assign iwb_dat_o = 0;
- // assign iwb_tag_o = 3'b000; // clasic wishbone without burst
- // assign dwb_tag_o = 3'b000; // clasic wishbone without burst
- // assign iwb_adr_o[31:30] = 2'b00;
- // assign dwb_adr_o[31:30] = 2'b00;
-
-endmodule
-
+
+`include "system_conf.v"
+`include "lm32_include.v"
+
+module lm32 #(
+ parameter INTR_NUM=32,
+ parameter CFG_PL_MULTIPLY= "ENABLED", //"ENABLED","DISABLED"
+ parameter CFG_PL_BARREL_SHIFT= "ENABLED",
+ parameter CFG_SIGN_EXTEND="ENABLED",
+ parameter CFG_MC_DIVIDE="DISABLED"
+
+)(
+ // ----- Inputs -------
+ clk_i,
+ rst_i,
+ interrupt,
+ // Instruction Wishbone master
+ I_DAT_I,
+ I_ACK_I,
+ I_ERR_I,
+ I_RTY_I,
+ I_DAT_O,
+ I_ADR_O,
+ I_CYC_O,
+ I_SEL_O,
+ I_STB_O,
+ I_WE_O,
+ I_CTI_O,
+ //I_LOCK_O,
+ I_BTE_O,
+
+ // Data Wishbone master
+ D_DAT_I,
+ D_ACK_I,
+ D_ERR_I,
+ D_RTY_I,
+ D_DAT_O,
+ D_ADR_O,
+ D_CYC_O,
+ D_SEL_O,
+ D_STB_O,
+ D_WE_O,
+ D_CTI_O,
+ //D_LOCK_O,
+ D_BTE_O
+
+);
+
+
+
+input clk_i; // Clock
+input rst_i; // Reset
+
+//`ifdef CFG_INTERRUPTS_ENABLED
+input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
+//`endif
+
+`ifdef CFG_USER_ENABLED
+input [`LM32_WORD_RNG] user_result; // User-defined instruction result
+input user_complete; // Indicates the user-defined instruction result is valid
+`endif
+
+`ifdef CFG_IWB_ENABLED
+input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
+input I_ACK_I; // Instruction Wishbone interface acknowledgement
+input I_ERR_I; // Instruction Wishbone interface error
+input I_RTY_I; // Instruction Wishbone interface retry
+`endif
+
+
+
+`ifdef CFG_USER_ENABLED
+output user_valid; // Indicates that user_opcode and user_operand_* are valid
+wire user_valid;
+output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
+reg [`LM32_USER_OPCODE_RNG] user_opcode;
+output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
+wire [`LM32_WORD_RNG] user_operand_0;
+output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
+wire [`LM32_WORD_RNG] user_operand_1;
+`endif
+
+
+
+
+
+`ifdef CFG_IWB_ENABLED
+output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
+wire [`LM32_WORD_RNG] I_DAT_O;
+output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
+wire [`LM32_WORD_RNG] I_ADR_O;
+output I_CYC_O; // Instruction Wishbone interface cycle
+wire I_CYC_O;
+output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
+wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
+output I_STB_O; // Instruction Wishbone interface strobe
+wire I_STB_O;
+output I_WE_O; // Instruction Wishbone interface write enable
+wire I_WE_O;
+output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] I_CTI_O;
+//output I_LOCK_O; // Instruction Wishbone interface lock bus
+//wire I_LOCK_O;
+output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] I_BTE_O;
+`endif
+
+
+input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
+input D_ACK_I; // Data Wishbone interface acknowledgement
+input D_ERR_I; // Data Wishbone interface error
+input D_RTY_I; // Data Wishbone interface retry
+
+
+output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
+wire [`LM32_WORD_RNG] D_DAT_O;
+output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
+wire [`LM32_WORD_RNG] D_ADR_O;
+output D_CYC_O; // Data Wishbone interface cycle
+wire D_CYC_O;
+output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
+wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
+output D_STB_O; // Data Wishbone interface strobe
+wire D_STB_O;
+output D_WE_O; // Data Wishbone interface write enable
+wire D_WE_O;
+output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
+wire [`LM32_CTYPE_RNG] D_CTI_O;
+//output D_LOCK_O; // Date Wishbone interface lock bus
+//wire D_LOCK_O;
+output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
+wire [`LM32_BTYPE_RNG] D_BTE_O;
+
+
+wire [31:0] iadr_o,dadr_o;
+
+lm32_top the_lm32_top(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+ .interrupt_n(~interrupt),
+ .I_DAT_I(I_DAT_I),
+ .I_ACK_I(I_ACK_I),
+ .I_ERR_I(I_ERR_I),
+ .I_RTY_I(I_RTY_I),
+ .D_DAT_I(D_DAT_I),
+ .D_ACK_I(D_ACK_I),
+ .D_ERR_I(D_ERR_I),
+ .D_RTY_I(D_RTY_I),
+ .I_DAT_O(I_DAT_O),
+ .I_ADR_O(iadr_o),
+ .I_CYC_O(I_CYC_O),
+ .I_SEL_O(I_SEL_O),
+ .I_STB_O(I_STB_O),
+ .I_WE_O(I_WE_O),
+ .I_CTI_O(I_CTI_O),
+ .I_LOCK_O(),
+ .I_BTE_O(I_BTE_O),
+ .D_DAT_O(D_DAT_O),
+ .D_ADR_O(dadr_o),
+ .D_CYC_O(D_CYC_O),
+ .D_SEL_O(D_SEL_O),
+ .D_STB_O(D_STB_O),
+ .D_WE_O(D_WE_O),
+ .D_CTI_O(D_CTI_O),
+ .D_LOCK_O(),
+ .D_BTE_O(D_BTE_O)
+);
+
+ assign D_ADR_O= {2'b00,dadr_o[31:2]};
+ assign I_ADR_O= {2'b00,iadr_o[31:2]};
+ // assign iwb_dat_o = 0;
+ // assign iwb_tag_o = 3'b000; // clasic wishbone without burst
+ // assign dwb_tag_o = 3'b000; // clasic wishbone without burst
+ // assign iwb_adr_o[31:30] = 2'b00;
+ // assign dwb_adr_o[31:30] = 2'b00;
+
+endmodule
+
Index: lm32/verilog/src/lm32_interrupt.v
===================================================================
--- lm32/verilog/src/lm32_interrupt.v (revision 17)
+++ lm32/verilog/src/lm32_interrupt.v (revision 19)
@@ -20,7 +20,7 @@
// Dependencies : lm32_include.v
// Version : 6.1.17
// =============================================================================
-
+
`include "system_conf.v"
`include "lm32_include.v"
@@ -138,7 +138,7 @@
// };
wire ip_csr_read_data = ip;
wire im_csr_read_data = im;
-// XXX JB XXX
+// XXX JB XXX
// generate
// if (interrupts > 1)
// begin
@@ -160,7 +160,7 @@
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
-// XXX JB XXX
+// XXX JB XXX
// end
// else
// begin
@@ -188,7 +188,7 @@
// Sequential Logic
/////////////////////////////////////////////////////
-// XXX JB XXX
+// XXX JB XXX
//generate
// if (interrupts > 1)
// begin
/lm32/verilog/src/lm32_dp_ram.v
1,41 → 1,41
module lm32_dp_ram( |
clk_i, |
rst_i, |
we_i, |
waddr_i, |
wdata_i, |
raddr_i, |
rdata_o); |
|
parameter addr_width = 32; |
parameter addr_depth = 1024; |
parameter data_width = 8; |
|
input clk_i; |
input rst_i; |
input we_i; |
input [addr_width-1:0] waddr_i; |
input [data_width-1:0] wdata_i; |
input [addr_width-1:0] raddr_i; |
output [data_width-1:0] rdata_o; |
|
reg [data_width-1:0] ram[addr_depth-1:0]; |
|
reg [addr_width-1:0] raddr_r; |
assign rdata_o = ram[raddr_r]; |
|
integer i; |
initial begin |
for (i=0;i<addr_depth-1;i=i+1) |
ram[i] = 0; |
end |
|
always @ (posedge clk_i) |
begin |
if (we_i) |
ram[waddr_i] <= wdata_i; |
raddr_r <= raddr_i; |
end |
|
endmodule |
|
module lm32_dp_ram( |
clk_i, |
rst_i, |
we_i, |
waddr_i, |
wdata_i, |
raddr_i, |
rdata_o); |
|
parameter addr_width = 32; |
parameter addr_depth = 1024; |
parameter data_width = 8; |
|
input clk_i; |
input rst_i; |
input we_i; |
input [addr_width-1:0] waddr_i; |
input [data_width-1:0] wdata_i; |
input [addr_width-1:0] raddr_i; |
output [data_width-1:0] rdata_o; |
|
reg [data_width-1:0] ram[addr_depth-1:0]; |
|
reg [addr_width-1:0] raddr_r; |
assign rdata_o = ram[raddr_r]; |
|
integer i; |
initial begin |
for (i=0;i<addr_depth-1;i=i+1) |
ram[i] = 0; |
end |
|
always @ (posedge clk_i) |
begin |
if (we_i) |
ram[waddr_i] <= wdata_i; |
raddr_r <= raddr_i; |
end |
|
endmodule |
|