URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
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- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/mpsoc/src_peripheral/ram/Altera_single_port_ram.v
33,9 → 33,11
|
module Altera_single_port_ram #( |
parameter Dw =32, |
parameter Aw =10, |
parameter Aw =10, |
parameter TAGw =3, |
parameter SELw =4, |
parameter CTIw = 3, |
parameter BTEw = 2, |
parameter RAM_TAG_STRING="2" //use for programming the memory at run time |
|
) |
48,6 → 50,8
sa_sel_i, |
sa_addr_i, |
sa_tag_i, |
sa_cti_i, |
sa_bte_i, |
sa_stb_i, |
sa_cyc_i, |
sa_we_i, |
70,6 → 74,8
input sa_stb_i; |
input sa_cyc_i; |
input sa_we_i; |
input [CTIw-1 : 0] sa_cti_i; |
input [BTEw-1 : 0] sa_bte_i; |
|
output [Dw-1 : 0] sa_dat_o; |
output sa_ack_o; |
81,25 → 87,24
|
wire [TAGw-1 : 0] sa_cti_i; |
|
assign sa_cti_i = sa_tag_i; |
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|
|
wire [Dw-1 : 0] data_a; |
wire [Aw-1 : 0] addr_a; |
wire we_a; |
wire [(Dw-1) : 0] q_a; |
reg sa_ack_classic, sa_ack_classic_next; |
wire sa_ack_burst; |
wire sa_ack_ni_burst; |
|
assign sa_dat_o = q_a; |
assign data_a = sa_dat_i ; |
assign addr_a = sa_addr_i; |
assign we_a = sa_stb_i & sa_we_i; |
assign sa_ack_burst = sa_stb_i ; //the ack is registerd inside the master in burst mode |
assign sa_ack_ni_burst = sa_stb_i ; //the ack is registerd inside the master in burst mode |
assign sa_err_o = 1'b0; |
assign sa_rty_o = 1'b0; |
|
assign sa_ack_o = (sa_cti_i == 3'b000 ) ? sa_ack_classic : sa_ack_burst; |
// 3'b100 is reserved in wb4 interface. It used for ni |
assign sa_ack_o = (sa_cti_i == 3'b100 ) ? sa_ack_ni_burst: sa_ack_classic; |
|
|
always @(*) begin |
/mpsoc/src_peripheral/ni/ni.v
114,7 → 114,7
s_dat_i, |
s_sel_i, |
s_addr_i, |
s_tag_i, |
s_cti_i, |
s_stb_i, |
s_cyc_i, |
s_we_i, |
129,7 → 129,7
m_sel_o, |
m_dat_o, |
m_addr_o, |
m_tag_o, |
m_cti_o, |
m_stb_o, |
m_cyc_o, |
m_we_o, |
252,7 → 252,7
input [Dw-1 : 0] s_dat_i; |
input [SELw-1 : 0] s_sel_i; |
input [S_Aw-1 : 0] s_addr_i; |
input [TAGw-1 : 0] s_tag_i; |
input [TAGw-1 : 0] s_cti_i; |
input s_stb_i; |
input s_cyc_i; |
input s_we_i; |
267,7 → 267,7
output [SELw-1 : 0] m_sel_o; |
output [Dw-1 : 0] m_dat_o; |
output [M_Aw-1 : 0] m_addr_o; |
output [TAGw-1 : 0] m_tag_o; |
output [TAGw-1 : 0] m_cti_o; |
output m_stb_o; |
output m_cyc_o; |
output m_we_o; |
360,7 → 360,8
assign m_waitrequest = ~m_ack_i_delayed ; //in busrt mode the ack is regisered inside the ni insted of ram to avoid combinational loop |
assign m_cyc_o = m_we_o | m_read; |
assign s_ack_o_next = s_stb_i & (~s_ack_o); |
assign m_tag_o = (m_stb_o) ? ((last_rw)? 3'b111 : 3'b010) : 3'b000; |
// assign m_cti_o = (m_stb_o) ? ((last_rw)? 3'b111 : 3'b100) : 3'b000; |
assign m_cti_o = (m_stb_o) ? 3'b100 : 3'b000; |
|
assign irq = (rsv_pck_isr & rsv_pck_int_en) | (rd_done_isr & rd_done_int_en) | (wr_done_isr & wr_done_int_en); |
|
/mpsoc/src_peripheral/bus/wishbone_bus.v
33,12 → 33,14
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module wishbone_bus #( |
|
parameter M = 4, //number of master port |
parameter S = 4, //number of slave port |
parameter Dw = 32, // maximum data width |
parameter Aw = 32, // address width |
parameter SELw = 2, |
parameter TAGw = 3 //merged {tga,tgb,tgc} |
parameter M = 4, //number of master port |
parameter S = 4, //number of slave port |
parameter Dw = 32, // maximum data width |
parameter Aw = 32, // address width |
parameter SELw = 2, |
parameter TAGw = 3, //merged {tga,tgb,tgc} |
parameter CTIw = 3, |
parameter BTEw = 2 |
|
|
) |
51,12 → 53,14
s_we_o_all, |
s_cyc_o_all, |
s_stb_o_all, |
s_cti_o_all, |
s_bte_o_all, |
|
s_dat_i_all, |
s_ack_i_all, |
s_err_i_all, |
s_rty_i_all, |
|
|
|
//masters interface |
m_dat_o_all, |
72,6 → 76,8
m_we_i_all, |
m_stb_i_all, |
m_cyc_i_all, |
m_cti_i_all, |
m_bte_i_all, |
|
//address compar |
m_grant_addr, |
100,12 → 106,16
AwS = Aw * S, |
SELwS = SELw * S, |
TAGwS = TAGw * S, |
CTIwS = CTIw * S, |
BTEwS = BTEw * S, |
DwM = Dw * M, |
AwM = Aw * M, |
SELwM = SELw * M, |
TAGwM = TAGw * M, |
Mw = (M>1)? log2(M):1, |
Sw = (S>1)? log2(S):1; |
Sw = (S>1)? log2(S):1, |
CTIwM = CTIw * M, |
BTEwM = BTEw * M; |
|
|
|
118,6 → 128,8
output [S-1 : 0] s_we_o_all; |
output [S-1 : 0] s_cyc_o_all; |
output [S-1 : 0] s_stb_o_all; |
output [CTIwS-1 : 0] s_cti_o_all; |
output [BTEwS-1 : 0] s_bte_o_all; |
|
|
input [DwS-1 : 0] s_dat_i_all; |
124,15 → 136,18
input [S-1 : 0] s_ack_i_all; |
input [S-1 : 0] s_err_i_all; |
input [S-1 : 0] s_rty_i_all; |
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//masters interface |
output [DwM-1 : 0] m_dat_o_all; |
output [M-1 : 0] m_ack_o_all; |
output [M-1 : 0] m_err_o_all; |
output [M-1 : 0] m_rty_o_all; |
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input [AwM-1 : 0] m_adr_i_all; |
input [DwM-1 : 0] m_dat_i_all; |
input [SELwM-1 : 0] m_sel_i_all; |
140,6 → 155,8
input [M-1 : 0] m_we_i_all; |
input [M-1 : 0] m_stb_i_all; |
input [M-1 : 0] m_cyc_i_all; |
input [CTIwM-1 : 0] m_cti_i_all; |
input [BTEwM-1 : 0] m_bte_i_all; |
|
// |
output [Aw-1 : 0] m_grant_addr; |
154,6 → 171,8
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wire [Dw-1 : 0] m_grant_dat,s_read_dat; |
wire [SELw-1 : 0] m_grant_sel; |
wire [BTEw-1 : 0] m_grant_bte; |
wire [CTIw-1 : 0] m_grant_cti; |
wire [TAGw-1 : 0] m_grant_tag; |
|
|
164,6 → 183,9
wire [Aw-1 : 0] s_adr_o; |
wire [Dw-1 : 0] s_dat_o; |
wire [SELw-1 : 0] s_sel_o; |
wire [BTEw-1 : 0] s_bte_o; |
wire [CTIw-1 : 0] s_cti_o; |
|
wire [TAGw-1 : 0] s_tag_o; |
wire s_we_o; |
wire s_cyc_o; |
173,6 → 195,9
assign s_adr_o_all = {S{s_adr_o}}; |
assign s_dat_o_all = {S{s_dat_o}}; |
assign s_sel_o_all = {S{s_sel_o}}; |
assign s_cti_o_all = {S{s_cti_o}}; |
assign s_bte_o_all = {S{s_bte_o}}; |
|
assign s_tag_o_all = {S{s_tag_o}}; |
assign s_we_o_all = {S{s_we_o}}; |
assign s_cyc_o_all = {S{s_cyc_o}}; |
185,6 → 210,8
assign s_adr_o = m_grant_addr; |
assign s_dat_o = m_grant_dat; |
assign s_sel_o = m_grant_sel; |
assign s_bte_o = m_grant_bte; |
assign s_cti_o = m_grant_cti; |
assign s_tag_o = m_grant_tag; |
assign s_we_o = m_grant_we; |
assign s_cyc_o = m_grant_cyc; |
282,9 → 309,32
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); |
|
binary_mux #( |
.IN_WIDTH (BTEwM), |
.OUT_WIDTH (BTEw) |
) |
m_bte_mux |
( |
.mux_in (m_bte_i_all), |
.mux_out (m_grant_bte), |
.sel (m_grant_bin) |
|
); |
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binary_mux #( |
.IN_WIDTH (CTIwM), |
.OUT_WIDTH (CTIw) |
) |
m_cti_mux |
( |
.mux_in (m_cti_i_all), |
.mux_out (m_grant_cti), |
.sel (m_grant_bin) |
|
); |
|
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binary_mux #( |
.IN_WIDTH (TAGwM), |
.OUT_WIDTH (TAGw) |
) |
336,6 → 386,10
.sel (m_grant_bin) |
|
); |
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generate |
if(M > 1) begin |
/mpsoc/src_noc/credit_count.v
170,7 → 170,7
inport_module #( |
.V (V), // vc_num_per_port |
.P (P) // router port num |
)inport_module |
)the_inport_module |
( |
.flit_is_tail (flit_is_tail_all [(i+1)*V-1 :i*V]), |
.assigned_ovc_num (assigned_ovc_num_all [(i+1)*VV-1 :i*VV]), |
/mpsoc/src_noc/flit_buffer.v
1,53 → 1,53
`timescale 1ns/1ps |
`timescale 1ns/1ps |
|
module flit_buffer #( |
parameter V = 4, |
parameter P = 5, |
parameter B = 4, // buffer space :flit per VC |
parameter Fpay = 32, |
parameter DEBUG_EN = 1 |
) |
( |
din, // Data in |
vc_num_wr,//write vertual channel |
vc_num_rd,//read vertual channel |
wr_en, // Write enable |
rd_en, // Read the next word |
dout, // Data out |
vc_not_empty, |
reset, |
clk |
); |
parameter V = 4, |
parameter P = 5, |
parameter B = 4, // buffer space :flit per VC |
parameter Fpay = 32, |
parameter DEBUG_EN = 1 |
) |
( |
din, // Data in |
vc_num_wr,//write vertual channel |
vc_num_rd,//read vertual channel |
wr_en, // Write enable |
rd_en, // Read the next word |
dout, // Data out |
vc_not_empty, |
reset, |
clk |
); |
|
function integer log2; |
input integer number; begin |
log2=0; |
while(2**log2<number) begin |
log2=log2+1; |
end |
end |
function integer log2; |
input integer number; begin |
log2=0; |
while(2**log2<number) begin |
log2=log2+1; |
end |
end |
endfunction // log2 |
|
localparam Fw = 2+V+Fpay, //flit width |
BV = B * V; |
|
|
input [Fw-1 :0] din; // Data in |
input [V-1 :0] vc_num_wr;//write vertual channel |
input [V-1 :0] vc_num_rd;//read vertual channel |
input wr_en; // Write enable |
input rd_en; // Read the next word |
output [Fw-1 :0] dout; // Data out |
output [V-1 :0] vc_not_empty; |
input reset; |
input clk; |
|
|
localparam BVw = log2(BV), |
Bw = log2(B), |
DEPTHw = Bw+1, |
BwV = Bw * V, |
BVw_Bw = BVw-Bw, |
|
localparam Fw = 2+V+Fpay, //flit width |
BV = B * V; |
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|
input [Fw-1 :0] din; // Data in |
input [V-1 :0] vc_num_wr;//write vertual channel |
input [V-1 :0] vc_num_rd;//read vertual channel |
input wr_en; // Write enable |
input rd_en; // Read the next word |
output [Fw-1 :0] dout; // Data out |
output [V-1 :0] vc_not_empty; |
input reset; |
input clk; |
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|
localparam BVw = log2(BV), |
Bw = (B==1)? 1 : log2(B), |
Vw = (V==1)? 1 : log2(V), |
DEPTHw = Bw+1, |
BwV = Bw * V, |
BVwV = BVw * V, |
RAM_DATA_WIDTH = Fw - V; |
|
64,85 → 64,85
assign dout = {fifo_ram_dout[Fpay+1:Fpay],{V{1'bX}},fifo_ram_dout[Fpay-1 : 0]}; |
assign wr = (wr_en)? vc_num_wr : {V{1'b0}}; |
assign rd = (rd_en)? vc_num_rd : {V{1'b0}}; |
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genvar i; |
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generate |
if((2**Bw)==B)begin :pow2 |
/***************** |
Buffer width is power of 2 |
******************/ |
reg [Bw- 1 : 0] rd_ptr [V-1 :0]; |
reg [Bw- 1 : 0] wr_ptr [V-1 :0]; |
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wire [BwV-1 : 0] rd_ptr_array; |
wire [BwV-1 : 0] wr_ptr_array; |
wire [Bw-1 : 0] vc_wr_addr; |
wire [Bw-1 : 0] vc_rd_addr; |
wire [BVw_Bw-1 : 0] wr_select_addr; |
wire [BVw_Bw-1 : 0] rd_select_addr; |
wire [BVw- 1 : 0] wr_addr; |
wire [BVw- 1 : 0] rd_addr; |
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assign wr_addr = {wr_select_addr,vc_wr_addr}; |
assign rd_addr = {rd_select_addr,vc_rd_addr}; |
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one_hot_mux #( |
.IN_WIDTH (BwV), |
.SEL_WIDTH (V) |
) |
wr_ptr_mux |
( |
.mux_in (wr_ptr_array), |
.mux_out (vc_wr_addr), |
.sel (vc_num_wr) |
); |
|
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one_hot_mux #( |
.IN_WIDTH (BwV), |
.SEL_WIDTH (V) |
) |
rd_ptr_mux |
( |
.mux_in (rd_ptr_array), |
.mux_out (vc_rd_addr), |
.sel (vc_num_rd) |
); |
|
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one_hot_to_bin #( |
.ONE_HOT_WIDTH (V) |
|
) |
wr_vc_start_addr |
( |
.one_hot_code (vc_num_wr), |
.bin_code (wr_select_addr) |
/***************** |
Buffer width is power of 2 |
******************/ |
reg [Bw- 1 : 0] rd_ptr [V-1 :0]; |
reg [Bw- 1 : 0] wr_ptr [V-1 :0]; |
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wire [BwV-1 : 0] rd_ptr_array; |
wire [BwV-1 : 0] wr_ptr_array; |
wire [Bw-1 : 0] vc_wr_addr; |
wire [Bw-1 : 0] vc_rd_addr; |
wire [Vw-1 : 0] wr_select_addr; |
wire [Vw-1 : 0] rd_select_addr; |
wire [Bw+Vw-1 : 0] wr_addr; |
wire [Bw+Vw-1 : 0] rd_addr; |
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assign wr_addr = {wr_select_addr,vc_wr_addr}; |
assign rd_addr = {rd_select_addr,vc_rd_addr}; |
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one_hot_mux #( |
.IN_WIDTH (BwV), |
.SEL_WIDTH (V) |
) |
wr_ptr_mux |
( |
.mux_in (wr_ptr_array), |
.mux_out (vc_wr_addr), |
.sel (vc_num_wr) |
); |
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one_hot_mux #( |
.IN_WIDTH (BwV), |
.SEL_WIDTH (V) |
) |
rd_ptr_mux |
( |
.mux_in (rd_ptr_array), |
.mux_out (vc_rd_addr), |
.sel (vc_num_rd) |
); |
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one_hot_to_bin #( |
.ONE_HOT_WIDTH (V) |
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) |
wr_vc_start_addr |
( |
.one_hot_code (vc_num_wr), |
.bin_code (wr_select_addr) |
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); |
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one_hot_to_bin #( |
.ONE_HOT_WIDTH (V) |
|
) |
rd_vc_start_addr |
( |
.one_hot_code (vc_num_rd), |
.bin_code (rd_select_addr) |
); |
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one_hot_to_bin #( |
.ONE_HOT_WIDTH (V) |
|
) |
rd_vc_start_addr |
( |
.one_hot_code (vc_num_rd), |
.bin_code (rd_select_addr) |
|
); |
); |
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fifo_ram #( |
.DATA_WIDTH (RAM_DATA_WIDTH), |
151,8 → 151,8
the_queue |
( |
.wr_data (fifo_ram_din), |
.wr_addr (wr_addr), |
.rd_addr (rd_addr), |
.wr_addr (wr_addr[BVw-1 : 0]), |
.rd_addr (rd_addr[BVw-1 : 0]), |
.wr_en (wr_en), |
.rd_en (rd_en), |
.clk (clk), |
159,60 → 159,60
.rd_data (fifo_ram_dout) |
); |
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for(i=0;i<V;i=i+1) begin :loop0 |
|
assign wr_ptr_array[(i+1)*Bw- 1 : i*Bw] = wr_ptr[i]; |
assign rd_ptr_array[(i+1)*Bw- 1 : i*Bw] = rd_ptr[i]; |
//assign vc_nearly_full[i] = (depth[i] >= B-1); |
assign vc_not_empty [i] = (depth[i] > 0); |
|
|
always @(posedge clk or posedge reset) |
begin |
if (reset) begin |
rd_ptr [i] <= {Bw{1'b0}}; |
wr_ptr [i] <= {Bw{1'b0}}; |
depth [i] <= {DEPTHw{1'b0}}; |
end |
else begin |
if (wr[i] ) wr_ptr[i] <= wr_ptr [i]+ 1'h1; |
if (rd[i] ) rd_ptr [i]<= rd_ptr [i]+ 1'h1; |
if (wr[i] & ~rd[i]) depth [i]<= |
//synthesis translate_off |
//synopsys translate_off |
#1 |
//synopsys translate_on |
// synthesis translate_on |
depth[i] + 1'h1; |
else if (~wr[i] & rd[i]) depth [i]<= |
// synthesis translate_off |
//synopsys translate_off |
#1 |
//synopsys translate_on |
// synthesis translate_on |
depth[i] - 1'h1; |
end//else |
end//always |
for(i=0;i<V;i=i+1) begin :loop0 |
|
assign wr_ptr_array[(i+1)*Bw- 1 : i*Bw] = wr_ptr[i]; |
assign rd_ptr_array[(i+1)*Bw- 1 : i*Bw] = rd_ptr[i]; |
//assign vc_nearly_full[i] = (depth[i] >= B-1); |
assign vc_not_empty [i] = (depth[i] > 0); |
|
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always @(posedge clk or posedge reset) |
begin |
if (reset) begin |
rd_ptr [i] <= {Bw{1'b0}}; |
wr_ptr [i] <= {Bw{1'b0}}; |
depth [i] <= {DEPTHw{1'b0}}; |
end |
else begin |
if (wr[i] ) wr_ptr[i] <= wr_ptr [i]+ 1'h1; |
if (rd[i] ) rd_ptr [i]<= rd_ptr [i]+ 1'h1; |
if (wr[i] & ~rd[i]) depth [i]<= |
//synthesis translate_off |
//synopsys translate_off |
#1 |
//synopsys translate_on |
// synthesis translate_on |
depth[i] + 1'h1; |
else if (~wr[i] & rd[i]) depth [i]<= |
// synthesis translate_off |
//synopsys translate_off |
#1 |
//synopsys translate_on |
// synthesis translate_on |
depth[i] - 1'h1; |
end//else |
end//always |
|
|
// synthesis translate_off |
//synopsys translate_off |
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always @(posedge clk) begin |
if (wr[i] && (depth[i] == B) && !rd[i]) |
$display("%t: ERROR: Attempt to write to full FIFO: %m",$time); |
if (rd[i] && (depth[i] == {DEPTHw{1'b0}} )) |
$display("%t: ERROR: Attempt to read an empty FIFO: %m",$time); |
|
//if (wr_en) $display($time, " %h is written on fifo ",din); |
end//always |
|
always @(posedge clk) begin |
if (wr[i] && (depth[i] == B) && !rd[i]) |
$display("%t: ERROR: Attempt to write to full FIFO: %m",$time); |
if (rd[i] && (depth[i] == {DEPTHw{1'b0}} )) |
$display("%t: ERROR: Attempt to read an empty FIFO: %m",$time); |
|
//if (wr_en) $display($time, " %h is written on fifo ",din); |
end//always |
//synopsys translate_on |
// synthesis translate_on |
end//for |
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|
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end else begin :no_pow2 //pow2 |
end//for |
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end else begin :no_pow2 //pow2 |
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|
|
225,17 → 225,17
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//pointers |
reg [BVw- 1 : 0] rd_ptr [V-1 :0]; |
|
//pointers |
reg [BVw- 1 : 0] rd_ptr [V-1 :0]; |
reg [BVw- 1 : 0] wr_ptr [V-1 :0]; |
|
// memory address |
wire [BVw- 1 : 0] wr_addr; |
|
// memory address |
wire [BVw- 1 : 0] wr_addr; |
wire [BVw- 1 : 0] rd_addr; |
|
//pointer array |
wire [BVwV- 1 : 0] wr_addr_all; |
|
//pointer array |
wire [BVwV- 1 : 0] wr_addr_all; |
wire [BVwV- 1 : 0] rd_addr_all; |
|
for(i=0;i<V;i=i+1) begin :loop0 |
257,17 → 257,17
if (rd[i] ) rd_ptr[i] <=(rd_ptr[i]==(B*(i+1))-1)? (B*i) : rd_ptr [i]+ 1'h1; |
if (wr[i] & ~rd[i]) depth [i]<= |
//synthesis translate_off |
//synopsys translate_off |
//synopsys translate_off |
#1 |
//synopsys translate_on |
//synopsys translate_on |
//synthesis translate_on |
depth[i] + 1'h1; |
else if (~wr[i] & rd[i]) depth [i]<= |
//synthesis translate_off |
//synopsys translate_off |
#1 |
//synopsys translate_off |
#1 |
//synthesis translate_on |
//synopsys translate_on |
//synopsys translate_on |
depth[i] - 1'h1; |
end//else |
end//always |
274,7 → 274,7
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//synthesis translate_off |
//synopsys translate_off |
//synopsys translate_off |
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always @(posedge clk) begin |
if (wr[i] && (depth[i] == B) && !rd[i]) |
284,32 → 284,32
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//if (wr_en) $display($time, " %h is written on fifo ",din); |
end//always |
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//synopsys translate_on |
//synthesis translate_on |
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//synopsys translate_on |
//synthesis translate_on |
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end//FOR |
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one_hot_mux #( |
.IN_WIDTH(BVwV), |
.SEL_WIDTH(V), |
.OUT_WIDTH(BVw) |
) |
wr_mux |
( |
.mux_in(wr_addr_all), |
.mux_out(wr_addr), |
.sel(vc_num_wr) |
); |
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one_hot_mux #( |
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one_hot_mux #( |
.IN_WIDTH(BVwV), |
.SEL_WIDTH(V), |
.OUT_WIDTH(BVw) |
) |
wr_mux |
( |
.mux_in(wr_addr_all), |
.mux_out(wr_addr), |
.sel(vc_num_wr) |
); |
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one_hot_mux #( |
.IN_WIDTH(BVwV), |
.SEL_WIDTH(V), |
.OUT_WIDTH(BVw) |
) |
rd_mux |
( |
.mux_in(rd_addr_all), |
316,8 → 316,8
.mux_out(rd_addr), |
.sel(vc_num_rd) |
); |
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fifo_ram_mem_size #( |
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fifo_ram_mem_size #( |
.DATA_WIDTH (RAM_DATA_WIDTH), |
.MEM_SIZE (BV ) |
) |
331,34 → 331,34
.clk (clk), |
.rd_data (fifo_ram_dout) |
); |
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end |
endgenerate |
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end |
endgenerate |
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//synthesis translate_off |
//synopsys translate_off |
generate |
if(DEBUG_EN) begin :dbg |
always @(posedge clk) begin |
if(wr_en && vc_num_wr == {V{1'b0}}) |
$display("%t: ERROR: Attempt to write when no wr VC is asserted: %m",$time); |
if(rd_en && vc_num_rd == {V{1'b0}}) |
$display("%t: ERROR: Attempt to read when no rd VC is asserted: %m",$time); |
end |
end |
endgenerate |
if(DEBUG_EN) begin :dbg |
always @(posedge clk) begin |
if(wr_en && vc_num_wr == {V{1'b0}}) |
$display("%t: ERROR: Attempt to write when no wr VC is asserted: %m",$time); |
if(rd_en && vc_num_rd == {V{1'b0}}) |
$display("%t: ERROR: Attempt to read when no rd VC is asserted: %m",$time); |
end |
end |
endgenerate |
//synopsys translate_on |
//synthesis translate_on |
//synthesis translate_on |
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endmodule |
|
371,36 → 371,36
*****************************/ |
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module fifo_ram #( |
parameter DATA_WIDTH = 32, |
parameter ADDR_WIDTH = 8 |
) |
( |
input [DATA_WIDTH-1 : 0] wr_data, |
input [ADDR_WIDTH-1 : 0] wr_addr, |
input [ADDR_WIDTH-1 : 0] rd_addr, |
input wr_en, |
input rd_en, |
input clk, |
output reg [DATA_WIDTH-1 : 0] rd_data |
); |
module fifo_ram #( |
parameter DATA_WIDTH = 32, |
parameter ADDR_WIDTH = 8 |
) |
( |
input [DATA_WIDTH-1 : 0] wr_data, |
input [ADDR_WIDTH-1 : 0] wr_addr, |
input [ADDR_WIDTH-1 : 0] rd_addr, |
input wr_en, |
input rd_en, |
input clk, |
output reg [DATA_WIDTH-1 : 0] rd_data |
); |
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reg [DATA_WIDTH-1:0] queue [2**ADDR_WIDTH-1:0] /* synthesis ramstyle = "no_rw_check , M9K" */; |
|
always @(posedge clk ) begin |
if (wr_en) |
queue[wr_addr] <= wr_data; |
if (rd_en) |
rd_data <= |
// synthesis translate_off |
#1 |
// synthesis translate_on |
queue[rd_addr]; |
end |
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reg [DATA_WIDTH-1:0] queue [2**ADDR_WIDTH-1:0] /* synthesis ramstyle = "no_rw_check , M9K" */; |
|
always @(posedge clk ) begin |
if (wr_en) |
queue[wr_addr] <= wr_data; |
if (rd_en) |
rd_data <= |
// synthesis translate_off |
#1 |
// synthesis translate_on |
queue[rd_addr]; |
end |
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endmodule |
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621,7 → 621,7
end//always |
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//synthesis translate_off |
//synopsys translate_off |
//synopsys translate_off |
always @(posedge clk) |
begin |
if (wr_en && ~rd_en && full) begin |
631,7 → 631,7
$display("%t ERROR: Attempt to read an empty FIFO: %m", $time); |
end |
end // always @ (posedge clk) |
//synopsys translate_on |
//synopsys translate_on |
//synthesis translate_on |
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748,53 → 748,3
//synthesis translate_on |
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endmodule // fifo |
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/mpsoc/src_noc/arbiter.v
29,8 → 29,12
input reset; |
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generate |
if(ARBITER_WIDTH<=4) begin: w4 |
if(ARBITER_WIDTH==1) begin: w1 |
assign grant= request; |
assign any_grant =request; |
end else if(ARBITER_WIDTH<=4) begin: w4 |
//my own arbiter |
my_one_hot_arbiter #( |
.ARBITER_WIDTH (ARBITER_WIDTH) |
/mpsoc/src_noc/traffic_gen.v
221,7 → 221,7
( |
.wr_in (ovc_wr_in), |
.credit_in (credit_in), |
.full_vc (full_vc), |
.nearly_full_vc (full_vc), |
.empty_vc (empty_vc), |
.cand_vc (cand_vc), |
.cand_wr_vc_en (cand_wr_vc_en), |