URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
- from Rev 29 to Rev 30
- ↔ Reverse comparison
Rev 29 → Rev 30
/mpsoc/perl_gui/lib/ip/Eth/ethmac_100.IP
3,7 → 3,7
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## This file is part of ProNoC 1.5.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
39,9 → 39,8
'/mpsoc/src_peripheral/ethmac/rtl/eth_wishbone.v', |
'/mpsoc/src_peripheral/ethmac/rtl/timescale.v', |
'/mpsoc/src_peripheral/ethmac/rtl/xilinx_dist_ram_16x32.v', |
'/mpsoc/src_peripheral/ram/general_single_port_ram.v', |
'/mpsoc/src_peripheral/ram/general_dual_port_ram.v', |
'/mpsoc/src_peripheral/ethmac/ethtop.v' |
'/mpsoc/src_peripheral/ethmac/ethtop.v', |
'/mpsoc/src_peripheral/ethmac/eth_generic_ram.v' |
], |
'custom_file' => { |
'0' => {} |
150,9 → 149,56
}, |
'category' => 'Eth', |
'sw_files' => [], |
'modules' => { |
'ethtop' => {} |
}, |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'0' => { |
'name' => 'wb_master' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_slave' => { |
'0' => { |
'width' => 11, |
'name' => 'wb_slave', |
'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
'status' => 'ideal', |
'timeout' => 0 |
}, |
'parameters' => { |
'RX_FIFO_DEPTH' => { |
160,8 → 206,8
'deafult' => ' 16', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'TX_FIFO_DATA_WIDTH' => { |
'info' => undef, |
168,8 → 214,8
'deafult' => ' 32', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'RX_FIFO_DATA_WIDTH' => { |
'info' => undef, |
176,8 → 222,8
'deafult' => ' 32', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'RX_FIFO_CNT_WIDTH' => { |
'info' => undef, |
184,8 → 230,8
'deafult' => ' 5', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'TX_FIFO_CNT_WIDTH' => { |
'info' => undef, |
192,8 → 238,8
'deafult' => ' 5', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'TX_FIFO_DEPTH' => { |
'info' => undef, |
200,267 → 246,220
'deafult' => ' 16', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
'redefine_param' => 1, |
'type' => 'Fixed' |
} |
}, |
'modules' => { |
'ethtop' => {} |
}, |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'value' => 1, |
'0' => { |
'name' => 'wb_master' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'width' => 11, |
'name' => 'wb_slave', |
'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller' |
}, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'ports' => { |
'wb_sel_i' => { |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'range' => '3:0', |
'type' => 'input' |
}, |
'm_wb_we_o' => { |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'we_o', |
'range' => '', |
'type' => 'output' |
}, |
'wb_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'wb_err_o' => { |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output' |
}, |
'wb_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'range' => '', |
'type' => 'input' |
}, |
'wb_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => '31:0', |
'type' => 'output' |
}, |
'wb_rst_i' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'input' |
}, |
'wb_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'type' => 'input' |
}, |
'm_wb_err_i' => { |
'intfc_port' => 'err_i', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'err_i', |
'range' => '', |
'type' => 'input' |
}, |
'm_wb_dat_i' => { |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'dat_i', |
'range' => '31:0', |
'type' => 'input' |
}, |
'mdc_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'm_wb_sel_o' => { |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'sel_o', |
'range' => '3:0', |
'type' => 'output' |
}, |
'md_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'mcrs_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'm_wb_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'dat_o', |
'range' => '31:0', |
'type' => 'output' |
}, |
'md_padoe_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'wb_adr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '9:0', |
'type' => 'input' |
}, |
'm_wb_adr_o' => { |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'adr_o', |
'range' => '31:0', |
'type' => 'output' |
}, |
'wb_adr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => '9:0', |
'type' => 'input' |
}, |
'mrxerr_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'mrxd_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '3:0', |
'type' => 'input' |
}, |
'mtxd_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '3:0', |
'type' => 'output' |
}, |
'wb_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'mtxen_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'mcoll_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'int_o' => { |
'intfc_port' => 'int_o', |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'intfc_port' => 'int_o', |
'range' => '', |
'type' => 'output' |
}, |
'm_wb_ack_i' => { |
'intfc_port' => 'ack_i', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'ack_i', |
'range' => '', |
'type' => 'input' |
}, |
'wb_stb_i' => { |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
}, |
'mrx_clk_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'wb_clk_i' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
'md_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'm_wb_cyc_o' => { |
'intfc_port' => 'cyc_o', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cyc_o', |
'range' => '', |
'type' => 'output' |
}, |
'mrxdv_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'mtxerr_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'mtx_clk_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'm_wb_stb_o' => { |
'intfc_port' => 'stb_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output' |
}, |
'wb_dat_i' => { |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'range' => '31:0', |
'type' => 'input' |
}, |
'm_wb_stb_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'stb_o', |
'range' => '', |
'type' => 'output' |
} |
} |
} |
}, 'ip_gen' ); |
/mpsoc/perl_gui/lib/ip/JTAG/jtag_wb.IP
3,7 → 3,7
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## This file is part of ProNoC 1.5.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
10,210 → 10,210
################################################################################ |
|
$vjtag_wb = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/jtag/jtag_wb' |
], |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'wbm' |
} |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'type' => 'num', |
'0' => { |
'name' => 'reset' |
} |
}, |
'clk' => { |
'type' => 'num', |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'clk' => {} |
} |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/jtag/jtag_wb/vjtag_wb.v', |
'parameters_order' => [ |
'DW', |
'AW', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'VJTAG_INDEX' |
], |
'modules' => { |
'vjtag_wb' => {}, |
'wb_if' => {}, |
'vjtag_ctrl' => {} |
}, |
'description' => 'A jtag to wishbone interface', |
'ip_name' => 'jtag_wb', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'module_name' => 'vjtag_wb', |
'parameters' => { |
'AW' => { |
'info' => 'Parameter', |
'deafult' => '32', |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'SELw' => { |
'info' => 'Parameter', |
'content' => '', |
'type' => 'Fixed', |
'deafult' => ' 4', |
'redefine_param' => 1, |
'global_param' => 'Localparam' |
}, |
'TAGw' => { |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'content' => '', |
'deafult' => ' 3', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'TAGw' => { |
'S_Aw' => { |
'global_param' => 'Localparam', |
'type' => 'Fixed', |
'deafult' => ' 7', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'deafult' => ' 3', |
'content' => '' |
}, |
'M_Aw' => { |
'global_param' => 'Localparam', |
'content' => '', |
'info' => 'Parameter', |
'redefine_param' => 1, |
'type' => 'Fixed', |
'redefine_param' => 1 |
'deafult' => ' 32' |
}, |
'VJTAG_INDEX' => { |
'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.', |
'deafult' => 'CORE_ID', |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Entry' |
}, |
'DW' => { |
'global_param' => 'Localparam', |
'deafult' => '32', |
'type' => 'Spin-button', |
'redefine_param' => 1, |
'info' => 'Parameter', |
'deafult' => '32', |
'content' => '4,1024,8' |
}, |
'AW' => { |
'global_param' => 'Localparam', |
'info' => 'Parameter', |
'content' => '', |
'type' => 'Fixed', |
'deafult' => '32', |
'redefine_param' => 1 |
}, |
'S_Aw' => { |
'info' => 'Parameter', |
'deafult' => ' 7', |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
}, |
'M_Aw' => { |
'info' => 'Parameter', |
'deafult' => ' 32', |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 1 |
} |
'VJTAG_INDEX' => { |
'content' => '', |
'info' => 'JTAG control host identifies each instance of this IP core by a unique index number. The default value is the tile ID number. You assign an index value between 0 to 255.', |
'redefine_param' => 1, |
'deafult' => 'CORE_ID', |
'type' => 'Entry', |
'global_param' => 'Localparam' |
} |
}, |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'0' => { |
'name' => 'wbm' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
} |
}, |
'modules' => { |
'wb_if' => {}, |
'vjtag_wb' => {}, |
'vjtag_ctrl' => {} |
}, |
'ports_order' => [ |
'clk', |
'reset', |
'm_sel_o', |
'm_dat_o', |
'm_addr_o', |
'm_cti_o', |
'm_stb_o', |
'm_cyc_o', |
'm_we_o', |
'm_dat_i', |
'm_ack_i', |
'status_i' |
], |
'ports' => { |
'm_we_o' => { |
'range' => '', |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[0]', |
'type' => 'output' |
}, |
'm_dat_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'range' => 'DW-1 : 0', |
'intfc_port' => 'dat_i', |
'range' => 'DW-1 : 0', |
'type' => 'input' |
'type' => 'input', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'm_sel_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'sel_o', |
'range' => 'SELw-1 : 0', |
'type' => 'output' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'range' => '', |
'intfc_name' => 'plug:clk[0]', |
'type' => 'input' |
}, |
'm_addr_o' => { |
'range' => 'M_Aw-1 : 0', |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'adr_o', |
'range' => 'M_Aw-1 : 0', |
'type' => 'output' |
}, |
'm_dat_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'dat_o', |
'range' => 'DW-1 : 0', |
'type' => 'output' |
}, |
'm_cyc_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cyc_o', |
'range' => '', |
'type' => 'output' |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'm_cti_o' => { |
'm_dat_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'cti_o', |
'range' => 'TAGw-1 : 0', |
'type' => 'output' |
'range' => 'DW-1 : 0', |
'intfc_port' => 'dat_o' |
}, |
'm_stb_o' => { |
'm_sel_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'stb_o', |
'range' => '', |
'type' => 'output' |
'range' => 'SELw-1 : 0', |
'intfc_port' => 'sel_o' |
}, |
'm_we_o' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'we_o', |
'range' => '', |
'type' => 'output' |
}, |
'status_i' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'NC', |
'range' => '', |
'type' => 'input' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'type' => 'input', |
'range' => '', |
'type' => 'input' |
'intfc_port' => 'reset_i' |
}, |
'm_ack_i' => { |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'ack_i', |
'type' => 'input', |
'range' => '', |
'type' => 'input' |
'intfc_port' => 'ack_i' |
}, |
'status_i' => { |
'range' => '', |
'intfc_port' => 'NC', |
'intfc_name' => 'IO', |
'type' => 'input' |
}, |
'm_cti_o' => { |
'intfc_port' => 'cti_o', |
'range' => 'TAGw-1 : 0', |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]' |
}, |
'm_stb_o' => { |
'type' => 'output', |
'intfc_name' => 'plug:wb_master[0]', |
'intfc_port' => 'stb_o', |
'range' => '' |
} |
}, |
'parameters_order' => [ |
'DW', |
'AW', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'VJTAG_INDEX' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/jtag/jtag_wb/vjtag_wb.v', |
'module_name' => 'vjtag_wb', |
'hdl_files' => [ |
'/mpsoc/src_peripheral/jtag/jtag_wb' |
], |
'ip_name' => 'jtag_wb', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'unused' => { |
'plug:wb_master[0]' => [ |
'bte_o', |
'tag_o', |
'bte_o', |
'err_i', |
'rty_i' |
'rty_i', |
'err_i' |
] |
}, |
'category' => 'JTAG' |
'category' => 'JTAG', |
'ports_order' => [ |
'clk', |
'reset', |
'm_sel_o', |
'm_dat_o', |
'm_addr_o', |
'm_cti_o', |
'm_stb_o', |
'm_cyc_o', |
'm_we_o', |
'm_dat_i', |
'm_ack_i', |
'status_i' |
] |
}, 'ip_gen' ); |
/mpsoc/perl_gui/lib/ip/NoC/ni_sep.IP
3,7 → 3,7
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## This file is part of ProNoC 1.5.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
112,15 → 112,160
${IP}_wait_for_reading_pck(); |
}', |
'ip_name' => 'ni_sep', |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'parameters_order' => [ |
'V', |
'B', |
'NX', |
'NY', |
'Fpay', |
'TOPOLOGY', |
'ROUTE_NAME', |
'DEBUG_EN', |
'COMB_MEM_PTR_W', |
'COMB_PCK_SIZE_W', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'Yw', |
'Fw', |
'Xw' |
], |
'ports_order' => [ |
'reset', |
'clk', |
'current_x', |
'current_y', |
'flit_out', |
'flit_out_wr', |
'credit_in', |
'flit_in', |
'flit_in_wr', |
'credit_out', |
's_dat_i', |
's_sel_i', |
's_addr_i', |
's_cti_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
'm_rd_sel_o', |
'm_rd_dat_o', |
'm_rd_addr_o', |
'm_rd_cti_o', |
'm_rd_stb_o', |
'm_rd_cyc_o', |
'm_rd_we_o', |
'm_rd_ack_i', |
'm_wr_sel_o', |
'm_wr_addr_o', |
'm_wr_cti_o', |
'm_wr_stb_o', |
'm_wr_cyc_o', |
'm_wr_we_o', |
'm_wr_dat_i', |
'm_wr_ack_i', |
'irq' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ni/ni_sep.v', |
'sockets' => { |
'ni' => { |
'connection_num' => 'single connection', |
'0' => { |
'name' => 'ni' |
}, |
'value' => 1, |
'type' => 'num', |
'ni' => {} |
} |
}, |
'module_name' => 'ni_sep', |
'unused' => { |
'plug:wb_master[1]' => [ |
'tag_o', |
'bte_o', |
'dat_o', |
'err_i', |
'rty_i' |
], |
'plug:wb_slave[0]' => [ |
'err_o', |
'rty_o', |
'tag_i', |
'bte_i' |
], |
'plug:wb_master[0]' => [ |
'tag_o', |
'dat_i', |
'bte_o', |
'err_i', |
'rty_i' |
] |
}, |
'category' => 'NoC', |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'1' => { |
'name' => 'wb_wr' |
}, |
'0' => { |
'name' => 'wb_rd' |
}, |
'value' => 2, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'intrpt_prhl' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'1' => { |
'width' => 1, |
'name' => 'wb_slave_1', |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
}, |
'0' => { |
'width' => 9, |
'name' => 'wb_slave', |
'addr' => '0xb800_0000 0xbfff_ffff custom devices' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'modules' => { |
'ni_sep' => {} |
}, |
'parameters' => { |
'Dw' => { |
'info' => undef, |
'deafult' => ' 32', |
'global_param' => 0, |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
128,7 → 273,7
'DEBUG_EN' => { |
'info' => undef, |
'deafult' => '0', |
'global_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
136,7 → 281,7
'NY' => { |
'info' => undef, |
'deafult' => ' 2', |
'global_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
144,7 → 289,7
'NX' => { |
'info' => undef, |
'deafult' => ' 2', |
'global_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
152,7 → 297,7
'V' => { |
'info' => '', |
'deafult' => ' 4', |
'global_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
168,7 → 313,7
'Fw' => { |
'info' => undef, |
'deafult' => '2+V+Fpay', |
'global_param' => 0, |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 0, |
'type' => 'Fixed' |
176,7 → 321,7
'COMB_PCK_SIZE_W' => { |
'info' => undef, |
'deafult' => '12', |
'global_param' => 0, |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
184,7 → 329,7
'TAGw' => { |
'info' => undef, |
'deafult' => '3', |
'global_param' => 0, |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
192,7 → 337,7
'M_Aw' => { |
'info' => undef, |
'deafult' => '32', |
'global_param' => 0, |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
200,7 → 345,7
'COMB_MEM_PTR_W' => { |
'info' => undef, |
'deafult' => '20', |
'global_param' => 0, |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
208,7 → 353,7
'ROUTE_NAME' => { |
'info' => undef, |
'deafult' => '"XY"', |
'global_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
224,7 → 369,7
'Fpay' => { |
'info' => undef, |
'deafult' => ' 32', |
'global_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
240,7 → 385,7
'SELw' => { |
'info' => undef, |
'deafult' => '4 ', |
'global_param' => 0, |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
256,7 → 401,7
'B' => { |
'info' => '', |
'deafult' => ' 4', |
'global_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
263,8 → 408,8
}, |
'S_Aw' => { |
'info' => undef, |
'deafult' => ' 3', |
'global_param' => 0, |
'deafult' => '7', |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
272,7 → 417,7
'TOPOLOGY' => { |
'info' => undef, |
'deafult' => '"MESH"', |
'global_param' => 1, |
'global_param' => 'Parameter', |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
280,7 → 425,7
'Xw' => { |
'info' => undef, |
'deafult' => 'log2(NX)', |
'global_param' => 0, |
'global_param' => 'Localparam', |
'content' => '', |
'type' => 'Fixed', |
'redefine_param' => 0 |
288,7 → 433,7
'Yw' => { |
'info' => undef, |
'deafult' => 'log2(NY)', |
'global_param' => 0, |
'global_param' => 'Localparam', |
'content' => '', |
'redefine_param' => 0, |
'type' => 'Fixed' |
310,119 → 455,10
'redefine_param' => 1 |
} |
}, |
'modules' => { |
'ni_sep' => {} |
}, |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'1' => { |
'name' => 'wb_wr' |
}, |
'0' => { |
'name' => 'wb_rd' |
}, |
'value' => 2, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'intrpt_prhl' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'1' => { |
'width' => 1, |
'name' => 'wb_slave_1', |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
}, |
'0' => { |
'width' => 5, |
'name' => 'wb_slave', |
'addr' => '0xb800_0000 0xbfff_ffff custom devices' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'ports_order' => [ |
'reset', |
'clk', |
'current_x', |
'current_y', |
'flit_out', |
'flit_out_wr', |
'credit_in', |
'flit_in', |
'flit_in_wr', |
'credit_out', |
's_dat_i', |
's_sel_i', |
's_addr_i', |
's_cti_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
'm_rd_sel_o', |
'm_rd_dat_o', |
'm_rd_addr_o', |
'm_rd_cti_o', |
'm_rd_stb_o', |
'm_rd_cyc_o', |
'm_rd_we_o', |
'm_rd_ack_i', |
'm_wr_sel_o', |
'm_wr_addr_o', |
'm_wr_cti_o', |
'm_wr_stb_o', |
'm_wr_cyc_o', |
'm_wr_we_o', |
'm_wr_dat_i', |
'm_wr_ack_i', |
'irq' |
], |
'parameters_order' => [ |
'V', |
'B', |
'NX', |
'NY', |
'Fpay', |
'TOPOLOGY', |
'ROUTE_NAME', |
'DEBUG_EN', |
'COMB_MEM_PTR_W', |
'COMB_PCK_SIZE_W', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'Yw', |
'Fw', |
'Xw' |
], |
'gui_status' => { |
'timeout' => 0, |
'status' => 'ideal' |
}, |
'ports' => { |
'm_rd_cyc_o' => { |
'intfc_port' => 'cyc_o', |
640,41 → 676,5
'range' => '', |
'type' => 'output' |
} |
}, |
'sockets' => { |
'ni' => { |
'connection_num' => 'single connection', |
'0' => { |
'name' => 'ni' |
}, |
'value' => 1, |
'type' => 'num', |
'ni' => {} |
} |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ni/ni_sep.v', |
'module_name' => 'ni_sep', |
'unused' => { |
'plug:wb_master[1]' => [ |
'tag_o', |
'bte_o', |
'dat_o', |
'err_i', |
'rty_i' |
], |
'plug:wb_slave[0]' => [ |
'err_o', |
'rty_o', |
'tag_i', |
'bte_i' |
], |
'plug:wb_master[0]' => [ |
'tag_o', |
'dat_i', |
'bte_o', |
'err_i', |
'rty_i' |
] |
}, |
'category' => 'NoC' |
} |
}, 'ip_gen' ); |
/mpsoc/perl_gui/lib/mpsoc/lm32_noc.MPSOC
3,7 → 3,7
## |
## Copyright (C) 2014-2016 Alireza Monemi |
## |
## This file is part of ProNoC 1.5.0 |
## This file is part of ProNoC 1.5.1 |
## |
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT |
## MAY CAUSE UNEXPECTED BEHAIVOR. |
10,6 → 10,10
################################################################################ |
|
$lm32_noc = bless( { |
'class_param' => { |
'Cn_1' => '2\'b11', |
'Cn_0' => '2\'b11' |
}, |
'socs' => { |
'test' => { |
'top' => bless( { |
1706,13 → 1710,6
'range' => 'led_PORT_WIDTH-1 : 0', |
'type' => 'output' |
}, |
'ni_flit_out' => { |
'intfc_port' => 'flit_out', |
'intfc_name' => 'socket:ni[0]', |
'instance_name' => 'ni0', |
'range' => 'ni_Fw-1 : 0', |
'type' => 'output' |
}, |
'ni_current_y' => { |
'intfc_port' => 'current_y', |
'intfc_name' => 'socket:ni[0]', |
1727,6 → 1724,13
'range' => '', |
'type' => 'output' |
}, |
'ni_flit_out' => { |
'intfc_port' => 'flit_out', |
'intfc_name' => 'socket:ni[0]', |
'instance_name' => 'ni0', |
'range' => 'ni_Fw-1 : 0', |
'type' => 'output' |
}, |
'ni_credit_out' => { |
'intfc_port' => 'credit_out', |
'intfc_name' => 'socket:ni[0]', |
2538,7 → 2542,7
} |
}, |
'setting' => { |
'show_adv_setting' => 0, |
'show_adv_setting' => 1, |
'soc_path' => 'lib/soc', |
'show_noc_setting' => 1, |
'show_tile_setting' => 1 |
2557,6 → 2561,10
'timeout' => 0 |
}, |
'parameters_order' => { |
'class_param' => [ |
'Cn_0', |
'Cn_1' |
], |
'noc_param' => [ |
'NX', |
'NY', |
2587,10 → 2595,10
'DEBUG_EN' => '0', |
'NX' => ' 2', |
'VC_REALLOCATION_TYPE' => '"NONATOMIC"', |
'V' => '2', |
'V' => 2, |
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0', |
'ROUTE_SUBFUNC' => '"XY"', |
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0', |
'C' => 0, |
'C' => 2, |
'ROUTE_NAME' => '"XY"', |
'Fpay' => '32', |
'MUX_TYPE' => '"BINARY"', |
/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl
5,7 → 5,7
require "widget.pl"; |
|
|
use constant SIM_RAM_GEN => 1; |
use constant SIM_RAM_GEN => 0; |
|
use constant JTAG_RAM_INDEX => 128; |
use constant JTAG_DONE_RESET_INDEX => 127; |
/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl
181,7 → 181,7
my %param_value; |
my $top=$mpsoc->mpsoc_get_soc($soc_name); |
my @insts=$top->top_get_all_instances(); |
my @exceptions=('ni0'); |
my @exceptions=get_NI_instance_list($top); |
@insts=get_diff_array(\@insts,\@exceptions); |
foreach my $inst (@insts){ |
my @params=$top->top_get_parameter_list($inst); |
221,8 → 221,8
my @instance_list=$top->top_get_all_instances(); |
#check if the soc has ni port |
foreach my $instanc(@instance_list){ |
my $module=$top->top_get_def_of_instance($instanc,'module'); |
if($module eq 'ni') |
my $category=$top->top_get_def_of_instance($instanc,'category'); |
if($category eq 'NoC') |
{ |
my $name=$soc->object_get_attribute('soc_name'); |
$mpsoc->mpsoc_add_soc($name,$top); |
251,6 → 251,20
|
|
} |
|
|
sub get_NI_instance_list { |
my $top=shift; |
my @nis; |
my @instance_list=$top->top_get_all_instances(); |
#check if the soc has ni port |
foreach my $instanc(@instance_list){ |
my $category=$top->top_get_def_of_instance($instanc,'category'); |
push(@nis,$instanc) if($category eq 'NoC') ; |
} |
return @nis; |
} |
|
#################### |
# get_conflict_decision |
########################### |
419,7 → 433,7
|
|
my @insts=$top->top_get_all_instances(); |
my @exceptions=('ni0'); |
my @exceptions=get_NI_instance_list($top); |
@insts=get_diff_array(\@insts,\@exceptions); |
foreach my $inst (@insts){ |
my @params=$top->top_get_parameter_list($inst); |
964,7 → 978,7
$type="Check-box"; |
$content=$v; |
$info="Select the permitted VCs which the message class $i can be sent via them."; |
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param',undef); |
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'class_param',undef); |
|
|
} |
993,7 → 1007,7
$type="Check-box"; |
$content=1; |
$default="1\'b0"; |
$info="If ebabled it adds a pipline register at the output port of the router."; |
$info="If enabeled it adds a pipline register at the output port of the router."; |
$row=noc_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,'noc_param'); |
|
|
1177,7 → 1191,9
#update NoC param |
#my %nocparam = %{$mpsoc->object_get_attribute('noc_param',undef)}; |
my $nocparam =$mpsoc->object_get_attribute('noc_param',undef); |
$soc->soc_add_instance_param('ni0' ,$nocparam ); |
my $top=$mpsoc->mpsoc_get_soc($soc_name); |
my @nis=get_NI_instance_list($top); |
$soc->soc_add_instance_param($nis[0] ,$nocparam ); |
#foreach my $p ( sort keys %nocparam ) { |
|
# print "$p = $nocparam{$p} \n"; |
/mpsoc/perl_gui/lib/perl/mpsoc_verilog_gen.pl
179,6 → 179,11
my $class=$mpsoc->object_get_attribute('noc_param',"C"); |
my $str; |
if( $class > 1){ |
for (my $i=0; $i<=$class-1; $i++){ |
my $n="Cn_$i"; |
my $val=$mpsoc->object_get_attribute('class_param',$n); |
add_text_to_string (\$param_v,"\tlocalparam $n=$val;\n"); |
} |
$str="CLASS_SETTING={"; |
for (my $i=$class-1; $i>=0;$i--){ |
$str=($i==0)? "${str}Cn_0};\n " : "${str}Cn_$i,"; |
438,8 → 443,9
|
# ni parameter |
my $top=$mpsoc->mpsoc_get_soc($soc_name); |
my @noc_param=$top->top_get_parameter_list('ni0'); |
my $inst_name=$top->top_get_def_of_instance('ni0','instance'); |
my @nis=get_NI_instance_list($top); |
my @noc_param=$top->top_get_parameter_list($nis[0]); |
my $inst_name=$top->top_get_def_of_instance($nis[0],'instance'); |
|
#other parameters |
my %params=$top->top_get_default_soc_param(); |
/mpsoc/src_emulate/fpga/DE4_230/src/emulator_top.v
83,8 → 83,8
assign LED[7:3] = 5'b11111; |
|
|
assign reset = (jtag_reset | reset_in); |
|
|
reg[31:0]time_cnt; |
|
// two reset sources which can be controled using jtag. One for reseting NoC another packet injectors |
/mpsoc/src_noc/traffic_gen.v.old
File deleted
mpsoc/src_noc/traffic_gen.v.old
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: mpsoc/src_noc/inout_ports.v.classic
===================================================================
--- mpsoc/src_noc/inout_ports.v.classic (revision 29)
+++ mpsoc/src_noc/inout_ports.v.classic (nonexistent)
@@ -1,383 +0,0 @@
-`timescale 1ns/1ps
-
-module inout_ports #(
- parameter V = 4, // vc_num_per_port
- parameter P = 5, // router port num
- parameter B = 4, // buffer space :flit per VC
- parameter NX = 4, // number of node in x axis
- parameter NY = 4, // number of node in y axis
- parameter C = 4, // number of flit class
- parameter Fpay = 32, //payload width
- parameter CLASS_CONFIG_NUM= 0,
- parameter VC_REALLOCATION_TYPE= "NONATOMIC",
- parameter COMBINATION_TYPE= "BASELINE",// "BASELINE", "COMB_SPEC1", "COMB_SPEC2", "COMB_NONSPEC"
- parameter TOPOLOGY= "MESH",//"MESH","TORUS"
- parameter ROUTE_NAME="XY",// "XY", "TRANC_XY"
- parameter ROUTE_TYPE="DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
- parameter CONGESTION_INDEX = 2,//"CREDIT","VC"
- parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000, // mask scape vc, valid only for full adaptive
- parameter DEBUG_EN = 1,
- parameter AVC_ATOMIC_EN = 1,
- parameter ROUTE_SUBFUNC = "XY",
- parameter CONGw = 2
-
-)
-(
- current_x,
- current_y,
- // to/from neighboring router
- flit_in_all,
- flit_in_we_all,
- credit_out_all,
- credit_in_all,
- congestion_in_all,
- congestion_out_all,
-
- // from vc/sw allocator
- ovc_allocated_all,
- granted_ovc_num_all,
- ivc_num_getting_sw_grant,
- ivc_num_getting_ovc_grant,
- spec_ovc_num_all,
- nonspec_first_arbiter_granted_ivc_all,
- spec_first_arbiter_granted_ivc_all,
- nonspec_granted_dest_port_all,
- spec_granted_dest_port_all,
- granted_dest_port_all,
- any_ivc_sw_request_granted_all,
-
- // to vc/sw allocator
- dest_port_all,
- ovc_is_assigned_all,
- ivc_request_all,
- assigned_ovc_not_full_all,
- masked_ovc_request_all,
- lk_destination_all,
-
-
- // to crossbar
- flit_out_all,
- clk,reset
-
-);
-
- function integer log2;
- input integer number; begin
- log2=0;
- while(2**log2
mpsoc/src_noc/inout_ports.v.classic
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: mpsoc/src_noc/routing.v
===================================================================
--- mpsoc/src_noc/routing.v (revision 29)
+++ mpsoc/src_noc/routing.v (revision 30)
@@ -683,7 +683,7 @@
input [Xw-1 :0] current_x;
input [Yw-1 :0] current_y;
- input [Yw-1 :0] dest_x;
+ input [Xw-1 :0] dest_x;
input [Yw-1 :0] dest_y;
output [DSTw-1 :0] destport;
@@ -961,7 +961,7 @@
input [Xw-1 :0] current_x;
input [Yw-1 :0] current_y;
- input [Yw-1 :0] dest_x;
+ input [Xw-1 :0] dest_x;
input [Yw-1 :0] dest_y;
output [P_1-1 :0] destport;
/mpsoc/src_noc/ss_allocator.v
267,9 → 267,7
|
|
|
localparam SSA_EN = ((ROUTE_TYPE == "FULL_ADAPTIVE") && (SS_PORT==2 || SS_PORT == 4) && ((1<<V_LOCAL & ~ESCAP_VC_MASK ) != {V{1'b0}})) ? 1'b0 :1'b1; |
|
|
|
|
|
//header packet filds width |
279,6 → 277,11
X_Y_IN_HDR_WIDTH =4, |
SW_LOC =V_GLOBAL/V, |
V_LOCAL =V_GLOBAL%V; |
|
|
localparam SSA_EN = ((ROUTE_TYPE == "FULL_ADAPTIVE") && (SS_PORT==2 || SS_PORT == 4) && ((1<<V_LOCAL & ~ESCAP_VC_MASK ) != {V{1'b0}})) ? 1'b0 :1'b1; |
|
|
|
|
input [Fw-1 : 0] flit_in; |
/mpsoc/src_peripheral/ethmac/eth
90,8 → 90,8
int ${IP}_rx_len; |
unsigned char ${IP}_tx_packet[1536]; //max length |
unsigned char ${IP}_rx_packet[1536]; |
unsigned char * ethmac_tx_data= & ethmac_tx_packet[HDR_LEN]; |
unsigned char * ethmac_rx_data= & ethmac_rx_packet[HDR_LEN]; |
unsigned char * ${IP}_tx_data= & ${IP}_tx_packet[HDR_LEN]; |
unsigned char * ${IP}_rx_data= & ${IP}_rx_packet[HDR_LEN]; |
|
void ${IP}_recv_ack(void) |
{ |
/mpsoc/src_peripheral/ethmac/eth_generic_ram.v
0,0 → 1,105
|
/**************** |
*simple_dual_port_ram |
* |
*****************/ |
|
|
|
// Quartus II Verilog Template |
// Simple Dual Port RAM with separate read/write addresses and |
// single read/write clock |
|
module eth_simple_dual_port_ram #( |
parameter Dw=8, |
parameter Aw=6 |
) |
( |
data, |
read_addr, |
write_addr, |
we, |
clk, |
q |
); |
|
input [Dw-1 :0] data; |
input [Aw-1 :0] read_addr; |
input [Aw-1 :0] write_addr; |
input we; |
input clk; |
output reg [Dw-1 :0] q; |
|
|
// Declare the RAM variable |
reg [Dw-1:0] ram [2**Aw-1:0]; |
|
always @ (posedge clk) |
begin |
// Write |
if (we) |
ram[write_addr] <= data; |
|
// Read (if read_addr == write_addr, return OLD data). To return |
// NEW data, use = (blocking write) rather than <= (non-blocking write) |
// in the write assignment. NOTE: NEW data may require extra bypass |
// logic around the RAM. |
q <= ram[read_addr]; |
end |
|
endmodule |
|
|
|
|
|
|
|
|
/***************************** |
|
single_port_ram |
|
|
*****************************/ |
|
// Quartus II Verilog Template |
// Single port RAM with single read/write address |
|
module eth_single_port_ram #( |
parameter Dw=8, |
parameter Aw=6 |
) |
( |
data, |
addr, |
we, |
clk, |
q |
); |
|
input [(Dw-1):0] data; |
input [(Aw-1):0] addr; |
input we, clk; |
output [(Dw-1):0] q; |
|
// Declare the RAM variable |
reg [Dw-1:0] ram[2**Aw-1:0]; |
|
// Variable to hold the registered read address |
reg [Aw-1:0] addr_reg; |
|
always @ (posedge clk) |
begin |
// Write |
if (we) |
ram[addr] <= data; |
addr_reg <= addr; |
end |
|
// Continuous assignment implies read returns NEW data. |
// This is the natural behavior of the TriMatrix memory |
// blocks in Single Port mode. |
assign q = ram[addr_reg]; |
|
endmodule |
mpsoc/src_peripheral/ethmac/eth_generic_ram.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v
===================================================================
--- mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v (revision 29)
+++ mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v (revision 30)
@@ -176,7 +176,7 @@
);
*/
- simple_dual_port_ram
+ eth_simple_dual_port_ram
#(
.Dw(DATA_WIDTH),
.Aw(CNT_WIDTH-1)
/mpsoc/src_peripheral/ethmac/rtl/eth_spram_256x32.v
254,7 → 254,7
); |
|
|
single_port_ram #( |
eth_single_port_ram #( |
.Dw(32), |
.Aw(8) |
) |
/mpsoc/src_peripheral/ni/old_ni.v
File deleted
mpsoc/src_peripheral/ni/old_ni.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: mpsoc/src_peripheral/ni/bak
===================================================================
--- mpsoc/src_peripheral/ni/bak (revision 29)
+++ mpsoc/src_peripheral/ni/bak (nonexistent)
@@ -1,834 +0,0 @@
-/**************************************
-* Module: ni
-* Date:2015-03-30
-* Author: alireza
-*
-* Description:
-***************************************/
-
-
-/**********************************************************************
- File: ni.v
-
- Copyright (C) 2013 Alireza Monemi
-
- This AUTOram is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 3 of the License, or
- (at your option) any later version.
-
- This AUTOram is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this AUTOram. If not, see .
-
-
- Purpose:
- A DMA based NI for connecting the NoC router to a processor. The NI has 3
- memory mapped registers:
- // ni status register
- STATUS_ADDR = 0,
- // update memory pinter, packet size and send packet read command. If memory pointer and packet size width are smaller than COMB_MEM_PTR_W and COMB_PCK_SIZE_W respectively.
- RD_MEM_PCKSIZ_ADDR = 1,
- // update memory pinter, packet size and send packet write command. If memory pointer and packet size width are smaller than COMB_MEM_PTR_W and COMB_PCK_SIZE_W respectively.
- WR_MEM_PCKSIZ_ADDR = 2,
- //update packet size
- PCK_SIZE_ADDR = 3,
- //update the memory pointer address and send read command. The packet size must be updated before setting this register. use it when memory pointer width is larger than COMB_MEM_PTR_W
- RD_MEM_ADDR = 4,
- //update the memory pointer address and send write command. The packet size must be updated before setting this register. use it when memory pointer width is larger than COMB_MEM_PTR_W
- WR_MEM_ADDR = 5;
-
- status_reg
- bit_loc flag_name
- 12 rsv_pck_isr
- 11 rd_done_isr
- 10 wr_done_isr
- 9 rsv_pck_int_en
- 8 rd_done_int_en
- 7 wr_done_int_en
- 6 all_vcs_full
- 5 any_vc_has_data
- 4 rd_no_pck_err
- 3 rd_ovr_size_err
- 2 rd_done
- 1 wr_done
- 0 busy
-
-
-
- RD/WR registers ={pck_size_next,memory_ptr_next}
-
- Info: monemi@fkegraduate.utm.my
- *************************************************************************/
-
-
-`timescale 1ns/1ps
-
-
-
-module ni #(
-
- parameter V = 4, // V
- parameter P = 5, // router port num
- parameter B = 4, // buffer space :flit per VC
- parameter NX = 2, // number of node in x axis
- parameter NY = 2, // number of node in y axis
- parameter Fpay = 32,
- parameter TOPOLOGY = "MESH",//"MESH","TORUS"
- parameter ROUTE_TYPE = "DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
- parameter ROUTE_NAME = "XY",
- parameter DEBUG_EN = 1,
-
- parameter COMB_MEM_PTR_W=20,
- parameter COMB_PCK_SIZE_W= 12,
-
- //wishbone port parameters
- parameter Dw = 32,
- parameter S_Aw = 3,
- parameter M_Aw = 32,
- parameter TAGw = 3,
- parameter SELw = 4
-
-
- )
- (
-
- reset,
- clk,
-
- //noc interface
- current_x,
- current_y,
- flit_out,
- flit_out_wr,
- credit_in,
- flit_in,
- flit_in_wr,
- credit_out,
-
- //wishbone slave interface signals
- s_dat_i,
- s_sel_i,
- s_addr_i,
- s_cti_i,
- s_stb_i,
- s_cyc_i,
- s_we_i,
- s_dat_o,
- s_ack_o,
- s_err_o,
- s_rty_o,
-
-
-
- //wishbone master interface signals
- m_sel_o,
- m_dat_o,
- m_addr_o,
- m_cti_o,
- m_stb_o,
- m_cyc_o,
- m_we_o,
- m_dat_i,
- m_ack_i,
- m_err_i,
- m_rty_i,
- //intruupt interface
- irq
-
-
-);
-
- function integer log2;
- input integer number; begin
- log2=0;
- while(2**log2
mpsoc/src_peripheral/ni/bak
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: mpsoc/src_peripheral/ni/sub_ni_rd.v
===================================================================
--- mpsoc/src_peripheral/ni/sub_ni_rd.v (revision 29)
+++ mpsoc/src_peripheral/ni/sub_ni_rd.v (revision 30)
@@ -356,6 +356,7 @@
reg [Vw-1 :0] cand_rd_vc_binary;
wire [V-1 :0] cand_rd_vc_onehot;
+ wire [V-1 :0] rd_vc_not_empty;
assign {wb_v_addr_binary, wb_wr_rd_addr, wb_general_reg_addr} = s_addr_i[3+Vw :0];
@@ -683,7 +684,7 @@
);
-
+ assign rd_vc_not_empty = ififo_vc_not_empty;
@@ -705,3 +706,5 @@
+
+
/mpsoc/src_peripheral/ni/sub_ni_wr.v
156,7 → 156,8
localparam P_1 = P-1 , |
Fw = 2+V+Fpay, //flit width |
Xw = log2(NX), |
Yw = log2(NY); |
Yw = log2(NY), |
Vw = (V>1) ? log2(V) : 1; |
|
|
//wishbone slave addresses |
415,7 → 416,7
|
//status register |
assign wr_busy = ps!=IDEAL; |
assign status_reg = {/*rd_vc_not_empty*/{Vw{1'b0}},wr_vc_not_empty,/*rsv_pck_isr*/1'b0, /*rd_done_isr*/1'b0,wr_done_isr,/*rsv_pck_int_en*/1'b0,/*rd_done_int_en*/1'b0,wr_done_int_en,all_vcs_full,/*any_vc_has_data*/1'b0,/*rd_no_pck_err*/1'b0,/*rd_ovr_size_err*/1'b0,/*rd_done*/1'b0,wr_done,/*rd_busy*/,wr_busy}; |
assign status_reg = {/*rd_vc_not_empty*/{Vw{1'b0}}, wr_vc_not_empty,/*rsv_pck_isr*/1'b0, /*rd_done_isr*/1'b0, wr_done_isr,/*rsv_pck_int_en*/1'b0,/*rd_done_int_en*/1'b0,wr_done_int_en,all_vcs_full,/*any_vc_has_data*/1'b0,/*rd_no_pck_err*/1'b0,/*rd_ovr_size_err*/1'b0,/*rd_done*/1'b0,wr_done,/*rd_busy*/1'b0,wr_busy}; |
assign s_dat_o = status_reg; |
|
reg [M_Aw-1 : 0] m_addr; |
696,3 → 697,4
|
|
|
|
/mpsoc/src_verilator/testbench.cpp
150,7 → 150,7
traffic[i]->current_x = x; |
traffic[i]->current_y = y; |
traffic[i]->start=0; |
traffic[i]->pck_size=PACKET_SIZE; |
traffic[i]->pck_size_in=PACKET_SIZE; |
traffic[i]->ratio=ratio; |
traffic[i]->pck_class_in= pck_class_in_gen( i); |
pck_dst_gen ( x,y,i, &dest_x, &dest_y); |
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