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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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    /an-fpga-implementation-of-low-latency-noc-based-mpsoc
    from Rev 2 to Rev 3
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Rev 2 → Rev 3

/trunk/noc_based_mpsoc/src/NoC/sdram_core.v
1,5 → 1,7
`include "../define.v"
module sdram_core #(
parameter TOPOLOGY = "TORUS", // "MESH" or "TORUS"
parameter ROUTE_ALGRMT = "XY", //"XY" or "MINIMAL"
parameter VC_NUM_PER_PORT = 2,
parameter PYLD_WIDTH = 32,
parameter BUFFER_NUM_PER_VC = 16,
85,7 → 87,8
 
 
ext_ram_nic #(
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.VC_NUM_PER_PORT (VC_NUM_PER_PORT ),
.PYLD_WIDTH (PYLD_WIDTH),
.BUFFER_NUM_PER_VC (BUFFER_NUM_PER_VC),
/trunk/noc_based_mpsoc/src/NoC/router.v
30,6 → 30,8
 
 
module router#(
parameter TOPOLOGY = "TORUS", // "MESH" or "TORUS"
parameter ROUTE_ALGRMT = "XY", //"XY" or "MINIMAL"
parameter VC_NUM_PER_PORT = 2,
parameter BUFFER_NUM_PER_VC = 4,
parameter PORT_NUM = 5,
319,8 → 321,10
);
//look ahead routing module
look_ahead_routing #(
//look ahead routing module
look_ahead_routing_sync #(
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.PORT_NUM (PORT_NUM),
.X_NODE_NUM (X_NODE_NUM),
.Y_NODE_NUM (Y_NODE_NUM),
/trunk/noc_based_mpsoc/src/NoC/ext_ram_nic.v
24,7 → 24,8
`include "../define.v"
 
module ext_ram_nic #(
parameter TOPOLOGY = "TORUS", // "MESH" or "TORUS"
parameter ROUTE_ALGRMT = "XY", //"XY" or "MINIMAL"
parameter VC_NUM_PER_PORT = 2,
parameter PYLD_WIDTH = 32,
parameter BUFFER_NUM_PER_VC = 16,
199,16 → 200,19
.clk (clk),
.reset (reset)
);
xy #(
 
 
route_compute #(
.ROUTE_TYPE ("NORMAL"),
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.PORT_NUM (PORT_NUM),
.X_NODE_NUM (X_NODE_NUM),
.Y_NODE_NUM (Y_NODE_NUM),
.SW_X_ADDR (SW_X_ADDR),
.SW_Y_ADDR (SW_Y_ADDR),
.SENDER_PORT (NIC_CONNECT_PORT) // 0:Local 1:East, 2:North, 3:West, 4:South
.SW_Y_ADDR (SW_Y_ADDR)
)
th_xy_rout
the_normal_routting
(
.dest_x_node_in (dest_x_addr),
.dest_y_node_in (dest_y_addr),
215,6 → 219,8
.port_num_out (port_num_next)
);
 
always @(*)begin
ns = ps;
ram_write = 1'b0;
/trunk/noc_based_mpsoc/src/NoC/ni.v
40,6 → 40,8
 
 
module ni #(
parameter TOPOLOGY = "TORUS", // "MESH" or "TORUS"
parameter ROUTE_ALGRMT = "XY", //"XY" or "MINIMAL"
parameter VC_NUM_PER_PORT = 2,
parameter PYLD_WIDTH = 32,
parameter BUFFER_NUM_PER_VC = 16,
571,16 → 573,17
 
 
 
xy #(
route_compute #(
.ROUTE_TYPE ("NORMAL"),
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.PORT_NUM (PORT_NUM),
.X_NODE_NUM (X_NODE_NUM),
.Y_NODE_NUM (Y_NODE_NUM),
.SW_X_ADDR (SW_X_ADDR),
.SW_Y_ADDR (SW_Y_ADDR),
.SENDER_PORT (NIC_CONNECT_PORT) // 0:Local 1:East, 2:North, 3:West, 4:South
.SW_Y_ADDR (SW_Y_ADDR)
)
th_xy_rout
the_normal_routting
(
.dest_x_node_in (dest_x_addr),
.dest_y_node_in (dest_y_addr),
/trunk/noc_based_mpsoc/src/IP_core/aeMB_IP.v
60,6 → 60,8
parameter AEMB_MUL = 1, ///< optional multiplier
// noc parameter
parameter TOPOLOGY = "TORUS", // "MESH" or "TORUS"
parameter ROUTE_ALGRMT = "XY", //"XY" or "MINIMAL"
parameter VC_NUM_PER_PORT = 2,
parameter PYLD_WIDTH = 32,
parameter BUFFER_NUM_PER_VC = 16,
353,6 → 355,8
if(NOC_EN) begin : noc_gen
ni #(
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.VC_NUM_PER_PORT (VC_NUM_PER_PORT),
.PYLD_WIDTH (PYLD_WIDTH),
.BUFFER_NUM_PER_VC (BUFFER_NUM_PER_VC),
/trunk/noc_based_mpsoc/src/IP_core/aeMB_mpsoc.v
31,7 → 31,7
/*
// the routers address in mesh topology
// the routers address in mesh/torus topology
CORE_NUM
(x,y)
79,7 → 79,8
Defining it as "testbench" will remove the processors
in simulation. Hence, the simulation time will be decreased. The tasks to control
NI pins are written in tasks.V file */
parameter TOPOLOGY = `TOPOLOGY_DEF,
parameter ROUTE_ALGRMT = `ROUTE_ALGRMT_DEF, //"XY" or "MINIMAL"
parameter VC_NUM_PER_PORT = `VC_NUM_PER_PORT_DEF ,
parameter PYLD_WIDTH = `PYLD_WIDTH_DEF,
parameter BUFFER_NUM_PER_VC = `BUFFER_NUM_PER_VC_DEF,
208,6 → 209,8
if( SDRAM_EN == 1 && x == SDRAM_SW_X_ADDR && y == SDRAM_SW_Y_ADDR) begin : sdram_gen
sdram_core #(
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.VC_NUM_PER_PORT (VC_NUM_PER_PORT),
.PYLD_WIDTH (PYLD_WIDTH),
.BUFFER_NUM_PER_VC (BUFFER_NUM_PER_VC),
260,6 → 263,8
.AEMB_DWB (AEMB_DWB), ///< DATA bus width
.NI_CTRL_SIMULATION (NI_CTRL_SIMULATION),
.NOC_S_ADDR_WIDTH (NOC_S_ADDR_WIDTH),
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT), //"XY" or "MINIMAL"
.VC_NUM_PER_PORT (VC_NUM_PER_PORT),
.PYLD_WIDTH (PYLD_WIDTH),
.BUFFER_NUM_PER_VC (BUFFER_NUM_PER_VC),
310,6 → 315,8
end
router#(
.TOPOLOGY (TOPOLOGY), // "MESH" or "TORUS"
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.VC_NUM_PER_PORT (VC_NUM_PER_PORT),
.BUFFER_NUM_PER_VC (BUFFER_NUM_PER_VC),
.PORT_NUM (PORT_NUM),
350,9 → 357,15
assign router_credit_in_array [`SELECT_WIRE(x,y,1,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE((x+1),y,3,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][1] = router_wr_out_en_array [`CORE_NUM((x+1),y)][3];
end else begin
assign router_flit_in_array [`SELECT_WIRE(x,y,1,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,1,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][1] = 1'b0;
if(TOPOLOGY == "MESH") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,1,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,1,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][1] = 1'b0;
end else if(TOPOLOGY == "TORUS") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,1,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE(0,y,3,FLIT_WIDTH)];
assign router_credit_in_array [`SELECT_WIRE(x,y,1,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE(0,y,3,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][1] = router_wr_out_en_array [`CORE_NUM(0,y)][3];
end //topology
end
361,10 → 374,16
assign router_credit_in_array [`SELECT_WIRE(x,y,2,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE(x,(y-1),4,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][2] = router_wr_out_en_array [`CORE_NUM(x,(y-1))][4];
end else begin
assign router_flit_in_array [`SELECT_WIRE(x,y,2,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,2,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][2] = 1'b0;
end
if(TOPOLOGY == "MESH") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,2,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,2,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][2] = 1'b0;
end else if(TOPOLOGY == "TORUS") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,2,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE(x,(Y_NODE_NUM-1),4,FLIT_WIDTH)];
assign router_credit_in_array [`SELECT_WIRE(x,y,2,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE(x,(Y_NODE_NUM-1),4,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][2] = router_wr_out_en_array [`CORE_NUM(x,(Y_NODE_NUM-1))][4];
end//topology
end//y>0
if(x>0)begin
371,12 → 390,17
assign router_flit_in_array [`SELECT_WIRE(x,y,3,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE((x-1),y,1,FLIT_WIDTH)] ;
assign router_credit_in_array [`SELECT_WIRE(x,y,3,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE((x-1),y,1,VC_NUM_PER_PORT)] ;
assign router_wr_in_en_array [`CORE_NUM(x,y)][3] = router_wr_out_en_array [`CORE_NUM((x-1),y)][1];
end else begin
if(TOPOLOGY == "MESH") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,3,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,3,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][3] = 1'b0;
end
end else if(TOPOLOGY == "TORUS") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,3,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE((X_NODE_NUM-1),y,1,FLIT_WIDTH)] ;
assign router_credit_in_array [`SELECT_WIRE(x,y,3,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE((X_NODE_NUM-1),y,1,VC_NUM_PER_PORT)] ;
assign router_wr_in_en_array [`CORE_NUM(x,y)][3] = router_wr_out_en_array [`CORE_NUM((X_NODE_NUM-1),y)][1];
end//topology
end
if(y < Y_NODE_NUM-1)begin
assign router_flit_in_array [`SELECT_WIRE(x,y,4,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE(x,(y+1),2,FLIT_WIDTH)];
383,9 → 407,16
assign router_credit_in_array [`SELECT_WIRE(x,y,4,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE(x,(y+1),2,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][4] = router_wr_out_en_array [`CORE_NUM(x,(y+1))][2];
end else begin
assign router_flit_in_array [`SELECT_WIRE(x,y,4,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,4,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][4] = 1'b0;
if(TOPOLOGY == "MESH") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,4,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,4,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][4] = 1'b0;
end else if(TOPOLOGY == "TORUS") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,4,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE(x,0,2,FLIT_WIDTH)];
assign router_credit_in_array [`SELECT_WIRE(x,y,4,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE(x,0,2,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][4] = router_wr_out_en_array [`CORE_NUM(x,0)][2];
end//topology
end
//connection to the ip_core
/trunk/noc_based_mpsoc/src/testbench_noc.v
35,7 → 35,7
`include "define.v"
 
module testbench_noc ();
parameter NI_CTRL_SIMULATION = "testbench"; //"aeMB";
parameter NI_CTRL_SIMULATION = "testbench"; //"aeMB";
/*"aeMB" or "testbench".
Definig it as " aeMB" will generate the same MPSoC for both simulation and
implementation.
42,7 → 42,8
Defining it as "testbench" will remove the processors
in simulation. Hence, the simulation time will be decreased. The tasks to control
NI pins are written in tasks.V file */
parameter TOPOLOGY = `TOPOLOGY_DEF; //"MESH" or "TORUS"
parameter ROUTE_ALGRMT = `ROUTE_ALGRMT_DEF;
parameter X_NODE_NUM = 4;//`X_NODE_NUM_DEF;
parameter Y_NODE_NUM = 4;//`Y_NODE_NUM_DEF;
parameter PORT_NUM = 5;
147,6 → 148,8
 
aeMB_mpsoc #(
.NI_CTRL_SIMULATION (NI_CTRL_SIMULATION),
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.X_NODE_NUM (X_NODE_NUM),
.Y_NODE_NUM (Y_NODE_NUM),
.AEMB_RAM_WIDTH_IN_WORD (AEMB_RAM_WIDTH_IN_WORD),
/trunk/noc_based_mpsoc/src/testbench.v
42,7 → 42,8
Defining it as "testbench" will remove the processors
in simulation. Hence, the simulation time will be decreased. The tasks to control
NI pins are written in tasks.v file */
parameter TOPOLOGY = `TOPOLOGY_DEF;
parameter ROUTE_ALGRMT = `ROUTE_ALGRMT_DEF;
parameter X_NODE_NUM = `X_NODE_NUM_DEF;
parameter Y_NODE_NUM = `Y_NODE_NUM_DEF;
parameter PORT_NUM = 5;
122,6 → 123,8
 
aeMB_mpsoc #(
.NI_CTRL_SIMULATION (NI_CTRL_SIMULATION),
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.X_NODE_NUM (X_NODE_NUM),
.Y_NODE_NUM (Y_NODE_NUM),
.AEMB_RAM_WIDTH_IN_WORD (AEMB_RAM_WIDTH_IN_WORD),
/trunk/noc_based_mpsoc/src/define.v
35,7 → 35,10
a 4X4 noC
 
********************************************************************/
 
//define the topology: "MESH" or "TORUS"
`define TOPOLOGY_DEF "MESH"
//define the routing algorithm : "XY" or "MINIMAL"
`define ROUTE_ALGRMT_DEF "XY"
// The number of virtual channel (VC) for each individual physical channel. this value must be power of 2. The typical value is two and four.
`define VC_NUM_PER_PORT_DEF 2
 
/trunk/noc_based_mpsoc/mpsoc.qsf
1119,6 → 1119,7
set_global_assignment -name EDA_TEST_BENCH_FILE src/testbench_noc.v -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_FILE src/testbench.v -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_FILE src/testbench_noc.v -section_id testbench_noc
set_global_assignment -name VERILOG_FILE src/NoC/route_compute.v
set_global_assignment -name VERILOG_FILE src/top_de115.v
set_global_assignment -name VERILOG_FILE src/NoC/ext_ram_nic.v
set_global_assignment -name VERILOG_FILE src/NoC/sdram_core.v
1126,7 → 1127,6
set_global_assignment -name VERILOG_FILE src/IP_core/sdram/synthesis/submodules/sdram_sdram_controller.v
set_global_assignment -name VERILOG_FILE src/IP_core/sdram/synthesis/submodules/altera_reset_controller.v
set_global_assignment -name VERILOG_FILE src/IP_core/sdram/synthesis/sdram.v
set_global_assignment -name VERILOG_FILE src/NoC/xy.v
set_global_assignment -name VERILOG_FILE src/NoC/tasks.v
set_global_assignment -name VERILOG_FILE src/NoC/switch_in.v
set_global_assignment -name VERILOG_FILE src/NoC/sw_sep_alloc.v
1139,8 → 1139,6
set_global_assignment -name VERILOG_FILE src/NoC/MUX.v
set_global_assignment -name VERILOG_FILE src/NoC/min_number.v
set_global_assignment -name VERILOG_FILE src/NoC/mask.v
set_global_assignment -name VERILOG_FILE src/NoC/look_ahead_xy.v
set_global_assignment -name VERILOG_FILE src/NoC/look_ahead_routing.v
set_global_assignment -name VERILOG_FILE src/NoC/fwft_fifo.v
set_global_assignment -name VERILOG_FILE src/NoC/fifo_buffer.v
set_global_assignment -name VERILOG_FILE src/NoC/dual_port_ram.v

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