URL
https://opencores.org/ocsvn/ao486/ao486/trunk
Subversion Repositories ao486
Compare Revisions
- This comparison shows the changes necessary to convert path
/ao486/trunk/rtl/ao486
- from Rev 2 to Rev 7
- ↔ Reverse comparison
Rev 2 → Rev 7
/ao486_hw.tcl
1,18 → 1,18
# TCL File Generated by Component Editor 13.1 |
# Sun Mar 30 12:22:06 CEST 2014 |
# TCL File Generated by Component Editor 14.0 |
# Mon Aug 18 22:50:23 CEST 2014 |
# DO NOT MODIFY |
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|
# |
# ao486 "ao486" v1.0 |
# 2014.03.30.12:22:06 |
# 2014.08.18.22:50:23 |
# |
# |
|
# |
# request TCL package from ACDS 13.1 |
# request TCL package from ACDS 14.0 |
# |
package require -exact qsys 13.1 |
package require -exact qsys 14.0 |
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# |
28,9 → 28,9
set_module_property DISPLAY_NAME ao486 |
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true |
set_module_property EDITABLE true |
set_module_property ANALYZE_HDL AUTO |
set_module_property REPORT_TO_TALKBACK false |
set_module_property ALLOW_GREYBOX_GENERATION false |
set_module_property REPORT_HIERARCHY false |
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|
# |
39,6 → 39,7
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" |
set_fileset_property QUARTUS_SYNTH TOP_LEVEL ao486 |
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false |
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false |
add_fileset_file ao486.v VERILOG PATH ao486.v TOP_LEVEL_FILE |
add_fileset_file avalon_io.v VERILOG PATH avalon_io.v |
add_fileset_file defines.v VERILOG PATH defines.v |
158,6 → 159,7
set_interface_property avalon_memory holdTime 0 |
set_interface_property avalon_memory linewrapBursts false |
set_interface_property avalon_memory maximumPendingReadTransactions 0 |
set_interface_property avalon_memory maximumPendingWriteTransactions 0 |
set_interface_property avalon_memory readLatency 0 |
set_interface_property avalon_memory readWaitTime 1 |
set_interface_property avalon_memory setupTime 0 |
185,7 → 187,7
# |
add_interface interrupt conduit end |
set_interface_property interrupt associatedClock clock |
set_interface_property interrupt associatedReset reset_sink |
set_interface_property interrupt associatedReset "" |
set_interface_property interrupt ENABLED true |
set_interface_property interrupt EXPORT_OF "" |
set_interface_property interrupt PORT_NAME_MAP "" |
192,9 → 194,9
set_interface_property interrupt CMSIS_SVD_VARIABLES "" |
set_interface_property interrupt SVD_ADDRESS_GROUP "" |
|
add_interface_port interrupt interrupt_do export Input 1 |
add_interface_port interrupt interrupt_vector export Input 8 |
add_interface_port interrupt interrupt_done export Output 1 |
add_interface_port interrupt interrupt_do interrupt_do Input 1 |
add_interface_port interrupt interrupt_vector interrupt_vector Input 8 |
add_interface_port interrupt interrupt_done interrupt_done Output 1 |
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# |
212,6 → 214,7
set_interface_property avalon_io holdTime 0 |
set_interface_property avalon_io linewrapBursts false |
set_interface_property avalon_io maximumPendingReadTransactions 0 |
set_interface_property avalon_io maximumPendingWriteTransactions 0 |
set_interface_property avalon_io readLatency 0 |
set_interface_property avalon_io readWaitTime 1 |
set_interface_property avalon_io setupTime 0 |
232,18 → 235,3
add_interface_port avalon_io avalon_io_writedata writedata Output 32 |
add_interface_port avalon_io avalon_io_waitrequest waitrequest Input 1 |
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# |
# connection point reset_only_ao486 |
# |
add_interface reset_only_ao486 reset end |
set_interface_property reset_only_ao486 associatedClock clock |
set_interface_property reset_only_ao486 synchronousEdges DEASSERT |
set_interface_property reset_only_ao486 ENABLED true |
set_interface_property reset_only_ao486 EXPORT_OF "" |
set_interface_property reset_only_ao486 PORT_NAME_MAP "" |
set_interface_property reset_only_ao486 CMSIS_SVD_VARIABLES "" |
set_interface_property reset_only_ao486 SVD_ADDRESS_GROUP "" |
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add_interface_port reset_only_ao486 rst_internal_n reset_n Input 1 |
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/ao486.v
30,8 → 30,6
input clk, |
input rst_n, |
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input rst_internal_n, |
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//-------------------------------------------------------------------------- |
input interrupt_do, |
input [7:0] interrupt_vector, |
154,7 → 152,7
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exception exception_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
//exception indicators |
.dec_gp_fault (dec_gp_fault), //input |
342,7 → 340,7
|
global_regs global_regs_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
//input |
.glob_param_1_set (glob_param_1_set), //input |
450,7 → 448,6
memory memory_inst( |
.clk (clk), |
.rst_n (rst_n), |
.rst_internal_n (rst_internal_n), |
|
//REQ: |
.read_do (read_do), //input |
564,7 → 561,7
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pipeline pipeline_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
//to memory |
.pr_reset (pr_reset), //output |
/memory/memory.v
28,9 → 28,7
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module memory( |
input clk, |
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input rst_n, |
input rst_internal_n, |
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//REQ: |
input read_do, |
173,7 → 171,7
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link_writeburst link_writeburst_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
// writeburst REQ |
.req_writeburst_do (req_writeburst_do), //input |
210,7 → 208,7
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link_writeline link_writeline_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
// writeline REQ |
.req_writeline_do (req_writeline_do), //input |
245,7 → 243,7
|
link_readburst link_readburst_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
// readburst REQ |
.req_readburst_do (req_readburst_do), //input |
281,7 → 279,7
|
link_readline link_readline_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
// readline REQ |
.req_readline_do (req_readline_do), //input |
316,7 → 314,7
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link_readcode link_readcode_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
// readcode REQ |
.req_readcode_do (req_readcode_do), //input |
355,7 → 353,7
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link_dcacheread link_dcacheread_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
// dcacheread REQ |
.req_dcacheread_do (req_dcacheread_do), //input |
396,7 → 394,7
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link_dcachewrite link_dcachewrite_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
// dcachewrite REQ |
.req_dcachewrite_do (req_dcachewrite_do), //input |
578,7 → 576,7
dcache dcache_inst( |
// global |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
//RESP: |
.dcacheread_do (resp_dcacheread_do), //input |
659,7 → 657,7
|
dcache_to_icache_fifo dcache_to_icache_fifo_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
//RESP: |
.dcachetoicache_write_do (dcachetoicache_write_do), //input |
678,7 → 676,7
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icache icache_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
//RESP: |
.pr_reset (pr_reset), //input |
727,7 → 725,7
memory_read memory_read_inst( |
// global |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
// read step |
.rd_reset (rd_reset), //input |
768,7 → 766,7
|
memory_write memory_write_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
// write step |
.wr_reset (wr_reset), //input |
808,7 → 806,7
|
prefetch prefetch_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
.pr_reset (pr_reset), //input |
|
836,7 → 834,7
|
prefetch_fifo prefetch_fifo_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
.pr_reset (pr_reset), //input |
|
867,7 → 865,7
|
prefetch_control prefetch_control_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
.pr_reset (pr_reset), //input //same as reset to icache |
|
906,7 → 904,7
|
tlb tlb_inst( |
.clk (clk), |
.rst_n (rst_internal_n), |
.rst_n (rst_n), |
|
.pr_reset (pr_reset), //input |
.rd_reset (rd_reset), //input |