OpenCores
URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /ao486/trunk/rtl/soc/pic
    from Rev 2 to Rev 7
    Reverse comparison

Rev 2 → Rev 7

/pic_hw.tcl
1,18 → 1,18
# TCL File Generated by Component Editor 13.1
# Fri Jan 17 22:12:28 CET 2014
# TCL File Generated by Component Editor 14.0
# Mon Aug 18 22:49:43 CEST 2014
# DO NOT MODIFY
 
 
#
# pic "pic" v1.0
# 2014.01.17.22:12:28
# 2014.08.18.22:49:43
#
#
 
#
# request TCL package from ACDS 13.1
# request TCL package from ACDS 14.0
#
package require -exact qsys 13.1
package require -exact qsys 14.0
 
 
#
28,9 → 28,9
set_module_property DISPLAY_NAME pic
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
 
 
#
39,6 → 39,7
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL pic
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file pic.v VERILOG PATH pic.v TOP_LEVEL_FILE
 
 
80,6 → 81,7
set_interface_property master holdTime 0
set_interface_property master linewrapBursts false
set_interface_property master maximumPendingReadTransactions 0
set_interface_property master maximumPendingWriteTransactions 0
set_interface_property master readLatency 0
set_interface_property master readWaitTime 1
set_interface_property master setupTime 0
116,6 → 118,7
set_interface_property slave holdTime 0
set_interface_property slave linewrapBursts false
set_interface_property slave maximumPendingReadTransactions 0
set_interface_property slave maximumPendingWriteTransactions 0
set_interface_property slave readLatency 0
set_interface_property slave readWaitTime 1
set_interface_property slave setupTime 0
158,7 → 161,7
#
add_interface conduit_interrupt conduit end
set_interface_property conduit_interrupt associatedClock clock
set_interface_property conduit_interrupt associatedReset reset_sink
set_interface_property conduit_interrupt associatedReset ""
set_interface_property conduit_interrupt ENABLED true
set_interface_property conduit_interrupt EXPORT_OF ""
set_interface_property conduit_interrupt PORT_NAME_MAP ""
165,9 → 168,9
set_interface_property conduit_interrupt CMSIS_SVD_VARIABLES ""
set_interface_property conduit_interrupt SVD_ADDRESS_GROUP ""
 
add_interface_port conduit_interrupt interrupt_do export Output 1
add_interface_port conduit_interrupt interrupt_vector export Output 8
add_interface_port conduit_interrupt interrupt_done export Input 1
add_interface_port conduit_interrupt interrupt_vector interrupt_vector Output 8
add_interface_port conduit_interrupt interrupt_done interrupt_done Input 1
add_interface_port conduit_interrupt interrupt_do interrupt_do Output 1
 
 
#

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