URL
https://opencores.org/ocsvn/ao486/ao486/trunk
Subversion Repositories ao486
Compare Revisions
- This comparison shows the changes necessary to convert path
/ao486/trunk/syn/components
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/ao486/ao486.qsf
41,7 → 41,7
set_global_assignment -name TOP_LEVEL_ENTITY ao486 |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:37:57 JULY 09, 2013" |
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" |
set_global_assignment -name LAST_QUARTUS_VERSION 13.1 |
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files |
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 |
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 |
50,73 → 50,73
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_global_assignment -name SEARCH_PATH /home/alek/aktualne/ao486/rtl |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_string.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_stack.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_register.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_debug.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_commands.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_segment.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_mutex.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_effective_address.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_debug.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_commands.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/pipeline.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/microcode_commands.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/microcode.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/fetch.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_shift.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_offset.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_multiply.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_divide.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_commands.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_regs.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_ready.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_prefix.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_commands.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode.v |
set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/condition.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb_regs.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb_memtype.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch_fifo.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch_control.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_write.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_read.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_writeline.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_writeburst.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readline.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readcode.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readburst.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_dcachewrite.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_dcacheread.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_read.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_matched.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_control_ram.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_write.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_to_icache_fifo.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_read.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_matched.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_control_ram.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/cache_data_ram.v |
set_global_assignment -name VERILOG_FILE ../../rtl/memory/avalon_mem.v |
set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_prefetch_fifo.v |
set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_icache_control_ram.v |
set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_dcache_to_icache_fifo.v |
set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_dcache_control_ram.v |
set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_cache_data_ram.v |
set_global_assignment -name VERILOG_FILE ../../rtl/exception.v |
set_global_assignment -name VERILOG_FILE ../../rtl/global_regs.v |
set_global_assignment -name VERILOG_FILE ../../rtl/defines.v |
set_global_assignment -name VERILOG_FILE ../../rtl/avalon_io.v |
set_global_assignment -name VERILOG_FILE ../../rtl/ao486.v |
set_global_assignment -name SEARCH_PATH ./../../../rtl/ao486 |
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_single_rom.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_bidir_ram.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_rom.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_ram.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_mult.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/common/simple_fifo.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write_string.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write_stack.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write_register.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write_debug.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write_commands.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/write.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read_segment.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read_mutex.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read_effective_address.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read_debug.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read_commands.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/read.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/pipeline.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/microcode_commands.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/microcode.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/fetch.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute_shift.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute_offset.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute_multiply.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute_divide.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute_commands.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/execute.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/decode_regs.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/decode_ready.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/decode_prefix.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/decode_commands.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/decode.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/pipeline/condition.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/tlb_regs.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/tlb_memtype.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/tlb.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/prefetch_fifo.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/prefetch_control.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/prefetch.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/memory_write.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/memory_read.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/memory.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_writeline.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_writeburst.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_readline.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_readcode.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_readburst.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_dcachewrite.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/link_dcacheread.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/icache_read.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/icache_matched.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/icache_control_ram.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/icache.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache_write.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache_to_icache_fifo.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache_read.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache_matched.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache_control_ram.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/dcache.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/cache_data_ram.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/memory/avalon_mem.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/exception.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/global_regs.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/avalon_io.v |
set_global_assignment -name VERILOG_FILE ../../../rtl/ao486/ao486.v |
set_global_assignment -name SDC_FILE ao486.sdc |
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED |
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON |
/ao486/ao486.sdc
23,7 → 23,7
|
# Clock constraints |
|
create_clock -name "clk" -period 20.000ns [get_ports {clk}] |
create_clock -name "clk" -period 30.000ns [get_ports {clk}] |
|
|
# Automatically constrain PLL and other generated clocks |