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URL https://opencores.org/ocsvn/ao68000/ao68000/trunk

Subversion Repositories ao68000

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    /ao68000/trunk/doc/src
    from Rev 12 to Rev 13
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Rev 12 → Rev 13

/specification_template.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/documentation.v
78,6 → 78,7
* <td>Rev. </td><td>Date </td><td>Author </td><td>Description </td></tr>
* <tr><td>1.0 </td><td>28.03.2010 </td><td>Aleksander Osman </td><td>First Draft </td></tr>
* <tr><td>1.1 </td><td>11.12.2010 </td><td>Aleksander Osman </td><td>DBcc opcode microcode fix. Wishbone SEL signal fix. Project directory structure simplification.</td></tr>
* <tr><td>1.2 </td><td>15.01.2011 </td><td>Aleksander Osman, Frederic Requin</td><td>Core area optimization: biggest gain in ALU multiplication and division reimplementation.</td></tr>
* </table>
*/
89,10 → 90,9
* - CISC processor with microcode,
* - WISHBONE revision B.3 compatible MASTER interface,
* - Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,
* - Uses about 7500 LE on Altera Cyclone II and about 45000 bits of RAM for microcode,
* - Uses about 4925 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,
* - Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents
* (\ref page_verification). The result of execution was compared,
* - Runs Linux kernel version 2.6.33.1 up to init process lookup (\ref page_soc_linux),
* - Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,
* - Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch (http://developer.berlios.de/projects/doxverilog/). The specification
* is automatically extracted from the Doxygen HTML output.
110,10 → 110,11
* - Data port maximum operand size: 32-bits,
* - Data transfer ordering: BIG ENDIAN,
* - Data transfer sequencing: UNDEFINED,
* - Constraints on <tt>CLK_I</tt> signal: described in \ref page_spec_clocks, maximum frequency: about 70 MHz.
* - Constraints on <tt>CLK_I</tt> signal: described in \ref page_spec_clocks, maximum frequency: about 64 MHz.
*
* <h3>Use</h3>
* The ao68000 can be used as an processor in a System-on-Chip booting Linux kernel up to <tt>init</tt> program lookup (\ref page_soc_linux).
* - The ao68000 is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC(http://opencores.org/project,aoocs).
* - It can also be used as a processor in a System-on-Chip booting Linux kernel version 2.6.33.1 up to <tt>init</tt> program lookup (\ref page_soc_linux).
*
* <h3>Similar projects</h3>
* Other free soft-core implementations of M68000 microprocessor include:
125,22 → 126,19
* <h3>Limitations</h3>
* - Microcode not optimized: some instructions take more cycles to execute than the original MC68000,
* - TRACE not tested,
* - The core is large compared to other implementations.
* - The core is still large compared to other implementations.
*
* <h3>TODO</h3>
* - Optimize the microcode and count the exact cycle count for every instruction,
* - Optimize the desgin and microcode,
* - Count the exact cycle count for every instruction,
* - Test TRACE,
* - Run WISHBONE verification models,
* - More documentation of the ao68000 module: signal description, operation, FSM in <tt>bus_control</tt>,
* - Describe changes done in WinUAE sources (copy from ao.c),
* - Describe microcode words and subprocedures,
* - Document the <tt>soc_for_linux</tt> modules,
* - Prepare scripts for VATS: run_sim -r -> regresion test,
* - Use memories from OpenCore common.
* - Write more documentation.
*
* <h3>Status</h3>
* - Tested with WinUAE software MC68000 emulator,
* - Booted Linux kernel up to <tt>init</tt> process lookup.
* - April 2010: Tested with WinUAE software MC68000 emulator,
* - April 2010: Booted Linux kernel up to <tt>init</tt> process lookup,
* - December 2010: Runs as a processor in OpenCores aoOCS project,
* - January 2011: Core area optimization by over 33% (Thanks to Frederic Requin).
*
* <h3>Requirements</h3>
* - Icarus Verilog simulator (http://www.icarus.com/eda/verilog/) is required to compile the <tt>tb_ao68000</tt> testbench/wrapper,
374,7 → 372,7
* <tr style="background: #CCCCCC; font-weight: bold;">
* <td>Max</td><td>Min</td><td>Resolution</td></tr>
*
* <tr><td>CLK_I</td><td>Input Port</td><td>70</td><td>-</td><td>-</td><td>-</td><td>System clock.</td></tr>
* <tr><td>CLK_I</td><td>Input Port</td><td>64</td><td>-</td><td>-</td><td>-</td><td>System clock.</td></tr>
* </table>
*/
 

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