OpenCores
URL https://opencores.org/ocsvn/apb_mstr/apb_mstr/trunk

Subversion Repositories apb_mstr

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /apb_mstr/trunk
    from Rev 7 to Rev 8
    ↔ Reverse comparison
  •

Rev 7 → Rev 8

/run/robust_apb_master.pro File deleted
/run/run.bat
1,6 → 1,6
 
echo off
 
::..\..\..\robust.exe ../src/base/apb_master.v -od out -I ../src/gen -list list.txt -listpath -header -gui -debug
::..\..\..\..\robust.exe ../src/base/apb_master.v -od out -I ../src/gen -list list.txt -listpath -header -gui -debug
 
..\..\..\robust.exe robust_apb_master.pro -gui %1 %2 %3
..\..\..\..\robust.exe ../robust_apb_master.pro -gui %1 %2 %3
/run/run.sh
1,12 → 1,12
#!/bin/bash
 
../../../robust -null
../../../../robust -null
if [ $? -eq 0 ];then
ROBUST=../../../robust
ROBUST=../../../../robust
else
echo "RobustVerilog warning: GUI version not supported - using non-GUI version robust-lite"
ROBUST=../../../robust-lite
ROBUST=../../../../robust-lite
fi
 
#$ROBUST ../src/base/apb_master.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@}
$ROBUST robust_apb_master.pro -gui ${@}
#$ROBUST src/base/apb_master.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@}
$ROBUST ../robust_apb_master.pro -gui ${@}
/src/gen/prgen_rand.v
66,7 → 66,6
input [31:0] num;
input [31:0] align_size;
integer align;
begin
align = num - (num % align_size);
end
76,14 → 75,13
function integer rand_align;
input [31:0] min;
input [31:0] max;
input [31:0] align;
input [31:0] align_val;
 
integer rand_align;
begin
rand_align = rand(min, max);
if (rand_align > align)
rand_align = align(rand_align, align);
if (rand_align > align_val)
rand_align = align(rand_align, align_val);
end
endfunction
 
/src/base/apb_master.v
26,147 → 26,147
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////
//
// General:
// The APB master is built of an AXI master and an AXI2APB bridge.
// The stub support APB (Amba2) and APB3 (Amba3) protocols,
// the define APB3 determines this (in def_apb_master.txt)
//
//
// Tasks:
//
// write_single(input addr, input wdata)
// Description: write a single APB burst
// Parameters:
// addr - address
// wdata - write data
//
// read_single(input master_num, input addr, output rdata)
// Description: read a single AB burst
// Parameters:
// addr - address
// rdata - return read data
//
// check_single(input master_num, input addr, input expected)
// Description: read a single AB burst and give an error if the data read does not match expected
// Parameters:
// addr - address
// expected - expected read data
//
// write_and_check_single(input master_num, input addr, input data)
// Description: write a single AB burst read it back and give an error if the write and read data don't match
// Parameters:
// addr - address
// data - data to write and expect on read
//
//
//////////////////////////////////////
 
 
OUTFILE PREFIX.v
 
INCLUDE def_apb_master.txt
 
VERIFY (DATA_BITS==32) else only 32 bit data supported
module PREFIX(PORTS);
 
input clk;
input reset;
output psel;
output penable;
output [ADDR_BITS-1:0] paddr;
output pwrite;
output [DATA_BITS-1:0] pwdata;
input [DATA_BITS-1:0] prdata;
IFDEF APB3
input pslverr;
input pready;
ELSE APB3
 
wire pslverr = 1'b0;
wire pready = 1'b1;
ENDIF APB3
 
wire GROUP_STUB_AXI;
 
//set random tasks to be only 32 bit singles
initial
begin
#1;
PREFIX_axi_master.enable_all;
PREFIX_axi_master.use_addr_base=1;
PREFIX_axi_master.len_min=0;
PREFIX_axi_master.len_max=0;
PREFIX_axi_master.size_min=2;
PREFIX_axi_master.size_max=2;
end
CREATE axi_master.v DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi_master)
PREFIX_axi_master PREFIX_axi_master(
.clk(clk),
.reset(reset),
.GROUP_STUB_AXI(GROUP_STUB_AXI),
.idle()
);
 
CREATE axi2apb.v DEFCMD(SWAP CONST(SLAVE_NUM) 1) DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi2apb)
 
PREFIX_axi2apb PREFIX_axi2apb(
.clk(clk),
.reset(reset),
.GROUP_STUB_AXI(GROUP_STUB_AXI),
 
.penable(penable),
.pwrite(pwrite),
.paddr(paddr),
.pwdata(pwdata),
.psel(psel),
.prdata(prdata),
.pready(pready),
.pslverr(pslverr)
);
task write_single;
input [ADDR_BITS-1:0] addr;
input [DATA_BITS-1:0] wdata;
begin
PREFIX_axi_master.write_single(0, addr, wdata);
end
endtask
 
task read_single;
input [ADDR_BITS-1:0] addr;
output [DATA_BITS-1:0] rdata;
begin
PREFIX_axi_master.read_single(0, addr, rdata);
end
endtask
 
task check_single;
input [ADDR_BITS-1:0] addr;
input [DATA_BITS-1:0] expected;
begin
PREFIX_axi_master.check_single(0, addr, expected);
end
endtask
 
task write_and_check_single;
input [ADDR_BITS-1:0] addr;
input [DATA_BITS-1:0] data;
begin
PREFIX_axi_master.write_and_check_single(0, addr, data);
end
endtask
 
endmodule
 
//////////////////////////////////////
//
// General:
// The APB master is built of an AXI master and an AXI2APB bridge.
// The stub support APB (Amba2) and APB3 (Amba3) protocols,
// the define APB3 determines this (in def_apb_master.txt)
//
//
// Tasks:
//
// write_single(input addr, input wdata)
// Description: write a single APB burst
// Parameters:
// addr - address
// wdata - write data
//
// read_single(input master_num, input addr, output rdata)
// Description: read a single AB burst
// Parameters:
// addr - address
// rdata - return read data
//
// check_single(input master_num, input addr, input expected)
// Description: read a single AB burst and give an error if the data read does not match expected
// Parameters:
// addr - address
// expected - expected read data
//
// write_and_check_single(input master_num, input addr, input data)
// Description: write a single AB burst read it back and give an error if the write and read data don't match
// Parameters:
// addr - address
// data - data to write and expect on read
//
//
//////////////////////////////////////
 
 
OUTFILE PREFIX.v
 
INCLUDE def_apb_master.txt
 
VERIFY (DATA_BITS==32) ##only 32 bit data supported
module PREFIX(PORTS);
 
input clk;
input reset;
output psel;
output penable;
output [ADDR_BITS-1:0] paddr;
output pwrite;
output [DATA_BITS-1:0] pwdata;
input [DATA_BITS-1:0] prdata;
IFDEF APB3
input pslverr;
input pready;
ELSE APB3
 
wire pslverr = 1'b0;
wire pready = 1'b1;
ENDIF APB3
 
wire GROUP_STUB_AXI;
 
//set random tasks to be only 32 bit singles
initial
begin
#1;
PREFIX_axi_master.enable_all;
PREFIX_axi_master.use_addr_base=1;
PREFIX_axi_master.len_min=0;
PREFIX_axi_master.len_max=0;
PREFIX_axi_master.size_min=2;
PREFIX_axi_master.size_max=2;
end
CREATE axi_master.v DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi_master)
PREFIX_axi_master PREFIX_axi_master(
.clk(clk),
.reset(reset),
.GROUP_STUB_AXI(GROUP_STUB_AXI),
.idle()
);
 
CREATE axi2apb.v DEFCMD(SWAP CONST(SLAVE_NUM) 1) DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX_axi2apb)
 
PREFIX_axi2apb PREFIX_axi2apb(
.clk(clk),
.reset(reset),
.GROUP_STUB_AXI(GROUP_STUB_AXI),
 
.penable(penable),
.pwrite(pwrite),
.paddr(paddr),
.pwdata(pwdata),
.psel(psel),
.prdata(prdata),
.pready(pready),
.pslverr(pslverr)
);
task write_single;
input [ADDR_BITS-1:0] addr;
input [DATA_BITS-1:0] wdata;
begin
PREFIX_axi_master.write_single(0, addr, wdata);
end
endtask
 
task read_single;
input [ADDR_BITS-1:0] addr;
output [DATA_BITS-1:0] rdata;
begin
PREFIX_axi_master.read_single(0, addr, rdata);
end
endtask
 
task check_single;
input [ADDR_BITS-1:0] addr;
input [DATA_BITS-1:0] expected;
begin
PREFIX_axi_master.check_single(0, addr, expected);
end
endtask
 
task write_and_check_single;
input [ADDR_BITS-1:0] addr;
input [DATA_BITS-1:0] data;
begin
PREFIX_axi_master.write_and_check_single(0, addr, data);
end
endtask
 
endmodule
/src/base/def_axi2apb.txt
27,25 → 27,27
//// ////
//////////////////////////////////////////////////////////////////##>
 
REQUIRE(1.4)
 
INCLUDE def_axi2apb_static.txt
 
SWAP.GLOBAL #FFD #1 ## flip-flop delay
 
SWAP.USER PREFIX axi2apb ## prefix for all modules and file names
SWAP.USER PREFIX axi2apb ## Prefix for all modules and file names
 
SWAP.USER SLAVE_NUM 8 ## number of APB slaves
SWAP.USER SLAVE_NUM 8 ## Number of APB slaves
 
SWAP.USER CMD_DEPTH 2 ## number of AXI command FIFO
SWAP.USER CMD_DEPTH 2 ## Number of AXI command FIFO
 
SWAP.USER ADDR_BITS 24 ## AXI and APB address bits
SWAP.USER ID_BITS 4 ## AXI ID bits
SWAP.USER DEC_BITS 8 ## Address MSBits for slave decoding
 
SWAP.USER DEC_ADDR0 DEC_BITS'h00 ## Slave 0 address deciding
SWAP.USER DEC_ADDR1 DEC_BITS'h01 ## Slave 1 address deciding
SWAP.USER DEC_ADDR2 DEC_BITS'h02 ## Slave 2 address deciding
SWAP.USER DEC_ADDR3 DEC_BITS'h03 ## Slave 3 address deciding
SWAP.USER DEC_ADDR4 DEC_BITS'h10 ## Slave 4 address deciding
SWAP.USER DEC_ADDR5 DEC_BITS'h11 ## Slave 5 address deciding
SWAP.USER DEC_ADDR6 DEC_BITS'h12 ## Slave 6 address deciding
SWAP.USER DEC_ADDR7 DEC_BITS'h13 ## Slave 7 address deciding
SWAP.USER DEC_ADDR0 'h00 ## Slave 0 address deciding
SWAP.USER DEC_ADDR1 'h01 ## Slave 1 address deciding
SWAP.USER DEC_ADDR2 'h02 ## Slave 2 address deciding
SWAP.USER DEC_ADDR3 'h03 ## Slave 3 address deciding
SWAP.USER DEC_ADDR4 'h10 ## Slave 4 address deciding
SWAP.USER DEC_ADDR5 'h11 ## Slave 5 address deciding
SWAP.USER DEC_ADDR6 'h12 ## Slave 6 address deciding
SWAP.USER DEC_ADDR7 'h13 ## Slave 7 address deciding
/src/base/axi2apb_mux.v
68,7 → 68,7
always @(*)
begin
casex (cmd_addr[ADDR_MSB:ADDR_LSB])
DEC_ADDRSX : slave_num = SLV_BITS'dSX;
DEC_BITSDEC_ADDRSX : slave_num = SLV_BITS'dSX;
default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error
endcase
/src/base/def_axi_master.txt
27,6 → 27,8
//// ////
//////////////////////////////////////////////////////////////////##>
 
REQUIRE(1.4)
 
INCLUDE def_axi_master_static.txt
 
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay
33,7 → 35,6
 
SWAP.USER PREFIX axi_master ##prefix for all module and file names
SWAP.USER ID_BITS 4 ##AXI ID bits
SWAP.USER ADDR_BITS 32 ##AXI address bits
SWAP.USER DATA_BITS 64 ##AXI data bits
SWAP.USER LEN_BITS 4 ##AXI LEN bits
41,8 → 42,11
 
SWAP.USER CMD_DEPTH 4 ##AXI command depth for read and write
 
SWAP.USER ID_NUM 3 ##Number of IDs (internal masters)
SWAP.USER ID0_VAL ID_BITS'b0011 ##AXI ID0
SWAP.USER ID1_VAL ID_BITS'b0010 ##AXI ID1
SWAP.USER ID2_VAL ID_BITS'b1010 ##AXI ID2
SWAP.USER ID_BITS 4 ##AXI ID bits
GROUP.USER AXI_ID is { ##Supported AXI IDs (one per internal master)
b0011
b0010
b1010
}
 
/src/base/def_axi2apb_static.txt
28,7 → 28,7
//////////////////////////////////////////////////////////////////##>
 
SWAP.GLOBAL MODEL_NAME AXI2APB bridge
 
SWAP SLV_BITS LOG2(EXPR(SLAVE_NUM+1)) ##one more for decerr slave
 
LOOP SX SLAVE_NUM
/src/base/def_axi_master_static.txt
28,10 → 28,10
//////////////////////////////////////////////////////////////////##>
 
SWAP.GLOBAL MODEL_NAME AXI master stub
VERIFY (DATA_BITS <= 64) else stub supports 32 or 64 bits data bus
VERIFY (SIZE_BITS <= 3) else stub supports 32 or 64 bits data bus
 
VERIFY (DATA_BITS <= 64) ##stub supports 32 or 64 bits data bus
VERIFY (SIZE_BITS <= 3) ##stub supports 32 or 64 bits data bus
 
GROUP STUB_AXI_A is {
ID ID_BITS output
ADDR ADDR_BITS output
79,6 → 79,7
}
 
GROUP AXI_MASTER_RAND is {
ahb_bursts SON(DEFAULT 0)
use_addr_base SON(DEFAULT 0)
len_min SON(DEFAULT 0)
len_max SON(DEFAULT 15)
87,4 → 88,7
addr_min SON(DEFAULT 0)
addr_max SON(DEFAULT {DATA_BITS{1'b1}})
}
 
SWAP ID_NUM GROUP_AXI_ID.NUM
/src/base/axi_master.v
103,11 → 103,15
// Parameters: master_num - number of internal master
// burst_num - total number of bursts to check
//
 
// insert_rand(input burst_num)
// Description: disperces burst_num between internal masters and calls insert_rand_chk for each master
// Parameters: burst_num - total number of bursts to check (combined)
//
//
// Parameters:
//
// For random testing: (changing these values automatically update interanl masters)
// ahb_bursts - if set, bursts will only be of length 1, 4, 8 or 16.
// len_min - minimum burst AXI LEN (length)
// len_max - maximum burst AXI LEN (length)
// size_min - minimum burst AXI SIZE (width)
121,10 → 125,11
 
INCLUDE def_axi_master.txt
 
ITER IX ID_NUM
ITER IDX ID_NUM
module PREFIX(PORTS);
 
`include "prgen_rand.v"
input clk;
input reset;
137,33 → 142,34
//random parameters
integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
wire GROUP_STUB_AXI_IX;
wire idle_IX;
wire scrbrd_empty_IX;
wire GROUP_STUB_AXI_IDX;
wire idle_IDX;
wire scrbrd_empty_IDX;
 
 
always @(*)
begin
#FFD;
PREFIX_singleIX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
PREFIX_singleIDX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
end
assign idle = CONCAT(idle_IX &);
assign scrbrd_empty = CONCAT(scrbrd_empty_IX &);
assign idle = CONCAT(idle_IDX &);
assign scrbrd_empty = CONCAT(scrbrd_empty_IDX &);
CREATE axi_master_single.v
 
LOOP IX ID_NUM
PREFIX_single #(IX, IDIX_VAL, CMD_DEPTH)
PREFIX_singleIX(
LOOP IDX ID_NUM
PREFIX_single #(IDX, ID_BITS'GROUP_AXI_ID[IDX], CMD_DEPTH)
PREFIX_singleIDX(
.clk(clk),
.reset(reset),
.GROUP_STUB_AXI(GROUP_STUB_AXI_IX),
.idle(idle_IX),
.scrbrd_empty(scrbrd_empty_IX)
.GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
.idle(idle_IDX),
.scrbrd_empty(scrbrd_empty_IDX)
);
ENDLOOP IX
ENDLOOP IDX
 
IFDEF TRUE(ID_NUM==1)
172,18 → 178,27
ELSE TRUE(ID_NUM==1)
 
CREATE ic.v DEFCMD(SWAP.GLOBAL PARENT PREFIX) DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS)
LOOP IX ID_NUM
STOMP NEWLINE
DEFCMD(LOOP.GLOBAL MIX_IDX 1)
STOMP NEWLINE
DEFCMD(SWAP.GLOBAL ID_MIX_ID0 IDIX_VAL)
ENDLOOP IX
CREATE ic.v \\
DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX) \\
DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\
DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\
DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\
DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\
DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
DEFCMD(SWAP.GLOBAL CONST(USER_BITS) 0)
LOOP IDX ID_NUM
STOMP NEWLINE
DEFCMD(GROUP.GLOBAL MIDX_ID overrides { ) \\
DEFCMD(GROUP_AXI_ID[IDX]) \\
DEFCMD(})
ENDLOOP IDX
 
PREFIX_ic PREFIX_ic(
.clk(clk),
.reset(reset),
.MIX_GROUP_STUB_AXI(GROUP_STUB_AXI_IX),
.MIDX_GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
.S0_GROUP_STUB_AXI(GROUP_STUB_AXI),
STOMP ,
209,7 → 224,7
begin
check_master_num("enable", master_num);
case (master_num)
IX : PREFIX_singleIX.enable = 1;
IDX : PREFIX_singleIDX.enable = 1;
endcase
end
endtask
216,7 → 231,7
 
task enable_all;
begin
PREFIX_singleIX.enable = 1;
PREFIX_singleIDX.enable = 1;
end
endtask
227,7 → 242,7
begin
check_master_num("write_single", master_num);
case (master_num)
IX : PREFIX_singleIX.write_single(addr, wdata);
IDX : PREFIX_singleIDX.write_single(addr, wdata);
endcase
end
endtask
239,7 → 254,7
begin
check_master_num("read_single", master_num);
case (master_num)
IX : PREFIX_singleIX.read_single(addr, rdata);
IDX : PREFIX_singleIDX.read_single(addr, rdata);
endcase
end
endtask
251,7 → 266,7
begin
check_master_num("check_single", master_num);
case (master_num)
IX : PREFIX_singleIX.check_single(addr, expected);
IDX : PREFIX_singleIDX.check_single(addr, expected);
endcase
end
endtask
263,7 → 278,7
begin
check_master_num("write_and_check_single", master_num);
case (master_num)
IX : PREFIX_singleIX.write_and_check_single(addr, data);
IDX : PREFIX_singleIDX.write_and_check_single(addr, data);
endcase
end
endtask
276,7 → 291,7
begin
check_master_num("insert_wr_cmd", master_num);
case (master_num)
IX : PREFIX_singleIX.insert_wr_cmd(addr, len, size);
IDX : PREFIX_singleIDX.insert_wr_cmd(addr, len, size);
endcase
end
endtask
289,7 → 304,7
begin
check_master_num("insert_rd_cmd", master_num);
case (master_num)
IX : PREFIX_singleIX.insert_rd_cmd(addr, len, size);
IDX : PREFIX_singleIDX.insert_rd_cmd(addr, len, size);
endcase
end
endtask
300,7 → 315,7
begin
check_master_num("insert_wr_data", master_num);
case (master_num)
IX : PREFIX_singleIX.insert_wr_data(wdata);
IDX : PREFIX_singleIDX.insert_wr_data(wdata);
endcase
end
endtask
313,7 → 328,7
begin
check_master_num("insert_wr_incr_data", master_num);
case (master_num)
IX : PREFIX_singleIX.insert_wr_incr_data(addr, len, size);
IDX : PREFIX_singleIDX.insert_wr_incr_data(addr, len, size);
endcase
end
endtask
324,11 → 339,28
begin
check_master_num("insert_rand_chk", master_num);
case (master_num)
IX : PREFIX_singleIX.insert_rand_chk(burst_num);
IDX : PREFIX_singleIDX.insert_rand_chk(burst_num);
endcase
end
endtask
 
task insert_rand;
input [31:0] burst_num;
reg [31:0] burst_numIDX;
integer remain;
begin
remain = burst_num;
LOOP IDX ID_NUM
if (remain > 0)
begin
burst_numIDX = rand(1, remain);
remain = remain - burst_numIDX;
insert_rand_chk(IDX, burst_numIDX);
end
ENDLOOP IDX
end
endtask
 
endmodule
/src/base/axi_master_single.v
36,7 → 36,7
parameter MASTER_NUM = 0;
parameter MASTER_ID = 0;
parameter MASTER_PEND = 0;
 
CREATE prgen_rand.v DEFCMD(DEFINE NOT_IN_LIST)
`include "prgen_rand.v"
50,7 → 50,6
(MAX_CMDS <= 256) ? 8 :
(MAX_CMDS <= 512) ? 9 : 0; //0 is ilegal
input clk;
input reset;
75,6 → 74,8
reg rd_enable = 0;
reg wr_enable = 0;
reg wait_for_write = 0;
reg err_on_wr_resp = 1;
reg err_on_rd_resp = 1;
reg scrbrd_enable = 0;
reg [LEN_BITS-1:0] wvalid_cnt;
225,7 → 226,7
assign AWADDR = wr_cmd_addr;
assign AWLEN = wr_cmd_len;
assign AWSIZE = wr_cmd_size;
assign AWID = MASTER_ID;
assign AWID = MASTER_ID;
assign AWBURST = 2'd1; //INCR only
assign AWCACHE = 4'd0; //not supported
assign AWPROT = 4'd0; //not supported
249,7 → 250,7
assign ARLOCK = 2'd0; //not supported
 
assign rd_fifo_data_in = RDATA;
assign rd_fifo_resp_in = BRESP;
assign rd_fifo_resp_in = RRESP;
assign wr_data_bytes = 1'b1 << wr_data_size;
 
325,7 → 326,7
 
if (rd_cmd_full) enable = 1; //start stub not started yet
wait ((!rd_cmd_full) & (!rd_resp_full));
#FFD; wait ((!rd_cmd_full) & (!rd_resp_full));
@(negedge clk); #FFD;
rd_cmd_push = 1;
rd_resp_push = 1;
350,7 → 351,7
if (wr_cmd_full) enable = 1; //start stub not started yet
wait ((!wr_cmd_full) & (!wr_data_full));
#FFD; wait ((!wr_cmd_full) & (!wr_data_full));
@(negedge clk); #FFD;
wr_cmd_push = 1;
wr_data_push = 1;
366,7 → 367,7
begin
wr_fifo_data_in = wdata;
wait (!wr_fifo_full);
#FFD; wait (!wr_fifo_full);
@(negedge clk); #FFD;
wr_fifo_push = 1;
@(posedge clk); #FFD;
413,7 → 414,7
scrbrd_data_in = data;
scrbrd_mask_in = mask;
wait (!scrbrd_full);
#FFD; wait (!scrbrd_full);
@(negedge clk); #FFD;
scrbrd_push = 1;
@(posedge clk); #FFD;
480,11 → 481,24
reg [ADDR_BITS-1:0] addr;
reg [LEN_BITS-1:0] len;
reg [SIZE_BITS-1:0] size;
 
begin
if (DATA_BITS==32) size_max = 2'b10;
len = rand(len_min, len_max);
size = rand(size_min, size_max);
addr = rand_align(addr_min, addr_max, 1 << size);
if (ahb_bursts)
begin
len =
len[3] ? 15 :
len[2] ? 7 :
len[1] ? 3 : 0;
if (len > 0)
size = (DATA_BITS == 64) ? 2'b11 : 2'b10; //AHB bursts always full data
 
addr = align(addr, EXPR(DATA_BITS/8)*(len+1)); //address aligned to burst size
end
insert_wr_rd_scrbrd(addr, len, size);
end
endtask
528,7 → 542,7
reg [DATA_BITS-1:0] rdata;
reg [1:0] resp;
begin
wait (!rd_fifo_empty);
#FFD; wait (!rd_fifo_empty);
rdata = rd_fifo_data;
resp = rd_fifo_resp;
@(negedge clk); #FFD;
535,6 → 549,8
rd_fifo_pop = 1;
@(posedge clk); #FFD;
rd_fifo_pop = 0;
if ((resp != 2'b00) && (err_on_rd_resp))
$display("PREFIX_MASTER%0d: RRESP_ERROR: Received RRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time);
end
endtask
547,7 → 563,7
reg [DATA_BITS-1:0] rdata;
reg [DATA_BITS-1:0] mask;
begin
wait (!scrbrd_empty);
#FFD; wait (!scrbrd_empty);
addr = scrbrd_addr;
rdata = scrbrd_data;
mask = scrbrd_mask;
563,12 → 579,14
 
reg [1:0] resp;
begin
wait (!wr_resp_empty);
#FFD; wait (!wr_resp_empty);
resp = wr_resp_resp;
@(negedge clk); #FFD;
wr_resp_pop = 1;
@(posedge clk); #FFD;
wr_resp_pop = 0;
if ((resp != 2'b00) && (err_on_wr_resp))
$display("PREFIX_MASTER%0d: BRESP_ERROR: Received BRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time);
end
endtask
625,7 → 643,7
begin
read_single_ack(addr, rdata, resp);
if (rdata !== expected)
$display("MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time);
$display("PREFIX_MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time);
end
endtask
665,7 → 683,7
rdata_masked = rdata & mask;
if (expected_data !== rdata_masked)
$display("MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time);
$display("PREFIX_MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time);
end
endtask
 
/src/base/def_apb_master.txt
27,7 → 27,7
//// ////
//////////////////////////////////////////////////////////////////##>
 
REQUIRE(1.3)
REQUIRE(1.4)
 
INCLUDE def_apb_master_static.txt
 
/robust_apb_master.pro
0,0 → 1,14
PROJDIR = run
 
SRCFILE = apb_master.v
DEFFILE =
 
OUTDIR = out
 
INCDIR += ../src/base
INCDIR += ../src/gen
 
LIST = list.txt
+LISTPATH
 
+HEADER

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.