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URL https://opencores.org/ocsvn/astron_r2sdf_fft/astron_r2sdf_fft/trunk

Subversion Repositories astron_r2sdf_fft

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  • This comparison shows the changes necessary to convert path
    /astron_r2sdf_fft/trunk
    from Rev 3 to Rev 4
    Reverse comparison

Rev 3 → Rev 4

/hdllib.cfg
1,6 → 1,6
hdl_lib_name = rTwoSDF
hdl_library_clause_name = rTwoSDF_lib
hdl_lib_uses_synth = common_pkg common_components common_counter common_mult common_requantize common_ram technology
hdl_lib_name = astron_r2sdf_fft
hdl_library_clause_name = astron_r2sdf_fft_lib
hdl_lib_uses_synth = common_pkg common_components astron_counter astron_multiplier astron_requantize astron_ram
hdl_lib_uses_sim =
hdl_lib_technology =
 
/rTwoOrder.vhd
18,11 → 18,11
--
--------------------------------------------------------------------------------
 
library ieee, common_pkg_lib, common_counter_lib, common_ram_lib;
library ieee, common_pkg_lib, astron_counter_lib, astron_ram_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_pkg_lib.common_pkg.all;
use common_ram_lib.common_ram_pkg.all;
use astron_ram_lib.common_ram_pkg.all;
 
entity rTwoOrder is
generic (
105,7 → 105,7
rd_adr <= adr_tot_cnt;
u_adr_point_cnt : entity common_counter_lib.common_counter
u_adr_point_cnt : entity astron_counter_lib.common_counter
generic map(
g_latency => 1,
g_init => 0,
126,7 → 126,7
cnt_ena <= '1' when in_val = '1' and TO_UINT(adr_chan_cnt) = c_nof_channels-1 else '0';
end generate;
u_adr_chan_cnt : entity common_counter_lib.common_counter
u_adr_chan_cnt : entity astron_counter_lib.common_counter
generic map(
g_latency => 1,
g_init => 0,
139,7 → 139,7
count => adr_chan_cnt
);
u_buff : ENTITY common_ram_lib.common_paged_ram_r_w
u_buff : ENTITY astron_ram_lib.common_paged_ram_r_w
GENERIC MAP (
g_str => "use_adr",
g_data_w => c_dat_w,
/rTwoSDF.vhd
23,7 → 23,7
-- Remarks: doc/readme.txt
 
 
library ieee, common_pkg_lib, common_requantize_lib;
library ieee, common_pkg_lib, astron_requantize_lib;
use IEEE.std_logic_1164.all;
use common_pkg_lib.common_pkg.all;
use work.twiddlesPkg.all;
148,7 → 148,7
------------------------------------------------------------------------------
-- pipelined FFT output requantization
------------------------------------------------------------------------------
u_requantize_re : entity common_requantize_lib.common_requantize
u_requantize_re : entity astron_requantize_lib.common_requantize
generic map (
g_representation => "SIGNED",
g_lsb_w => c_out_scale_w,
169,7 → 169,7
out_ovr => open
);
 
u_requantize_im : entity common_requantize_lib.common_requantize
u_requantize_im : entity astron_requantize_lib.common_requantize
generic map (
g_representation => "SIGNED",
g_lsb_w => c_out_scale_w,
/rTwoSDFStage.vhd
18,7 → 18,7
--
--------------------------------------------------------------------------------
 
library ieee, common_pkg_lib, common_components_lib, common_counter_lib, common_requantize_lib;
library ieee, common_pkg_lib, common_components_lib, astron_counter_lib, astron_requantize_lib;
use IEEE.std_logic_1164.all;
use common_pkg_lib.common_pkg.all;
use work.twiddlesPkg.all;
80,7 → 80,7
------------------------------------------------------------------------------
-- stage counter
------------------------------------------------------------------------------
u_control : entity common_counter_lib.common_counter
u_control : entity astron_counter_lib.common_counter
generic map (
g_latency => c_cnt_lat,
g_init => c_cnt_init,
165,7 → 165,7
------------------------------------------------------------------------------
-- stage requantization
------------------------------------------------------------------------------
u_requantize_re : entity common_requantize_lib.common_requantize
u_requantize_re : entity astron_requantize_lib.common_requantize
generic map (
g_representation => "SIGNED",
g_lsb_w => c_rtwo_stage_bit_growth,
186,7 → 186,7
out_ovr => open
);
 
u_requantize_im : entity common_requantize_lib.common_requantize
u_requantize_im : entity astron_requantize_lib.common_requantize
generic map (
g_representation => "SIGNED",
g_lsb_w => c_rtwo_stage_bit_growth,
/rTwoWMul.vhd
18,14 → 18,14
--
--------------------------------------------------------------------------------
 
library ieee, common_pkg_lib, common_components_lib, common_mult_lib, technology_lib;
library ieee, common_pkg_lib, common_components_lib, astron_multiplier_lib;
use IEEE.std_logic_1164.all;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
use common_pkg_lib.common_pkg.all;
 
entity rTwoWMul is
generic (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_stage : natural := 1;
g_lat : natural := 3+1 -- 3 for mult, 1 for round
);
106,7 → 106,7
------------------------------------------------------------------------------
 
gen_rtl : if g_stage=1 or c_in_dat_w>c_dsp_mult_w or c_lat<c_dsp_mult_lat generate
u_CmplxMul : entity common_mult_lib.common_complex_mult
u_CmplxMul : entity astron_multiplier_lib.common_complex_mult
generic map (
g_technology => g_technology,
g_variant => "RTL",
134,7 → 134,7
end generate;
gen_ip : if g_stage>1 and c_in_dat_w<=c_dsp_mult_w and c_lat>=c_dsp_mult_lat generate
u_cmplx_mul : entity common_mult_lib.common_complex_mult
u_cmplx_mul : entity astron_multiplier_lib.common_complex_mult
generic map (
g_technology => g_technology,
g_variant => "IP",

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