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URL https://opencores.org/ocsvn/astron_ram/astron_ram/trunk

Subversion Repositories astron_ram

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  • This comparison shows the changes necessary to convert path 
    /astron_ram/trunk
    from Rev 3 to Rev 4
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Rev 3 → Rev 4

/common_paged_ram_crw_crw.vhd
33,17 → 33,17
-- pages are then mapped at subsequent addresses in the buf RAM.
-- . The "use_adr" variant is optimal for speed, so that is set as default.
 
LIBRARY IEEE, technology_lib;
LIBRARY IEEE; --, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
LIBRARY common_pkg_lib;
USE common_pkg_lib.common_pkg.ALL;
USE work.common_ram_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- USE technology_lib.technology_select_pkg.ALL;
 
ENTITY common_paged_ram_crw_crw IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_str : STRING := "use_adr";
g_data_w : NATURAL;
g_nof_pages : NATURAL := 2; -- >= 2
/common_paged_ram_r_w.vhd
24,16 → 24,16
-- Remarks:
-- . See common_paged_ram_crw_crw for details.
 
LIBRARY IEEE, technology_lib;
LIBRARY IEEE; --, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
LIBRARY common_pkg_lib;
USE common_pkg_lib.common_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY common_paged_ram_r_w IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_str : STRING := "use_adr";
g_data_w : NATURAL;
g_nof_pages : NATURAL := 2; -- >= 2
/common_paged_ram_rw_rw.vhd
24,16 → 24,16
-- Remarks:
-- . See common_paged_ram_crw_crw for details.
 
LIBRARY IEEE, technology_lib;
LIBRARY IEEE; --, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
LIBRARY common_pkg_lib;
USE common_pkg_lib.common_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY common_paged_ram_rw_rw IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_str : STRING := "use_adr";
g_data_w : NATURAL;
g_nof_pages : NATURAL := 2; -- >= 2
/common_ram_crw_crw.vhd
18,15 → 18,15
--
-------------------------------------------------------------------------------
 
LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib, tech_ram_lib;
LIBRARY IEEE, common_pkg_lib, common_components_lib;
USE IEEE.std_logic_1164.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE work.common_ram_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY common_ram_crw_crw IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED";
g_true_dual_port : BOOLEAN := TRUE
77,7 → 77,7
-- memory access
gen_true_dual_port : IF g_true_dual_port = TRUE GENERATE
u_ram : ENTITY tech_ram_lib.tech_memory_ram_crw_crw
u_ram : ENTITY work.tech_memory_ram_crw_crw
GENERIC MAP (
g_technology => g_technology,
g_adr_w => g_ram.adr_w,
103,7 → 103,7
END GENERATE;
gen_simple_dual_port : IF g_true_dual_port = FALSE GENERATE
u_ram : ENTITY tech_ram_lib.tech_memory_ram_cr_cw
u_ram : ENTITY work.tech_memory_ram_cr_cw
GENERIC MAP (
g_technology => g_technology,
g_adr_w => g_ram.adr_w,
/common_ram_crw_crw_ratio.vhd
18,15 → 18,15
--
-------------------------------------------------------------------------------
 
LIBRARY IEEE, common_pkg_lib, common_components_lib, common_ram_lib, technology_lib, tech_ram_lib;
LIBRARY IEEE, common_pkg_lib, common_components_lib;
USE IEEE.std_logic_1164.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE common_ram_lib.common_ram_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE work.common_ram_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY common_ram_crw_crw_ratio IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_ram_a : t_c_mem := c_mem_ram; -- settings for port a
g_ram_b : t_c_mem := c_mem_ram; -- data width and address range for port b
g_init_file : STRING := "UNUSED"
82,7 → 82,7
SEVERITY FAILURE;
-- memory access
u_ramk : ENTITY tech_ram_lib.tech_memory_ram_crwk_crw
u_ramk : ENTITY work.tech_memory_ram_crwk_crw
GENERIC MAP (
g_technology => g_technology,
g_adr_a_w => g_ram_a.adr_w,
/common_ram_r_w.vhd
18,14 → 18,14
--
-------------------------------------------------------------------------------
 
LIBRARY IEEE, technology_lib;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE work.common_ram_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY common_ram_r_w IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED";
g_true_dual_port : BOOLEAN := TRUE
/common_ram_rw_rw.vhd
18,14 → 18,14
--
-------------------------------------------------------------------------------
 
LIBRARY IEEE, technology_lib;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE work.common_ram_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY common_ram_rw_rw IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED";
g_true_dual_port : BOOLEAN := TRUE
/hdllib.cfg
1,11 → 1,12
hdl_lib_name = astron_ram
hdl_library_clause_name = astron_ram_lib
hdl_lib_uses_synth = technology ip_stratixiv_ram common_pkg common_components
hdl_lib_uses_synth = common_pkg common_components
#ip_stratixiv_ram
 
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_ram ip_stratixiv_ram_lib
#hdl_lib_disclose_library_clause_names =
# ip_stratixiv_ram ip_stratixiv_ram_lib
 
synth_files =
altera_mf_components.vhd
/ip_stratixiv_ram_cr_cw.vhd
33,14 → 33,15
--applicable agreement for further details.
 
 
LIBRARY ieee;
LIBRARY ieee, common_pkg_lib;
USE ieee.std_logic_1164.all;
USE common_pkg_lib.common_pkg.ALL;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
LIBRARY technology_lib;
USE technology_lib.technology_pkg.ALL;
--LIBRARY technology_lib;
--USE technology_lib.technology_pkg.ALL;
 
ENTITY ip_stratixiv_ram_cr_cw IS
GENERIC (
67,7 → 68,7
 
ARCHITECTURE SYN OF ip_stratixiv_ram_cr_cw IS
 
CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
CONSTANT c_outdata_reg_b : STRING := sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
/ip_stratixiv_ram_crw_crw.vhd
33,14 → 33,15
--applicable agreement for further details.
 
 
LIBRARY ieee;
LIBRARY ieee, common_pkg_lib;
USE ieee.std_logic_1164.all;
USE common_pkg_lib.common_pkg.ALL;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
LIBRARY technology_lib;
USE technology_lib.technology_pkg.ALL;
--LIBRARY technology_lib;
--USE technology_lib.technology_pkg.ALL;
 
ENTITY ip_stratixiv_ram_crw_crw IS
GENERIC (
72,8 → 73,8
 
ARCHITECTURE SYN OF ip_stratixiv_ram_crw_crw IS
 
CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
CONSTANT c_outdata_reg_a : STRING := sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
CONSTANT c_outdata_reg_b : STRING := sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
/tech_memory_ram_cr_cw.vhd
18,14 → 18,14
--
-------------------------------------------------------------------------------
 
LIBRARY ieee, technology_lib;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.tech_memory_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_ram_lib;
--LIBRARY ip_stratixiv_ram_lib;
--LIBRARY ip_arria10_ram_lib;
--LIBRARY ip_arria10_e3sge3_ram_lib;
--LIBRARY ip_arria10_e1sg_ram_lib;
32,7 → 32,7
 
ENTITY tech_memory_ram_cr_cw IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0; --c_tech_select_default;
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
g_nof_words : NATURAL := 2**5;
56,7 → 56,7
ARCHITECTURE str OF tech_memory_ram_cr_cw IS
BEGIN
 
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
gen_ip_stratixiv : IF g_technology=0 GENERATE
u0 : ip_stratixiv_ram_cr_cw
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (data, rdaddress, rdclock, rdclocken, wraddress, wrclock, wrclocken, wren, q);
/tech_memory_ram_crw_crw.vhd
18,14 → 18,14
--
-------------------------------------------------------------------------------
 
LIBRARY ieee, technology_lib;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.tech_memory_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_ram_lib;
--LIBRARY ip_stratixiv_ram_lib;
--LIBRARY ip_arria10_ram_lib;
--LIBRARY ip_arria10_e3sge3_ram_lib;
--LIBRARY ip_arria10_e1sg_ram_lib;
32,7 → 32,7
 
ENTITY tech_memory_ram_crw_crw IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0; --c_tech_select_default;
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
g_nof_words : NATURAL := 2**5;
63,7 → 63,7
 
BEGIN
 
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
gen_ip_stratixiv : IF g_technology=0 GENERATE
u0 : ip_stratixiv_ram_crw_crw
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
/tech_memory_ram_crwk_crw.vhd
18,14 → 18,14
--
-------------------------------------------------------------------------------
 
LIBRARY ieee, technology_lib;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.tech_memory_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_ram_lib;
--LIBRARY ip_stratixiv_ram_lib;
--LIBRARY ip_arria10_ram_lib;
--LIBRARY ip_arria10_e3sge3_ram_lib;
--LIBRARY ip_arria10_e1sg_ram_lib;
32,7 → 32,7
 
ENTITY tech_memory_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0; --c_tech_select_default;
g_adr_a_w : NATURAL := 5;
g_dat_a_w : NATURAL := 32;
g_adr_b_w : NATURAL := 7;
65,7 → 65,7
ARCHITECTURE str OF tech_memory_ram_crwk_crw IS
BEGIN
 
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
gen_ip_stratixiv : IF g_technology=0 GENERATE
u0 : ip_stratixiv_ram_crwk_crw
GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);

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