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  • This comparison shows the changes necessary to convert path 
    /async_sdm_noc/branches/clos_opt/common
    from Rev 61 to Rev 62
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Rev 61 → Rev 62

/src/pipe4.v
16,20 → 16,15
05/05/2009 Initial version. <wsong83@gmail.com>
17/04/2011 Replace the common ack generation. <wsong83@gmail.com>
26/05/2011 Clean up for opensource. <wsong83@gmail.com>
21/06/2011 Remove the eof as it makes confusion. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module pipe4(/*AUTOARG*/
// Outputs
ia, o0, o1, o2, o3,
// Inputs
i0, i1, i2, i3, oa
`ifdef ENABLE_EOF
, i4, o4
`endif
);
parameter DW = 32; // the data width of the pipeline stage
40,11 → 35,6
input oa; // input ack
output ia; // output ack
 
`ifdef ENABLE_EOF
output o4; // the eof bit
input i4;
`endif
// internal signals
wire [SCN-1:0] tack;
59,11 → 49,6
dc2 DC3 (.d(i3[i]), .a(oa), .q(o3[i]));
end endgenerate
 
// the eof bit
`ifdef ENABLE_EOF
dc2 DD_DC4 (.d(i4), .a(oa), .q(o4));
`endif
 
// generate the input ack
assign tack = o0|o1|o2|o3;
ctree #(.DW(SCN)) ACKT (.ci(tack), .co(ia));
/src/dclos.v
16,6 → 16,7
17/07/2010 Initial version. <wsong83@gmail.com>
20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
21/06/2011 Prepare to support buffered Clos. <wsong83@gmail.com>
*/
 
22,7 → 23,7
// the router structure definitions
`include "define.v"
 
module dclos (/*AUTOARG*/
module dclos (
// Outputs
so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
31,6 → 32,9
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg
`ifdef ENABLE_BUFFERED_CLOS
, soa4, woa4, noa4, eoa4, loa4
`endif
);
parameter MN = 2; // number of CMs
55,11 → 59,17
output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
`ifdef ENABLE_BUFFERED_CLOS
input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
`endif
`else
input [NN-1:0] si4, wi4, ni4, ei4, li4;
output [NN-1:0] so4, wo4, no4, eo4, lo4;
output [NN-1:0] sia, wia, nia, eia, lia;
input [NN-1:0] soa, woa, noa, eoa, loa;
`ifdef ENABLE_BUFFERED_CLOS
input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
`endif
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs
77,9 → 87,15
`ifdef ENABLE_CHANNEL_SLICING
wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4;
wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola;
`ifdef ENABLE_BUFFERED_CLOS
wire [MN-1:0][SCN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
`endif
`else
wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4;
wire [MN-1:0] imosa, imowa, imona, imoea, imola;
`ifdef ENABLE_BUFFERED_CLOS
wire [MN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
`endif
`endif
 
// input of CMs
94,8 → 110,14
wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
`ifdef ENABLE_CHANNEL_SLICING
wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa;
`ifdef ENABLE_BUFFERED_CLOS
wire [MN-1:0][4:0][SCN-1:0] cmoa4;
`endif
`else
wire [MN-1:0][4:0] cmo4, cmoa;
`ifdef ENABLE_BUFFERED_CLOS
wire [MN-1:0][4:0] cmoa4;
`endif
`endif
genvar i,j,k;
/src/dcb.v
15,6 → 15,7
History:
17/07/2010 Initial version. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
21/06/2011 Prepare to support buffered Clos. <wsong83@gmail.com>
*/
 
21,11 → 22,14
// the router structure definitions
`include "define.v"
 
module dcb (/*AUTOARG*/
module dcb (
// Outputs
o0, o1, o2, o3, ia, o4,
// Inputs
i0, i1, i2, i3, oa, i4, cfg
`ifdef ENABLE_BUFFERED_CLOS
, o4a
`endif
);
 
parameter NN = 2; // number of input ports
39,6 → 43,9
`ifdef ENABLE_CHANNEL_SLICING
output [NN-1:0][SCN-1:0] ia, o4; // eof and ack
input [MN-1:0][SCN-1:0] oa, i4;
`ifdef ENABLE_BUFFERED_CLOS
input [MN-1:0][SCN-1:0] oa4; // the eof ack from output buffer
`endif
`else
output [NN-1:0] ia, o4; // eof and ack
input [MN-1:0] oa, i4;
50,8 → 57,14
 
`ifdef ENABLE_CHANNEL_SLICING
wire [NN-1:0][SCN-1:0][MN-1:0] am, dm4;
`ifdef ENABLE_BUFFERED_CLOS
wire [NN-1:0][SCN-1:0][MN-1:0] amd, am4;
`endif
`else
wire [NN-1:0][MN-1:0] am, dm4;
`ifdef ENABLE_BUFFERED_CLOS
wire [NN-1:0][MN-1:0] amd, am4;
`endif
`endif
genvar i, j, k;
66,13 → 79,25
and A3 (dm3[i][k][j], i3[j][k], cfg[i][j]);
`ifdef ENABLE_CHANNEL_SLICING
and A4 (dm4[i][k][j], i4[j][k], cfg[i][j]);
`ifdef ENABLE_BUFFERED_CLOS
and Aad (amd[j][k][i], oa[i][k], cfg[i][j]);
c2 Aa4 (.q(am4[j][k][i]), .a0(oa4[i][k]), .a1(cfg[i][j]));
assign am[j][k][i] = amd[j][k][i] | am4[j][k][i];
`else
and Aa (am[j][k][i], oa[i][k], cfg[i][j]);
`endif
`endif
end
 
`ifndef ENABLE_CHANNEL_SLICING
and A4 (dm4[i][j], i4[j], cfg[i][j]);
`ifdef ENABLE_BUFFERED_CLOS
and Aa (amd[j][i], oa[i], cfg[i][j]);
c2 Aa4 (.q(am4[j][i]), .a0(oa4[i]), .a1(cfg[i][j]));
assign am[j][i] = amd[j][i] | am4[j][i];
`else
and Aa (am[j][i], oa[i], cfg[i][j]);
`endif
`endif
end // block: IP
end // block: EN

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