Subversion Repositories async_sdm_noc

/input_buf.v

/im_alloc.v

/clos_sch.v

/subc_ctl.v

/router.v

router.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sdm_sch.v =================================================================== --- sdm_sch.v (nonexistent) +++ sdm_sch.v (revision 57) @@ -0,0 +1,244 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + Crossbar based SDM switch allocator + *** SystemVerilog is used *** + + References + For the detail structure, please refer to Section 6.3.1 of the thesis: + Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011. + + History: + 28/09/2009 Initial version. + 27/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +module sdm_sch (/*AUTOARG*/ + // Outputs + sack, wack, nack, eack, lack, scfg, ncfg, wcfg, ecfg, lcfg, + // Inputs + sreq, nreq, lreq, wreq, ereq, rst_n + ); + + parameter VCN = 2; // the number of virtual circuits per port + + // income requests + input [VCN-1:0][3:0] sreq, nreq, lreq; + input [VCN-1:0][1:0] wreq, ereq; + + // ack to input buffers + output [VCN-1:0] sack, wack, nack, eack, lack; + + // configuration to the crossbar + output [VCN-1:0][1:0][VCN-1:0] scfg, ncfg; + output [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg; + + input rst_n; // active low global reset + + // requests to arbiters +`ifndef ENABLE_MRMA + wire [1:0][VCN-1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals + wire [3:0][VCN-1:0][VCN-1:0] r2w, r2e, r2l; +`else + wire [1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals + wire [3:0][VCN-1:0] r2w, r2e, r2l; +`endif + + // ack from arbiters + wire [VCN-1:0][3:0] a2s, a2n, a2l; + wire [VCN-1:0][1:0] a2w, a2e; + + // ack of the arbiters + wire [1:0][VCN-1:0] r2sa, r2na; + wire [3:0][VCN-1:0] r2wa, r2ea, r2la; + +`ifdef ENABLE_MRMA + wire [VCN:0] OPrst_n; // the buffered resets to avoid metastability + wire [VCN-1:0] SOPrdy, SOPblk; // OP ready and blocked status + wire [VCN-1:0] WOPrdy, WOPblk; // OP ready and blocked status + wire [VCN-1:0] NOPrdy, NOPblk; // OP ready and blocked status + wire [VCN-1:0] EOPrdy, EOPblk; // OP ready and blocked status + wire [VCN-1:0] LOPrdy, LOPblk; // OP ready and blocked status +`endif + + genvar i,j; + + // wire shuffle + generate for(i=0; i + 20/09/2010 Modified for the Clos SDM router + 25/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +module cm_alloc (/*AUTOARG*/ +`ifndef ENABLE_CRRD + s, +`endif + // Outputs + sra, wra, nra, era, lra, scfg, ncfg, wcfg, ecfg, lcfg, + // Inputs + wr, er, sr, nr, lr + ) ; + + //requests from all IMs + input [1:0] wr, er; + input [3:0] sr, nr, lr; + + // ack to IMs + output sra, wra, nra, era, lra; + + // the configuration to the local CM + output [1:0] scfg, ncfg; + output [3:0] wcfg, ecfg, lcfg; + + // when using the asynchronous dispatching algorithm, status is sent back to IMs +`ifndef ENABLE_CRRD + output [4:0] s; +`endif + + // arbiters + mutex_arb #(2) + SA ( .req ( {lr[0], nr[0]} ), + .gnt ( scfg ) + ); + + mutex_arb #(4) + WA ( .req ( {lr[1], er[0], nr[1], sr[0]} ), + .gnt ( wcfg ) + ); + + mutex_arb #(2) + NA ( .req ( {lr[2], sr[1]} ), + .gnt ( ncfg ) + ); + + mutex_arb #(4) + EA ( .req ( {lr[3], nr[2], wr[0], sr[2]} ), + .gnt ( ecfg ) + ); + + mutex_arb #(4) + LA ( .req ( {er[1], nr[3], wr[1], sr[3]} ), + .gnt ( lcfg ) + ); + + // generating the ack + assign sra = |{wcfg[0], ncfg[0], ecfg[0], lcfg[0]}; + assign wra = |{ecfg[1], lcfg[1]}; + assign nra = |{scfg[0], wcfg[1], ecfg[2], lcfg[2]}; + assign era = |{wcfg[2], lcfg[3]}; + assign lra = |{scfg[1], wcfg[3], ncfg[1], ecfg[3]}; + + // generating the status +`ifndef ENABLE_CRRD + assign s = {|lcfg, |ecfg, |ncfg, |wcfg, |scfg}; +`endif + +endmodule // cm_alloc + +

cm_alloc.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: output_buf.v =================================================================== --- output_buf.v (nonexistent) +++ output_buf.v (revision 57) @@ -0,0 +1,143 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + Output buffer for Wormhole/SDM routers. + *** SystemVerilog is used *** + + References + * Lookahead pipelines + Montek Singh and Steven M. Nowick}, The design of high-performance dynamic asynchronous pipelines: lookahead style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007(15), 1256-1269. doi:10.1109/TVLSI.2007.902205 + + History: + 26/05/2009 Initial version. + 20/09/2010 Supporting channel slicing and SDM using macro difinitions. + 22/10/2010 Parameterize the number of pipelines in output buffers. + 23/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +// the out buffer +module outp_buf (/*AUTOARG*/ + // Outputs + o0, o1, o2, o3, o4, ia, + // Inputs + rst_n, i0, i1, i2, i3, i4, oa + ); + + parameter DW = 16; // the datawidth of a single virtual circuit + parameter PD = 2; // buffer depth + parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit + + input rst_n; // global reset, active low + input [SCN-1:0] i0, i1, i2, i3; // data input + output [SCN-1:0] o0, o1, o2, o3; // data output + wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges +`ifdef ENABLE_CHANNEL_SLICING + input [SCN-1:0] i4, oa; // eof and ack + output [SCN-1:0] o4, ia; + wire [SCN-1:0] ian_dly; + wire [PD:0][SCN-1:0] pd4, pda, pdan; // internal eof and ack +`else + input i4, oa; // eof and ack + output o4, ia; + wire ian_dly; + wire [PD:0] pd4, pda, pdan; // internal eof and ack +`endif + + +//-------------------------- pipeline ---------------------------------------// + genvar i,j; + generate for(i=0; i

output_buf.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property