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Rev 57 → Rev 58
/common/src/minus1.v
0,0 → 1,55
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
1-of-4 data decrease by one |
|
History: |
10/06/2010 Initial version. <wsong83@gmail.com> |
|
*/ |
|
module minus1 (/*AUTOARG*/ |
// Outputs |
d_o, co, zero, nzero, |
// Inputs |
en, nen, d_i |
); |
|
input en, nen; // enable and disable |
input [3:0] d_i; // the data to be reduced by one |
output [3:0] d_o; // the data output of deduction |
output co; // the carry output |
output zero; // the zero output |
output nzero; // the non-zero status |
|
wire [3:0] d_d; // the deducted data |
wire [3:0] d_r; // the remained data |
|
// remain the data |
c2 CR0 (.a0(d_i[0]), .a1(nen), .q(d_r[0])); |
c2 CR1 (.a0(d_i[1]), .a1(nen), .q(d_r[1])); |
c2 CR2 (.a0(d_i[2]), .a1(nen), .q(d_r[2])); |
c2 CR3 (.a0(d_i[3]), .a1(nen), .q(d_r[3])); |
|
// reduce the data |
c2 CD0 (.a0(d_i[1]), .a1(en), .q(d_d[0])); |
c2 CD1 (.a0(d_i[2]), .a1(en), .q(d_d[1])); |
c2 CD2 (.a0(d_i[3]), .a1(en), .q(d_d[2])); |
c2 CD2 (.a0(d_i[0]), .a1(en), .q(d_d[2])); |
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assign d_o = d_d | d_r; |
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assign zero = d_i[0]; |
assign nzero = |d_i[3:1]; |
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endmodule // minus1 |
|
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/common/src/addr_dec.v
0,0 → 1,70
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
Reduce the XY address by one |
|
History: |
10/06/2010 Initial version. <wsong83@gmail.com> |
|
*/ |
|
module addr_dec(/*AUTOARG*/); |
input [7:0] xi, yi; // the addresses input |
output [7:0] xo, yo; // the addresses output |
|
wire [7:0] xm, ym; // internal deduction output |
wire [3:0] co, zero, nzero, en, nen; // internal control bit |
|
// address X |
minus1 DECX0 ( |
.d_o ( xm[3:0] ), |
.co ( co[0] ), |
.zero ( zero[0] ), |
.nzero ( nzero[0] ), |
.en ( en[0] ), |
.nen ( nen[0] ), |
.d_i ( xi[3:0] ) |
); |
|
minus1 DECX1 ( |
.d_o ( xm[7:4] ), |
.co ( co[1] ), |
.zero ( zero[1] ), |
.nzero ( nzero[1] ), |
.en ( en[1] ), |
.nen ( nen[1] ), |
.d_i ( xi[7:4] ) |
); |
|
// address Y |
minus1 DECY0 ( |
.d_o ( ym[3:0] ), |
.co ( co[2] ), |
.zero ( zero[2] ), |
.nzero ( nzero[2] ), |
.en ( en[2] ), |
.nen ( nen[2] ), |
.d_i ( yi[3:0] ) |
); |
|
minus1 DECY1 ( |
.d_o ( ym[7:4] ), |
.co ( co[3] ), |
.zero ( zero[3] ), |
.nzero ( nzero[3] ), |
.en ( en[3] ), |
.nen ( nen[3] ), |
.d_i ( yi[7:4] ) |
); |
|
// handle the control bits |
assign en[0] = |nzero[1:0]; // reduce the |
assign |