URL
https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
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- This comparison shows the changes necessary to convert path
/async_sdm_noc/branches/init/common/script
- from Rev 22 to Rev 24
- ↔ Reverse comparison
Rev 22 → Rev 24
/cell_constraint.tcl
0,0 → 1,71
# Asynchronous SDM NoC |
# (C)2011 Wei Song |
# Advanced Processor Technologies Group |
# Computer Science, the Univ. of Manchester, UK |
# |
# Authors: |
# Wei Song wsong83@gmail.com |
# |
# License: LGPL 3.0 or later |
# |
# Disable the timing loops in asynchronous cells |
# currently using the Nangate 45nm cell lib. |
# |
# History: |
# 03/07/2009 Initial version. <wsong83@gmail.com> |
# 21/05/2011 Change to the Nangate cell library. <wsong83@gmail.com> |
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set_dont_touch mutex |
set_dont_touch delay |
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uniquify -force |
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# C-gates on control path |
foreach_in_collection celln [get_references -hierarchical c2_*] { |
set_disable_timing [get_object_name $celln]/U2 -from B -to Z |
set_disable_timing [get_object_name $celln]/U3 -from B -to Z |
} |
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# C-gates on data path, feedback and data input are disabled from timing analysis |
foreach_in_collection celln [get_references -hierarchical dc2_*] { |
set_disable_timing [get_object_name $celln]/U1 -from B -to Z |
set_disable_timing [get_object_name $celln]/U2 -from A -to Z |
set_disable_timing [get_object_name $celln]/U2 -from B -to Z |
set_disable_timing [get_object_name $celln]/U3 -from B -to Z |
} |
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# c2n gates |
foreach_in_collection celln [get_references -hierarchical c2n_*] { |
set_disable_timing [get_object_name $celln]/U1 -from B -to Z |
} |
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# c2p gates |
foreach_in_collection celln [get_references -hierarchical c2p_*] { |
set_disable_timing [get_object_name $celln]/U1 -from B -to O |
} |
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# mutex gates |
foreach_in_collection celln [get_references -hierarchical mutex_*] { |
set_disable_timing [get_object_name $celln]/U1 -from A2 -to ZN |
set_disable_timing [get_object_name $celln]/U4 -from A2 -to ZN |
set_dont_touch [get_object_name $celln]/U2 |
set_dont_touch [get_object_name $celln]/U3 |
} |
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# c2p1 gates |
foreach_in_collection celln [get_references -hierarchical c2p1_*] { |
set_disable_timing [get_object_name $celln]/U2 -from B -to Z |
set_disable_timing [get_object_name $celln]/U3 -from B -to Z |
} |
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# tarb |
foreach_in_collection celln [get_references -hierarchical tarb_*] { |
set_disable_timing [get_object_name $celln]/U2 -from A -to Z |
set_disable_timing [get_object_name $celln]/U3 -from A -to Z |
} |
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# cr_blk |
foreach_in_collection celln [get_references -hierarchical cr_blk_*] { |
set_disable_timing [get_object_name $celln]/XG/U1 -from C -to Z |
} |
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/tech.tcl
0,0 → 1,28
# Asynchronous SDM NoC |
# (C)2011 Wei Song |
# Advanced Processor Technologies Group |
# Computer Science, the Univ. of Manchester, UK |
# |
# Authors: |
# Wei Song wsong83@gmail.com |
# |
# License: LGPL 3.0 or later |
# |
# Script for cell library setting up. |
# currently using the Nangate 45nm cell lib. |
# |
# History: |
# 05/07/2009 Initial version. <wsong83@gmail.com> |
# 20/05/2011 Change to the Nangate cell library. <wsong83@gmail.com> |
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set rm_lib_dirs "../../lib" |
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set rm_library "Nangate_typ.db" |
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set search_path [concat ${search_path} "${rm_lib_dirs}/"] |
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set synthetic_library dw_foundation.sldb |
set link_library [list *] |
set link_library [concat ${link_library} ${rm_library} $synthetic_library] |
set target_library "${rm_library}" |
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