URL
https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
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- This comparison shows the changes necessary to convert path
/async_sdm_noc/branches/init/common
- from Rev 26 to Rev 27
- ↔ Reverse comparison
Rev 26 → Rev 27
/script/cell_constraint.tcl
13,7 → 13,7
# |
# History: |
# 03/07/2009 Initial version. <wsong83@gmail.com> |
# 21/05/2011 Change to the Nangate cell library. <wsong83@gmail.com> |
# 27/05/2011 Change to the Nangate cell library. <wsong83@gmail.com> |
|
set_dont_touch mutex2 |
set_dont_touch delay |
75,6 → 75,13
} |
# It is not a problem if MRMA is not used in the design. |
|
# mrma multi-resource match arbiter |
foreach_in_collection celln [get_references -hierarchical mrma_*] { |
set_disable_timing [get_object_name $celln]/*.AND_*G* -from B -to Z |
set_disable_timing [get_object_name $celln]/*.AND_RG* -from A -to Z |
} |
# It is not a problem if MRMA is not used in the design. |
|
# dcb data crossbar |
foreach_in_collection celln [get_references -hierarchical dcb_*] { |
set_disable_timing [get_object_name $celln]/*.A* -from B -to Z |
85,3 → 92,9
set_disable_timing [get_object_name $celln]/*.A* -from B -to Z |
} |
#It is not a problem if there is no rcb modules in the design. |
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# mnmr m-n match allocator |
foreach_in_collection celln [get_references -hierarchical mnma_*] { |
set_disable_timing [get_object_name $celln]/*.AND_OPRen* -from B -to Z |
} |
#It is not a problem if MNMA is not used in the design. |
/src/mrma.v
19,7 → 19,7
History: |
05/09/2009 Initial version. <wsong83@gmail.com> |
05/11/2009 Speed up the arbiter. <wsong83@gmail.com> |
24/05/2011 Clean up for opensource. <wsong83@gmail.com> |
27/05/2011 Clean up for opensource. <wsong83@gmail.com> |
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*/ |
|
88,7 → 88,7
assign scfg[j][i] = cfg[i][j]; |
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// store the match results |
c2p C (.q(cfg[i][j]), .a0(c[j]), .a1(hs[i][j])); |
c2p C (.q(cfg[i][j]), .a(c[j]), .b(hs[i][j])); |
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end // block: Clm |
end // block: Row |
/src/rcb.v
15,7 → 15,7
History: |
10/12/2009 Initial version. <wsong83@gmail.com> |
23/05/2011 Use SystemVerilog for wire declaration. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
27/05/2011 Clean up for opensource. <wsong83@gmail.com> |
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*/ |
|
33,11 → 33,11
input [NN-1:0][DW-1:0] ireq; // input requests |
output [NN-1:0] ira; // ack for input requests |
output [MN-1:0][DW-1:0] oreq; // output requests |
input [DW-1:0] ora; // ack for output requests |
input [MN-1:0] ora; // ack for output requests |
input [MN-1:0][NN-1:0] cfg; // the crossbar configuration |
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wire [MN-1:0][DW-1:0][NN-1-1:0] m; // the internal wires for requests |
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks |
wire [MN-1:0][DW-1:0][NN-1:0] m; // the internal wires for requests |
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks |
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// generate variable |
genvar i, j, k; |
45,8 → 45,8
// request matrix |
generate |
for (i=0; i<MN; i++) begin: EN |
for (j=0; j<DW; j=j+1) begin: SC |
for (k=0; k<NN; k=k+1) begin: IP |
for (j=0; j<DW; j++) begin: SC |
for (k=0; k<NN; k++) begin: IP |
and AC (m[i][j][k], ireq[k][j], cfg[i][k]); |
end |
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58,8 → 58,8
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// ack matrix |
generate |
for (k=0; k<NN; k=k+1) begin: ENA |
for (i=0; i<MN; i=i+1) begin: OP |
for (k=0; k<NN; k++) begin: ENA |
for (i=0; i<MN; i++) begin: OP |
and AC (ma[k][i], ora[i], cfg[i][k]); |
end |
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