URL
https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
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- This comparison shows the changes necessary to convert path
/async_sdm_noc/branches/init/sdm/syn
- from Rev 24 to Rev 26
- ↔ Reverse comparison
Rev 24 → Rev 26
/script/source.tcl
0,0 → 1,37
# Asynchronous SDM NoC |
# (C)2011 Wei Song |
# Advanced Processor Technologies Group |
# Computer Science, the Univ. of Manchester, UK |
# |
# Authors: |
# Wei Song wsong83@gmail.com |
# |
# License: LGPL 3.0 or later |
# |
# Source files for the wormhole/SDM routers |
# |
# History: |
# 26/05/2011 Initial version. <wsong83@gmail.com> |
|
# the common verilog source files between VC and SDM |
analyze -format verilog ../../common/src/cell_lib.v |
analyze -format verilog ../../common/src/ctree.v |
analyze -format sverilog ../../common/src/dcb.v |
analyze -format sverilog ../../common/src/dcb_xy.v |
analyze -format sverilog ../../common/src/dclos.v |
analyze -format sverilog ../../common/src/mnma.v |
analyze -format sverilog ../../common/src/mrma.v |
analyze -format verilog ../../common/src/mutex_arb.v |
analyze -format sverilog ../../common/src/pipe4.v |
analyze -format sverilog ../../common/src/rcb.v |
analyze -format verilog ../../common/src/tree_arb.v |
|
# the private code of wormhole/SDM routers |
analyze -format sverilog ../src/clos_sch.v |
analyze -format sverilog ../src/cm_alloc.v |
analyze -format sverilog ../src/im_alloc.v |
analyze -format sverilog ../src/input_buf.v |
analyze -format sverilog ../src/output_buf.v |
analyze -format sverilog ../src/router.v |
analyze -format sverilog ../src/sdm_sch.v |
analyze -format sverilog ../src/subc_ctl.v |
/script/constraint.tcl
0,0 → 1,84
# Asynchronous SDM NoC |
# (C)2011 Wei Song |
# Advanced Processor Technologies Group |
# Computer Science, the Univ. of Manchester, UK |
# |
# Authors: |
# Wei Song wsong83@gmail.com |
# |
# License: LGPL 3.0 or later |
# |
# Constraints for wormhole/SDM routers |
# |
# History: |
# 26/05/2011 Initial version. <wsong83@gmail.com> |
|
# loading the baic cell constraints |
source ../../common/script/cell_constraint.tcl |
|
# ensure the basic blocks are not ungrouped for better debugging capability |
set_ungroup [get_references -hierarchical inp_buf*] false |
set_ungroup [get_references -hierarchical outp_buf*] false |
set_ungroup CB false |
set_ungroup ALLOC false |
|
|
######### break the timing loops in the design ############## |
|
# route decision address bus |
set_disable_timing [get_cells -hierarchical Px_* ] -from A -to Z |
set_disable_timing [get_cells -hierarchical Px_* ] -from B -to Z |
set_disable_timing [get_cells -hierarchical Py_* ] -from A -to Z |
set_disable_timing [get_cells -hierarchical Py_* ] -from B -to Z |
|
# input buffer control input |
foreach_in_collection celln [get_references -hierarchical inp_buf_*] { |
set_disable_timing [get_object_name $celln]/C_RTD0/U2 -from B -to Z |
set_disable_timing [get_object_name $celln]/C_RTD1/U2 -from B -to Z |
set_disable_timing [get_object_name $celln]/C_RT_XEQ/U2 -from B -to Z |
} |
|
# the delay cell in the lookahead pipeline |
# It is not a problem to get errors here if ENABLE_LOOKAHEAD is not defined. |
foreach_in_collection celln [get_references -hierarchical outp_buf_*] { |
set_disable_timing [get_object_name $celln]/DLY/U -from A -to Z |
} |
|
# set some timing path ending points |
set DPD [] |
set DPA [] |
foreach_in_collection celln [get_references -hierarchical dc2_*] { |
append_to_collection DPD [ get_pins [get_object_name $celln]/U1/B] |
append_to_collection DPD [ get_pins [get_object_name $celln]/U2/A] |
append_to_collection DPA [ get_pins [get_object_name $celln]/U1/A] |
append_to_collection DPA [ get_pins [get_object_name $celln]/U3/A] |
} |
|
set IODI [filter [get_ports *i*] "@port_direction == in"] |
set IODO [filter [get_ports *o*] "@port_direction == out"] |
set IOAI [filter [get_ports *i*] "@port_direction == out"] |
set IOAO [filter [get_ports *o*] "@port_direction == in"] |
|
# set the timing constraints for data paths and ack paths |
# For better speed performance, please tune these delay and factors according different cell libraries |
set DATA_dly 5 |
set ACK_dly 8 |
|
set_max_delay [expr ${DATA_dly} * 1.00] -from ${DPA} -to ${DPD} -group G_DATA |
set_max_delay [expr ${ACK_dly} * 1.00] -from ${DPA} -to ${DPA} -group G_ACK |
set_max_delay [expr ${DATA_dly} * 0.30] -from ${IODI} -to ${DPD} -group G_DATA |
set_max_delay [expr ${ACK_dly} * 0.75] -from ${DPA} -to ${IOAI} -group G_ACK |
set_max_delay [expr ${DATA_dly} * 0.70] -from ${DPA} -to ${IODO} -group G_DATA |
set_max_delay [expr ${ACK_dly} * 0.25] -from ${IOAO} -to ${DPA} -group G_ACK |
|
group_path -weight 1.5 -critical_range 40 -name G_DATA |
group_path -weight 1.5 -critical_range 40 -name G_ACK |
|
set_critical_range 20 ${current_design} |
|
set_max_leakage_power 0.0 |
set_max_dynamic_power 0.0 |
set_max_area 0 |
|
# timing path disabled by user constraints |
suppress_message TIM-175 |
/script/cleanup.tcl
0,0 → 1,4
rm * |
rm -fr work |
rm -fr file |
|
/script/compile.tcl
0,0 → 1,67
# Asynchronous SDM NoC |
# (C)2011 Wei Song |
# Advanced Processor Technologies Group |
# Computer Science, the Univ. of Manchester, UK |
# |
# Authors: |
# Wei Song wsong83@gmail.com |
# |
# License: LGPL 3.0 or later |
# |
# Synthesis script |
# currently using the Nangate 45nm cell lib. |
# |
# History: |
# 26/05/2009 Initial version. <wsong83@gmail.com> |
|
set rm_top router |
set rm_para "VCN=>1, DW=>8, IPD=>1, OPD=>1" |
|
# working directory |
if {[file exists work ] && [file isdirectory work ]} { |
file delete -force work |
} |
file mkdir work |
define_design_lib work -path work |
|
if {![file exists file ]} { |
file mkdir file |
} |
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# set the technology libraries |
source ../../common/script/tech.tcl |
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# read in source codes |
source script/source.tcl |
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# elaborate the design |
elaborate ${rm_top} -parameters ${rm_para} |
|
link |
|
check_design |
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# read in constraints |
echo "It will be many errors in this step. Normally they are fine. For further info. please read the comments in the constraint scripts." |
source script/constraint.tcl |
|
link |
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#report loops |
report_timing -loops -max_paths 2 |
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compile -boundary_optimization |
|
|
define_name_rules verilog -allowed "A-Za-z0-9_" -first_restricted "\\" |
change_name -rules verilog -hierarchy |
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write -format verilog -hierarchy -out file/${current_design}_syn.v $current_design |
write_sdf -significant_digits 5 file/${current_design}.sdf |
write_sdc file/${current_design}.sdc |
|
report_constraints -verbose |
|
report_constraints |
report_area |
exit |